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feas: correct default clock divider

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This commit is contained in:
hap 2024-11-16 00:28:06 +01:00
parent 2d94f582a9
commit 6ee00e94f9
4 changed files with 21 additions and 16 deletions
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4
src/mame/fidelity/elegance.cpp
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@ -188,7 +188,7 @@ void elegance_state::main_map(address_map &map)
*******************************************************************************/
static INPUT_PORTS_START( feleg )
PORT_INCLUDE( fidel_clockdiv_4 )
PORT_INCLUDE( fidel_clockdiv_4 ) // default for >3MHz
PORT_START("IN.0")
PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_1) PORT_CODE(KEYCODE_1_PAD) PORT_NAME("RV / Pawn")
@ -210,7 +210,7 @@ INPUT_PORTS_END
static INPUT_PORTS_START( felega )
PORT_INCLUDE( feleg )
PORT_MODIFY("CPU") // default to 3.57MHz
PORT_MODIFY("CPU") // modify default to 3.57MHz
PORT_CONFNAME( 0x03, 0x01, "CPU Frequency" ) PORT_CHANGED_MEMBER(DEVICE_SELF, FUNC(elegance_state::change_cpu_freq), 0) // factory set
PORT_CONFSETTING( 0x00, "3MHz (original)" )
PORT_CONFSETTING( 0x01, "3.57MHz (AS12)" )

25
src/mame/fidelity/elite.cpp
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@ -368,9 +368,7 @@ void elite_state::eag2100_map(address_map &map)
Input Ports
*******************************************************************************/
static INPUT_PORTS_START( eas )
PORT_INCLUDE( fidel_clockdiv_4 )
static INPUT_PORTS_START( eas_base )
PORT_START("IN.0")
PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_G) PORT_NAME("Game Control")
PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_SPACE) PORT_NAME("Speaker")
@ -385,6 +383,11 @@ static INPUT_PORTS_START( eas )
PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_M) PORT_NAME("DM")
PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_DEL) PORT_CODE(KEYCODE_BACKSPACE) PORT_NAME("CL")
PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_V) PORT_NAME("RV")
INPUT_PORTS_END
static INPUT_PORTS_START( eas )
PORT_INCLUDE( eas_base )
PORT_INCLUDE( fidel_clockdiv_2 ) // default for 3MHz
PORT_START("CPU")
PORT_CONFNAME( 0x03, 0x00, "CPU Frequency" ) PORT_CHANGED_MEMBER(DEVICE_SELF, FUNC(elite_state::change_cpu_freq), 0) // factory set
@ -394,9 +397,10 @@ static INPUT_PORTS_START( eas )
INPUT_PORTS_END
static INPUT_PORTS_START( ewc )
PORT_INCLUDE( eas )
PORT_INCLUDE( eas_base )
PORT_INCLUDE( fidel_clockdiv_4 ) // default for >3MHz
PORT_MODIFY("CPU") // default to 3.57MHz
PORT_START("CPU")
PORT_CONFNAME( 0x03, 0x01, "CPU Frequency" ) PORT_CHANGED_MEMBER(DEVICE_SELF, FUNC(elite_state::change_cpu_freq), 0) // factory set
PORT_CONFSETTING( 0x00, "3MHz (EAS)" )
PORT_CONFSETTING( 0x01, "3.57MHz (EWC)" )
@ -404,9 +408,10 @@ static INPUT_PORTS_START( ewc )
INPUT_PORTS_END
static INPUT_PORTS_START( easc )
PORT_INCLUDE( eas )
PORT_INCLUDE( eas_base )
PORT_INCLUDE( fidel_clockdiv_4 ) // default for >3MHz
PORT_MODIFY("CPU") // default to 4MHz
PORT_START("CPU")
PORT_CONFNAME( 0x03, 0x02, "CPU Frequency" ) PORT_CHANGED_MEMBER(DEVICE_SELF, FUNC(elite_state::change_cpu_freq), 0) // factory set
PORT_CONFSETTING( 0x00, "3MHz (EAS)" )
PORT_CONFSETTING( 0x01, "3.57MHz (EWC)" )
@ -421,7 +426,7 @@ static INPUT_PORTS_START( pc )
INPUT_PORTS_END
static INPUT_PORTS_START( easx )
PORT_INCLUDE( eas )
PORT_INCLUDE( easc )
PORT_MODIFY("CPU") // 5MHz
PORT_BIT(0x03, IP_ACTIVE_HIGH, IPT_UNUSED)
@ -529,8 +534,8 @@ void elite_state::easx(machine_config &config)
irq_clock.signal_handler().set_inputline(m_maincpu, M6502_IRQ_LINE);
config.device_remove("nvram");
NVRAM(config, "nvram.ic8", nvram_device::DEFAULT_ALL_0);
NVRAM(config, "nvram.ic6", nvram_device::DEFAULT_ALL_0);
NVRAM(config, "nvram.ic8", nvram_device::DEFAULT_ALL_1);
NVRAM(config, "nvram.ic6", nvram_device::DEFAULT_ALL_1);
}
void elite_state::eag(machine_config &config)

4
src/mame/fidelity/sc12.cpp
View File

@ -205,7 +205,7 @@ static INPUT_PORTS_START( sc12_base )
INPUT_PORTS_END
static INPUT_PORTS_START( sc12 )
PORT_INCLUDE( fidel_clockdiv_2 )
PORT_INCLUDE( fidel_clockdiv_2 ) // default for 3MHz
PORT_INCLUDE( sc12_base )
PORT_START("CPU")
@ -216,7 +216,7 @@ static INPUT_PORTS_START( sc12 )
INPUT_PORTS_END
static INPUT_PORTS_START( sc12b )
PORT_INCLUDE( fidel_clockdiv_4 )
PORT_INCLUDE( fidel_clockdiv_4 ) // default for >3MHz
PORT_INCLUDE( sc12_base )
PORT_START("CPU")

4
src/mame/saitek/turbo16k.cpp
View File

@ -351,7 +351,7 @@ INPUT_PORTS_END
static INPUT_PORTS_START( compan3 )
PORT_INCLUDE( turbo16k )
PORT_MODIFY("FREQ") // default to 8MHz
PORT_MODIFY("FREQ") // modify default to 8MHz
PORT_CONFNAME( 0x88, 0x08, "CPU Frequency" ) PORT_CHANGED_MEMBER(DEVICE_SELF, FUNC(turbo16k_state::change_cpu_freq), 0) // factory set
PORT_CONFSETTING( 0x00, "4MHz (unofficial)" )
PORT_CONFSETTING( 0x08, "8MHz (Companion III, Express 16K)" )
@ -391,7 +391,7 @@ INPUT_PORTS_END
static INPUT_PORTS_START( tmate )
PORT_INCLUDE( conquist )
PORT_MODIFY("FREQ") // default to 8MHz
PORT_MODIFY("FREQ") // modify default to 8MHz
PORT_CONFNAME( 0x88, 0x08, "CPU Frequency" ) PORT_CHANGED_MEMBER(DEVICE_SELF, FUNC(turbo16k_state::change_cpu_freq), 0) // factory set
PORT_CONFSETTING( 0x08, "8MHz (Team-Mate)" )
PORT_CONFSETTING( 0x80, "12MHz (Conquistador)" )