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arm: blocking irq here isnt right, this fixes chessmachine isa card lockup (nw)

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This commit is contained in:
hap 2019-05-30 02:21:45 +02:00
parent 7c46f7ae77
commit 6ef307855a
4 changed files with 15 additions and 15 deletions
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4
hash/ibm5170.xml
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@ -8543,7 +8543,7 @@
</part>
</software>
<software name="chessm" supported="no">
<software name="chessm">
<!-- uses ChessMachine or Final ChessCard(ROM v3.6) ISA card -->
<description>The ChessMachine (Installer v3.0)</description>
<year>1991</year>
@ -8571,7 +8571,7 @@
</part>
</software>
<software name="chessm22" supported="no">
<software name="chessm22">
<!-- uses ChessMachine or Final ChessCard(ROM v3.6) ISA card -->
<description>The ChessMachine (Installer v2.2)</description>
<year>1991</year>

14
src/devices/bus/isa/chessm.cpp
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@ -12,10 +12,6 @@ VLSI VY86C010-12QC (ARM2), seen with 30MHz XTAL, but XTAL label usually scratche
Also seen with VY86C061PSTC (ARM6) @ 32MHz, very rare or prototype.
TODO:
- It doesn't work. Card detection routine works, comms test works, RAM test works,
program checksum works. But after it's done with tests and needs to start the chess
game, it doesn't acknowledge IRQ and locks up. The client software works fine with
finalchs (chess.exe 6502 180).
- add RAM/CPU configuration
*/
@ -34,6 +30,7 @@ isa8_chessm_device::isa8_chessm_device(const machine_config &mconfig, const char
device_t(mconfig, ISA8_CHESSM, tag, owner, clock),
device_isa8_card_interface(mconfig, *this),
m_maincpu(*this, "maincpu"),
m_ram(*this, "ram"),
m_mainlatch(*this, "mainlatch"),
m_sublatch(*this, "sublatch")
{ }
@ -46,6 +43,11 @@ isa8_chessm_device::isa8_chessm_device(const machine_config &mconfig, const char
void isa8_chessm_device::device_start()
{
if (!m_ram->started())
throw device_missing_dependencies();
m_maincpu->space(AS_PROGRAM).install_ram(0, m_ram->size() - 1, m_ram->pointer());
set_isa_device();
m_installed = false;
}
@ -118,6 +120,9 @@ void isa8_chessm_device::device_add_mconfig(machine_config &config)
m_maincpu->set_addrmap(AS_PROGRAM, &isa8_chessm_device::chessm_mem);
m_maincpu->set_copro_type(arm_cpu_device::copro_type::VL86C020);
RAM(config, m_ram).set_extra_options("128K, 512K, 1M");
m_ram->set_default_size("512K");
GENERIC_LATCH_8(config, m_mainlatch);
GENERIC_LATCH_8(config, m_sublatch);
m_sublatch->data_pending_callback().set_inputline(m_maincpu, ARM_FIRQ_LINE);
@ -163,6 +168,5 @@ WRITE8_MEMBER(isa8_chessm_device::chessm_w)
void isa8_chessm_device::chessm_mem(address_map &map)
{
map(0x00000000, 0x0007ffff).ram();
map(0x00380000, 0x00380000).r(m_sublatch, FUNC(generic_latch_8_device::read)).w(m_mainlatch, FUNC(generic_latch_8_device::write));
}

2
src/devices/bus/isa/chessm.h
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@ -13,6 +13,7 @@
#include "isa.h"
#include "cpu/arm/arm.h"
#include "machine/ram.h"
#include "machine/gen_latch.h"
@ -36,6 +37,7 @@ protected:
private:
required_device<arm_cpu_device> m_maincpu;
required_device<ram_device> m_ram;
required_device<generic_latch_8_device> m_mainlatch;
required_device<generic_latch_8_device> m_sublatch;

10
src/devices/cpu/arm/arm.cpp
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@ -488,17 +488,11 @@ void arm_cpu_device::execute_set_input(int irqline, int state)
switch (irqline)
{
case ARM_IRQ_LINE: /* IRQ */
if (state && (R15&0x3)!=eARM_MODE_IRQ) /* Don't allow nested IRQs */
m_pendingIrq=1;
else
m_pendingIrq=0;
m_pendingIrq = state ? 1 : 0;
break;
case ARM_FIRQ_LINE: /* FIRQ */
if (state && (R15&0x3)!=eARM_MODE_FIQ) /* Don't allow nested FIRQs */
m_pendingFiq=1;
else
m_pendingFiq=0;
m_pendingFiq = state ? 1 : 0;
break;
}