From 6f35b941d5bb893ea27658880c867a15434b701a Mon Sep 17 00:00:00 2001 From: cracyc Date: Tue, 12 Feb 2019 19:08:26 -0600 Subject: [PATCH] i186: make drq level triggered (nw) --- src/devices/cpu/i86/i186.cpp | 17 +++++++++++++++++ src/devices/cpu/i86/i186.h | 5 +++-- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/src/devices/cpu/i86/i186.cpp b/src/devices/cpu/i86/i186.cpp index 7738ee64d6c..8cbabf2a4ab 100644 --- a/src/devices/cpu/i86/i186.cpp +++ b/src/devices/cpu/i86/i186.cpp @@ -173,6 +173,22 @@ void i80186_cpu_device::execute_run() { while(m_icount > 0 ) { + if((m_dma[0].drq_state && (m_dma[0].control & ST_STOP)) || (m_dma[1].drq_state && (m_dma[1].control & ST_STOP))) + { + int channel = m_last_dma ? 0 : 1; + m_last_dma = !m_last_dma; + if(!(m_dma[1].drq_state && (m_dma[1].control & ST_STOP))) + channel = 0; + else if(!(m_dma[0].drq_state && (m_dma[0].control & ST_STOP))) + channel = 1; + else if((m_dma[0].control & CHANNEL_PRIORITY) && !(m_dma[1].control & CHANNEL_PRIORITY)) + channel = 0; + else if((m_dma[1].control & CHANNEL_PRIORITY) && !(m_dma[0].control & CHANNEL_PRIORITY)) + channel = 1; + m_icount--; + drq_callback(channel); + continue; + } if ( m_seg_prefix_next ) { m_seg_prefix = true; @@ -627,6 +643,7 @@ void i80186_cpu_device::device_start() save_item(NAME(m_mem.middle_size)); save_item(NAME(m_mem.peripheral)); save_item(NAME(m_reloc)); + save_item(NAME(m_last_dma)); // zerofill memset(m_timer, 0, sizeof(m_timer)); diff --git a/src/devices/cpu/i86/i186.h b/src/devices/cpu/i86/i186.h index 01960a619f5..62743f4c4b1 100644 --- a/src/devices/cpu/i86/i186.h +++ b/src/devices/cpu/i86/i186.h @@ -22,8 +22,8 @@ public: auto tmrout1_handler() { return m_out_tmrout1_func.bind(); } IRQ_CALLBACK_MEMBER(int_callback); - DECLARE_WRITE_LINE_MEMBER(drq0_w) { if(state) drq_callback(0); m_dma[0].drq_state = state; } - DECLARE_WRITE_LINE_MEMBER(drq1_w) { if(state) drq_callback(1); m_dma[1].drq_state = state; } + DECLARE_WRITE_LINE_MEMBER(drq0_w) { m_dma[0].drq_state = state; } + DECLARE_WRITE_LINE_MEMBER(drq1_w) { m_dma[1].drq_state = state; } DECLARE_WRITE_LINE_MEMBER(tmrin0_w) { if(state && (m_timer[0].control & 0x8004) == 0x8004) { inc_timer(0); } } DECLARE_WRITE_LINE_MEMBER(tmrin1_w) { if(state && (m_timer[1].control & 0x8004) == 0x8004) { inc_timer(1); } } DECLARE_WRITE_LINE_MEMBER(int0_w) { external_int(0, state); } @@ -132,6 +132,7 @@ private: dma_state m_dma[2]; intr_state m_intr; mem_state m_mem; + bool m_last_dma; static const device_timer_id TIMER_INT0 = 0; static const device_timer_id TIMER_INT1 = 1;