From 6f5982304df354a52b19603c2cb32c3b0642841f Mon Sep 17 00:00:00 2001 From: smf- Date: Sun, 23 Jun 2013 07:02:14 +0000 Subject: [PATCH] added IDE_CONTROLLER_32 for systems that have 32 bit prefetch (nw) --- src/emu/machine/ataintf.c | 4 + src/emu/machine/idectrl.c | 208 +++++++++++++++++++++++++----------- src/emu/machine/idectrl.h | 57 +++++++--- src/emu/machine/vt83c461.c | 74 +------------ src/emu/machine/vt83c461.h | 12 +-- src/mame/drivers/calchase.c | 6 +- src/mame/drivers/chihiro.c | 4 +- src/mame/drivers/mediagx.c | 8 +- src/mame/drivers/savquest.c | 12 +-- src/mame/drivers/seattle.c | 12 +-- src/mame/drivers/vegas.c | 34 ++---- 11 files changed, 219 insertions(+), 212 deletions(-) diff --git a/src/emu/machine/ataintf.c b/src/emu/machine/ataintf.c index d82d5c850a0..1f8369d6e58 100644 --- a/src/emu/machine/ataintf.c +++ b/src/emu/machine/ataintf.c @@ -24,6 +24,8 @@ void ata_interface_device::set_irq(int state) { +// printf( "irq %d\n", state ); + if (state == ASSERT_LINE) LOG(("ATA interrupt assert\n")); else @@ -35,6 +37,8 @@ void ata_interface_device::set_irq(int state) void ata_interface_device::set_dmarq(int state) { +// printf( "dmarq %d\n", state ); + m_dmarq_handler(state); } diff --git a/src/emu/machine/idectrl.c b/src/emu/machine/idectrl.c index 495ffd0510a..addb43552f1 100644 --- a/src/emu/machine/idectrl.c +++ b/src/emu/machine/idectrl.c @@ -39,6 +39,7 @@ ide_controller_device::ide_controller_device(const machine_config &mconfig, devi READ16_MEMBER( ide_controller_device::read_cs0 ) { + if (mem_mask == 0xffff && offset == 1 ){ offset = 0; popmessage( "requires ide_controller_32_device" ); } if (mem_mask == 0xff00) { return ata_interface_device::read_cs0(space, (offset * 2) + 1, 0xff) << 8; @@ -63,6 +64,7 @@ READ16_MEMBER( ide_controller_device::read_cs1 ) WRITE16_MEMBER( ide_controller_device::write_cs0 ) { + if (mem_mask == 0xffff && offset == 1 ){ offset = 0; popmessage( "requires ide_controller_32_device" ); } if (mem_mask == 0xff00) { return ata_interface_device::write_cs0(space, (offset * 2) + 1, data >> 8, 0xff); @@ -85,6 +87,82 @@ WRITE16_MEMBER( ide_controller_device::write_cs1 ) } } + +const device_type IDE_CONTROLLER_32 = &device_creator; + +ide_controller_32_device::ide_controller_32_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : + ide_controller_device(mconfig, IDE_CONTROLLER, "IDE Controller (32 bit)", tag, owner, clock, "ide_controller", __FILE__) +{ +} + +ide_controller_32_device::ide_controller_32_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source) : + ide_controller_device(mconfig, type, name, tag, owner, clock, shortname, source) +{ +} + +READ32_MEMBER(ide_controller_32_device::read_cs0) +{ + UINT32 data = 0; + + if (ACCESSING_BITS_0_15) + { + data = ide_controller_device::read_cs0(space, (offset * 2), mem_mask); + + if (offset == 0 && ACCESSING_BITS_16_31) + data |= ide_controller_device::read_cs0(space, (offset * 2), mem_mask >> 16) << 16; + } + else if (ACCESSING_BITS_16_31) + { + data = ide_controller_device::read_cs0(space, (offset * 2) + 1, mem_mask >> 16) << 16; + } + + return data; +} + +READ32_MEMBER(ide_controller_32_device::read_cs1) +{ + UINT32 data = 0; + + if (ACCESSING_BITS_0_15) + { + data = ide_controller_device::read_cs1(space, (offset * 2), mem_mask); + } + else if (ACCESSING_BITS_16_23) + { + data = ide_controller_device::read_cs1(space, (offset * 2) + 1, mem_mask >> 16) << 16; + } + + return data; +} + +WRITE32_MEMBER(ide_controller_32_device::write_cs0) +{ + if (ACCESSING_BITS_0_15) + { + ide_controller_device::write_cs0(space, (offset * 2), data, mem_mask); + + if (offset == 0 && ACCESSING_BITS_16_31) + ata_interface_device::write_cs0(space, (offset * 2), data >> 16, mem_mask >> 16); + } + else if (ACCESSING_BITS_16_31) + { + ide_controller_device::write_cs0(space, (offset * 2) + 1, data >> 16, mem_mask >> 16); + } +} + +WRITE32_MEMBER(ide_controller_32_device::write_cs1) +{ + if (ACCESSING_BITS_0_7) + { + ide_controller_device::write_cs1(space, (offset * 2), data, mem_mask); + } + else if (ACCESSING_BITS_16_23) + { + ide_controller_device::write_cs1(space, (offset * 2) + 1, data >> 16, mem_mask >> 16); + } +} + + #define IDE_BUSMASTER_STATUS_ACTIVE 0x01 #define IDE_BUSMASTER_STATUS_ERROR 0x02 #define IDE_BUSMASTER_STATUS_IRQ 0x04 @@ -92,14 +170,14 @@ WRITE16_MEMBER( ide_controller_device::write_cs1 ) const device_type BUS_MASTER_IDE_CONTROLLER = &device_creator; bus_master_ide_controller_device::bus_master_ide_controller_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : - ide_controller_device(mconfig, BUS_MASTER_IDE_CONTROLLER, "Bus Master IDE Controller", tag, owner, clock, "bus_master_ide_controller", __FILE__), - dma_address(0), - dma_bytes_left(0), - dma_descriptor(0), - dma_last_buffer(0), - bus_master_command(0), - bus_master_status(0), - bus_master_descriptor(0), + ide_controller_32_device(mconfig, BUS_MASTER_IDE_CONTROLLER, "Bus Master IDE Controller", tag, owner, clock, "bus_master_ide_controller", __FILE__), + m_dma_address(0), + m_dma_bytes_left(0), + m_dma_descriptor(0), + m_dma_last_buffer(0), + m_bus_master_command(0), + m_bus_master_status(0), + m_bus_master_descriptor(0), m_irq(0), m_dmarq(0) { @@ -107,28 +185,28 @@ bus_master_ide_controller_device::bus_master_ide_controller_device(const machine void bus_master_ide_controller_device::device_start() { - ide_controller_device::device_start(); + ide_controller_32_device::device_start(); /* find the bus master space */ - if (bmcpu != NULL) + if (m_bmcpu != NULL) { - device_t *bmtarget = machine().device(bmcpu); + device_t *bmtarget = machine().device(m_bmcpu); if (bmtarget == NULL) - throw emu_fatalerror("IDE controller '%s' bus master target '%s' doesn't exist!", tag(), bmcpu); + throw emu_fatalerror("IDE controller '%s' bus master target '%s' doesn't exist!", tag(), m_bmcpu); device_memory_interface *memory; if (!bmtarget->interface(memory)) - throw emu_fatalerror("IDE controller '%s' bus master target '%s' has no memory!", tag(), bmcpu); - dma_space = &memory->space(bmspace); - dma_address_xor = (dma_space->endianness() == ENDIANNESS_LITTLE) ? 0 : 3; + throw emu_fatalerror("IDE controller '%s' bus master target '%s' has no memory!", tag(), m_bmcpu); + m_dma_space = &memory->space(m_bmspace); + m_dma_address_xor = (m_dma_space->endianness() == ENDIANNESS_LITTLE) ? 0 : 3; } - save_item(NAME(dma_address)); - save_item(NAME(dma_bytes_left)); - save_item(NAME(dma_descriptor)); - save_item(NAME(dma_last_buffer)); - save_item(NAME(bus_master_command)); - save_item(NAME(bus_master_status)); - save_item(NAME(bus_master_descriptor)); + save_item(NAME(m_dma_address)); + save_item(NAME(m_dma_bytes_left)); + save_item(NAME(m_dma_descriptor)); + save_item(NAME(m_dma_last_buffer)); + save_item(NAME(m_bus_master_command)); + save_item(NAME(m_bus_master_status)); + save_item(NAME(m_bus_master_descriptor)); } void bus_master_ide_controller_device::set_irq(int state) @@ -140,7 +218,7 @@ void bus_master_ide_controller_device::set_irq(int state) m_irq = state; if( m_irq ) - bus_master_status |= IDE_BUSMASTER_STATUS_IRQ; + m_bus_master_status |= IDE_BUSMASTER_STATUS_IRQ; } } @@ -162,7 +240,7 @@ void bus_master_ide_controller_device::set_dmarq(int state) * *************************************/ -READ32_MEMBER( bus_master_ide_controller_device::ide_bus_master32_r ) +READ32_MEMBER( bus_master_ide_controller_device::bmdma_r ) { LOG(("%s:ide_bus_master32_r(%d, %08x)\n", machine().describe_context(), offset, mem_mask)); @@ -170,11 +248,11 @@ READ32_MEMBER( bus_master_ide_controller_device::ide_bus_master32_r ) { case 0: /* command register/status register */ - return bus_master_command | (bus_master_status << 16); + return m_bus_master_command | (m_bus_master_status << 16); case 1: /* descriptor table register */ - return bus_master_descriptor; + return m_bus_master_descriptor; } return 0xffffffff; @@ -188,7 +266,7 @@ READ32_MEMBER( bus_master_ide_controller_device::ide_bus_master32_r ) * *************************************/ -WRITE32_MEMBER( bus_master_ide_controller_device::ide_bus_master32_w ) +WRITE32_MEMBER( bus_master_ide_controller_device::bmdma_w ) { LOG(("%s:ide_bus_master32_w(%d, %08x, %08X)\n", machine().describe_context(), offset, mem_mask, data)); @@ -198,29 +276,29 @@ WRITE32_MEMBER( bus_master_ide_controller_device::ide_bus_master32_w ) if( ACCESSING_BITS_0_7 ) { /* command register */ - UINT8 old = bus_master_command; + UINT8 old = m_bus_master_command; UINT8 val = data & 0xff; /* save the read/write bit and the start/stop bit */ - bus_master_command = (old & 0xf6) | (val & 0x09); + m_bus_master_command = (old & 0xf6) | (val & 0x09); - if ((old ^ bus_master_command) & 1) + if ((old ^ m_bus_master_command) & 1) { - if (bus_master_command & 1) + if (m_bus_master_command & 1) { /* handle starting a transfer */ - bus_master_status |= IDE_BUSMASTER_STATUS_ACTIVE; + m_bus_master_status |= IDE_BUSMASTER_STATUS_ACTIVE; /* reset all the DMA data */ - dma_bytes_left = 0; - dma_descriptor = bus_master_descriptor; + m_dma_bytes_left = 0; + m_dma_descriptor = m_bus_master_descriptor; /* if we're going live, start the pending read/write */ execute_dma(); } - else if (bus_master_status & IDE_BUSMASTER_STATUS_ACTIVE) + else if (m_bus_master_status & IDE_BUSMASTER_STATUS_ACTIVE) { - bus_master_status &= ~IDE_BUSMASTER_STATUS_ACTIVE; + m_bus_master_status &= ~IDE_BUSMASTER_STATUS_ACTIVE; LOG(("DMA Aborted!\n")); } @@ -230,23 +308,23 @@ WRITE32_MEMBER( bus_master_ide_controller_device::ide_bus_master32_w ) if( ACCESSING_BITS_16_23 ) { /* status register */ - UINT8 old = bus_master_status; + UINT8 old = m_bus_master_status; UINT8 val = data >> 16; /* save the DMA capable bits */ - bus_master_status = (old & 0x9f) | (val & 0x60); + m_bus_master_status = (old & 0x9f) | (val & 0x60); /* clear interrupt and error bits */ if (val & IDE_BUSMASTER_STATUS_IRQ) - bus_master_status &= ~IDE_BUSMASTER_STATUS_IRQ; + m_bus_master_status &= ~IDE_BUSMASTER_STATUS_IRQ; if (val & IDE_BUSMASTER_STATUS_ERROR) - bus_master_status &= ~IDE_BUSMASTER_STATUS_ERROR; + m_bus_master_status &= ~IDE_BUSMASTER_STATUS_ERROR; } break; case 1: /* descriptor table register */ - bus_master_descriptor = data & 0xfffffffc; + m_bus_master_descriptor = data & 0xfffffffc; break; } } @@ -255,55 +333,55 @@ void bus_master_ide_controller_device::execute_dma() { write_dmack(ASSERT_LINE); - while (m_dmarq && (bus_master_status & IDE_BUSMASTER_STATUS_ACTIVE)) + while (m_dmarq && (m_bus_master_status & IDE_BUSMASTER_STATUS_ACTIVE)) { /* if we're out of space, grab the next descriptor */ - if (dma_bytes_left == 0) + if (m_dma_bytes_left == 0) { /* fetch the address */ - dma_address = dma_space->read_byte(dma_descriptor++ ^ dma_address_xor); - dma_address |= dma_space->read_byte(dma_descriptor++ ^ dma_address_xor) << 8; - dma_address |= dma_space->read_byte(dma_descriptor++ ^ dma_address_xor) << 16; - dma_address |= dma_space->read_byte(dma_descriptor++ ^ dma_address_xor) << 24; - dma_address &= 0xfffffffe; + m_dma_address = m_dma_space->read_byte(m_dma_descriptor++ ^ m_dma_address_xor); + m_dma_address |= m_dma_space->read_byte(m_dma_descriptor++ ^ m_dma_address_xor) << 8; + m_dma_address |= m_dma_space->read_byte(m_dma_descriptor++ ^ m_dma_address_xor) << 16; + m_dma_address |= m_dma_space->read_byte(m_dma_descriptor++ ^ m_dma_address_xor) << 24; + m_dma_address &= 0xfffffffe; /* fetch the length */ - dma_bytes_left = dma_space->read_byte(dma_descriptor++ ^ dma_address_xor); - dma_bytes_left |= dma_space->read_byte(dma_descriptor++ ^ dma_address_xor) << 8; - dma_bytes_left |= dma_space->read_byte(dma_descriptor++ ^ dma_address_xor) << 16; - dma_bytes_left |= dma_space->read_byte(dma_descriptor++ ^ dma_address_xor) << 24; - dma_last_buffer = (dma_bytes_left >> 31) & 1; - dma_bytes_left &= 0xfffe; - if (dma_bytes_left == 0) - dma_bytes_left = 0x10000; + m_dma_bytes_left = m_dma_space->read_byte(m_dma_descriptor++ ^ m_dma_address_xor); + m_dma_bytes_left |= m_dma_space->read_byte(m_dma_descriptor++ ^ m_dma_address_xor) << 8; + m_dma_bytes_left |= m_dma_space->read_byte(m_dma_descriptor++ ^ m_dma_address_xor) << 16; + m_dma_bytes_left |= m_dma_space->read_byte(m_dma_descriptor++ ^ m_dma_address_xor) << 24; + m_dma_last_buffer = (m_dma_bytes_left >> 31) & 1; + m_dma_bytes_left &= 0xfffe; + if (m_dma_bytes_left == 0) + m_dma_bytes_left = 0x10000; -// LOG(("New DMA descriptor: address = %08X bytes = %04X last = %d\n", dma_address, dma_bytes_left, dma_last_buffer)); +// LOG(("New DMA descriptor: address = %08X bytes = %04X last = %d\n", m_dma_address, m_dma_bytes_left, m_dma_last_buffer)); } - if (bus_master_command & 8) + if (m_bus_master_command & 8) { // read from ata bus UINT16 data = read_dma(); // write to memory - dma_space->write_byte(dma_address++, data & 0xff); - dma_space->write_byte(dma_address++, data >> 8); + m_dma_space->write_byte(m_dma_address++, data & 0xff); + m_dma_space->write_byte(m_dma_address++, data >> 8); } else { // read from memory; - UINT16 data = dma_space->read_byte(dma_address++); - data |= dma_space->read_byte(dma_address++) << 8; + UINT16 data = m_dma_space->read_byte(m_dma_address++); + data |= m_dma_space->read_byte(m_dma_address++) << 8; // write to ata bus write_dma(data); } - dma_bytes_left -= 2; + m_dma_bytes_left -= 2; - if (dma_bytes_left == 0 && dma_last_buffer) + if (m_dma_bytes_left == 0 && m_dma_last_buffer) { - bus_master_status &= ~IDE_BUSMASTER_STATUS_ACTIVE; + m_bus_master_status &= ~IDE_BUSMASTER_STATUS_ACTIVE; if (m_dmarq) { diff --git a/src/emu/machine/idectrl.h b/src/emu/machine/idectrl.h index 896b25b2aa7..61b7dd9a4cf 100644 --- a/src/emu/machine/idectrl.h +++ b/src/emu/machine/idectrl.h @@ -41,6 +41,33 @@ public: extern const device_type IDE_CONTROLLER; +#define MCFG_IDE_CONTROLLER_32_ADD(_tag, _slotintf, _master, _slave, _fixed) \ + MCFG_DEVICE_ADD(_tag, IDE_CONTROLLER_32, 0) \ + MCFG_ATA_SLOT_ADD(_tag ":0", _slotintf, _master, _fixed) \ + MCFG_ATA_SLOT_ADD(_tag ":1", _slotintf, _slave, _fixed) \ + MCFG_DEVICE_MODIFY(_tag) + +class ide_controller_32_device : public ide_controller_device +{ +public: + ide_controller_32_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + ide_controller_32_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source); + + virtual DECLARE_READ32_MEMBER(read_cs0); + virtual DECLARE_READ32_MEMBER(read_cs1); + virtual DECLARE_WRITE32_MEMBER(write_cs0); + virtual DECLARE_WRITE32_MEMBER(write_cs1); + +private: + using ide_controller_device::read_cs0; + using ide_controller_device::read_cs1; + using ide_controller_device::write_cs0; + using ide_controller_device::write_cs1; +}; + +extern const device_type IDE_CONTROLLER_32; + + #define MCFG_BUS_MASTER_IDE_CONTROLLER_ADD(_tag, _slotintf, _master, _slave, _fixed) \ MCFG_DEVICE_ADD(_tag, BUS_MASTER_IDE_CONTROLLER, 0) \ MCFG_ATA_SLOT_ADD(_tag ":0", _slotintf, _master, _fixed) \ @@ -50,14 +77,14 @@ extern const device_type IDE_CONTROLLER; #define MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE(bmcpu, bmspace) \ bus_master_ide_controller_device::set_bus_master_space(*device, bmcpu, bmspace); -class bus_master_ide_controller_device : public ide_controller_device +class bus_master_ide_controller_device : public ide_controller_32_device { public: bus_master_ide_controller_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - static void set_bus_master_space(device_t &device, const char *bmcpu, UINT32 bmspace) {bus_master_ide_controller_device &ide = downcast(device); ide.bmcpu = bmcpu; ide.bmspace = bmspace; } + static void set_bus_master_space(device_t &device, const char *bmcpu, UINT32 bmspace) {bus_master_ide_controller_device &ide = downcast(device); ide.m_bmcpu = bmcpu; ide.m_bmspace = bmspace; } - DECLARE_READ32_MEMBER( ide_bus_master32_r ); - DECLARE_WRITE32_MEMBER( ide_bus_master32_w ); + DECLARE_READ32_MEMBER( bmdma_r ); + DECLARE_WRITE32_MEMBER( bmdma_w ); protected: virtual void device_start(); @@ -68,18 +95,18 @@ protected: private: void execute_dma(); - const char *bmcpu; - UINT32 bmspace; - address_space * dma_space; - UINT8 dma_address_xor; + const char *m_bmcpu; + UINT32 m_bmspace; + address_space * m_dma_space; + UINT8 m_dma_address_xor; - offs_t dma_address; - UINT32 dma_bytes_left; - offs_t dma_descriptor; - UINT8 dma_last_buffer; - UINT8 bus_master_command; - UINT8 bus_master_status; - UINT32 bus_master_descriptor; + offs_t m_dma_address; + UINT32 m_dma_bytes_left; + offs_t m_dma_descriptor; + UINT8 m_dma_last_buffer; + UINT8 m_bus_master_command; + UINT8 m_bus_master_status; + UINT32 m_bus_master_descriptor; int m_irq; int m_dmarq; }; diff --git a/src/emu/machine/vt83c461.c b/src/emu/machine/vt83c461.c index 05400710197..c485d558e1b 100644 --- a/src/emu/machine/vt83c461.c +++ b/src/emu/machine/vt83c461.c @@ -17,7 +17,7 @@ const device_type VT83C461 = &device_creator; vt83c461_device::vt83c461_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : - ide_controller_device(mconfig, VT83C461, "VIA VT83C461", tag, owner, clock, "vt83c461", __FILE__), + ide_controller_32_device(mconfig, VT83C461, "VIA VT83C461", tag, owner, clock, "vt83c461", __FILE__), m_config_unknown(0), m_config_register_num(0) { @@ -29,7 +29,7 @@ vt83c461_device::vt83c461_device(const machine_config &mconfig, const char *tag, void vt83c461_device::device_start() { - ide_controller_device::device_start(); + ide_controller_32_device::device_start(); /* register ide states */ save_item(NAME(m_config_unknown)); @@ -101,73 +101,3 @@ WRITE32_MEMBER( vt83c461_device::write_config ) break; } } - -READ32_MEMBER(vt83c461_device::read_cs0) -{ - UINT32 data = 0; - - if (ACCESSING_BITS_0_15) - { - data = ide_controller_device::read_cs0(space, (offset * 2), mem_mask); - - if (offset == 0 && ACCESSING_BITS_16_31) - data |= ide_controller_device::read_cs0(space, (offset * 2), mem_mask >> 16) << 16; - } - else if (ACCESSING_BITS_16_31) - { - data = ide_controller_device::read_cs0(space, (offset * 2) + 1, mem_mask >> 16) << 16; - } - -// printf( "vt83c461 read cs0 %08x %08x %08x\n", offset, data, mem_mask ); - - return data; -} - -READ32_MEMBER(vt83c461_device::read_cs1) -{ - UINT32 data = 0; - - if (ACCESSING_BITS_0_15) - { - data = ide_controller_device::read_cs1(space, (offset * 2), mem_mask); - } - else if (ACCESSING_BITS_16_23) - { - data = ide_controller_device::read_cs1(space, (offset * 2) + 1, mem_mask >> 16) << 16; - } - -// printf( "vt83c461 read cs1 %08x %08x %08x\n", offset, data, mem_mask ); - - return data; -} - -WRITE32_MEMBER(vt83c461_device::write_cs0) -{ -// printf( "vt83c461 write cs0 %08x %08x %08x\n", offset, data, mem_mask ); - - if (ACCESSING_BITS_0_15) - { - ide_controller_device::write_cs0(space, (offset * 2), data, mem_mask); - - if (offset == 0 && ACCESSING_BITS_16_31) - ata_interface_device::write_cs0(space, (offset * 2), data >> 16, mem_mask >> 16); - } - else if (ACCESSING_BITS_16_31) - { - ide_controller_device::write_cs0(space, (offset * 2) + 1, data >> 16, mem_mask >> 16); - } -} - -WRITE32_MEMBER(vt83c461_device::write_cs1) -{ -// printf( "vt83c461 write cs1 %08x %08x %08x\n", offset, data, mem_mask ); - - if (ACCESSING_BITS_0_7) - { - ide_controller_device::write_cs1(space, (offset * 2), data, mem_mask); - } - else if (ACCESSING_BITS_16_23) - { - ide_controller_device::write_cs1(space, (offset * 2) + 1, data >> 16, mem_mask >> 16); - } -} diff --git a/src/emu/machine/vt83c461.h b/src/emu/machine/vt83c461.h index 5e1a8c5bb06..ff1e739663a 100644 --- a/src/emu/machine/vt83c461.h +++ b/src/emu/machine/vt83c461.h @@ -28,7 +28,7 @@ #define IDE_CONFIG_REGISTERS 0x10 -class vt83c461_device : public ide_controller_device +class vt83c461_device : public ide_controller_32_device { public: vt83c461_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); @@ -36,20 +36,10 @@ public: DECLARE_READ32_MEMBER(read_config); DECLARE_WRITE32_MEMBER(write_config); - virtual DECLARE_READ32_MEMBER(read_cs0); - virtual DECLARE_READ32_MEMBER(read_cs1); - virtual DECLARE_WRITE32_MEMBER(write_cs0); - virtual DECLARE_WRITE32_MEMBER(write_cs1); - protected: virtual void device_start(); private: - using ide_controller_device::read_cs0; - using ide_controller_device::read_cs1; - using ide_controller_device::write_cs0; - using ide_controller_device::write_cs1; - UINT8 m_config_unknown; UINT8 m_config_register[IDE_CONFIG_REGISTERS]; UINT8 m_config_register_num; diff --git a/src/mame/drivers/calchase.c b/src/mame/drivers/calchase.c index ea5095a1297..622b50999f0 100644 --- a/src/mame/drivers/calchase.c +++ b/src/mame/drivers/calchase.c @@ -409,7 +409,7 @@ static ADDRESS_MAP_START( calchase_io, AS_IO, 32, calchase_state ) //AM_RANGE(0x00e8, 0x00eb) AM_NOP AM_RANGE(0x00e8, 0x00ef) AM_NOP //AMI BIOS write to this ports as delays between I/O ports operations sending al value -> NEWIODELAY AM_RANGE(0x0170, 0x0177) AM_NOP //To debug - AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff) + AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE("ide", ide_controller_32_device, read_cs0, write_cs0) AM_RANGE(0x0200, 0x021f) AM_NOP //To debug AM_RANGE(0x0260, 0x026f) AM_NOP //To debug AM_RANGE(0x0278, 0x027b) AM_WRITENOP//AM_WRITE(pnp_config_w) @@ -428,7 +428,7 @@ static ADDRESS_MAP_START( calchase_io, AS_IO, 32, calchase_state ) AM_RANGE(0x0378, 0x037f) AM_NOP //To debug // AM_RANGE(0x0300, 0x03af) AM_NOP // AM_RANGE(0x03b0, 0x03df) AM_NOP - AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff) + AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE("ide", ide_controller_32_device, read_cs1, write_cs1) AM_RANGE(0x03f8, 0x03ff) AM_NOP // To debug Serial Port COM1: AM_RANGE(0x0a78, 0x0a7b) AM_WRITENOP//AM_WRITE(pnp_data_w) AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write) @@ -644,7 +644,7 @@ static MACHINE_CONFIG_START( calchase, calchase_state ) MCFG_FRAGMENT_ADD( pcat_common ) - MCFG_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", NULL, true) + MCFG_IDE_CONTROLLER_32_ADD("ide", ata_devices, "hdd", NULL, true) MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w)) MCFG_PCI_BUS_LEGACY_ADD("pcibus", 0) diff --git a/src/mame/drivers/chihiro.c b/src/mame/drivers/chihiro.c index 14577ba1c33..62bd9c9aca6 100644 --- a/src/mame/drivers/chihiro.c +++ b/src/mame/drivers/chihiro.c @@ -2949,11 +2949,11 @@ static ADDRESS_MAP_START(xbox_map_io, AS_IO, 32, chihiro_state ) AM_RANGE(0x0020, 0x0023) AM_DEVREADWRITE8("pic8259_1", pic8259_device, read, write, 0xffffffff) AM_RANGE(0x0040, 0x0043) AM_DEVREADWRITE8("pit8254", pit8254_device, read, write, 0xffffffff) AM_RANGE(0x00a0, 0x00a3) AM_DEVREADWRITE8("pic8259_2", pic8259_device, read, write, 0xffffffff) - AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", bus_master_ide_controller_device, read_cs0, write_cs0, 0xffffffff) + AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE("ide", bus_master_ide_controller_device, read_cs0, write_cs0) AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write) AM_RANGE(0x8000, 0x80ff) AM_READWRITE(dummy_r, dummy_w) AM_RANGE(0xc000, 0xc0ff) AM_READWRITE(smbus_r, smbus_w) - AM_RANGE(0xff60, 0xff67) AM_DEVREADWRITE("ide", bus_master_ide_controller_device, ide_bus_master32_r, ide_bus_master32_w) + AM_RANGE(0xff60, 0xff67) AM_DEVREADWRITE("ide", bus_master_ide_controller_device, bmdma_r, bmdma_w) ADDRESS_MAP_END static INPUT_PORTS_START( chihiro ) diff --git a/src/mame/drivers/mediagx.c b/src/mame/drivers/mediagx.c index 25e37a9adf2..1e4a74a4549 100644 --- a/src/mame/drivers/mediagx.c +++ b/src/mame/drivers/mediagx.c @@ -92,7 +92,7 @@ public: m_bios_ram(*this, "bios_ram"), m_vram(*this, "vram") { } - required_device m_ide; + required_device m_ide; required_shared_ptr m_main_ram; required_shared_ptr m_cga_ram; required_shared_ptr m_bios_ram; @@ -750,9 +750,9 @@ static ADDRESS_MAP_START(mediagx_io, AS_IO, 32, mediagx_state ) AM_RANGE(0x0020, 0x0023) AM_READWRITE8(io20_r, io20_w, 0xffff0000) AM_IMPORT_FROM(pcat32_io_common) AM_RANGE(0x00e8, 0x00eb) AM_NOP // I/O delay port - AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff) + AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE("ide", ide_controller_32_device, read_cs0, write_cs0) AM_RANGE(0x0378, 0x037b) AM_READWRITE(parallel_port_r, parallel_port_w) - AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff) + AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE("ide", ide_controller_32_device, read_cs1, write_cs1) AM_RANGE(0x0400, 0x04ff) AM_READWRITE(ad1847_r, ad1847_w) AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write) ADDRESS_MAP_END @@ -881,7 +881,7 @@ static MACHINE_CONFIG_START( mediagx, mediagx_state ) MCFG_PCI_BUS_LEGACY_ADD("pcibus", 0) MCFG_PCI_BUS_LEGACY_DEVICE(18, NULL, cx5510_pci_r, cx5510_pci_w) - MCFG_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", NULL, true) + MCFG_IDE_CONTROLLER_32_ADD("ide", ata_devices, "hdd", NULL, true) MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w)) MCFG_TIMER_DRIVER_ADD("sound_timer", mediagx_state, sound_timer_callback) diff --git a/src/mame/drivers/savquest.c b/src/mame/drivers/savquest.c index 96b52270f8d..35d65c08f6c 100644 --- a/src/mame/drivers/savquest.c +++ b/src/mame/drivers/savquest.c @@ -613,14 +613,14 @@ static ADDRESS_MAP_START(savquest_io, AS_IO, 32, savquest_state) AM_RANGE(0x00e8, 0x00ef) AM_NOP - AM_RANGE(0x0170, 0x0177) AM_DEVREADWRITE16("ide2", ide_controller_device, read_cs0, write_cs0, 0xffffffff) - AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff) + AM_RANGE(0x0170, 0x0177) AM_DEVREADWRITE("ide2", ide_controller_32_device, read_cs0, write_cs0) + AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE("ide", ide_controller_32_device, read_cs0, write_cs0) AM_RANGE(0x0378, 0x037b) AM_READWRITE(parallel_port_r, parallel_port_w) AM_RANGE(0x03b0, 0x03bf) AM_DEVREADWRITE8("vga", vga_device, port_03b0_r, port_03b0_w, 0xffffffff) AM_RANGE(0x03c0, 0x03cf) AM_DEVREADWRITE8("vga", vga_device, port_03c0_r, port_03c0_w, 0xffffffff) AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff) - AM_RANGE(0x0370, 0x0377) AM_DEVREADWRITE16("ide2", ide_controller_device, read_cs1, write_cs1, 0xffffffff) - AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff) + AM_RANGE(0x0370, 0x0377) AM_DEVREADWRITE("ide2", ide_controller_32_device, read_cs1, write_cs1) + AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE("ide", ide_controller_32_device, read_cs1, write_cs1) AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write) @@ -682,10 +682,10 @@ static MACHINE_CONFIG_START( savquest, savquest_state ) MCFG_PCI_BUS_LEGACY_DEVICE(0, NULL, intel82439tx_pci_r, intel82439tx_pci_w) MCFG_PCI_BUS_LEGACY_DEVICE(7, NULL, intel82371ab_pci_r, intel82371ab_pci_w) - MCFG_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", NULL, true) + MCFG_IDE_CONTROLLER_32_ADD("ide", ata_devices, "hdd", NULL, true) MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w)) - MCFG_IDE_CONTROLLER_ADD("ide2", ata_devices, NULL, NULL, true) + MCFG_IDE_CONTROLLER_32_ADD("ide2", ata_devices, NULL, NULL, true) MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir7_w)) /* video hardware */ diff --git a/src/mame/drivers/seattle.c b/src/mame/drivers/seattle.c index 780513410b4..f0fcab680dd 100644 --- a/src/mame/drivers/seattle.c +++ b/src/mame/drivers/seattle.c @@ -482,7 +482,7 @@ public: DECLARE_WRITE32_MEMBER(ethernet_w); DECLARE_READ32_MEMBER(widget_r); DECLARE_WRITE32_MEMBER(widget_w); - DECLARE_READ16_MEMBER(seattle_ide_r); + DECLARE_READ32_MEMBER(seattle_ide_r); DECLARE_WRITE_LINE_MEMBER(ide_interrupt); DECLARE_WRITE_LINE_MEMBER(vblank_assert); DECLARE_WRITE_LINE_MEMBER(voodoo_stall); @@ -1773,10 +1773,10 @@ PCI Mem = 08000000-09FFFFFF */ -READ16_MEMBER(seattle_state::seattle_ide_r) +READ32_MEMBER(seattle_state::seattle_ide_r) { /* note that blitz times out if we don't have this cycle stealing */ - if (offset == 6/2) + if (offset == 6/4) m_maincpu->eat_cycles(100); return m_ide->read_cs1(space, offset, mem_mask); } @@ -1785,10 +1785,10 @@ static ADDRESS_MAP_START( seattle_map, AS_PROGRAM, 32, seattle_state ) ADDRESS_MAP_UNMAP_HIGH AM_RANGE(0x00000000, 0x007fffff) AM_RAM AM_SHARE("rambase") // wg3dh only has 4MB; sfrush, blitz99 8MB AM_RANGE(0x08000000, 0x08ffffff) AM_DEVREAD_LEGACY("voodoo", voodoo_r) AM_WRITE(seattle_voodoo_w) - AM_RANGE(0x0a0001f0, 0x0a0001f7) AM_DEVREADWRITE16("ide", bus_master_ide_controller_device, read_cs0, write_cs0, 0xffffffff) - AM_RANGE(0x0a0003f0, 0x0a0003f7) AM_READ16(seattle_ide_r, 0xffffffff) AM_DEVWRITE16("ide", bus_master_ide_controller_device, write_cs1, 0xffffffff) + AM_RANGE(0x0a0001f0, 0x0a0001f7) AM_DEVREADWRITE("ide", bus_master_ide_controller_device, read_cs0, write_cs0) + AM_RANGE(0x0a0003f0, 0x0a0003f7) AM_READ(seattle_ide_r) AM_DEVWRITE("ide", bus_master_ide_controller_device, write_cs1) AM_RANGE(0x0a00040c, 0x0a00040f) AM_NOP // IDE-related, but annoying - AM_RANGE(0x0a000f00, 0x0a000f07) AM_DEVREADWRITE("ide", bus_master_ide_controller_device, ide_bus_master32_r, ide_bus_master32_w) + AM_RANGE(0x0a000f00, 0x0a000f07) AM_DEVREADWRITE("ide", bus_master_ide_controller_device, bmdma_r, bmdma_w) AM_RANGE(0x0c000000, 0x0c000fff) AM_READWRITE(galileo_r, galileo_w) AM_RANGE(0x13000000, 0x13000003) AM_WRITE(asic_fifo_w) AM_RANGE(0x16000000, 0x1600003f) AM_READWRITE_LEGACY(midway_ioasic_r, midway_ioasic_w) diff --git a/src/mame/drivers/vegas.c b/src/mame/drivers/vegas.c index 4880be59e6e..773d221f3fc 100644 --- a/src/mame/drivers/vegas.c +++ b/src/mame/drivers/vegas.c @@ -1459,64 +1459,42 @@ static WRITE32_HANDLER( asic_fifo_w ) static READ32_DEVICE_HANDLER( ide_main_r ) { bus_master_ide_controller_device *ide = (bus_master_ide_controller_device *) device; - - UINT32 data = 0; - if (ACCESSING_BITS_0_15) - data |= ide->read_cs0(space, offset * 2, mem_mask); - if (ACCESSING_BITS_16_31) - data |= ide->read_cs0(space, (offset * 2) + 1, mem_mask >> 16) << 16; - - return data; + return ide->read_cs0(space, offset, mem_mask); } static WRITE32_DEVICE_HANDLER( ide_main_w ) { bus_master_ide_controller_device *ide = (bus_master_ide_controller_device *) device; - - if (ACCESSING_BITS_0_15) - ide->write_cs0(space, offset * 2, data, mem_mask); - if (ACCESSING_BITS_16_31) - ide->write_cs0(space, (offset * 2) + 1, data >> 16, mem_mask >> 16); + ide->write_cs0(space, offset, data, mem_mask); } static READ32_DEVICE_HANDLER( ide_alt_r ) { bus_master_ide_controller_device *ide = (bus_master_ide_controller_device *) device; - - UINT32 data = 0; - if (ACCESSING_BITS_0_15) - data |= ide->read_cs1(space, (4/2) + (offset * 2), mem_mask); - if (ACCESSING_BITS_16_31) - data |= ide->read_cs1(space, (4/2) + (offset * 2) + 1, mem_mask >> 16) << 16; - - return data; + return ide->read_cs1(space, offset + 1, mem_mask); } static WRITE32_DEVICE_HANDLER( ide_alt_w ) { bus_master_ide_controller_device *ide = (bus_master_ide_controller_device *) device; - - if (ACCESSING_BITS_0_15) - ide->write_cs1(space, 6/2 + offset * 2, data, mem_mask); - if (ACCESSING_BITS_16_31) - ide->write_cs1(space, 6/2 + (offset * 2) + 1, data >> 16, mem_mask >> 16); + ide->write_cs1(space, offset + 1, data, mem_mask); } static READ32_DEVICE_HANDLER( ide_bus_master32_r ) { bus_master_ide_controller_device *ide = (bus_master_ide_controller_device *) device; - return ide->ide_bus_master32_r(space, offset, mem_mask); + return ide->bmdma_r(space, offset, mem_mask); } static WRITE32_DEVICE_HANDLER( ide_bus_master32_w ) { bus_master_ide_controller_device *ide = (bus_master_ide_controller_device *) device; - ide->ide_bus_master32_w(space, offset, data, mem_mask); + ide->bmdma_w(space, offset, data, mem_mask); }