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Implement 7404 as macro device. (nw)

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This commit is contained in:
couriersud 2016-05-02 23:42:32 +02:00
parent b2f6ce4a4f
commit 6f889d51ae
7 changed files with 98 additions and 195 deletions
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2
scripts/src/netlist.lua
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@ -88,8 +88,6 @@ project "netlist"
MAME_DIR .. "src/lib/netlist/devices/nld_4066.h",
MAME_DIR .. "src/lib/netlist/devices/nld_7402.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_7402.h",
MAME_DIR .. "src/lib/netlist/devices/nld_7404.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_7404.h",
MAME_DIR .. "src/lib/netlist/devices/nld_7408.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_7408.h",
MAME_DIR .. "src/lib/netlist/devices/nld_7410.cpp",

2
src/lib/netlist/devices/net_lib.cpp
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@ -99,7 +99,6 @@ void initialize_factory(factory_list_t &factory)
ENTRY(nicRSFF, NETDEV_RSFF, "+S,R")
ENTRY(nicDelay, NETDEV_DELAY, "-")
ENTRY(7402, TTL_7402_NOR, "+A,B")
ENTRY(7404, TTL_7404_INVERT, "+A")
ENTRY(7408, TTL_7408_AND, "+A,B")
ENTRY(7410, TTL_7410_NAND, "+A,B,C")
ENTRY(7411, TTL_7411_AND, "+A,B,C")
@ -138,7 +137,6 @@ void initialize_factory(factory_list_t &factory)
ENTRY(r2r_dac, R2R_DAC, "+VIN,R,N")
ENTRY(4538_dip, CD4538_DIP, "-")
ENTRY(7402_dip, TTL_7402_DIP, "-")
ENTRY(7404_dip, TTL_7404_DIP, "-")
ENTRY(7408_dip, TTL_7408_DIP, "-")
ENTRY(7410_dip, TTL_7410_DIP, "-")
ENTRY(7411_dip, TTL_7411_DIP, "-")

1
src/lib/netlist/devices/net_lib.h
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@ -18,7 +18,6 @@
#include "nld_4020.h"
#include "nld_4066.h"
#include "nld_7402.h"
#include "nld_7404.h"
#include "nld_7408.h"
#include "nld_7410.h"
#include "nld_7411.h"

90
src/lib/netlist/devices/nld_7404.cpp
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@ -1,90 +0,0 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
* nld_7404.c
*
*/
#include "nld_7404.h"
NETLIB_NAMESPACE_DEVICES_START()
#if 1 && (USE_TRUTHTABLE)
nld_7404::truthtable_t nld_7404::m_ttbl;
const char *nld_7404::m_desc[] = {
"A | Q ",
"0 | 1|22",
"1 | 0|15",
""
};
#else
NETLIB_START(7404)
{
register_input("A", m_I[0]);
register_output("Q", m_Q[0]);
}
NETLIB_RESET(7404)
{
}
NETLIB_UPDATE(7404)
{
/* static */ const netlist_time delay[2] = { NLTIME_FROM_NS(15), NLTIME_FROM_NS(22) };
UINT8 t = (INPLOGIC(m_I[0])) ^ 1;
OUTLOGIC(m_Q[0], t, delay[t]);
}
#endif
NETLIB_START(7404_dip)
{
register_sub("1", m_1);
register_sub("2", m_2);
register_sub("3", m_3);
register_sub("4", m_4);
register_sub("5", m_5);
register_sub("6", m_6);
register_subalias("1", m_1->m_I[0]);
register_subalias("2", m_1->m_Q[0]);
register_subalias("3", m_2->m_I[0]);
register_subalias("4", m_2->m_Q[0]);
register_subalias("5", m_3->m_I[0]);
register_subalias("6", m_3->m_Q[0]);
register_subalias("8", m_4->m_Q[0]);
register_subalias("9", m_4->m_I[0]);
register_subalias("10", m_5->m_Q[0]);
register_subalias("11", m_5->m_I[0]);
register_subalias("12", m_6->m_Q[0]);
register_subalias("13", m_6->m_I[0]);
}
NETLIB_UPDATE(7404_dip)
{
/* only called during startup */
m_1->update_dev();
m_2->update_dev();
m_3->update_dev();
m_4->update_dev();
m_5->update_dev();
m_6->update_dev();
}
NETLIB_RESET(7404_dip)
{
m_1->do_reset();
m_2->do_reset();
m_3->do_reset();
m_4->do_reset();
m_5->do_reset();
m_6->do_reset();
}
NETLIB_NAMESPACE_DEVICES_END()

67
src/lib/netlist/devices/nld_7404.h
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@ -1,67 +0,0 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
* nld_7404.h
*
* DM7404: Hex Inverting Gates
*
* +--------------+
* A1 |1 ++ 14| VCC
* Y1 |2 13| A6
* A2 |3 12| Y6
* Y2 |4 7404 11| A5
* A3 |5 10| Y5
* Y3 |6 9| A4
* GND |7 8| Y4
* +--------------+
* _
* Y = A
* +---++---+
* | A || Y |
* +===++===+
* | 0 || 1 |
* | 1 || 0 |
* +---++---+
*
* Naming conventions follow National Semiconductor datasheet
*
*/
#ifndef NLD_7404_H_
#define NLD_7404_H_
#include "nld_signal.h"
#include "nld_truthtable.h"
#define TTL_7404_INVERT(_name, _A) \
NET_REGISTER_DEV(TTL_7404_INVERT, _name) \
NET_CONNECT(_name, A, _A)
#define TTL_7404_DIP(_name) \
NET_REGISTER_DEV(TTL_7404_DIP, _name)
NETLIB_NAMESPACE_DEVICES_START()
#if 1 && (USE_TRUTHTABLE)
NETLIB_TRUTHTABLE(7404, 1, 1, 0);
#else
NETLIB_DEVICE(7404,
public:
logic_input_t m_I[1];
logic_output_t m_Q[1];
);
#endif
NETLIB_DEVICE(7404_dip,
NETLIB_SUB(7404) m_1;
NETLIB_SUB(7404) m_2;
NETLIB_SUB(7404) m_3;
NETLIB_SUB(7404) m_4;
NETLIB_SUB(7404) m_5;
NETLIB_SUB(7404) m_6;
);
NETLIB_NAMESPACE_DEVICES_END()
#endif /* NLD_7404_H_ */

114
src/lib/netlist/macro/nlm_ttl74xx.cpp
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@ -5,34 +5,6 @@
#include "devices/nld_truthtable.h"
#include "devices/nld_system.h"
/*
* DM7416: Hex Inverting Buffers with
* High Voltage Open-Collector Outputs
*
*/
NETLIST_START(TTL_7416_DIP)
TTL_7416_GATE(s1)
TTL_7416_GATE(s2)
TTL_7416_GATE(s3)
TTL_7416_GATE(s4)
TTL_7416_GATE(s5)
TTL_7416_GATE(s6)
DUMMY_INPUT(GND)
DUMMY_INPUT(VCC)
DIPPINS( /* +--------------+ */
s1.A, /* A1 |1 ++ 14| VCC */ VCC.I,
s1.Q, /* Y1 |2 13| A6 */ s6.A,
s2.A, /* A2 |3 12| Y6 */ s6.Q,
s2.Q, /* Y2 |4 7416 11| A5 */ s5.A,
s3.A, /* A3 |5 10| Y5 */ s5.Q,
s3.Q, /* Y3 |6 9| A4 */ s4.A,
GND.I, /* GND |7 8| Y4 */ s4.Q
/* +--------------+ */
)
NETLIST_END()
/*
* DM7400: Quad 2-Input NAND Gates
@ -73,6 +45,73 @@ NETLIST_START(TTL_7400_DIP)
)
NETLIST_END()
/*
* DM7404: Hex Inverting Gates
* _
* Y = A
* +---++---+
* | A || Y |
* +===++===+
* | 0 || 1 |
* | 1 || 0 |
* +---++---+
*
* Naming conventions follow National Semiconductor datasheet
*
*/
NETLIST_START(TTL_7404_DIP)
TTL_7404_GATE(s1)
TTL_7404_GATE(s2)
TTL_7404_GATE(s3)
TTL_7404_GATE(s4)
TTL_7404_GATE(s5)
TTL_7404_GATE(s6)
DUMMY_INPUT(GND)
DUMMY_INPUT(VCC)
DIPPINS( /* +--------------+ */
s1.A, /* A1 |1 ++ 14| VCC */ VCC.I,
s1.Q, /* Y1 |2 13| A6 */ s6.A,
s2.A, /* A2 |3 12| Y6 */ s6.Q,
s2.Q, /* Y2 |4 7404 11| A5 */ s5.A,
s3.A, /* A3 |5 10| Y5 */ s5.Q,
s3.Q, /* Y3 |6 9| A4 */ s4.A,
GND.I, /* GND |7 8| Y4 */ s4.Q
/* +--------------+ */
)
NETLIST_END()
/*
* DM7416: Hex Inverting Buffers with
* High Voltage Open-Collector Outputs
*
*/
NETLIST_START(TTL_7416_DIP)
TTL_7416_GATE(s1)
TTL_7416_GATE(s2)
TTL_7416_GATE(s3)
TTL_7416_GATE(s4)
TTL_7416_GATE(s5)
TTL_7416_GATE(s6)
DUMMY_INPUT(GND)
DUMMY_INPUT(VCC)
DIPPINS( /* +--------------+ */
s1.A, /* A1 |1 ++ 14| VCC */ VCC.I,
s1.Q, /* Y1 |2 13| A6 */ s6.A,
s2.A, /* A2 |3 12| Y6 */ s6.Q,
s2.Q, /* Y2 |4 7416 11| A5 */ s5.A,
s3.A, /* A3 |5 10| Y5 */ s5.Q,
s3.Q, /* Y3 |6 9| A4 */ s4.A,
GND.I, /* GND |7 8| Y4 */ s4.Q
/* +--------------+ */
)
NETLIST_END()
NETLIST_START(TTL74XX_lib)
TRUTHTABLE_START(TTL_7400_GATE, 2, 1, 0, "")
@ -80,7 +119,6 @@ NETLIST_START(TTL74XX_lib)
TT_LINE("0,X|1|22")
TT_LINE("X,0|1|22")
TT_LINE("1,1|0|15")
/* Open Collector */
TT_FAMILY("74XX")
TRUTHTABLE_END()
@ -89,7 +127,20 @@ NETLIST_START(TTL74XX_lib)
TT_LINE("0,X|1|22")
TT_LINE("X,0|1|22")
TT_LINE("1,1|0|15")
/* Open Collector */
TT_FAMILY("74XX")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_7404_GATE, 1, 1, 0, "")
TT_HEAD(" A | Q ")
TT_LINE(" 0 | 1 |22")
TT_LINE(" 1 | 0 |15")
TT_FAMILY("74XX")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_7404_INVERT, 1, 1, 0, "A")
TT_HEAD(" A | Q ")
TT_LINE(" 0 | 1 |22")
TT_LINE(" 1 | 0 |15")
TT_FAMILY("74XX")
TRUTHTABLE_END()
@ -101,6 +152,7 @@ NETLIST_START(TTL74XX_lib)
TT_FAMILY("74XXOC")
TRUTHTABLE_END()
LOCAL_LIB_ENTRY(TTL_7416_DIP)
LOCAL_LIB_ENTRY(TTL_7400_DIP)
LOCAL_LIB_ENTRY(TTL_7404_DIP)
LOCAL_LIB_ENTRY(TTL_7416_DIP)
NETLIST_END()

17
src/lib/netlist/macro/nlm_ttl74xx.h
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@ -13,14 +13,27 @@
#define TTL_7400_GATE(_name) \
NET_REGISTER_DEV(TTL_7400_GATE, _name)
#define TTL_7400_NAND(_name, _A, _B) \
NET_REGISTER_DEV(TTL_7400_NAND, _name) \
NET_CONNECT(_name, A, _A) \
NET_REGISTER_DEV(TTL_7400_NAND, _name) \
NET_CONNECT(_name, A, _A) \
NET_CONNECT(_name, B, _B)
#define TTL_7400_DIP(_name) \
NET_REGISTER_DEV(TTL_7400_DIP, _name)
#define TTL_7404_GATE(_name) \
NET_REGISTER_DEV(TTL_7404_GATE, _name)
#define TTL_7404_INVERT(_name, _A) \
NET_REGISTER_DEV(TTL_7404_INVERT, _name) \
NET_CONNECT(_name, A, _A)
#define TTL_7404_DIP(_name) \
NET_REGISTER_DEV(TTL_7404_DIP, _name)
#define TTL_7416_GATE(_name) \
NET_REGISTER_DEV(TTL_7416_GATE, _name)