mirror of
https://github.com/holub/mame
synced 2025-06-06 21:03:47 +03:00
improved 8bit timers
This commit is contained in:
Michaël Banaan Ananas
parent
b1592d4f2d
commit
6fa4137852
@ -85,7 +85,8 @@ bool mn10200_device::check_irq()
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take_irq(0, 0);
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else if (group)
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take_irq(level, group);
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else return false;
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else
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return false;
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return true;
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}
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@ -105,65 +106,58 @@ void mn10200_device::check_ext_irq()
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void mn10200_device::refresh_timer(int tmr)
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{
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// enabled?
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if (m_simple_timer[tmr].mode & 0x80)
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{
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UINT8 source = (m_simple_timer[tmr].mode & 3);
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// 0: external pin
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// 1: cascaded (handled elsewhere)
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// 2: prescaler 0
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// 3: prescaler 1
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int p = m_simple_timer[tmr].mode & 1;
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// source is a prescaler?
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if (source >= 2)
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// enabled, and source is prescaler?
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if ((m_simple_timer[tmr].mode & 0x82) == 0x82 && m_simple_timer[tmr].cur != 0 && m_prescaler[p].mode & 0x80)
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{
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INT32 rate;
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// is prescaler enabled?
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if (m_prescaler[source-2].mode & 0x80)
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{
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// rate = (sysclock / prescaler) / our count
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rate = unscaled_clock() / m_prescaler[source-2].cycles;
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rate /= m_simple_timer[tmr].base;
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if (tmr != 8) // HACK: timer 8 is run at 500 kHz by the Taito program for no obvious reason, which kills performance
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m_timer_timers[tmr]->adjust(attotime::from_hz(rate), tmr);
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attotime period = m_sysclock_base * (m_prescaler[p].base + 1) * (m_simple_timer[tmr].cur + 1);
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m_timer_timers[tmr]->adjust(period, tmr);
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}
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else
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{
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logerror("MN10200: timer %d using prescaler %d which isn't enabled!\n", tmr, source-2);
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}
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}
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}
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else // disabled, so stop it
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{
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m_timer_timers[tmr]->adjust(attotime::never, tmr);
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}
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}
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void mn10200_device::timer_tick_simple(int tmr)
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void mn10200_device::refresh_all_timers()
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{
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m_simple_timer[tmr].cur--;
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for (int tmr = 0; tmr < MN10200_NUM_TIMERS_8BIT; tmr++)
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refresh_timer(tmr);
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}
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// did we expire?
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if (m_simple_timer[tmr].cur == 0)
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int mn10200_device::timer_tick_simple(int tmr)
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{
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int next = tmr + 1;
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// is it a cascaded timer, and enabled?
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if (next < MN10200_NUM_TIMERS_8BIT && m_simple_timer[next].mode & 0x83 && (m_simple_timer[next].mode & 0x83) == 0x81)
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{
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// does timer auto-reload? apparently.
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// did it underflow?
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if (--m_simple_timer[next].cur == 0xff)
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{
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// cascaded underflow?
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if (timer_tick_simple(next) != 2)
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{
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m_simple_timer[next].cur = m_simple_timer[next].base;
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return 1;
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}
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}
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return 2;
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}
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else
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{
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// reload and trigger irq
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m_simple_timer[tmr].cur = m_simple_timer[tmr].base;
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// signal the cascade if we're not timer 9
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if (tmr < (MN10200_NUM_TIMERS_8BIT-1))
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{
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// is next timer enabled?
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if (m_simple_timer[tmr+1].mode & 0x80)
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{
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// is it's source "cascade"?
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if ((m_simple_timer[tmr+1].mode & 0x3) == 1)
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{
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// recurse!
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timer_tick_simple(tmr+1);
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}
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}
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}
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m_icrl[1 + (tmr / 4)] |= (1 << (4 + (tmr % 4)));
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m_icrl[1 + (tmr >> 2)] |= (1 << (4 + (tmr & 3)));
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check_irq();
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return 0;
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}
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}
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@ -172,8 +166,22 @@ TIMER_CALLBACK_MEMBER( mn10200_device::simple_timer_cb )
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int tmr = param;
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// handle our expiring and also tick our cascaded children
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m_simple_timer[tmr].cur = 1;
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timer_tick_simple(tmr);
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switch (timer_tick_simple(tmr))
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{
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// cascaded, underflow
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case 1:
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m_simple_timer[tmr].cur = m_simple_timer[tmr].base;
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break;
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// cascaded, no underflow
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case 2:
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m_simple_timer[tmr].cur = 0xff;
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break;
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// no action needed
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default:
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break;
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}
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// refresh this timer
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refresh_timer(tmr);
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@ -186,6 +194,8 @@ void mn10200_device::device_start()
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m_program = &space(AS_PROGRAM);
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m_io = &space(AS_IO);
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m_sysclock_base = attotime::from_hz(unscaled_clock() / 2);
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for (int tmr = 0; tmr < MN10200_NUM_TIMERS_8BIT; tmr++)
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{
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m_timer_timers[tmr] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(mn10200_device::simple_timer_cb), this));
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@ -210,11 +220,13 @@ void mn10200_device::device_start()
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}
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for (int i = 0; i < MN10200_NUM_PRESCALERS; i++)
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{
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m_prescaler[i].cycles = 0;
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m_prescaler[i].mode = 0;
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m_prescaler[i].base = 0;
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m_prescaler[i].cur = 0;
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save_item(NAME(m_prescaler[i].cycles), i);
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save_item(NAME(m_prescaler[i].mode), i);
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save_item(NAME(m_prescaler[i].base), i);
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save_item(NAME(m_prescaler[i].cur), i);
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}
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for (int i = 0; i < 8; i++)
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{
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@ -324,15 +336,6 @@ void mn10200_device::device_reset()
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for (int i = 0; i < 2; i++)
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for (int address = 0xfc04; address < 0x10000; address++)
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write_mem16(address, 0);
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// reset all timers
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for (int tmr = 0; tmr < MN10200_NUM_TIMERS_8BIT; tmr++)
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{
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m_simple_timer[tmr].mode = 0;
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m_simple_timer[tmr].cur = 0;
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m_simple_timer[tmr].base = 0;
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m_timer_timers[tmr]->adjust(attotime::never, tmr);
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}
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}
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@ -1640,6 +1643,7 @@ WRITE8_MEMBER(mn10200_device::io_control_w)
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case 0x036: case 0x037: // Memory mode reg 3
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break;
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// 0xfc40-0xfc57: irq control
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// group 0, NMI control
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case 0x040:
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m_nmicr &= data; // nmi ack
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@ -1651,7 +1655,10 @@ WRITE8_MEMBER(mn10200_device::io_control_w)
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case 0x042: case 0x044: case 0x046: case 0x048: case 0x04a:
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case 0x04c: case 0x04e: case 0x050: case 0x052: case 0x054:
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m_icrl[(offset & 0x3f) >> 1] &= data; // irq ack
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if (offset == 0x050) check_ext_irq(); // group 8, external irqs might still be active
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// group 8, external irqs might still be active
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if (offset == 0x050)
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check_ext_irq();
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break;
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case 0x043: case 0x045: case 0x047: case 0x049: case 0x04b:
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@ -1666,7 +1673,7 @@ WRITE8_MEMBER(mn10200_device::io_control_w)
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check_ext_irq();
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break;
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case 0x057:
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m_extmdh = data;
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m_extmdh = data & 3;
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break;
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case 0x100: case 0x101: // DRAM control reg
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@ -1717,49 +1724,39 @@ WRITE8_MEMBER(mn10200_device::io_control_w)
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log_event("MN102", "AN chans=0-%d current=%d", (data >> 4) & 7, data & 7);
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break;
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// 0xfe00-0xfe2f: 8-bit timers
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// timer base
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case 0x210: case 0x211: case 0x212: case 0x213: case 0x214:
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case 0x215: case 0x216: case 0x217: case 0x218: case 0x219:
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m_simple_timer[offset-0x210].base = data + 1;
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// printf("MN10200: Timer %d value set %02x\n", offset-0x210, data);
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refresh_timer(offset-0x210);
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m_simple_timer[offset & 0xf].base = data;
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break;
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case 0x21a:
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m_prescaler[0].cycles = data+1;
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// printf("MN10200: Prescale 0 cycle count %d\n", data+1);
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break;
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case 0x21b:
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m_prescaler[1].cycles = data+1;
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// printf("MN10200: Prescale 1 cycle count %d\n", data+1);
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// prescaler base
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case 0x21a: case 0x21b:
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m_prescaler[offset & 1].base = data;
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break;
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// timer mode
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case 0x220: case 0x221: case 0x222: case 0x223: case 0x224:
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case 0x225: case 0x226: case 0x227: case 0x228: case 0x229:
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{
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// const char *source[4] = { "TMxIO", "cascade", "prescale 0", "prescale 1" };
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m_simple_timer[offset-0x220].mode = data;
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// printf("MN10200: Timer %d %s b6=%d, source=%s\n", offset-0x220, data & 0x80 ? "on" : "off", (data & 0x40) != 0, source[data & 3]);
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m_simple_timer[offset & 0xf].mode = data & 0xc3;
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// reload
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if (data & 0x40)
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{
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// printf("MN10200: loading timer %d\n", offset-0x220);
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m_simple_timer[offset-0x220].cur = m_simple_timer[offset-0x220].base;
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}
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refresh_timer(offset-0x220);
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break;
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}
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m_simple_timer[offset & 0xf].cur = m_simple_timer[offset & 0xf].base;
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case 0x22a:
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// printf("MN10200: Prescale 0 %s, ps0bc %s\n",
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// data & 0x80 ? "on" : "off", data & 0x40 ? "-> ps0br" : "off");
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m_prescaler[0].mode = data;
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refresh_timer(offset & 0xf);
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break;
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case 0x22b:
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// printf("MN10200: Prescale 1 %s, ps1bc %s\n",
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// data & 0x80 ? "on" : "off", data & 0x40 ? "-> ps1br" : "off");
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m_prescaler[1].mode = data;
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// prescaler mode
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case 0x22a: case 0x22b:
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m_prescaler[offset & 1].mode = data & 0xc0;
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// reload
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if (data & 0x40)
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m_prescaler[offset & 1].cur = m_prescaler[offset & 1].base;
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refresh_all_timers();
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break;
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case 0x230: case 0x240: case 0x250:
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@ -2044,11 +2041,13 @@ READ8_MEMBER(mn10200_device::io_control_r)
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{
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switch(offset)
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{
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// active irq group
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case 0x00e:
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return m_iagr << 1;
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case 0x00f:
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return 0;
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// 0xfc40-0xfc57: irq control
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// group 0, NMI control
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case 0x040:
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return m_nmicr;
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@ -2069,7 +2068,7 @@ READ8_MEMBER(mn10200_device::io_control_r)
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case 0x056:
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return m_extmdl;
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case 0x057:
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return (m_extmdh & 3) | (m_p4 << 4);
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return m_extmdh | (m_p4 << 4);
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case 0x180: case 0x190:
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return m_serial[(offset-0x180) >> 4].ctrll;
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@ -2086,10 +2085,33 @@ READ8_MEMBER(mn10200_device::io_control_r)
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case 0x183:
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return 0x10;
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// 0xfe00-0xfe2f: 8-bit timers
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// timer counter (not accurate)
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case 0x200: case 0x201: case 0x202: case 0x203: case 0x204:
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case 0x205: case 0x206: case 0x207: case 0x208: case 0x209:
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// printf("MN10200: timer %d value read = %d\n", offset-0x200, m_simple_timer[offset-0x200].cur);
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return m_simple_timer[offset-0x200].cur;
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return m_simple_timer[offset & 0xf].cur;
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// prescaler counter (not accurate)
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case 0x20a: case 0x20b:
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return m_prescaler[offset & 1].cur;
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// timer base
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case 0x210: case 0x211: case 0x212: case 0x213: case 0x214:
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case 0x215: case 0x216: case 0x217: case 0x218: case 0x219:
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return m_simple_timer[offset & 0xf].base;
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// prescaler base
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case 0x21a: case 0x21b:
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return m_prescaler[offset & 1].base;
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// timer mode
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case 0x220: case 0x221: case 0x222: case 0x223: case 0x224:
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case 0x225: case 0x226: case 0x227: case 0x228: case 0x229:
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return m_simple_timer[offset & 0xf].mode;
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// prescaler mode
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case 0x22a: case 0x22b:
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return m_prescaler[offset & 1].mode;
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case 0x264: // port 1 data
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return m_io->read_byte(MN10200_PORT1);
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@ -71,8 +71,10 @@ protected:
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virtual void device_reset();
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// device_execute_interface overrides
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virtual UINT64 execute_clocks_to_cycles(UINT64 clocks) const { return (clocks + 2 - 1) / 2; }
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virtual UINT64 execute_cycles_to_clocks(UINT64 cycles) const { return (cycles * 2); }
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virtual UINT32 execute_min_cycles() const { return 1; }
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virtual UINT32 execute_max_cycles() const { return 8; }
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virtual UINT32 execute_max_cycles() const { return 13; }
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virtual UINT32 execute_input_lines() const { return 4; }
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virtual void execute_run();
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virtual void execute_set_input(int inputnum, int state);
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@ -119,8 +121,9 @@ private:
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emu_timer *m_timer_timers[MN10200_NUM_TIMERS_8BIT];
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struct {
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UINT8 cycles;
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UINT8 mode;
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UINT8 base;
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UINT8 cur;
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} m_prescaler[MN10200_NUM_PRESCALERS];
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struct {
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@ -140,6 +143,7 @@ private:
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UINT8 m_ddr[8];
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attotime m_sysclock_base;
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int m_cycles;
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address_space *m_program;
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@ -164,7 +168,8 @@ private:
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bool check_irq();
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void check_ext_irq();
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void refresh_timer(int tmr);
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void timer_tick_simple(int tmr);
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void refresh_all_timers();
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int timer_tick_simple(int tmr);
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TIMER_CALLBACK_MEMBER( simple_timer_cb );
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void illegal(UINT8 prefix, UINT8 op);
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UINT32 do_add(UINT32 a, UINT32 b, UINT32 c);
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