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some more cleanup (nw)

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This commit is contained in:
Miodrag Milanovic 2014-03-24 20:32:58 +00:00
parent 4ad1411f54
commit 6fb0c0d694
25 changed files with 173 additions and 206 deletions
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24
src/mame/drivers/gstriker.c
View File

@ -868,8 +868,8 @@ the zooming.To use it,you should use Player 2 Start button to show the test scre
or to advance into the tests.
******************************************************************************************/
#define PC(_num_)\
state->m_work_ram[0x000/2] = (_num_ & 0xffff0000) >> 16;\
state->m_work_ram[0x002/2] = (_num_ & 0x0000ffff) >> 0;
m_work_ram[0x000/2] = (_num_ & 0xffff0000) >> 16;\
m_work_ram[0x002/2] = (_num_ & 0x0000ffff) >> 0;
WRITE16_MEMBER(gstriker_state::twrldc94_mcu_w)
@ -884,7 +884,6 @@ READ16_MEMBER(gstriker_state::twrldc94_mcu_r)
WRITE16_MEMBER(gstriker_state::twrldc94_prot_reg_w)
{
gstriker_state *state = machine().driver_data<gstriker_state>();
m_prot_reg[1] = m_prot_reg[0];
m_prot_reg[0] = data;
@ -1015,15 +1014,15 @@ READ16_MEMBER(gstriker_state::twrldc94_prot_reg_r)
The tick count is usually set to 0x3c => it's driven off vblank?
*/
//state->m_work_ram[ (0xffe900 - 0xffc00) ]
#define COUNTER1_ENABLE state->m_work_ram[0x2900/2] >> 8
#define COUNTER2_ENABLE (state->m_work_ram[0x2900/2] & 0xff)
#define TICK_1 state->m_work_ram[0x2908/2]
#define TICKCOUNT_1 state->m_work_ram[0x290a/2]
#define TICK_2 state->m_work_ram[0x290c/2]
#define TICKCOUNT_3 state->m_work_ram[0x290e/2]
#define COUNTER_1 state->m_work_ram[0x2928/2]
#define COUNTER_2 state->m_work_ram[0x292a/2]
//m_work_ram[ (0xffe900 - 0xffc00) ]
#define COUNTER1_ENABLE m_work_ram[0x2900/2] >> 8
#define COUNTER2_ENABLE (m_work_ram[0x2900/2] & 0xff)
#define TICK_1 m_work_ram[0x2908/2]
#define TICKCOUNT_1 m_work_ram[0x290a/2]
#define TICK_2 m_work_ram[0x290c/2]
#define TICKCOUNT_3 m_work_ram[0x290e/2]
#define COUNTER_1 m_work_ram[0x2928/2]
#define COUNTER_2 m_work_ram[0x292a/2]
READ16_MEMBER(gstriker_state::vbl_toggle_r)
{
return 0xff;
@ -1031,7 +1030,6 @@ READ16_MEMBER(gstriker_state::vbl_toggle_r)
WRITE16_MEMBER(gstriker_state::vbl_toggle_w)
{
gstriker_state *state = machine().driver_data<gstriker_state>();
if( COUNTER1_ENABLE == 1 )
{
TICK_1 = (TICK_1 - 1) & 0xff; // 8bit

3
src/mame/drivers/hcastle.c
View File

@ -154,8 +154,7 @@ GFXDECODE_END
WRITE_LINE_MEMBER(hcastle_state::irqhandler)
{
// hcastle_state *state = device->machine().driver_data<hcastle_state>();
// state->m_audiocpu->set_input_line(linestate);
// m_audiocpu->set_input_line(state);
}
WRITE8_MEMBER(hcastle_state::volume_callback)

11
src/mame/drivers/m107.c
View File

@ -33,9 +33,9 @@ confirmed for m107 games as well.
#include "sound/iremga20.h"
#define M107_IRQ_0 ((state->m_irq_vectorbase+0)/4) /* VBL interrupt */
#define M107_IRQ_1 ((state->m_irq_vectorbase+4)/4) /* ??? */
#define M107_IRQ_2 ((state->m_irq_vectorbase+8)/4) /* Raster interrupt */
#define M107_IRQ_0 ((m_irq_vectorbase+0)/4) /* VBL interrupt */
#define M107_IRQ_1 ((m_irq_vectorbase+4)/4) /* ??? */
#define M107_IRQ_2 ((m_irq_vectorbase+8)/4) /* Raster interrupt */
#define M107_IRQ_3 ((m_irq_vectorbase+12)/4) /* Sound cpu interrupt */
@ -51,20 +51,19 @@ void m107_state::machine_start()
TIMER_DEVICE_CALLBACK_MEMBER(m107_state::m107_scanline_interrupt)
{
int scanline = param;
m107_state *state = machine().driver_data<m107_state>();
/* raster interrupt */
if (scanline == m_raster_irq_position)
{
m_screen->update_partial(scanline);
state->m_maincpu->set_input_line_and_vector(0, HOLD_LINE, M107_IRQ_2);
m_maincpu->set_input_line_and_vector(0, HOLD_LINE, M107_IRQ_2);
}
/* VBLANK interrupt */
else if (scanline == m_screen->visible_area().max_y + 1)
{
m_screen->update_partial(scanline);
state->m_maincpu->set_input_line_and_vector(0, HOLD_LINE, M107_IRQ_0);
m_maincpu->set_input_line_and_vector(0, HOLD_LINE, M107_IRQ_0);
}
}

13
src/mame/drivers/magicard.c
View File

@ -286,7 +286,7 @@ TODO: check this register,doesn't seem to be 100% correct.
w ........ ....aaaa VSR:H = video start address (MSB's)
*/
#define SCC_DCR_VREG (state->m_pcab_vregs[0x02/2] & 0xffff)
#define SCC_DCR_VREG (m_pcab_vregs[0x02/2] & 0xffff)
#define SCC_DE_VREG ((SCC_DCR_VREG & 0x8000)>>15)
#define SCC_FG_VREG ((SCC_DCR_VREG & 0x0080)>>7)
#define SCC_VSR_VREG_H ((SCC_DCR_VREG & 0xf)>>0)
@ -296,7 +296,7 @@ TODO: check this register,doesn't seem to be 100% correct.
w aaaaaaaa aaaaaaaa VSR:L = video start address (LSB's)
*/
#define SCC_VSR_VREG_L (state->m_pcab_vregs[0x04/2] & 0xffff)
#define SCC_VSR_VREG_L (m_pcab_vregs[0x04/2] & 0xffff)
#define SCC_VSR_VREG ((SCC_VSR_VREG_H)<<16) | (SCC_VSR_VREG_L)
/*
@ -315,7 +315,7 @@ TODO: check this register,doesn't seem to be 100% correct.
w ........ xxxx.... not used
w ........ ....aaaa "data" (dunno the purpose...)
*/
#define SCC_DCR2_VREG (state->m_pcab_vregs[0x08/2] & 0xffff)
#define SCC_DCR2_VREG (m_pcab_vregs[0x08/2] & 0xffff)
/*
(Note: not present on the original vreg listing)
@ -336,14 +336,14 @@ TODO: check this register,doesn't seem to be 100% correct.
1ffff0 a = source register a
w nnnnnnnn nnnnnnnn source
*/
#define SCC_SRCA_VREG (state->m_pcab_vregs[0x10/2] & 0xffff)
#define SCC_SRCA_VREG (m_pcab_vregs[0x10/2] & 0xffff)
/*
1ffff2 b = destination register b
rw nnnnnnnn nnnnnnnn destination
*/
#define SCC_DSTB_VREG (state->m_pcab_vregs[0x12/2] & 0xffff)
#define SCC_DSTB_VREG (m_pcab_vregs[0x12/2] & 0xffff)
/*
1ffff4 pcr = pixac command register
@ -390,7 +390,7 @@ TODO: check this register,doesn't seem to be 100% correct.
w ........ .......0
*/
#define SCC_PCR_VREG (state->m_pcab_vregs[0x14/2] & 0xffff)
#define SCC_PCR_VREG (m_pcab_vregs[0x14/2] & 0xffff)
/*
1ffff6 mask = mask register
@ -422,7 +422,6 @@ void magicard_state::video_start()
UINT32 magicard_state::screen_update_magicard(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
{
magicard_state *state = machine().driver_data<magicard_state>();
int x,y;
UINT32 count;

29
src/mame/drivers/mpu3.c
View File

@ -201,9 +201,9 @@ emu_timer *m_ic21_timer;
TIMER_DEVICE_CALLBACK_MEMBER(ic10_callback);
void update_triacs();
void mpu3_stepper_reset();
void ic11_update(mpu3_state *state);
void ic21_output(mpu3_state *state,int data);
void ic21_setup(mpu3_state *state);
void ic11_update();
void ic21_output(int data);
void ic21_setup();
void mpu3_config_common();
required_device<cpu_device> m_maincpu;
};
@ -308,7 +308,7 @@ IC23 is a 74LS138 1-of-8 Decoder
It is used as a multiplexer for the LEDs, lamp selects and inputs.*/
void mpu3_state::ic11_update(mpu3_state *state)
void mpu3_state::ic11_update()
{
if (!m_IC11G2A)
{
@ -354,19 +354,19 @@ t/ns = .34 * 47 * 2.2e6 [ 1+ (1/47)]
This seems less stable than the revised version used in MPU4
*/
void mpu3_state::ic21_output(mpu3_state *state,int data)
void mpu3_state::ic21_output(int data)
{
m_IC11G1 = data;
ic11_update(state);
ic11_update();
}
void mpu3_state::ic21_setup(mpu3_state *state)
void mpu3_state::ic21_setup()
{
if (m_IC11GA)
{
{
m_ic11_active=1;
ic21_output(state,1);
ic21_output(1);
m_ic21_timer->adjust(attotime::from_nsec( (0.34 * 47 * 2200000) *(1+(1/47))));
}
}
@ -375,7 +375,7 @@ void mpu3_state::ic21_setup(mpu3_state *state)
TIMER_CALLBACK_MEMBER(mpu3_state::ic21_timeout)
{
m_ic11_active=0;
ic21_output(this,0);
ic21_output(0);
}
READ8_MEMBER(mpu3_state::pia_ic3_porta_r)
@ -430,11 +430,10 @@ WRITE8_MEMBER(mpu3_state::pia_ic3_portb_w)
WRITE_LINE_MEMBER(mpu3_state::pia_ic3_ca2_w)
{
mpu3_state *mstate = machine().driver_data<mpu3_state>();
LOG(("%s: IC3 PIA Port CA2 Set to %2x (input A)\n", machine().describe_context(),state));
m_IC11GA = state;
ic21_setup(mstate);
ic11_update(mstate);
ic21_setup();
ic11_update();
}
READ8_MEMBER(mpu3_state::pia_ic4_porta_r)
@ -508,10 +507,9 @@ WRITE8_MEMBER(mpu3_state::pia_ic4_portb_w)
WRITE_LINE_MEMBER(mpu3_state::pia_ic4_ca2_w)
{
mpu3_state *mstate = machine().driver_data<mpu3_state>();
LOG(("%s: IC4 PIA Port CA2 Set to %2x (Input B)\n", machine().describe_context(),state));
m_IC11GB = state;
ic11_update(mstate);
ic11_update();
}
WRITE_LINE_MEMBER(mpu3_state::pia_ic4_cb2_w)
@ -570,10 +568,9 @@ WRITE8_MEMBER(mpu3_state::pia_ic5_portb_w)
WRITE_LINE_MEMBER(mpu3_state::pia_ic5_ca2_w)
{
mpu3_state *mstate = machine().driver_data<mpu3_state>();
LOG(("%s: IC5 PIA Port CA2 Set to %2x (C)\n", machine().describe_context(),state));
m_IC11GC = state;
ic11_update(mstate);
ic11_update();
}
WRITE_LINE_MEMBER(mpu3_state::pia_ic5_cb2_w)

5
src/mame/drivers/mpu4mod2sw.c
View File

@ -47,9 +47,8 @@ DRIVER_INIT_MEMBER( mpu4_state, m4_showstring_mod2 )
DRIVER_INIT_MEMBER (mpu4_state, connect4)
{
mpu4_state *state = machine().driver_data<mpu4_state>();
state->m_reels = 0; //reel-free game
state->m_led_lamp=1;
m_reels = 0; //reel-free game
m_led_lamp=1;
DRIVER_INIT_CALL( m4default_banks );
}

3
src/mame/drivers/nemesis.c
View File

@ -1489,8 +1489,7 @@ static const ay8910_interface ay8910_interface_2 =
WRITE_LINE_MEMBER(nemesis_state::sound_irq)
{
/* Interrupts _are_ generated, I wonder where they go.. */
// nemesis_state *driver_state = device->machine().driver_data<nemesis_state>();
// driver_state->audiocpu->set_input_line(0, HOLD_LINE);
// m_audiocpu->set_input_line(0, HOLD_LINE);
}
WRITE8_MEMBER(nemesis_state::volume_callback)

14
src/mame/drivers/sothello.c
View File

@ -79,6 +79,7 @@ public:
DECLARE_WRITE_LINE_MEMBER(irqhandler);
DECLARE_WRITE_LINE_MEMBER(adpcm_int);
DECLARE_WRITE_LINE_MEMBER(sothello_vdp_interrupt);
void unlock_shared_ram();
required_device<cpu_device> m_maincpu;
required_device<cpu_device> m_soundcpu;
required_device<cpu_device> m_subcpu;
@ -222,27 +223,26 @@ ADDRESS_MAP_END
/* sub 6809 */
static void unlock_shared_ram(address_space &space)
void sothello_state::unlock_shared_ram()
{
sothello_state *state = space.machine().driver_data<sothello_state>();
if(!state->m_subcpu->suspended(SUSPEND_REASON_HALT))
if(!m_subcpu->suspended(SUSPEND_REASON_HALT))
{
state->m_subcpu_status|=1;
m_subcpu_status|=1;
}
else
{
logerror("Sub cpu active! @%x\n",space.device().safe_pc());
//logerror("Sub cpu active! @%x\n",device().safe_pc());
}
}
WRITE8_MEMBER(sothello_state::subcpu_status_w)
{
unlock_shared_ram(space);
unlock_shared_ram();
}
READ8_MEMBER(sothello_state::subcpu_status_r)
{
unlock_shared_ram(space);
unlock_shared_ram();
return 0;
}

4
src/mame/drivers/tetrisp2.c
View File

@ -560,9 +560,7 @@ READ16_MEMBER(stepstag_state::unk_a42000_r)
WRITE16_MEMBER(stepstag_state::stepstag_soundlatch_word_w)
{
stepstag_state *state = machine().driver_data<stepstag_state>();
state->soundlatch_word_w(space, offset, data, mem_mask);
soundlatch_word_w(space, offset, data, mem_mask);
m_subcpu->set_input_line(M68K_IRQ_6, HOLD_LINE);

13
src/mame/drivers/williams.c
View File

@ -521,21 +521,20 @@ ADDRESS_MAP_END
void williams_state::defender_install_io_space(address_space &space)
{
williams_state *state = space.machine().driver_data<williams_state>();
pia6821_device *pia_0 = space.machine().device<pia6821_device>("pia_0");
pia6821_device *pia_1 = space.machine().device<pia6821_device>("pia_1");
/* this routine dynamically installs the memory mapped above from c000-cfff */
space.install_write_bank (0xc000, 0xc00f, 0, 0x03e0, "bank4");
space.install_write_handler (0xc010, 0xc01f, 0, 0x03e0, write8_delegate(FUNC(williams_state::defender_video_control_w),state));
space.install_write_handler (0xc3ff, 0xc3ff, write8_delegate(FUNC(williams_state::williams_watchdog_reset_w),state));
space.install_write_handler (0xc010, 0xc01f, 0, 0x03e0, write8_delegate(FUNC(williams_state::defender_video_control_w),this));
space.install_write_handler (0xc3ff, 0xc3ff, write8_delegate(FUNC(williams_state::williams_watchdog_reset_w),this));
space.install_read_bank(0xc400, 0xc4ff, 0, 0x0300, "bank3");
space.install_write_handler(0xc400, 0xc4ff, 0, 0x0300, write8_delegate(FUNC(williams_state::williams_cmos_w),state));
space.install_read_handler (0xc800, 0xcbff, 0, 0x03e0, read8_delegate(FUNC(williams_state::williams_video_counter_r),state));
space.install_write_handler(0xc400, 0xc4ff, 0, 0x0300, write8_delegate(FUNC(williams_state::williams_cmos_w),this));
space.install_read_handler (0xc800, 0xcbff, 0, 0x03e0, read8_delegate(FUNC(williams_state::williams_video_counter_r),this));
space.install_readwrite_handler(0xcc00, 0xcc03, 0, 0x03e0, read8_delegate(FUNC(pia6821_device::read), pia_1), write8_delegate(FUNC(pia6821_device::write), pia_1));
space.install_readwrite_handler(0xcc04, 0xcc07, 0, 0x03e0, read8_delegate(FUNC(pia6821_device::read), pia_0), write8_delegate(FUNC(pia6821_device::write), pia_0));
membank("bank3")->set_base(space.machine().driver_data<williams_state>()->m_nvram);
membank("bank4")->set_base(space.machine().driver_data<williams_state>()->m_generic_paletteram_8);
membank("bank3")->set_base(m_nvram);
membank("bank4")->set_base(m_generic_paletteram_8);
}

3
src/mame/drivers/wmg.c
View File

@ -164,7 +164,6 @@ WRITE8_MEMBER( wmg_state::wmg_vram_select_w )
void wmg_state::wmg_def_install_io_space(address_space &space)
{
williams_state *state = space.machine().driver_data<williams_state>();
pia6821_device *pia_0 = space.machine().device<pia6821_device>("pia_0");
pia6821_device *pia_1 = space.machine().device<pia6821_device>("pia_1");
@ -180,7 +179,7 @@ void wmg_state::wmg_def_install_io_space(address_space &space)
space.install_write_handler (0xcbff, 0xcbff, write8_delegate(FUNC(williams_state::williams_watchdog_reset_w),this));
space.install_read_handler (0xcb00, 0xcbff, read8_delegate(FUNC(williams_state::williams_video_counter_r),this));
space.install_readwrite_handler(0xcc00, 0xcfff, read8_delegate(FUNC(wmg_state::wmg_nvram_r), this), write8_delegate(FUNC(wmg_state::wmg_nvram_w),this));
membank("bank4")->set_base(state->m_generic_paletteram_8);
membank("bank4")->set_base(m_generic_paletteram_8);
}
WRITE8_MEMBER( wmg_state::wmg_def_rombank_w )

4
src/mame/includes/spacefb.h
View File

@ -55,8 +55,8 @@ public:
virtual void video_start();
UINT32 screen_update_spacefb(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
TIMER_CALLBACK_MEMBER(interrupt_callback);
inline void shift_star_generator(spacefb_state *state);
void get_starfield_pens(spacefb_state *state, pen_t *pens);
inline void shift_star_generator();
void get_starfield_pens(pen_t *pens);
void draw_starfield(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
void get_sprite_pens(pen_t *pens);
void draw_bullet(offs_t offs, pen_t pen, bitmap_rgb32 &bitmap, const rectangle &cliprect, int flip);

5
src/mame/machine/midtunit.c
View File

@ -590,14 +590,13 @@ WRITE16_MEMBER(midtunit_state::midtunit_sound_w)
}
/* call through based on the sound type */
midtunit_state *state = space.machine().driver_data<midtunit_state>();
if (ACCESSING_BITS_0_7 && ACCESSING_BITS_8_15)
switch (chip_type)
{
case SOUND_ADPCM:
case SOUND_ADPCM_LARGE:
state->m_adpcm_sound->reset_write(~data & 0x100);
state->m_adpcm_sound->write(space, offset, data & 0xff);
m_adpcm_sound->reset_write(~data & 0x100);
m_adpcm_sound->write(space, offset, data & 0xff);
/* the games seem to check for $82 loops, so this should be just barely enough */
fake_sound_state = 128;

4
src/mame/machine/namcos2.c
View File

@ -232,7 +232,7 @@ sws93 1993 334 $014e
READ16_MEMBER( namcos2_state::namcos2_68k_key_r )
{
switch (machine().driver_data<namcos2_shared_state>()->m_gametype)
switch (m_gametype)
{
case NAMCOS2_ORDYNE:
switch(offset)
@ -406,7 +406,7 @@ READ16_MEMBER( namcos2_state::namcos2_68k_key_r )
WRITE16_MEMBER( namcos2_state::namcos2_68k_key_w )
{
int gametype = machine().driver_data<namcos2_shared_state>()->m_gametype;
int gametype = m_gametype;
if( gametype == NAMCOS2_MARVEL_LAND && offset == 5 )
{
if (data == 0x615E) sendval = 1;

6
src/mame/video/ninjaw.c
View File

@ -124,6 +124,6 @@ UINT32 ninjaw_state::update_screen(screen_device &screen, bitmap_ind16 &bitmap,
return 0;
}
UINT32 ninjaw_state::screen_update_ninjaw_left(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect){ return update_screen(screen, bitmap, cliprect, 36 * 8 * 0, machine().driver_data<ninjaw_state>()->m_tc0100scn_1); }
UINT32 ninjaw_state::screen_update_ninjaw_middle(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect){ return update_screen(screen, bitmap, cliprect, 36 * 8 * 1, machine().driver_data<ninjaw_state>()->m_tc0100scn_2); }
UINT32 ninjaw_state::screen_update_ninjaw_right(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect){ return update_screen(screen, bitmap, cliprect, 36 * 8 * 2, machine().driver_data<ninjaw_state>()->m_tc0100scn_3); }
UINT32 ninjaw_state::screen_update_ninjaw_left(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect){ return update_screen(screen, bitmap, cliprect, 36 * 8 * 0, m_tc0100scn_1); }
UINT32 ninjaw_state::screen_update_ninjaw_middle(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect){ return update_screen(screen, bitmap, cliprect, 36 * 8 * 1, m_tc0100scn_2); }
UINT32 ninjaw_state::screen_update_ninjaw_right(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect){ return update_screen(screen, bitmap, cliprect, 36 * 8 * 2, m_tc0100scn_3); }

13
src/mame/video/spacefb.c
View File

@ -99,13 +99,13 @@ void spacefb_state::video_start()
#define NUM_STARFIELD_PENS (0x40)
inline void spacefb_state::shift_star_generator(spacefb_state *state)
inline void spacefb_state::shift_star_generator()
{
m_star_shift_reg = ((m_star_shift_reg << 1) | (((~m_star_shift_reg >> 16) & 0x01) ^ ((m_star_shift_reg >> 4) & 0x01))) & 0x1ffff;
}
void spacefb_state::get_starfield_pens(spacefb_state *state, pen_t *pens)
void spacefb_state::get_starfield_pens(pen_t *pens)
{
/* generate the pens based on the various enable bits */
int i;
@ -137,11 +137,10 @@ void spacefb_state::get_starfield_pens(spacefb_state *state, pen_t *pens)
void spacefb_state::draw_starfield(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
{
spacefb_state *state = screen.machine().driver_data<spacefb_state>();
int y;
pen_t pens[NUM_STARFIELD_PENS];
get_starfield_pens(state, pens);
get_starfield_pens(pens);
/* the shift register is always shifting -- do the portion in the top VBLANK */
if (cliprect.min_y == screen.visible_area().min_y)
@ -152,7 +151,7 @@ void spacefb_state::draw_starfield(screen_device &screen, bitmap_rgb32 &bitmap,
int clock_count = (SPACEFB_HBSTART - SPACEFB_HBEND) * SPACEFB_VBEND - 1;
for (i = 0; i < clock_count; i++)
shift_star_generator(state);
shift_star_generator();
}
/* visible region of the screen */
@ -174,7 +173,7 @@ void spacefb_state::draw_starfield(screen_device &screen, bitmap_rgb32 &bitmap,
bitmap.pix32(y, x) = pens[0];
}
shift_star_generator(state);
shift_star_generator();
}
}
@ -185,7 +184,7 @@ void spacefb_state::draw_starfield(screen_device &screen, bitmap_rgb32 &bitmap,
int clock_count = (SPACEFB_HBSTART - SPACEFB_HBEND) * (SPACEFB_VTOTAL - SPACEFB_VBSTART);
for (i = 0; i < clock_count; i++)
shift_star_generator(state);
shift_star_generator();
}
}

4
src/mame/video/warriorb.c
View File

@ -112,5 +112,5 @@ UINT32 warriorb_state::update_screen(screen_device &screen, bitmap_ind16 &bitmap
return 0;
}
UINT32 warriorb_state::screen_update_warriorb_left(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect){ return update_screen(screen, bitmap, cliprect, 40 * 8 * 0, machine().driver_data<warriorb_state>()->m_tc0100scn_1); }
UINT32 warriorb_state::screen_update_warriorb_right(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect){ return update_screen(screen, bitmap, cliprect, 40 * 8 * 1, machine().driver_data<warriorb_state>()->m_tc0100scn_2); }
UINT32 warriorb_state::screen_update_warriorb_left(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect){ return update_screen(screen, bitmap, cliprect, 40 * 8 * 0, m_tc0100scn_1); }
UINT32 warriorb_state::screen_update_warriorb_right(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect){ return update_screen(screen, bitmap, cliprect, 40 * 8 * 1, m_tc0100scn_2); }

5
src/mess/drivers/b16.c
View File

@ -83,7 +83,6 @@ void b16_state::video_start()
UINT32 b16_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
{
b16_state *state = machine().driver_data<b16_state>();
int x,y;
int xi,yi;
UINT8 *gfx_rom = memregion("pcg")->base();
@ -92,8 +91,8 @@ UINT32 b16_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, con
{
for(x=0;x<mc6845_h_display;x++)
{
int tile = state->m_vram[x+y*mc6845_h_display] & 0xff;
int color = (state->m_vram[x+y*mc6845_h_display] & 0x700) >> 8;
int tile = m_vram[x+y*mc6845_h_display] & 0xff;
int color = (m_vram[x+y*mc6845_h_display] & 0x700) >> 8;
int pen;
for(yi=0;yi<mc6845_tile_height;yi++)

29
src/mess/drivers/fm7.c
View File

@ -1000,7 +1000,6 @@ READ8_MEMBER(fm7_state::fm7_mmr_r)
void fm7_state::fm7_update_bank(address_space & space, int bank, UINT8 physical)
{
fm7_state *state = space.machine().driver_data<fm7_state>();
UINT8* RAM = memregion("maincpu")->base();
UINT16 size = 0xfff;
char bank_name[10];
@ -1015,40 +1014,40 @@ void fm7_state::fm7_update_bank(address_space & space, int bank, UINT8 physical)
switch(physical)
{
case 0x10:
space.install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram0_r),state),write8_delegate(FUNC(fm7_state::fm7_vram0_w),state));
space.install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram0_r),this),write8_delegate(FUNC(fm7_state::fm7_vram0_w),this));
break;
case 0x11:
space.install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram1_r),state),write8_delegate(FUNC(fm7_state::fm7_vram1_w),state));
space.install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram1_r),this),write8_delegate(FUNC(fm7_state::fm7_vram1_w),this));
break;
case 0x12:
space.install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram2_r),state),write8_delegate(FUNC(fm7_state::fm7_vram2_w),state));
space.install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram2_r),this),write8_delegate(FUNC(fm7_state::fm7_vram2_w),this));
break;
case 0x13:
space.install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram3_r),state),write8_delegate(FUNC(fm7_state::fm7_vram3_w),state));
space.install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram3_r),this),write8_delegate(FUNC(fm7_state::fm7_vram3_w),this));
break;
case 0x14:
space.install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram4_r),state),write8_delegate(FUNC(fm7_state::fm7_vram4_w),state));
space.install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram4_r),this),write8_delegate(FUNC(fm7_state::fm7_vram4_w),this));
break;
case 0x15:
space.install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram5_r),state),write8_delegate(FUNC(fm7_state::fm7_vram5_w),state));
space.install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram5_r),this),write8_delegate(FUNC(fm7_state::fm7_vram5_w),this));
break;
case 0x16:
space.install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram6_r),state),write8_delegate(FUNC(fm7_state::fm7_vram6_w),state));
space.install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram6_r),this),write8_delegate(FUNC(fm7_state::fm7_vram6_w),this));
break;
case 0x17:
space.install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram7_r),state),write8_delegate(FUNC(fm7_state::fm7_vram7_w),state));
space.install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram7_r),this),write8_delegate(FUNC(fm7_state::fm7_vram7_w),this));
break;
case 0x18:
space.install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram8_r),state),write8_delegate(FUNC(fm7_state::fm7_vram8_w),state));
space.install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram8_r),this),write8_delegate(FUNC(fm7_state::fm7_vram8_w),this));
break;
case 0x19:
space.install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram9_r),state),write8_delegate(FUNC(fm7_state::fm7_vram9_w),state));
space.install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram9_r),this),write8_delegate(FUNC(fm7_state::fm7_vram9_w),this));
break;
case 0x1a:
space.install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vramA_r),state),write8_delegate(FUNC(fm7_state::fm7_vramA_w),state));
space.install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vramA_r),this),write8_delegate(FUNC(fm7_state::fm7_vramA_w),this));
break;
case 0x1b:
space.install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vramB_r),state),write8_delegate(FUNC(fm7_state::fm7_vramB_w),state));
space.install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vramB_r),this),write8_delegate(FUNC(fm7_state::fm7_vramB_w),this));
break;
}
// membank(bank+1)->set_base(RAM+(physical<<12)-0x10000);
@ -1056,12 +1055,12 @@ void fm7_state::fm7_update_bank(address_space & space, int bank, UINT8 physical)
}
if(physical == 0x1c)
{
space.install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_console_ram_banked_r),state),write8_delegate(FUNC(fm7_state::fm7_console_ram_banked_w),state));
space.install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_console_ram_banked_r),this),write8_delegate(FUNC(fm7_state::fm7_console_ram_banked_w),this));
return;
}
if(physical == 0x1d)
{
space.install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_sub_ram_ports_banked_r),state),write8_delegate(FUNC(fm7_state::fm7_sub_ram_ports_banked_w),state));
space.install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_sub_ram_ports_banked_r),this),write8_delegate(FUNC(fm7_state::fm7_sub_ram_ports_banked_w),this));
return;
}
if(physical == 0x35)

49
src/mess/drivers/fmtowns.c
View File

@ -1183,51 +1183,50 @@ WRITE8_MEMBER( towns_state::towns_cmos_w )
void towns_state::towns_update_video_banks(address_space& space)
{
towns_state *state = space.machine().driver_data<towns_state>();
UINT8* ROM;
if(m_towns_mainmem_enable != 0) // first MB is RAM
{
ROM = m_user->base();
// state->membank(1)->set_base(m_messram->pointer()+0xc0000);
// state->membank(2)->set_base(m_messram->pointer()+0xc8000);
// state->membank(3)->set_base(m_messram->pointer()+0xc9000);
// state->membank(4)->set_base(m_messram->pointer()+0xca000);
// state->membank(5)->set_base(m_messram->pointer()+0xca000);
// state->membank(10)->set_base(m_messram->pointer()+0xca800);
state->membank("bank6")->set_base(m_messram->pointer()+0xcb000);
state->membank("bank7")->set_base(m_messram->pointer()+0xcb000);
// membank(1)->set_base(m_messram->pointer()+0xc0000);
// membank(2)->set_base(m_messram->pointer()+0xc8000);
// membank(3)->set_base(m_messram->pointer()+0xc9000);
// membank(4)->set_base(m_messram->pointer()+0xca000);
// membank(5)->set_base(m_messram->pointer()+0xca000);
// membank(10)->set_base(m_messram->pointer()+0xca800);
membank("bank6")->set_base(m_messram->pointer()+0xcb000);
membank("bank7")->set_base(m_messram->pointer()+0xcb000);
if(m_towns_system_port & 0x02)
state->membank("bank11")->set_base(m_messram->pointer()+0xf8000);
membank("bank11")->set_base(m_messram->pointer()+0xf8000);
else
state->membank("bank11")->set_base(ROM+0x238000);
state->membank("bank12")->set_base(m_messram->pointer()+0xf8000);
membank("bank11")->set_base(ROM+0x238000);
membank("bank12")->set_base(m_messram->pointer()+0xf8000);
return;
}
else // enable I/O ports and VRAM
{
ROM = m_user->base();
// state->membank(1)->set_base(towns_gfxvram+(towns_vram_rplane*0x8000));
// state->membank(2)->set_base(towns_txtvram);
// state->membank(3)->set_base(state->m_messram->pointer()+0xc9000);
// membank(1)->set_base(towns_gfxvram+(towns_vram_rplane*0x8000));
// membank(2)->set_base(towns_txtvram);
// membank(3)->set_base(m_messram->pointer()+0xc9000);
// if(towns_ankcg_enable != 0)
// state->membank(4)->set_base(ROM+0x180000+0x3d000); // ANK CG 8x8
// membank(4)->set_base(ROM+0x180000+0x3d000); // ANK CG 8x8
// else
// state->membank(4)->set_base(towns_txtvram+0x2000);
// state->membank(5)->set_base(towns_txtvram+0x2000);
// state->membank(10)->set_base(state->m_messram->pointer()+0xca800);
// membank(4)->set_base(towns_txtvram+0x2000);
// membank(5)->set_base(towns_txtvram+0x2000);
// membank(10)->set_base(m_messram->pointer()+0xca800);
if(m_towns_ankcg_enable != 0)
state->membank("bank6")->set_base(ROM+0x180000+0x3d800); // ANK CG 8x16
membank("bank6")->set_base(ROM+0x180000+0x3d800); // ANK CG 8x16
else
state->membank("bank6")->set_base(m_messram->pointer()+0xcb000);
state->membank("bank7")->set_base(m_messram->pointer()+0xcb000);
membank("bank6")->set_base(m_messram->pointer()+0xcb000);
membank("bank7")->set_base(m_messram->pointer()+0xcb000);
if(m_towns_system_port & 0x02)
state->membank("bank11")->set_base(m_messram->pointer()+0xf8000);
membank("bank11")->set_base(m_messram->pointer()+0xf8000);
else
state->membank("bank11")->set_base(ROM+0x238000);
state->membank("bank12")->set_base(m_messram->pointer()+0xf8000);
membank("bank11")->set_base(ROM+0x238000);
membank("bank12")->set_base(m_messram->pointer()+0xf8000);
return;
}
}

77
src/mess/drivers/m20.c
View File

@ -388,7 +388,6 @@ ADDRESS_MAP_END
void m20_state::install_memory()
{
m20_state *state = machine().driver_data<m20_state>();
m_memsize = m_ram->size();
UINT8 *memptr = m_ram->pointer();
@ -468,14 +467,14 @@ void m20_state::install_memory()
pspace.install_readwrite_bank(0xa4000, 0xa7fff, 0x3fff, 0, "dram0_c000");
dspace.install_readwrite_bank(0xa4000, 0xa7fff, 0x3fff, 0, "dram0_c000");
//state->membank("dram0_0000")->set_base(memptr);
state->membank("dram0_4000")->set_base(memptr + 0x4000);
state->membank("dram0_8000")->set_base(memptr + 0x8000);
state->membank("dram0_c000")->set_base(memptr + 0xc000);
state->membank("dram0_10000")->set_base(memptr + 0x10000);
state->membank("dram0_14000")->set_base(memptr + 0x14000);
state->membank("dram0_18000")->set_base(memptr + 0x18000);
state->membank("dram0_1c000")->set_base(memptr + 0x1c000);
//membank("dram0_0000")->set_base(memptr);
membank("dram0_4000")->set_base(memptr + 0x4000);
membank("dram0_8000")->set_base(memptr + 0x8000);
membank("dram0_c000")->set_base(memptr + 0xc000);
membank("dram0_10000")->set_base(memptr + 0x10000);
membank("dram0_14000")->set_base(memptr + 0x14000);
membank("dram0_18000")->set_base(memptr + 0x18000);
membank("dram0_1c000")->set_base(memptr + 0x1c000);
if (m_memsize > 128 * 1024) {
/* install memory expansions (DRAM1..DRAM3) */
@ -506,8 +505,8 @@ void m20_state::install_memory()
dspace.install_readwrite_bank(0x2c000, 0x2ffff, 0x3fff, 0, "dram1_0000");
dspace.install_readwrite_bank(0xa8000, 0xabfff, 0x3fff, 0, "dram1_4000");
state->membank("dram1_0000")->set_base(memptr + 0x20000);
state->membank("dram1_4000")->set_base(memptr + 0x24000);
membank("dram1_0000")->set_base(memptr + 0x20000);
membank("dram1_4000")->set_base(memptr + 0x24000);
if (m_memsize > 128 * 1024 + 32768) {
/* DRAM2, 32K */
@ -534,8 +533,8 @@ void m20_state::install_memory()
dspace.install_readwrite_bank(0x98000, 0x9bfff, 0x3fff, 0, "dram2_4000");
dspace.install_readwrite_bank(0xac000, 0xaffff, 0x3fff, 0, "dram2_0000");
state->membank("dram2_0000")->set_base(memptr + 0x28000);
state->membank("dram2_4000")->set_base(memptr + 0x2c000);
membank("dram2_0000")->set_base(memptr + 0x28000);
membank("dram2_4000")->set_base(memptr + 0x2c000);
}
if (m_memsize > 128 * 1024 + 2 * 32768) {
/* DRAM3, 32K */
@ -562,8 +561,8 @@ void m20_state::install_memory()
dspace.install_readwrite_bank(0xb0000, 0xb3fff, 0x3fff, 0, "dram3_4000");
dspace.install_readwrite_bank(0xc0000, 0xc3fff, 0x3fff, 0, "dram3_4000");
state->membank("dram3_0000")->set_base(memptr + 0x30000);
state->membank("dram3_4000")->set_base(memptr + 0x34000);
membank("dram3_0000")->set_base(memptr + 0x30000);
membank("dram3_4000")->set_base(memptr + 0x34000);
}
}
else {
@ -621,14 +620,14 @@ void m20_state::install_memory()
dspace.install_readwrite_bank(0xb4000, 0xb7fff, 0x3fff, 0, "dram1_18000");
dspace.install_readwrite_bank(0xb8000, 0xbbfff, 0x3fff, 0, "dram1_1c000");
state->membank("dram1_0000")->set_base(memptr + 0x20000);
state->membank("dram1_4000")->set_base(memptr + 0x24000);
state->membank("dram1_8000")->set_base(memptr + 0x28000);
state->membank("dram1_c000")->set_base(memptr + 0x2c000);
state->membank("dram1_10000")->set_base(memptr + 0x30000);
state->membank("dram1_14000")->set_base(memptr + 0x34000);
state->membank("dram1_18000")->set_base(memptr + 0x38000);
state->membank("dram1_1c000")->set_base(memptr + 0x3c000);
membank("dram1_0000")->set_base(memptr + 0x20000);
membank("dram1_4000")->set_base(memptr + 0x24000);
membank("dram1_8000")->set_base(memptr + 0x28000);
membank("dram1_c000")->set_base(memptr + 0x2c000);
membank("dram1_10000")->set_base(memptr + 0x30000);
membank("dram1_14000")->set_base(memptr + 0x34000);
membank("dram1_18000")->set_base(memptr + 0x38000);
membank("dram1_1c000")->set_base(memptr + 0x3c000);
if (m_memsize > 256 * 1024) {
/* DRAM2, 128K */
@ -680,14 +679,14 @@ void m20_state::install_memory()
dspace.install_readwrite_bank(0xd4000, 0xd7fff, 0x3fff, 0, "dram2_18000");
dspace.install_readwrite_bank(0xd8000, 0xdbfff, 0x3fff, 0, "dram2_1c000");
state->membank("dram2_0000")->set_base(memptr + 0x40000);
state->membank("dram2_4000")->set_base(memptr + 0x44000);
state->membank("dram2_8000")->set_base(memptr + 0x48000);
state->membank("dram2_c000")->set_base(memptr + 0x4c000);
state->membank("dram2_10000")->set_base(memptr + 0x50000);
state->membank("dram2_14000")->set_base(memptr + 0x54000);
state->membank("dram2_18000")->set_base(memptr + 0x58000);
state->membank("dram2_1c000")->set_base(memptr + 0x5c000);
membank("dram2_0000")->set_base(memptr + 0x40000);
membank("dram2_4000")->set_base(memptr + 0x44000);
membank("dram2_8000")->set_base(memptr + 0x48000);
membank("dram2_c000")->set_base(memptr + 0x4c000);
membank("dram2_10000")->set_base(memptr + 0x50000);
membank("dram2_14000")->set_base(memptr + 0x54000);
membank("dram2_18000")->set_base(memptr + 0x58000);
membank("dram2_1c000")->set_base(memptr + 0x5c000);
}
if (m_memsize > 384 * 1024) {
/* DRAM3, 128K */
@ -742,14 +741,14 @@ void m20_state::install_memory()
dspace.install_readwrite_bank(0xf8000, 0xfbfff, 0x3fff, 0, "dram3_1c000");
dspace.install_readwrite_bank(0xfc000, 0xfffff, 0x3fff, 0, "dram3_0000");
state->membank("dram3_0000")->set_base(memptr + 0x60000);
state->membank("dram3_4000")->set_base(memptr + 0x64000);
state->membank("dram3_8000")->set_base(memptr + 0x68000);
state->membank("dram3_c000")->set_base(memptr + 0x6c000);
state->membank("dram3_10000")->set_base(memptr + 0x70000);
state->membank("dram3_14000")->set_base(memptr + 0x74000);
state->membank("dram3_18000")->set_base(memptr + 0x78000);
state->membank("dram3_1c000")->set_base(memptr + 0x7c000);
membank("dram3_0000")->set_base(memptr + 0x60000);
membank("dram3_4000")->set_base(memptr + 0x64000);
membank("dram3_8000")->set_base(memptr + 0x68000);
membank("dram3_c000")->set_base(memptr + 0x6c000);
membank("dram3_10000")->set_base(memptr + 0x70000);
membank("dram3_14000")->set_base(memptr + 0x74000);
membank("dram3_18000")->set_base(memptr + 0x78000);
membank("dram3_1c000")->set_base(memptr + 0x7c000);
}
}
}

3
src/mess/drivers/nc.c
View File

@ -1093,7 +1093,6 @@ void nc_state::nc200_refresh_uart_interrupt()
WRITE_LINE_MEMBER(nc_state::nc200_txrdy_callback)
{
//nc_state *drvstate = machine().driver_data<nc_state>();
// m_nc200_uart_interrupt_irq &=~(1<<0);
//
// if (state)
@ -1101,7 +1100,7 @@ WRITE_LINE_MEMBER(nc_state::nc200_txrdy_callback)
// m_nc200_uart_interrupt_irq |=(1<<0);
// }
//
// nc200_refresh_uart_interrupt(machine());
// nc200_refresh_uart_interrupt();
}
WRITE_LINE_MEMBER(nc_state::nc200_rxrdy_callback)

18
src/mess/drivers/pes.c
View File

@ -121,31 +121,28 @@ WRITE8_MEMBER(pes_state::data_from_i8031)
/* Port Handlers */
WRITE8_MEMBER( pes_state::rsws_w )
{
pes_state *state = machine().driver_data<pes_state>();
m_wsstate = data&0x1; // /ws is bit 0
m_rsstate = (data&0x2)>>1; // /rs is bit 1
#ifdef DEBUG_PORTS
logerror("port0 write: RSWS states updated: /RS: %d, /WS: %d\n", m_rsstate, m_wsstate);
#endif
state->m_speech->rsq_w(m_rsstate);
state->m_speech->wsq_w(m_wsstate);
m_speech->rsq_w(m_rsstate);
m_speech->wsq_w(m_wsstate);
}
WRITE8_MEMBER( pes_state::port1_w )
{
pes_state *state = machine().driver_data<pes_state>();
#ifdef DEBUG_PORTS
logerror("port1 write: tms5220 data written: %02X\n", data);
#endif
state->m_speech->data_w(space, 0, data);
m_speech->data_w(space, 0, data);
}
READ8_MEMBER( pes_state::port1_r )
{
UINT8 data = 0xFF;
pes_state *state = machine().driver_data<pes_state>();
data = state->m_speech->status_r(space, 0);
data = m_speech->status_r(space, 0);
#ifdef DEBUG_PORTS
logerror("port1 read: tms5220 data read: 0x%02X\n", data);
#endif
@ -181,14 +178,13 @@ WRITE8_MEMBER( pes_state::port3_w )
READ8_MEMBER( pes_state::port3_r )
{
UINT8 data = m_port3_state & 0xE3; // return last written state with rts, /rdy and /int masked out
pes_state *state = machine().driver_data<pes_state>();
// check rts state; if virtual fifo is nonzero, rts is set, otherwise it is cleared
if (state->m_infifo_tail_ptr != state->m_infifo_head_ptr)
if (m_infifo_tail_ptr != m_infifo_head_ptr)
{
data |= 0x10; // set RTS bit
}
data |= (state->m_speech->intq_r()<<2);
data |= (state->m_speech->readyq_r()<<3);
data |= (m_speech->intq_r()<<2);
data |= (m_speech->readyq_r()<<3);
#ifdef DEBUG_PORTS
logerror("port3 read: returning 0x%02X: ", data);
logerror("RXD: %d; ", BIT(data,0));

15
src/mess/machine/hp48.c
View File

@ -43,10 +43,10 @@
/* current HP48 model */
#define HP48_G_SERIES ((state->m_model==HP48_G) || (state->m_model==HP48_GX) || (state->m_model==HP48_GP))
#define HP48_S_SERIES ((state->m_model==HP48_S) || (state->m_model==HP48_SX))
#define HP48_X_SERIES ((state->m_model==HP48_SX) || (state->m_model==HP48_GX))
#define HP48_GX_MODEL ((state->m_model==HP48_GX) || (state->m_model==HP48_GP))
#define HP48_G_SERIES ((m_model==HP48_G) || (m_model==HP48_GX) || (m_model==HP48_GP))
#define HP48_S_SERIES ((m_model==HP48_S) || (m_model==HP48_SX))
#define HP48_X_SERIES ((m_model==HP48_SX) || (m_model==HP48_GX))
#define HP48_GX_MODEL ((m_model==HP48_GX) || (m_model==HP48_GP))
/* OUT register from SATURN (actually 12-bit) */
@ -466,7 +466,6 @@ WRITE8_MEMBER(hp48_state::hp48_io_w)
READ8_MEMBER(hp48_state::hp48_io_r)
{
hp48_state *state = machine().driver_data<hp48_state>();
UINT8 data = 0;
switch( offset )
@ -692,7 +691,6 @@ void hp48_state::hp48_apply_modules()
m_io_addr = 0x100000;
hp48_state *state = machine().driver_data<hp48_state>();
if ( HP48_G_SERIES )
{
/* port 2 bank switch */
@ -1089,7 +1087,6 @@ void hp48_state::machine_reset()
void hp48_state::hp48_machine_start( hp48_models model )
{
hp48_state *state = machine().driver_data<hp48_state>();
UINT8* rom, *ram;
int ram_size, rom_size, i;
@ -1171,8 +1168,8 @@ void hp48_state::hp48_machine_start( hp48_models model )
save_item(NAME(m_io) );
//save_pointer(NAME(machine.generic.nvram.u8), machine.generic.nvram_size );
machine().save().register_postload( save_prepost_delegate(FUNC(hp48_state::hp48_update_annunciators), state ));
machine().save().register_postload( save_prepost_delegate(FUNC(hp48_state::hp48_apply_modules), state ));
machine().save().register_postload( save_prepost_delegate(FUNC(hp48_state::hp48_update_annunciators), this ));
machine().save().register_postload( save_prepost_delegate(FUNC(hp48_state::hp48_apply_modules), this ));
#ifdef CHARDEV
/* direct I/O */

25
src/mess/video/rm380z.c
View File

@ -126,8 +126,6 @@ void rm380z_state::decode_videoram_char(int pos,UINT8& chr,UINT8& attrib)
void rm380z_state::scroll_videoram()
{
rm380z_state *state = machine().driver_data<rm380z_state>();
int lineWidth=0x80;
if (m_videomode==RM380Z_VIDEOMODE_40COL)
{
@ -143,9 +141,9 @@ void rm380z_state::scroll_videoram()
int sourceaddr=(row*lineWidth)+c;
int destaddr=((row-1)*lineWidth)+c;
state->m_vram[destaddr]=state->m_vram[sourceaddr];
state->m_vramchars[destaddr]=state->m_vramchars[sourceaddr];
state->m_vramattribs[destaddr]=state->m_vramattribs[sourceaddr];
m_vram[destaddr]=m_vram[sourceaddr];
m_vramchars[destaddr]=m_vramchars[sourceaddr];
m_vramattribs[destaddr]=m_vramattribs[sourceaddr];
}
}
@ -153,9 +151,9 @@ void rm380z_state::scroll_videoram()
for (int c=0;c<lineWidth;c++)
{
state->m_vram[((RM380Z_SCREENROWS-1)*lineWidth)+c]=0x20;
state->m_vramchars[((RM380Z_SCREENROWS-1)*lineWidth)+c]=0x20;
state->m_vramattribs[((RM380Z_SCREENROWS-1)*lineWidth)+c]=0x00;
m_vram[((RM380Z_SCREENROWS-1)*lineWidth)+c]=0x20;
m_vramchars[((RM380Z_SCREENROWS-1)*lineWidth)+c]=0x20;
m_vramattribs[((RM380Z_SCREENROWS-1)*lineWidth)+c]=0x00;
}
}
@ -194,9 +192,7 @@ void rm380z_state::check_scroll_register()
WRITE8_MEMBER( rm380z_state::videoram_write )
{
rm380z_state *state = machine().driver_data<rm380z_state>();
//printf("vramw [%2.2x][%2.2x] port0 [%2.2x] fbfd [%2.2x] fbfe [%2.2x] PC [%4.4x]\n",offset,data,state->m_port0,m_fbfd,m_fbfe,m_maincpu->safe_pc());
//printf("vramw [%2.2x][%2.2x] port0 [%2.2x] fbfd [%2.2x] fbfe [%2.2x] PC [%4.4x]\n",offset,data,m_port0,m_fbfd,m_fbfe,m_maincpu->safe_pc());
int lineWidth=0x80;
if (m_videomode==RM380Z_VIDEOMODE_40COL)
@ -213,7 +209,7 @@ WRITE8_MEMBER( rm380z_state::videoram_write )
// we suppose videoram is being written as character/attribute couple
// fbfc 6th bit set=attribute, unset=char
if (!(state->m_port0&0x40))
if (!(m_port0&0x40))
{
m_vramchars[realA%RM380Z_SCREENSIZE]=data;
}
@ -224,13 +220,12 @@ WRITE8_MEMBER( rm380z_state::videoram_write )
//
state->m_mainVideoram[offset]=data;
m_mainVideoram[offset]=data;
}
READ8_MEMBER( rm380z_state::videoram_read )
{
rm380z_state *state = machine().driver_data<rm380z_state>();
return state->m_mainVideoram[offset];
return m_mainVideoram[offset];
}
void rm380z_state::putChar(int charnum,int attribs,int x,int y,bitmap_ind16 &bitmap,unsigned char* chsb,int vmode)