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started implementation of a Motorola 68230 PI/T (Parallell Interface / Timer) device
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src/emu/machine/68230pit.c
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44
src/emu/machine/68230pit.c
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// license:BSD-3-Clause
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// copyright-holders:Joakim Larsson Edström
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/**********************************************************************
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Motorola MC68230 PI/T Parallell Interface and Timer
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**********************************************************************/
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/*
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Registers
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-----------------------------------------------------------------------
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Offset Reset R/W
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RS1-RS5 Name Value Reset Description
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-----------------------------------------------------------------------
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0x00 RW PGCR No Port General Control register
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0x01 RW PSRR No Port Service Request register
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0x02 RW PADDR No Port A Data Direction register
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0x03 RW PBDDR No Port B Data Direction register
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0x04 RW PCDDR No Port C Data Direction register
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0x05 RW PIVR No Port Interrupt vector register
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0x06 RW PACR No Port A Control register
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0x07 RW PBCR No Port B Control register
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0x08 RW PADR May Port A Data register
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0x09 RW PBDR May Port B Data register
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0x0a RO PAAR No Port A Alternate register
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0x0b RO PBAR No Port B Alternate register
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0x0c RW PCDR No Port C Data register
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0x0d RW PSR May Port Status register
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0x0e n/a
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0x0f n/a
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0x10 RW TCR No Timer Control Register
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0x11 RW TIVR No Timer Interrupt Vector Register
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0x12 n/a
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0x13 RW CPRH No Counter Preload Register High
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0x14 RW CPRM No Counter Preload Register Middle
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0x15 RW CPRL No Counter Preload Register Low
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0x17 RO CNTRH No Counter Register High
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0x18 RO CNTRM No Counter Register Middle
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0x19 RO CNTRL No Counter Register Low
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0x1A RW TSR May Timer Status Register
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*/
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src/emu/machine/68230pit.h
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src/emu/machine/68230pit.h
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// license:BSD-3-Clause
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// copyright-holders:Joakim Larsson Edström
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/**********************************************************************
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Motorola MC68230 PI/T Parallell Interface and Timer
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**********************************************************************/
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#define PGCR 0x00 /* Port General Control register */
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#define PSRR 0x01 /* Port Service Request register */
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#define PADDR 0x02 /* Port A Data Direction register */
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#define PBDDR 0x03 /* Port B Data Direction register */
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#define PCDDR 0x04 /* Port C Data Direction register */
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#define PIVR 0x05 /* Port Interrupt vector register */
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#define PACR 0x06 /* Port A Control register */
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#define PBCR 0x07 /* Port B Control register */
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#define PADR 0x08 /* Port A Data register */
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#define PBDR 0x09 /* Port B Data register */
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#define PAAR 0x0a /* Port A Alternate register */
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#define PBAR 0x0b /* Port B Alternate register */
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#define PCDR 0x0c /* Port C Data register */
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#define PSR 0x0d /* Port Status register */
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#define TCR 0x10 /* Timer Control Register */
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#define TIVR 0x11 /* Timer Interrupt Vector Register */
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#define CPRH 0x13 /* Counter Preload Register High */
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#define CPRM 0x14 /* Counter Preload Register Middle */
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#define CPRL 0x15 /* Counter Preload Register Low */
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#define CNTRH 0x17 /* Counter Register High */
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#define CNTRM 0x18 /* Counter Register Middle */
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#define CNTRL 0x19 /* Counter Register Low */
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#define TSR 0x1A /* Timer Status Register */
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