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-bankdev: Remove MCFG, nw

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This commit is contained in:
mooglyguy 2018-08-15 22:07:25 +02:00
parent 99ff0a81e9
commit 70ab417e23
101 changed files with 283 additions and 1363 deletions
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6
src/devices/bus/interpro/keyboard/lle.cpp
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@ -442,11 +442,7 @@ MACHINE_CONFIG_START(lle_device_base::device_add_mconfig)
MCFG_MCS48_PORT_BUS_IN_CB(READ8(*this, lle_device_base, bus_r))
MCFG_MCS48_PORT_BUS_OUT_CB(WRITE8(*this, lle_device_base, bus_w))
MCFG_DEVICE_ADD(m_ext, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(ext_map)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(12)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x100)
ADDRESS_MAP_BANK(config, m_ext).set_map(&lle_device_base::ext_map).set_options(ENDIANNESS_NATIVE, 8, 12, 0x100);
SPEAKER(config, "keyboard").front_center();
MCFG_DEVICE_ADD("speaker", SPEAKER_SOUND, 0)

42
src/devices/machine/bankdev.h
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@ -6,21 +6,6 @@
#pragma once
#define MCFG_ADDRESS_MAP_BANK_ENDIANNESS(_endianness) \
downcast<address_map_bank_device &>(*device).set_endianness(_endianness);
#define MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(_data_width) \
downcast<address_map_bank_device &>(*device).set_data_width(_data_width);
#define MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(_addr_width) \
downcast<address_map_bank_device &>(*device).set_addr_width(_addr_width);
#define MCFG_ADDRESS_MAP_BANK_STRIDE(_stride) \
downcast<address_map_bank_device &>(*device).set_stride(_stride);
#define MCFG_ADDRESS_MAP_BANK_SHIFT(_shift) \
downcast<address_map_bank_device &>(*device).set_shift(_shift);
class address_map_bank_device :
public device_t,
public device_memory_interface
@ -30,12 +15,27 @@ public:
address_map_bank_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock = 0);
// configuration helpers
template <typename... T> void set_map(T &&... args) { set_addrmap(0, std::forward<T>(args)...); }
void set_endianness(endianness_t endianness) { m_endianness = endianness; }
void set_data_width(uint8_t data_width) { m_data_width = data_width; }
void set_addr_width(uint8_t addr_width) { m_addr_width = addr_width; }
void set_stride(uint32_t stride) { m_stride = stride; }
void set_shift(uint32_t shift) { m_shift = shift; }
template <typename... T> address_map_bank_device& set_map(T &&... args) { set_addrmap(0, std::forward<T>(args)...); return *this; }
address_map_bank_device& set_endianness(endianness_t endianness) { m_endianness = endianness; return *this; }
address_map_bank_device& set_data_width(uint8_t data_width) { m_data_width = data_width; return *this; }
address_map_bank_device& set_addr_width(uint8_t addr_width) { m_addr_width = addr_width; return *this; }
address_map_bank_device& set_stride(uint32_t stride) { m_stride = stride; return *this; }
address_map_bank_device& set_shift(uint32_t shift) { m_shift = shift; return *this; }
address_map_bank_device& set_options(endianness_t endianness, uint8_t data_width, uint8_t addr_width, uint32_t stride = 1)
{
set_endianness(endianness);
set_data_width(data_width);
set_addr_width(addr_width);
set_stride(stride);
return *this;
}
template <typename... T> address_map_bank_device& map(T &&... args) { set_addrmap(0, std::forward<T>(args)...); return *this; }
address_map_bank_device& endianness(endianness_t endianness) { m_endianness = endianness; return *this; }
address_map_bank_device& data_width(uint8_t data_width) { m_data_width = data_width; return *this; }
address_map_bank_device& addr_width(uint8_t addr_width) { m_addr_width = addr_width; return *this; }
address_map_bank_device& stride(uint32_t stride) { m_stride = stride; return *this; }
address_map_bank_device& shift(uint32_t shift) { m_shift = shift; return *this; }
void amap8(address_map &map);
void amap16(address_map &map);

14
src/mame/audio/dcs.cpp
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@ -2680,12 +2680,7 @@ MACHINE_CONFIG_START(dcs2_audio_dsio_device::device_add_mconfig)
MCFG_DEVICE_DATA_MAP(dsio_data_map)
MCFG_DEVICE_IO_MAP(dsio_io_map)
MCFG_DEVICE_ADD("data_map_bank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(dsio_rambank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(14)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
ADDRESS_MAP_BANK(config, "data_map_bank").set_map(&dcs2_audio_dsio_device::dsio_rambank_map).set_options(ENDIANNESS_LITTLE, 16, 14, 0x2000);
MCFG_TIMER_DEVICE_ADD("dcs_reg_timer", DEVICE_SELF, dcs_audio_device, dcs_irq)
MCFG_TIMER_DEVICE_ADD("dcs_int_timer", DEVICE_SELF, dcs_audio_device, internal_timer_callback)
@ -2719,12 +2714,7 @@ MACHINE_CONFIG_START(dcs2_audio_denver_device::device_add_mconfig)
MCFG_DEVICE_DATA_MAP(denver_data_map)
MCFG_DEVICE_IO_MAP(denver_io_map)
MCFG_DEVICE_ADD("data_map_bank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(denver_rambank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(14)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
ADDRESS_MAP_BANK(config, "data_map_bank").set_map(&dcs2_audio_denver_device::denver_rambank_map).set_options(ENDIANNESS_LITTLE, 16, 14, 0x2000);
MCFG_TIMER_DEVICE_ADD("dcs_reg_timer", DEVICE_SELF, dcs_audio_device, dcs_irq)
MCFG_TIMER_DEVICE_ADD("dcs_int_timer", DEVICE_SELF, dcs_audio_device, internal_timer_callback)

6
src/mame/drivers/agat.cpp
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@ -1099,11 +1099,7 @@ MACHINE_CONFIG_START(agat7_state::agat7)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.00)
/* /INH banking */
MCFG_DEVICE_ADD(m_upperbank, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(inhbank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x3000)
ADDRESS_MAP_BANK(config, m_upperbank).set_map(&agat7_state::inhbank_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x3000);
/* keyboard controller -- XXX must be replaced */
MCFG_DEVICE_ADD(m_ay3600, AY3600, 0)

7
src/mame/drivers/alg.cpp
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@ -309,12 +309,7 @@ MACHINE_CONFIG_START(alg_state::alg_r1)
MCFG_DEVICE_ADD("maincpu", M68000, amiga_state::CLK_7M_NTSC)
MCFG_DEVICE_PROGRAM_MAP(main_map_r1)
MCFG_DEVICE_ADD("overlay", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(overlay_512kb_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x200000)
ADDRESS_MAP_BANK(config, "overlay").set_map(&alg_state::overlay_512kb_map).set_options(ENDIANNESS_BIG, 16, 22, 0x200000);
MCFG_NVRAM_ADD_0FILL("nvram")

7
src/mame/drivers/aliens.cpp
View File

@ -205,12 +205,7 @@ MACHINE_CONFIG_START(aliens_state::aliens)
MCFG_DEVICE_ADD("audiocpu", Z80, XTAL(3'579'545)) /* verified on pcb */
MCFG_DEVICE_PROGRAM_MAP(aliens_sound_map)
MCFG_DEVICE_ADD("bank0000", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank0000_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(11)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x400)
ADDRESS_MAP_BANK(config, "bank0000").set_map(&aliens_state::bank0000_map).set_options(ENDIANNESS_BIG, 8, 11, 0x400);
MCFG_WATCHDOG_ADD("watchdog")

14
src/mame/drivers/alphatpx.cpp
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@ -1218,12 +1218,7 @@ MACHINE_CONFIG_START(alphatp_12_state::alphatp2)
MCFG_MCS48_PORT_P2_IN_CB(READ8(*this, alphatp_12_state, kbd_port2_r))
MCFG_MCS48_PORT_P2_OUT_CB(WRITE8(*this, alphatp_12_state, kbd_port2_w))
MCFG_DEVICE_ADD("bankdev", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(alphatp2_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(18)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x10000)
ADDRESS_MAP_BANK(config, "bankdev").set_map(&alphatp_12_state::alphatp2_map).set_options(ENDIANNESS_LITTLE, 8, 18, 0x10000);
// video hardware
MCFG_SCREEN_ADD_MONOCHROME("screen", RASTER, rgb_t::green())
@ -1300,12 +1295,7 @@ MACHINE_CONFIG_START(alphatp_34_state::alphatp3)
MCFG_MCS48_PORT_P2_IN_CB(READ8(*this, alphatp_34_state, kbd_port2_r))
MCFG_MCS48_PORT_P2_OUT_CB(WRITE8(*this, alphatp_34_state, kbd_port2_w))
MCFG_DEVICE_ADD("bankdev", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(alphatp3_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(18)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x10000)
ADDRESS_MAP_BANK(config, "bankdev").set_map(&alphatp_34_state::alphatp3_map).set_options(ENDIANNESS_LITTLE, 8, 18, 0x10000);
// video hardware
MCFG_SCREEN_ADD_MONOCHROME("screen", RASTER, rgb_t::green())

18
src/mame/drivers/alphatro.cpp
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@ -768,25 +768,13 @@ MACHINE_CONFIG_START(alphatro_state::alphatro)
MCFG_SOFTWARE_LIST_ADD("cart_list","alphatro_cart")
/* 0000 banking */
MCFG_DEVICE_ADD("lowbank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(rombank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x6000)
ADDRESS_MAP_BANK(config, "lowbank").set_map(&alphatro_state::rombank_map).set_options(ENDIANNESS_BIG, 8, 32, 0x6000);
/* A000 banking */
MCFG_DEVICE_ADD("cartbank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(cartbank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
ADDRESS_MAP_BANK(config, "cartbank").set_map(&alphatro_state::cartbank_map).set_options(ENDIANNESS_BIG, 8, 32, 0x4000);
/* F000 banking */
MCFG_DEVICE_ADD("monbank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(monbank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000)
ADDRESS_MAP_BANK(config, "monbank").set_map(&alphatro_state::monbank_map).set_options(ENDIANNESS_BIG, 8, 32, 0x1000);
MACHINE_CONFIG_END

79
src/mame/drivers/amiga.cpp
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@ -1457,19 +1457,8 @@ MACHINE_CONFIG_START(a1000_state::a1000)
MCFG_DEVICE_ADD("maincpu", M68000, amiga_state::CLK_7M_PAL)
MCFG_DEVICE_PROGRAM_MAP(a1000_mem)
MCFG_DEVICE_ADD("overlay", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(a1000_overlay_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x200000)
MCFG_DEVICE_ADD("bootrom", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(a1000_bootrom_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(19)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x40000)
ADDRESS_MAP_BANK(config, "overlay").set_map(&a1000_state::a1000_overlay_map).set_options(ENDIANNESS_BIG, 16, 22, 0x200000);
ADDRESS_MAP_BANK(config, "bootrom").set_map(&a1000_state::a1000_bootrom_map).set_options(ENDIANNESS_BIG, 16, 19, 0x40000);
MCFG_SOFTWARE_LIST_ADD("a1000_list", "amiga_a1000")
MACHINE_CONFIG_END
@ -1496,12 +1485,7 @@ MACHINE_CONFIG_START(a2000_state::a2000)
MCFG_DEVICE_ADD("maincpu", M68000, amiga_state::CLK_7M_PAL)
MCFG_DEVICE_PROGRAM_MAP(a2000_mem)
MCFG_DEVICE_ADD("overlay", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(overlay_512kb_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x200000)
ADDRESS_MAP_BANK(config, "overlay").set_map(&amiga_state::overlay_512kb_map).set_options(ENDIANNESS_BIG, 16, 22, 0x200000);
// real-time clock
MCFG_DEVICE_ADD("u65", MSM6242, XTAL(32'768))
@ -1542,13 +1526,7 @@ MACHINE_CONFIG_START(a500_state::a500)
MCFG_DEVICE_ADD("maincpu", M68000, amiga_state::CLK_7M_PAL)
MCFG_DEVICE_PROGRAM_MAP(a500_mem)
MCFG_DEVICE_ADD("overlay", ADDRESS_MAP_BANK, 0)
//MCFG_DEVICE_PROGRAM_MAP(overlay_512kb_map)
MCFG_DEVICE_PROGRAM_MAP(overlay_1mb_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x200000)
ADDRESS_MAP_BANK(config, "overlay").set_map(&amiga_state::overlay_1mb_map).set_options(ENDIANNESS_BIG, 16, 22, 0x200000);
// cpu slot
MCFG_EXPANSION_SLOT_ADD("maincpu", a500_expansion_cards, nullptr)
@ -1589,12 +1567,7 @@ MACHINE_CONFIG_START(cdtv_state::cdtv)
MCFG_DEVICE_PROGRAM_MAP(lcd_mem)
#endif
MCFG_DEVICE_ADD("overlay", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(overlay_1mb_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x200000)
ADDRESS_MAP_BANK(config, "overlay").set_map(&amiga_state::overlay_1mb_map).set_options(ENDIANNESS_BIG, 16, 22, 0x200000);
// standard sram
MCFG_NVRAM_ADD_0FILL("sram")
@ -1654,12 +1627,7 @@ MACHINE_CONFIG_START(a3000_state::a3000)
MCFG_DEVICE_ADD("maincpu", M68030, XTAL(32'000'000) / 2)
MCFG_DEVICE_PROGRAM_MAP(a3000_mem)
MCFG_DEVICE_ADD("overlay", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(overlay_1mb_map32)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x200000)
ADDRESS_MAP_BANK(config, "overlay").set_map(&amiga_state::overlay_1mb_map32).set_options(ENDIANNESS_BIG, 32, 22, 0x200000);
// real-time clock
MCFG_DEVICE_ADD("rtc", RP5C01, XTAL(32'768))
@ -1689,12 +1657,7 @@ MACHINE_CONFIG_START(a500p_state::a500p)
MCFG_DEVICE_ADD("maincpu", M68000, amiga_state::CLK_7M_PAL)
MCFG_DEVICE_PROGRAM_MAP(a500p_mem)
MCFG_DEVICE_ADD("overlay", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(overlay_1mb_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x200000)
ADDRESS_MAP_BANK(config, "overlay").set_map(&amiga_state::overlay_1mb_map).set_options(ENDIANNESS_BIG, 16, 22, 0x200000);
// real-time clock
MCFG_DEVICE_ADD("u9", MSM6242, XTAL(32'768))
@ -1728,12 +1691,7 @@ MACHINE_CONFIG_START(a600_state::a600)
MCFG_DEVICE_ADD("maincpu", M68000, amiga_state::CLK_7M_PAL)
MCFG_DEVICE_PROGRAM_MAP(a600_mem)
MCFG_DEVICE_ADD("overlay", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(overlay_2mb_map16)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x200000)
ADDRESS_MAP_BANK(config, "overlay").set_map(&amiga_state::overlay_2mb_map16).set_options(ENDIANNESS_BIG, 16, 22, 0x200000);
MCFG_GAYLE_ADD("gayle", amiga_state::CLK_28M_PAL / 2, a600_state::GAYLE_ID)
MCFG_GAYLE_INT2_HANDLER(WRITELINE(*this, a600_state, gayle_int2_w))
@ -1775,12 +1733,7 @@ MACHINE_CONFIG_START(a1200_state::a1200)
MCFG_DEVICE_ADD("maincpu", M68EC020, amiga_state::CLK_28M_PAL / 2)
MCFG_DEVICE_PROGRAM_MAP(a1200_mem)
MCFG_DEVICE_ADD("overlay", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(overlay_2mb_map32)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x200000)
ADDRESS_MAP_BANK(config, "overlay").set_map(&amiga_state::overlay_2mb_map32).set_options(ENDIANNESS_BIG, 32, 22, 0x200000);
MCFG_DEVICE_MODIFY("screen")
MCFG_SCREEN_UPDATE_DRIVER(amiga_state, screen_update_amiga_aga)
@ -1840,12 +1793,7 @@ MACHINE_CONFIG_START(a4000_state::a4000)
MCFG_DEVICE_ADD("maincpu", M68040, XTAL(50'000'000) / 2)
MCFG_DEVICE_PROGRAM_MAP(a4000_mem)
MCFG_DEVICE_ADD("overlay", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(overlay_2mb_map32)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x200000)
ADDRESS_MAP_BANK(config, "overlay").set_map(&amiga_state::overlay_2mb_map32).set_options(ENDIANNESS_BIG, 32, 22, 0x200000);
MCFG_DEVICE_MODIFY("screen")
MCFG_SCREEN_UPDATE_DRIVER(amiga_state, screen_update_amiga_aga)
@ -1919,12 +1867,7 @@ MACHINE_CONFIG_START(cd32_state::cd32)
MCFG_DEVICE_ADD("maincpu", M68EC020, amiga_state::CLK_28M_PAL / 2)
MCFG_DEVICE_PROGRAM_MAP(cd32_mem)
MCFG_DEVICE_ADD("overlay", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(overlay_2mb_map32)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x200000)
ADDRESS_MAP_BANK(config, "overlay").set_map(&amiga_state::overlay_2mb_map32).set_options(ENDIANNESS_BIG, 32, 22, 0x200000);
MCFG_I2CMEM_ADD("i2cmem")
MCFG_I2CMEM_PAGE_SIZE(16)

6
src/mame/drivers/apple2.cpp
View File

@ -1396,11 +1396,7 @@ MACHINE_CONFIG_START(napple2_state::apple2_common)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.00)
/* /INH banking */
MCFG_DEVICE_ADD(A2_UPPERBANK_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(inhbank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x3000)
ADDRESS_MAP_BANK(config, A2_UPPERBANK_TAG).set_map(&napple2_state::inhbank_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x3000);
/* soft switches */
F9334(config, m_softlatch); // F14 (labeled 74LS259 on some boards and in the Apple ][ Reference Manual)

72
src/mame/drivers/apple2e.cpp
View File

@ -4003,88 +4003,40 @@ MACHINE_CONFIG_START(apple2e_state::apple2e)
MCFG_RAM_DEFAULT_VALUE(0x00)
/* 0000 banking */
MCFG_DEVICE_ADD(A2_0000_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(r0000bank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x200)
ADDRESS_MAP_BANK(config, A2_0000_TAG).set_map(&apple2e_state::r0000bank_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x200);
/* 0200 banking */
MCFG_DEVICE_ADD(A2_0200_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(r0200bank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x200)
ADDRESS_MAP_BANK(config, A2_0200_TAG).set_map(&apple2e_state::r0200bank_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x200);
/* 0400 banking */
MCFG_DEVICE_ADD(A2_0400_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(r0400bank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x400)
ADDRESS_MAP_BANK(config, A2_0400_TAG).set_map(&apple2e_state::r0400bank_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x400);
/* 0800 banking */
MCFG_DEVICE_ADD(A2_0800_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(r0800bank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
ADDRESS_MAP_BANK(config, A2_0800_TAG).set_map(&apple2e_state::r0800bank_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x2000);
/* 2000 banking */
MCFG_DEVICE_ADD(A2_2000_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(r2000bank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
ADDRESS_MAP_BANK(config, A2_2000_TAG).set_map(&apple2e_state::r2000bank_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x2000);
/* 4000 banking */
MCFG_DEVICE_ADD(A2_4000_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(r4000bank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x8000)
ADDRESS_MAP_BANK(config, A2_4000_TAG).set_map(&apple2e_state::r4000bank_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x8000);
/* C100 banking */
MCFG_DEVICE_ADD(A2_C100_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(c100bank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x200)
ADDRESS_MAP_BANK(config, A2_C100_TAG).set_map(&apple2e_state::c100bank_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x200);
/* C300 banking */
MCFG_DEVICE_ADD(A2_C300_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(c300bank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x100)
ADDRESS_MAP_BANK(config, A2_C300_TAG).set_map(&apple2e_state::c300bank_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x100);
/* C400 banking */
MCFG_DEVICE_ADD(A2_C400_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(c400bank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x400)
ADDRESS_MAP_BANK(config, A2_C400_TAG).set_map(&apple2e_state::c400bank_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x400);
/* C800 banking */
MCFG_DEVICE_ADD(A2_C800_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(c800bank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x800)
ADDRESS_MAP_BANK(config, A2_C800_TAG).set_map(&apple2e_state::c800bank_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x800);
/* built-in language card emulation */
MCFG_DEVICE_ADD(A2_LCBANK_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(lcbank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x3000)
ADDRESS_MAP_BANK(config, A2_LCBANK_TAG).set_map(&apple2e_state::lcbank_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x3000);
/* /INH banking */
MCFG_DEVICE_ADD(A2_UPPERBANK_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(inhbank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x3000)
ADDRESS_MAP_BANK(config, A2_UPPERBANK_TAG).set_map(&apple2e_state::inhbank_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x3000);
/* keyboard controller */
MCFG_DEVICE_ADD("ay3600", AY3600, 0)

126
src/mame/drivers/apple2gs.cpp
View File

@ -4605,151 +4605,67 @@ MACHINE_CONFIG_START( apple2gs_state::apple2gs )
MCFG_RAM_DEFAULT_VALUE(0x00)
/* C100 banking */
MCFG_DEVICE_ADD(A2GS_C100_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(c100bank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x200)
ADDRESS_MAP_BANK(config, A2GS_C100_TAG).set_map(&apple2gs_state::c100bank_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x200);
/* C300 banking */
MCFG_DEVICE_ADD(A2GS_C300_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(c300bank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x100)
ADDRESS_MAP_BANK(config, A2GS_C300_TAG).set_map(&apple2gs_state::c300bank_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x100);
/* C400 banking */
MCFG_DEVICE_ADD(A2GS_C400_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(c400bank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x400)
ADDRESS_MAP_BANK(config, A2GS_C400_TAG).set_map(&apple2gs_state::c400bank_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x400);
/* C800 banking */
MCFG_DEVICE_ADD(A2GS_C800_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(c800bank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x800)
ADDRESS_MAP_BANK(config, A2GS_C800_TAG).set_map(&apple2gs_state::c800bank_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x800);
/* built-in language card emulation */
MCFG_DEVICE_ADD(A2GS_LCBANK_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(lcbank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x3000)
ADDRESS_MAP_BANK(config, A2GS_LCBANK_TAG).set_map(&apple2gs_state::lcbank_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x3000);
/* aux bank language card emulation */
MCFG_DEVICE_ADD(A2GS_LCAUX_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(lcaux_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x3000)
ADDRESS_MAP_BANK(config, A2GS_LCAUX_TAG).set_map(&apple2gs_state::lcaux_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x3000);
/* bank 00 language card emulation */
MCFG_DEVICE_ADD(A2GS_LC00_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(lc00_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x3000)
ADDRESS_MAP_BANK(config, A2GS_LC00_TAG).set_map(&apple2gs_state::lc00_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x3000);
/* bank 01 language card emulation */
MCFG_DEVICE_ADD(A2GS_LC01_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(lc01_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x3000)
ADDRESS_MAP_BANK(config, A2GS_LC01_TAG).set_map(&apple2gs_state::lc01_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x3000);
/* /INH banking */
MCFG_DEVICE_ADD(A2GS_UPPERBANK_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(inhbank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x3000)
ADDRESS_MAP_BANK(config, A2GS_UPPERBANK_TAG).set_map(&apple2gs_state::inhbank_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x3000);
/* /INH banking - aux bank */
MCFG_DEVICE_ADD(A2GS_AUXUPPER_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(inhaux_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x3000)
ADDRESS_MAP_BANK(config, A2GS_AUXUPPER_TAG).set_map(&apple2gs_state::inhaux_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x3000);
/* /INH banking - bank 00 */
MCFG_DEVICE_ADD(A2GS_00UPPER_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(inh00_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x3000)
ADDRESS_MAP_BANK(config, A2GS_00UPPER_TAG).set_map(&apple2gs_state::inh00_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x3000);
/* /INH banking - bank 01 */
MCFG_DEVICE_ADD(A2GS_01UPPER_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(inh01_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x3000)
ADDRESS_MAP_BANK(config, A2GS_01UPPER_TAG).set_map(&apple2gs_state::inh01_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x3000);
/* Bank 0 - I/O and LC area */
MCFG_DEVICE_ADD(A2GS_B0CXXX_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank0_iolc_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
ADDRESS_MAP_BANK(config, A2GS_B0CXXX_TAG).set_map(&apple2gs_state::bank0_iolc_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x4000);
/* Bank 1 - lower 48K */
MCFG_DEVICE_ADD(A2GS_B01_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank1_lower48_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0xc000)
ADDRESS_MAP_BANK(config, A2GS_B01_TAG).set_map(&apple2gs_state::bank1_lower48_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0xc000);
/* Bank 1 - I/O and LC area */
MCFG_DEVICE_ADD(A2GS_B1CXXX_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank1_iolc_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
ADDRESS_MAP_BANK(config, A2GS_B1CXXX_TAG).set_map(&apple2gs_state::bank1_iolc_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x4000);
/* Bank 0 0000 banking */
MCFG_DEVICE_ADD(A2GS_B00000_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(rb0000bank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x200)
ADDRESS_MAP_BANK(config, A2GS_B00000_TAG).set_map(&apple2gs_state::rb0000bank_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x200);
/* Bank 0 0200 banking */
MCFG_DEVICE_ADD(A2GS_B00200_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(rb0200bank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x200)
ADDRESS_MAP_BANK(config, A2GS_B00200_TAG).set_map(&apple2gs_state::rb0200bank_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x200);
/* Bank 0 0400 banking */
MCFG_DEVICE_ADD(A2GS_B00400_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(rb0400bank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x400)
ADDRESS_MAP_BANK(config, A2GS_B00400_TAG).set_map(&apple2gs_state::rb0400bank_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x400);
/* Bank 0 0800 banking */
MCFG_DEVICE_ADD(A2GS_B00800_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(rb0800bank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
ADDRESS_MAP_BANK(config, A2GS_B00800_TAG).set_map(&apple2gs_state::rb0800bank_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x2000);
/* Bank 0 2000 banking */
MCFG_DEVICE_ADD(A2GS_B02000_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(rb2000bank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
ADDRESS_MAP_BANK(config, A2GS_B02000_TAG).set_map(&apple2gs_state::rb2000bank_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x2000);
/* Bank 0 4000 banking */
MCFG_DEVICE_ADD(A2GS_B04000_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(rb4000bank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x8000)
ADDRESS_MAP_BANK(config, A2GS_B04000_TAG).set_map(&apple2gs_state::rb4000bank_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x8000);
/* serial */
MCFG_DEVICE_ADD(SCC_TAG, SCC85C30, A2GS_14M/2)

7
src/mame/drivers/arsystems.cpp
View File

@ -306,12 +306,7 @@ MACHINE_CONFIG_START(arcadia_amiga_state::arcadia)
MCFG_DEVICE_ADD("maincpu", M68000, amiga_state::CLK_7M_NTSC)
MCFG_DEVICE_PROGRAM_MAP(arcadia_map)
MCFG_DEVICE_ADD("overlay", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(overlay_512kb_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x200000)
ADDRESS_MAP_BANK(config, "overlay").set_map(&amiga_state::overlay_512kb_map).set_options(ENDIANNESS_BIG, 16, 22, 0x200000);
MCFG_NVRAM_ADD_0FILL("nvram")

12
src/mame/drivers/astrocde.cpp
View File

@ -1200,12 +1200,7 @@ MACHINE_CONFIG_START(astrocde_state::astrocade_16color_base)
astrocade_base(config);
/* basic machine hardware */
MCFG_DEVICE_ADD("bank4000", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank4000_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
ADDRESS_MAP_BANK(config, m_bank4000).set_map(&astrocde_state::bank4000_map).set_options(ENDIANNESS_LITTLE, 8, 16, 0x4000);
MCFG_NVRAM_ADD_0FILL("nvram")
@ -1464,9 +1459,8 @@ MACHINE_CONFIG_START(astrocde_state::profpac)
MCFG_DEVICE_PROGRAM_MAP(profpac_map)
MCFG_DEVICE_IO_MAP(port_map_16col_pattern)
MCFG_DEVICE_MODIFY("bank4000")
MCFG_DEVICE_PROGRAM_MAP(profpac_bank4000_map)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(20)
m_bank4000->set_map(&astrocde_state::profpac_bank4000_map);
m_bank4000->set_addr_width(20);
MCFG_DEVICE_ADD("outlatch", OUTPUT_LATCH, 0) // 74LS174 on game board at U6
MCFG_OUTPUT_LATCH_BIT0_HANDLER(WRITELINE(*this, astrocde_state, coin_counter_w<0>))

7
src/mame/drivers/atarisy2.cpp
View File

@ -1228,12 +1228,7 @@ MACHINE_CONFIG_START(atarisy2_state::atarisy2)
MCFG_SCREEN_PALETTE("palette")
MCFG_SCREEN_VBLANK_CALLBACK(WRITELINE(*this, atarisy2_state, vblank_int))
MCFG_DEVICE_ADD("vrambank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vrambank_map)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(15)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
ADDRESS_MAP_BANK(config, "vrambank").set_map(&atarisy2_state::vrambank_map).set_options(ENDIANNESS_LITTLE, 16, 15, 0x2000);
MCFG_VIDEO_START_OVERRIDE(atarisy2_state,atarisy2)

13
src/mame/drivers/avigo.cpp
View File

@ -802,17 +802,8 @@ MACHINE_CONFIG_START(avigo_state::avigo)
MCFG_RAM_ADD(RAM_TAG)
MCFG_RAM_DEFAULT_SIZE("128K")
MCFG_DEVICE_ADD("bank0", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(avigo_banked_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
MCFG_DEVICE_ADD("bank1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(avigo_banked_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
ADDRESS_MAP_BANK(config, "bank0").set_map(&avigo_state::avigo_banked_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x4000);
ADDRESS_MAP_BANK(config, "bank1").set_map(&avigo_state::avigo_banked_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x4000);
MCFG_NVRAM_ADD_CUSTOM_DRIVER("nvram", avigo_state, nvram_init)

7
src/mame/drivers/blockhl.cpp
View File

@ -284,12 +284,7 @@ MACHINE_CONFIG_START(blockhl_state::blockhl)
MCFG_DEVICE_PROGRAM_MAP(main_map)
MCFG_KONAMICPU_LINE_CB(WRITE8(*this, blockhl_state, banking_callback))
MCFG_DEVICE_ADD("bank5800", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank5800_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(12)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x0800)
ADDRESS_MAP_BANK(config, "bank5800").set_map(&blockhl_state::bank5800_map).set_options(ENDIANNESS_BIG, 8, 12, 0x800);
MCFG_DEVICE_ADD("audiocpu", Z80, XTAL(3'579'545))
MCFG_DEVICE_PROGRAM_MAP(audio_map)

7
src/mame/drivers/bwing.cpp
View File

@ -379,12 +379,7 @@ MACHINE_CONFIG_START(bwing_state::bwing)
MCFG_QUANTUM_TIME(attotime::from_hz(18000)) // high enough?
MCFG_DEVICE_ADD("vrambank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(15)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
ADDRESS_MAP_BANK(config, "vrambank").set_map(&bwing_state::bank_map).set_options(ENDIANNESS_BIG, 8, 15, 0x2000);
// video hardware
MCFG_SCREEN_ADD("screen", RASTER)

27
src/mame/drivers/cdc721.cpp
View File

@ -307,29 +307,10 @@ MACHINE_CONFIG_START(cdc721_state::cdc721)
MCFG_DEVICE_IO_MAP(io_map)
MCFG_DEVICE_IRQ_ACKNOWLEDGE_DRIVER(cdc721_state, restart_cb)
MCFG_DEVICE_ADD("block0", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_ADDRESS_MAP(0, block0_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
MCFG_DEVICE_ADD("block4", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_ADDRESS_MAP(0, block4_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
MCFG_DEVICE_ADD("block8", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_ADDRESS_MAP(0, block8_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
MCFG_DEVICE_ADD("blockc", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_ADDRESS_MAP(0, blockc_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
ADDRESS_MAP_BANK(config, "block0").set_map(&cdc721_state::block0_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x4000);
ADDRESS_MAP_BANK(config, "block4").set_map(&cdc721_state::block4_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x4000);
ADDRESS_MAP_BANK(config, "block8").set_map(&cdc721_state::block8_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x4000);
ADDRESS_MAP_BANK(config, "blockc").set_map(&cdc721_state::blockc_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x4000);
MCFG_NVRAM_ADD_0FILL("nvram") // MCM51L01C45 (256x4) + battery

27
src/mame/drivers/cedar_magnet.cpp
View File

@ -775,26 +775,9 @@ MACHINE_CONFIG_START(cedar_magnet_state::cedar_magnet)
MCFG_DEVICE_IO_MAP(cedar_magnet_io)
MCFG_DEVICE_VBLANK_INT_DRIVER("screen", cedar_magnet_state, irq)
MCFG_DEVICE_ADD("bank0", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(cedar_bank0)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(18)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x10000)
MCFG_DEVICE_ADD("mb_sub_ram", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(cedar_magnet_mainboard_sub_ram_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(18)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x10000)
MCFG_DEVICE_ADD("mb_sub_pal", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(cedar_magnet_mainboard_sub_pal_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(8+6)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x100)
ADDRESS_MAP_BANK(config, "bank0").set_map(&cedar_magnet_state::cedar_bank0).set_options(ENDIANNESS_LITTLE, 8, 18, 0x10000);
ADDRESS_MAP_BANK(config, "mb_sub_ram").set_map(&cedar_magnet_state::cedar_magnet_mainboard_sub_ram_map).set_options(ENDIANNESS_LITTLE, 8, 18, 0x10000);
ADDRESS_MAP_BANK(config, "mb_sub_pal").set_map(&cedar_magnet_state::cedar_magnet_mainboard_sub_pal_map).set_options(ENDIANNESS_LITTLE, 8, 8+6, 0x100);
MCFG_DEVICE_ADD("z80pio_ic48", Z80PIO, 4000000/2)
// MCFG_Z80PIO_OUT_INT_CB(INPUTLINE("maincpu", INPUT_LINE_IRQ0))
@ -867,7 +850,7 @@ ROM_START( mag_xain )
ROM_END
/*
/*
Data after 0xd56b0 would not read consistently, however the game only appears to use the first 24 tracks (up to 0x48fff)
as it loads once on startup, not during gameplay, and all tracks before that gave consistent reads. There is data after this
point but it is likely leftovers from another game / whatever was on the disk before, so for our purposes this should be fine.
@ -897,7 +880,7 @@ ROM_END
ROM_START( mag_burn )
BIOS_ROM
ROM_REGION( 0x100000, "flop:disk", ROMREGION_ERASE00 ) //
ROM_REGION( 0x100000, "flop:disk", ROMREGION_ERASE00 ) //
ROM_LOAD( "theburningcavern 31_3_87.img", 0x00000, 0xf0000, CRC(c95911f8) SHA1(eda3bdbbcc3e00a7da83253209e832855c2968b1) )
ROM_END

7
src/mame/drivers/chqflag.cpp
View File

@ -325,12 +325,7 @@ MACHINE_CONFIG_START(chqflag_state::chqflag)
MCFG_DEVICE_ADD("audiocpu", Z80, XTAL(3'579'545)) /* verified on pcb */
MCFG_DEVICE_PROGRAM_MAP(chqflag_sound_map)
MCFG_DEVICE_ADD("bank1000", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank1000_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(13)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000)
ADDRESS_MAP_BANK(config, "bank1000").set_map(&chqflag_state::bank1000_map).set_options(ENDIANNESS_BIG, 8, 13, 0x1000);
MCFG_QUANTUM_TIME(attotime::from_hz(600))

6
src/mame/drivers/ckz80.cpp
View File

@ -440,11 +440,7 @@ MACHINE_CONFIG_START(ckz80_state::master)
MCFG_TIMER_START_DELAY(attotime::from_hz(429) - attotime::from_nsec(22870)) // active for 22.87us
MCFG_TIMER_DRIVER_ADD_PERIODIC("irq_off", ckz80_state, irq_off, attotime::from_hz(429))
MCFG_DEVICE_ADD("master_map", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(master_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(16)
ADDRESS_MAP_BANK(config, "master_map").set_map(&ckz80_state::master_map).set_options(ENDIANNESS_LITTLE, 8, 16);
MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", ckz80_state, display_decay_tick, attotime::from_msec(1))
config.set_default_layout(layout_ck_master);

11
src/mame/drivers/coco12.cpp
View File

@ -407,13 +407,10 @@ void coco_state::coco_floating_map(address_map &map)
}
MACHINE_CONFIG_START(coco_state::coco_floating)
MCFG_DEVICE_ADD(FLOATING_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(coco_floating_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(16)
MACHINE_CONFIG_END
void coco_state::coco_floating(machine_config &config)
{
ADDRESS_MAP_BANK(config, FLOATING_TAG).set_map(&coco_state::coco_floating_map).set_options(ENDIANNESS_BIG, 8, 16);
}
//-------------------------------------------------

9
src/mame/drivers/crgolf.cpp
View File

@ -491,12 +491,9 @@ MACHINE_CONFIG_START(crgolf_state::crgolf)
MCFG_GENERIC_LATCH_8_ADD("soundlatch2")
MCFG_GENERIC_LATCH_DATA_PENDING_CB(INPUTLINE("maincpu", INPUT_LINE_NMI))
MCFG_DEVICE_ADD("vrambank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vrambank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x8000) /* technically 0x6000, but powers of 2 makes the memory map / address masking cleaner. */
/* stride is technically 0x6000, but powers of 2 makes the memory map / address masking cleaner. */
ADDRESS_MAP_BANK(config, "vrambank").set_map(&crgolf_state::vrambank_map).set_options(ENDIANNESS_LITTLE, 8, 16, 0x8000);
MCFG_PALETTE_ADD("palette", 0x20)
MCFG_PALETTE_INIT_OWNER(crgolf_state, crgolf)

7
src/mame/drivers/crimfght.cpp
View File

@ -311,12 +311,7 @@ MACHINE_CONFIG_START(crimfght_state::crimfght)
MCFG_DEVICE_PROGRAM_MAP(crimfght_sound_map)
MCFG_DEVICE_IRQ_ACKNOWLEDGE_DEVICE(DEVICE_SELF, crimfght_state, audiocpu_irq_ack)
MCFG_DEVICE_ADD("bank0000", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank0000_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(11)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x400)
ADDRESS_MAP_BANK(config, "bank0000").set_map(&crimfght_state::bank0000_map).set_options(ENDIANNESS_BIG, 8, 11, 0x400);
MCFG_WATCHDOG_ADD("watchdog")

7
src/mame/drivers/cubo.cpp
View File

@ -1036,12 +1036,7 @@ MACHINE_CONFIG_START(cubo_state::cubo)
MCFG_DEVICE_ADD("maincpu", M68EC020, amiga_state::CLK_28M_PAL / 2)
MCFG_DEVICE_PROGRAM_MAP(cubo_mem)
MCFG_DEVICE_ADD("overlay", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(overlay_2mb_map32)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x200000)
ADDRESS_MAP_BANK(config, "overlay").set_map(&amiga_state::overlay_2mb_map32).set_options(ENDIANNESS_BIG, 32, 22, 0x200000);
MCFG_I2CMEM_ADD("i2cmem")
MCFG_I2CMEM_PAGE_SIZE(16)

8
src/mame/drivers/cultures.cpp
View File

@ -412,13 +412,7 @@ MACHINE_CONFIG_START(cultures_state::cultures)
MCFG_DEVICE_IO_MAP(cultures_io_map)
MCFG_DEVICE_VBLANK_INT_DRIVER("screen", cultures_state, cultures_interrupt)
MCFG_DEVICE_ADD("vrambank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vrambank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(15)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
ADDRESS_MAP_BANK(config, "vrambank").set_map(&cultures_state::vrambank_map).set_options(ENDIANNESS_LITTLE, 8, 15, 0x4000);
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)

6
src/mame/drivers/cybstorm.cpp
View File

@ -239,11 +239,7 @@ MACHINE_CONFIG_START(cybstorm_state::round2)
MCFG_ATARI_VAD_ALPHA(cybstorm_state, "gfxdecode", get_alpha_tile_info)
MCFG_ATARI_VAD_MOB(cybstorm_state::s_mob_config, "gfxdecode")
MCFG_DEVICE_ADD("vadbank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vadbank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x90000)
ADDRESS_MAP_BANK(config, "vadbank").set_map(&cybstorm_state::vadbank_map).set_options(ENDIANNESS_BIG, 16, 32, 0x90000);
MCFG_DEVICE_ADD("gfxdecode", GFXDECODE, "palette", gfx_cybstorm)
MCFG_PALETTE_ADD("palette", 32768)

7
src/mame/drivers/ddragon.cpp
View File

@ -1127,12 +1127,7 @@ MACHINE_CONFIG_START(darktowr_state::darktowr)
MCFG_DEVICE_ADD("mcu", M68705P3, XTAL(4'000'000))
MCFG_M68705_PORTA_W_CB(WRITE8(*this, darktowr_state, mcu_port_a_w))
MCFG_DEVICE_ADD("darktowr_bank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(darktowr_banked_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(17)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
ADDRESS_MAP_BANK(config, "darktowr_bank").set_map(&darktowr_state::darktowr_banked_map).set_options(ENDIANNESS_BIG, 8, 17, 0x4000);
/* video hardware */
MACHINE_CONFIG_END

16
src/mame/drivers/dec0.cpp
View File

@ -2005,20 +2005,8 @@ MACHINE_CONFIG_START(dec0_state::slyspy)
audiocpu.set_addrmap(AS_PROGRAM, &dec0_state::slyspy_s_map);
audiocpu.add_route(ALL_OUTPUTS, "mono", 0); // internal sound unused
MCFG_DEVICE_ADD("pfprotect", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(slyspy_protection_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(18)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x10000)
MCFG_DEVICE_ADD("sndprotect", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(slyspy_sound_protection_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(21)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000)
ADDRESS_MAP_BANK(config, "pfprotect").set_map(&dec0_state::slyspy_protection_map).set_options(ENDIANNESS_BIG, 16, 18, 0x10000);
ADDRESS_MAP_BANK(config, "sndprotect").set_map(&dec0_state::slyspy_sound_protection_map).set_options(ENDIANNESS_LITTLE, 8, 21, 0x80000);
/* video hardware */
MCFG_SCREEN_MODIFY("screen")

7
src/mame/drivers/discoboy.cpp
View File

@ -467,12 +467,7 @@ MACHINE_CONFIG_START(discoboy_state::discoboy)
MCFG_DEVICE_ADD("audiocpu", Z80, XTAL(10'000'000)/2) /* 5 MHz? */
MCFG_DEVICE_PROGRAM_MAP(sound_map)
MCFG_DEVICE_ADD("rambank1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(rambank1_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(13)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x800)
ADDRESS_MAP_BANK(config, "rambank1").set_map(&discoboy_state::rambank1_map).set_options(ENDIANNESS_BIG, 8, 13, 0x800);
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)

27
src/mame/drivers/dynax.cpp
View File

@ -4328,11 +4328,7 @@ MACHINE_CONFIG_START(dynax_state::hnoridur)
MCFG_MACHINE_START_OVERRIDE(dynax_state,dynax)
MCFG_MACHINE_RESET_OVERRIDE(dynax_state,dynax)
MCFG_DEVICE_ADD("bankdev", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(hnoridur_banked_map)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(20)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x8000)
ADDRESS_MAP_BANK(config, m_bankdev).set_map(&dynax_state::hnoridur_banked_map).set_data_width(8).set_addr_width(20).set_stride(0x8000);
MCFG_NVRAM_ADD_0FILL("nvram")
@ -4400,11 +4396,7 @@ MACHINE_CONFIG_START(dynax_state::hjingi)
MCFG_MACHINE_START_OVERRIDE(dynax_state,hjingi)
MCFG_MACHINE_RESET_OVERRIDE(dynax_state,dynax)
MCFG_DEVICE_ADD("bankdev", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(hjingi_banked_map)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(20)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x8000)
ADDRESS_MAP_BANK(config, m_bankdev).set_map(&dynax_state::hjingi_banked_map).set_data_width(8).set_addr_width(20).set_stride(0x8000);
MCFG_NVRAM_ADD_0FILL("nvram")
@ -4622,8 +4614,7 @@ MACHINE_CONFIG_END
MACHINE_CONFIG_START(dynax_state::mjangels)
yarunara(config);
MCFG_DEVICE_MODIFY("bankdev")
MCFG_DEVICE_PROGRAM_MAP(mjangels_banked_map)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(21)
m_bankdev->set_map(&dynax_state::mjangels_banked_map).set_addr_width(21);
MACHINE_CONFIG_END
MACHINE_CONFIG_START(dynax_state::quiztvqq)
@ -4877,11 +4868,7 @@ MACHINE_CONFIG_START(dynax_state::tenkai)
MCFG_TLCS90_PORT_P8_READ_CB(READ8(*this, dynax_state, tenkai_p8_r))
MCFG_TLCS90_PORT_P8_WRITE_CB(WRITE8(*this, dynax_state, tenkai_p8_w))
MCFG_DEVICE_ADD("bankdev", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(tenkai_banked_map)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(20)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x8000)
ADDRESS_MAP_BANK(config, m_bankdev).set_map(&dynax_state::tenkai_banked_map).set_data_width(8).set_addr_width(20).set_stride(0x8000);
MCFG_MACHINE_START_OVERRIDE(dynax_state,dynax)
MCFG_MACHINE_RESET_OVERRIDE(dynax_state,dynax)
@ -4955,11 +4942,7 @@ MACHINE_CONFIG_START(dynax_state::gekisha)
MCFG_DEVICE_PROGRAM_MAP(gekisha_map)
MCFG_TLCS90_PORT_P4_WRITE_CB(WRITE8(*this, dynax_state, gekisha_p4_w))
MCFG_DEVICE_ADD("bankdev", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(gekisha_banked_map)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(17)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x8000)
ADDRESS_MAP_BANK(config, m_bankdev).set_map(&dynax_state::gekisha_banked_map).set_data_width(8).set_addr_width(17).set_stride(0x8000);
MCFG_MACHINE_START_OVERRIDE(dynax_state,dynax)
MCFG_MACHINE_RESET_OVERRIDE(dynax_state,dynax)

11
src/mame/drivers/elwro800.cpp
View File

@ -628,15 +628,8 @@ MACHINE_CONFIG_START(elwro800_state::elwro800)
MCFG_RAM_ADD(RAM_TAG)
MCFG_RAM_DEFAULT_SIZE("64K")
MCFG_DEVICE_ADD("bank1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(elwro800_bank1)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
MCFG_DEVICE_ADD("bank2", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(elwro800_bank2)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
ADDRESS_MAP_BANK(config, "bank1").set_map(&elwro800_state::elwro800_bank1).set_data_width(8).set_stride(0x2000);
ADDRESS_MAP_BANK(config, "bank2").set_map(&elwro800_state::elwro800_bank2).set_data_width(8).set_stride(0x2000);
MACHINE_CONFIG_END
/*************************************

12
src/mame/drivers/fidel6502.cpp
View File

@ -1919,11 +1919,7 @@ MACHINE_CONFIG_START(fidel6502_state::eas)
MCFG_TIMER_DRIVER_ADD_PERIODIC("dummy_timer", fidel6502_state, dummy, attotime::from_hz(3_MHz_XTAL))
MCFG_DEVICE_ADD("mainmap", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(eas_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(16)
ADDRESS_MAP_BANK(config, "mainmap").set_map(&fidel6502_state::eas_map).set_options(ENDIANNESS_LITTLE, 8, 16);
MCFG_DEVICE_ADD("ppi8255", I8255, 0) // port B: input, port A & C: output
MCFG_I8255_OUT_PORTA_CB(WRITE8(*this, fidel6502_state, eas_ppi_porta_w))
@ -2047,11 +2043,7 @@ MACHINE_CONFIG_START(fidel6502_state::sc12)
MCFG_TIMER_DRIVER_ADD_PERIODIC("dummy_timer", fidel6502_state, dummy, attotime::from_hz(3_MHz_XTAL))
MCFG_DEVICE_ADD("mainmap", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(sc12_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(16)
ADDRESS_MAP_BANK(config, "mainmap").set_map(&fidel6502_state::sc12_map).set_options(ENDIANNESS_LITTLE, 8, 16);
MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", fidelbase_state, display_decay_tick, attotime::from_msec(1))
config.set_default_layout(layout_fidel_sc12);

88
src/mame/drivers/fm7.cpp
View File

@ -1514,22 +1514,10 @@ void fm7_state::fm7_sub_mem(address_map &map)
void fm7_state::fm11_mem(address_map &map)
{
map(0x0000, 0x0fff).rw("av_bank1", FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0x1000, 0x1fff).rw("av_bank2", FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0x2000, 0x2fff).rw("av_bank3", FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0x3000, 0x3fff).rw("av_bank4", FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0x4000, 0x4fff).rw("av_bank5", FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0x5000, 0x5fff).rw("av_bank6", FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0x6000, 0x6fff).rw("av_bank7", FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0x7000, 0x7fff).rw("av_bank8", FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0x8000, 0x8fff).rw("av_bank9", FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0x9000, 0x9fff).rw("av_bank10", FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0xa000, 0xafff).rw("av_bank11", FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0xb000, 0xbfff).rw("av_bank12", FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0xc000, 0xcfff).rw("av_bank13", FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0xd000, 0xdfff).rw("av_bank14", FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0xe000, 0xefff).rw("av_bank15", FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0xf000, 0xfbff).rw("av_bank16", FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
for (int bank = 0; bank < 16; bank++)
{
map(bank << 12, (bank << 12) | 0x0fff).rw(m_avbank[bank], FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
}
map(0xfc00, 0xfc7f).ram();
map(0xfc80, 0xfcff).rw(FUNC(fm7_state::fm7_main_shared_r), FUNC(fm7_state::fm7_main_shared_w));
// I/O space (FD00-FDFF)
@ -1634,22 +1622,10 @@ void fm7_state::fm16_sub_mem(address_map &map)
void fm7_state::fm77av_mem(address_map &map)
{
map(0x0000, 0x0fff).rw("av_bank1", FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0x1000, 0x1fff).rw("av_bank2", FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0x2000, 0x2fff).rw("av_bank3", FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0x3000, 0x3fff).rw("av_bank4", FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0x4000, 0x4fff).rw("av_bank5", FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0x5000, 0x5fff).rw("av_bank6", FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0x6000, 0x6fff).rw("av_bank7", FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0x7000, 0x7fff).rw("av_bank8", FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0x8000, 0x8fff).rw("av_bank9", FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0x9000, 0x9fff).rw("av_bank10", FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0xa000, 0xafff).rw("av_bank11", FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0xb000, 0xbfff).rw("av_bank12", FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0xc000, 0xcfff).rw("av_bank13", FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0xd000, 0xdfff).rw("av_bank14", FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0xe000, 0xefff).rw("av_bank15", FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0xf000, 0xfbff).rw("av_bank16", FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
for (int bank = 0; bank < 16; bank++)
{
map(bank << 12, (bank << 12) | 0x0fff).rw(m_avbank[bank], FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
}
map(0xfc00, 0xfc7f).ram();
map(0xfc80, 0xfcff).rw(FUNC(fm7_state::fm7_main_shared_r), FUNC(fm7_state::fm7_main_shared_w));
// I/O space (FD00-FDFF)
@ -2058,14 +2034,6 @@ static void fm7_floppies(device_slot_interface &device)
}
#define MCFG_ADDRESS_BANK(tag) \
MCFG_DEVICE_ADD(tag, ADDRESS_MAP_BANK, 0) \
MCFG_DEVICE_PROGRAM_MAP(fm7_banked_mem) \
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE) \
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8) \
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000)
MACHINE_CONFIG_START(fm7_state::fm7)
/* basic machine hardware */
MCFG_DEVICE_ADD("maincpu", MC6809, 16.128_MHz_XTAL / 2)
@ -2188,22 +2156,10 @@ MACHINE_CONFIG_START(fm7_state::fm77av)
MCFG_MACHINE_START_OVERRIDE(fm7_state,fm77av)
MCFG_ADDRESS_BANK("av_bank1")
MCFG_ADDRESS_BANK("av_bank2")
MCFG_ADDRESS_BANK("av_bank3")
MCFG_ADDRESS_BANK("av_bank4")
MCFG_ADDRESS_BANK("av_bank5")
MCFG_ADDRESS_BANK("av_bank6")
MCFG_ADDRESS_BANK("av_bank7")
MCFG_ADDRESS_BANK("av_bank8")
MCFG_ADDRESS_BANK("av_bank9")
MCFG_ADDRESS_BANK("av_bank10")
MCFG_ADDRESS_BANK("av_bank11")
MCFG_ADDRESS_BANK("av_bank12")
MCFG_ADDRESS_BANK("av_bank13")
MCFG_ADDRESS_BANK("av_bank14")
MCFG_ADDRESS_BANK("av_bank15")
MCFG_ADDRESS_BANK("av_bank16")
for (int bank = 0; bank < 16; bank++)
{
ADDRESS_MAP_BANK(config, m_avbank[bank]).set_map(&fm7_state::fm7_banked_mem).set_options(ENDIANNESS_LITTLE, 8, 32, 0x1000);
}
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
@ -2261,22 +2217,10 @@ MACHINE_CONFIG_START(fm7_state::fm11)
MCFG_MACHINE_START_OVERRIDE(fm7_state,fm11)
MCFG_ADDRESS_BANK("av_bank1")
MCFG_ADDRESS_BANK("av_bank2")
MCFG_ADDRESS_BANK("av_bank3")
MCFG_ADDRESS_BANK("av_bank4")
MCFG_ADDRESS_BANK("av_bank5")
MCFG_ADDRESS_BANK("av_bank6")
MCFG_ADDRESS_BANK("av_bank7")
MCFG_ADDRESS_BANK("av_bank8")
MCFG_ADDRESS_BANK("av_bank9")
MCFG_ADDRESS_BANK("av_bank10")
MCFG_ADDRESS_BANK("av_bank11")
MCFG_ADDRESS_BANK("av_bank12")
MCFG_ADDRESS_BANK("av_bank13")
MCFG_ADDRESS_BANK("av_bank14")
MCFG_ADDRESS_BANK("av_bank15")
MCFG_ADDRESS_BANK("av_bank16")
for (int bank = 0; bank < 16; bank++)
{
ADDRESS_MAP_BANK(config, m_avbank[bank]).set_map(&fm7_state::fm7_banked_mem).set_options(ENDIANNESS_LITTLE, 8, 32, 0x1000);
}
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)

7
src/mame/drivers/funkball.cpp
View File

@ -778,12 +778,7 @@ MACHINE_CONFIG_START(funkball_state::funkball)
ide_controller_device &ide(IDE_CONTROLLER(config, "ide").options(ata_devices, "hdd", nullptr, true));
ide.irq_handler().set("pic8259_2", FUNC(pic8259_device::ir6_w));
MCFG_DEVICE_ADD("flashbank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(flashbank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x10000)
ADDRESS_MAP_BANK(config, "flashbank").set_map(&funkball_state::flashbank_map).set_options(ENDIANNESS_LITTLE, 32, 32, 0x10000);
/* video hardware */
MCFG_DEVICE_ADD("voodoo_0", VOODOO_1, STD_VOODOO_1_CLOCK)

114
src/mame/drivers/gimix.cpp
View File

@ -75,22 +75,7 @@ public:
, m_acia2(*this, "acia2")
, m_acia3(*this, "acia3")
, m_acia4(*this, "acia4")
, m_bank1(*this, "bank1")
, m_bank2(*this, "bank2")
, m_bank3(*this, "bank3")
, m_bank4(*this, "bank4")
, m_bank5(*this, "bank5")
, m_bank6(*this, "bank6")
, m_bank7(*this, "bank7")
, m_bank8(*this, "bank8")
, m_bank9(*this, "bank9")
, m_bank10(*this, "bank10")
, m_bank11(*this, "bank11")
, m_bank12(*this, "bank12")
, m_bank13(*this, "bank13")
, m_bank14(*this, "bank14")
, m_bank15(*this, "bank15")
, m_bank16(*this, "bank16")
, m_bank(*this, "bank%u", 1U)
, m_rombank1(*this, "rombank1")
, m_rombank2(*this, "rombank2")
, m_fixedrombank(*this, "fixedrombank")
@ -153,22 +138,7 @@ private:
required_device<acia6850_device> m_acia3;
required_device<acia6850_device> m_acia4;
required_device<address_map_bank_device> m_bank1;
required_device<address_map_bank_device> m_bank2;
required_device<address_map_bank_device> m_bank3;
required_device<address_map_bank_device> m_bank4;
required_device<address_map_bank_device> m_bank5;
required_device<address_map_bank_device> m_bank6;
required_device<address_map_bank_device> m_bank7;
required_device<address_map_bank_device> m_bank8;
required_device<address_map_bank_device> m_bank9;
required_device<address_map_bank_device> m_bank10;
required_device<address_map_bank_device> m_bank11;
required_device<address_map_bank_device> m_bank12;
required_device<address_map_bank_device> m_bank13;
required_device<address_map_bank_device> m_bank14;
required_device<address_map_bank_device> m_bank15;
required_device<address_map_bank_device> m_bank16;
required_device_array<address_map_bank_device, 16> m_bank;
required_memory_bank m_rombank1;
required_memory_bank m_rombank2;
required_memory_bank m_fixedrombank;
@ -198,22 +168,10 @@ void gimix_state::gimix_banked_mem(address_map &map)
void gimix_state::gimix_mem(address_map &map)
{
map(0x0000, 0x0fff).rw(m_bank1, FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0x1000, 0x1fff).rw(m_bank2, FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0x2000, 0x2fff).rw(m_bank3, FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0x3000, 0x3fff).rw(m_bank4, FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0x4000, 0x4fff).rw(m_bank5, FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0x5000, 0x5fff).rw(m_bank6, FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0x6000, 0x6fff).rw(m_bank7, FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0x7000, 0x7fff).rw(m_bank8, FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0x8000, 0x8fff).rw(m_bank9, FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0x9000, 0x9fff).rw(m_bank10, FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0xa000, 0xafff).rw(m_bank11, FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0xb000, 0xbfff).rw(m_bank12, FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0xc000, 0xcfff).rw(m_bank13, FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0xd000, 0xdfff).rw(m_bank14, FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0xe000, 0xefff).rw(m_bank15, FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
map(0xf000, 0xfeff).rw(m_bank16, FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
for (int bank = 0; bank < 16; bank++)
{
map(bank << 12, (bank << 12) | 0x0fff).rw(m_bank[bank], FUNC(address_map_bank_device::read8), FUNC(address_map_bank_device::write8));
}
map(0xff00, 0xffff).bankr("fixedrombank").w(FUNC(gimix_state::system_w));
}
@ -227,13 +185,9 @@ INPUT_PORTS_END
void gimix_state::refresh_memory()
{
int x;
address_map_bank_device* banknum[16] = { m_bank1, m_bank2, m_bank3, m_bank4, m_bank5, m_bank6, m_bank7, m_bank8,
m_bank9, m_bank10, m_bank11, m_bank12, m_bank13, m_bank14, m_bank15, m_bank16};
for(x=0;x<16;x++) // for each bank
for (int bank = 0; bank < 16; bank++)
{
banknum[x]->set_bank(m_task_banks[m_task][x]);
m_bank[bank]->set_bank(m_task_banks[m_task][bank]);
}
}
@ -261,10 +215,7 @@ WRITE8_MEMBER( gimix_state::system_w )
}
if(offset >= 0xf0) // Dynamic Address Translation RAM (write only)
{
address_map_bank_device* banknum[16] = { m_bank1, m_bank2, m_bank3, m_bank4, m_bank5, m_bank6, m_bank7, m_bank8,
m_bank9, m_bank10, m_bank11, m_bank12, m_bank13, m_bank14, m_bank15, m_bank16};
banknum[offset-0xf0]->set_bank(data & 0x0f);
m_bank[offset-0xf0]->set_bank(data & 0x0f);
m_task_banks[m_task][offset-0xf0] = data & 0x0f;
logerror("SYS: Bank %i set to physical bank %02x\n",offset-0xf0,data);
}
@ -490,22 +441,10 @@ void gimix_state::machine_start()
// install any extra RAM
if(m_ram->size() > 65536)
{
m_bank1->space(AS_PROGRAM).install_readwrite_bank(0x10000,m_ram->size()-1,"upper_ram");
m_bank2->space(AS_PROGRAM).install_readwrite_bank(0x10000,m_ram->size()-1,"upper_ram");
m_bank3->space(AS_PROGRAM).install_readwrite_bank(0x10000,m_ram->size()-1,"upper_ram");
m_bank4->space(AS_PROGRAM).install_readwrite_bank(0x10000,m_ram->size()-1,"upper_ram");
m_bank5->space(AS_PROGRAM).install_readwrite_bank(0x10000,m_ram->size()-1,"upper_ram");
m_bank6->space(AS_PROGRAM).install_readwrite_bank(0x10000,m_ram->size()-1,"upper_ram");
m_bank7->space(AS_PROGRAM).install_readwrite_bank(0x10000,m_ram->size()-1,"upper_ram");
m_bank8->space(AS_PROGRAM).install_readwrite_bank(0x10000,m_ram->size()-1,"upper_ram");
m_bank9->space(AS_PROGRAM).install_readwrite_bank(0x10000,m_ram->size()-1,"upper_ram");
m_bank10->space(AS_PROGRAM).install_readwrite_bank(0x10000,m_ram->size()-1,"upper_ram");
m_bank11->space(AS_PROGRAM).install_readwrite_bank(0x10000,m_ram->size()-1,"upper_ram");
m_bank12->space(AS_PROGRAM).install_readwrite_bank(0x10000,m_ram->size()-1,"upper_ram");
m_bank13->space(AS_PROGRAM).install_readwrite_bank(0x10000,m_ram->size()-1,"upper_ram");
m_bank14->space(AS_PROGRAM).install_readwrite_bank(0x10000,m_ram->size()-1,"upper_ram");
m_bank15->space(AS_PROGRAM).install_readwrite_bank(0x10000,m_ram->size()-1,"upper_ram");
m_bank16->space(AS_PROGRAM).install_readwrite_bank(0x10000,m_ram->size()-1,"upper_ram");
for (int bank = 0; bank < 16; bank++)
{
m_bank[bank]->space(AS_PROGRAM).install_readwrite_bank(0x10000,m_ram->size()-1,"upper_ram");
}
}
m_floppy0->get_device()->set_rpm(300);
m_floppy1->get_device()->set_rpm(300);
@ -541,13 +480,6 @@ static void gimix_floppies(device_slot_interface &device)
device.option_add("8dd", FLOPPY_8_DSDD);
}
#define MCFG_ADDRESS_BANK(tag) \
MCFG_DEVICE_ADD(tag, ADDRESS_MAP_BANK, 0) \
MCFG_DEVICE_PROGRAM_MAP(gimix_banked_mem) \
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE) \
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8) \
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000)
MACHINE_CONFIG_START(gimix_state::gimix)
// basic machine hardware
MCFG_DEVICE_ADD("maincpu", MC6809, 8_MHz_XTAL)
@ -618,22 +550,10 @@ MACHINE_CONFIG_START(gimix_state::gimix)
acia_clock.signal_handler().append(m_acia2, FUNC(acia6850_device::write_rxc));
/* banking */
MCFG_ADDRESS_BANK("bank1")
MCFG_ADDRESS_BANK("bank2")
MCFG_ADDRESS_BANK("bank3")
MCFG_ADDRESS_BANK("bank4")
MCFG_ADDRESS_BANK("bank5")
MCFG_ADDRESS_BANK("bank6")
MCFG_ADDRESS_BANK("bank7")
MCFG_ADDRESS_BANK("bank8")
MCFG_ADDRESS_BANK("bank9")
MCFG_ADDRESS_BANK("bank10")
MCFG_ADDRESS_BANK("bank11")
MCFG_ADDRESS_BANK("bank12")
MCFG_ADDRESS_BANK("bank13")
MCFG_ADDRESS_BANK("bank14")
MCFG_ADDRESS_BANK("bank15")
MCFG_ADDRESS_BANK("bank16")
for (int bank = 0; bank < 16; bank++)
{
ADDRESS_MAP_BANK(config, m_bank[bank]).set_map(&gimix_state::gimix_banked_mem).set_options(ENDIANNESS_LITTLE, 8, 32, 0x1000);
}
/* internal ram */
MCFG_RAM_ADD(RAM_TAG)

6
src/mame/drivers/goldnpkr.cpp
View File

@ -4705,11 +4705,7 @@ MACHINE_CONFIG_START(blitz_state::megadpkr)
MCFG_DEVICE_ADD("maincpu", M6502, CPU_CLOCK)
MCFG_DEVICE_PROGRAM_MAP(megadpkr_map)
MCFG_DEVICE_ADD("bankdev", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(megadpkr_banked_map)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
ADDRESS_MAP_BANK(config, "bankdev").set_map(&blitz_state::megadpkr_banked_map).set_data_width(8).set_addr_width(16).set_stride(0x1000);
MCFG_DEVICE_ADD("mcu", M68705P5, CPU_CLOCK) /* unknown */
MCFG_M68705_PORTB_W_CB(WRITE8(*this, blitz_state, mcu_portb_w))

7
src/mame/drivers/hp80.cpp
View File

@ -1336,12 +1336,7 @@ MACHINE_CONFIG_START(hp85_state::hp85)
MCFG_DEVICE_PROGRAM_MAP(cpu_mem_map)
MCFG_DEVICE_IRQ_ACKNOWLEDGE_DRIVER(hp85_state , irq_callback)
MCFG_DEVICE_ADD("rombank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(rombank_mem_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(21)
MCFG_ADDRESS_MAP_BANK_STRIDE(HP80_OPTROM_SIZE)
ADDRESS_MAP_BANK(config, "rombank").set_map(&hp85_state::rombank_mem_map).set_options(ENDIANNESS_LITTLE, 8, 21, HP80_OPTROM_SIZE);
MCFG_SCREEN_ADD("screen" , RASTER)
MCFG_SCREEN_RAW_PARAMS(MASTER_CLOCK / 2 , 312 , 0 , 256 , 256 , 0 , 192)

14
src/mame/drivers/hp_ipc.cpp
View File

@ -789,12 +789,7 @@ MACHINE_CONFIG_END
MACHINE_CONFIG_START(hp_ipc_state::hp_ipc)
hp_ipc_base(config);
MCFG_DEVICE_ADD("bankdev", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(hp_ipc_mem_inner_9807a)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(25)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000000)
ADDRESS_MAP_BANK(config, "bankdev").set_map(&hp_ipc_state::hp_ipc_mem_inner_9807a).set_options(ENDIANNESS_BIG, 16, 25, 0x1000000);
// 16kw/32kb video RAM
m_gpu->set_vram_size(16);
@ -815,12 +810,7 @@ MACHINE_CONFIG_END
MACHINE_CONFIG_START(hp_ipc_state::hp9808a)
hp_ipc_base(config);
MCFG_DEVICE_ADD("bankdev", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(hp_ipc_mem_inner_9808a)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(25)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000000)
ADDRESS_MAP_BANK(config, "bankdev").set_map(&hp_ipc_state::hp_ipc_mem_inner_9808a).set_options(ENDIANNESS_BIG, 16, 25, 0x1000000);
// 64kw/128kb video RAM
m_gpu->set_vram_size(64);

22
src/mame/drivers/hunter2.cpp
View File

@ -420,24 +420,10 @@ MACHINE_CONFIG_START(hunter2_state::hunter2)
MCFG_NVRAM_ADD_0FILL("nvram")
MCFG_DEVICE_ADD("bank1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(hunter2_banked_mem)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
MCFG_DEVICE_ADD("bank2", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(hunter2_banked_mem)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
MCFG_DEVICE_ADD("bank3", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(hunter2_banked_mem)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
ADDRESS_MAP_BANK(config, "bank1").set_map(&hunter2_state::hunter2_banked_mem).set_endianness(ENDIANNESS_LITTLE).set_data_width(8).set_stride(0x4000);
ADDRESS_MAP_BANK(config, "bank2").set_map(&hunter2_state::hunter2_banked_mem).set_endianness(ENDIANNESS_LITTLE).set_data_width(8).set_stride(0x4000);
ADDRESS_MAP_BANK(config, "bank3").set_map(&hunter2_state::hunter2_banked_mem).set_endianness(ENDIANNESS_LITTLE).set_data_width(8).set_stride(0x4000);
ADDRESS_MAP_BANK(config, "bank4").set_map(&hunter2_state::hunter2_banked_mem).set_endianness(ENDIANNESS_LITTLE).set_data_width(8).set_stride(0x4000);
MACHINE_CONFIG_END
/* ROM definition */

7
src/mame/drivers/itt3030.cpp
View File

@ -722,12 +722,7 @@ MACHINE_CONFIG_START(itt3030_state::itt3030)
MCFG_SCREEN_PALETTE("palette")
/* devices */
MCFG_DEVICE_ADD("lowerbank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(lower48_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(20)
MCFG_ADDRESS_MAP_BANK_STRIDE(0xc000)
ADDRESS_MAP_BANK(config, "lowerbank").set_map(&itt3030_state::lower48_map).set_options(ENDIANNESS_LITTLE, 8, 20, 0xc000);
MCFG_DEVICE_ADD("crt5027", CRT5027, 6_MHz_XTAL / 8)
MCFG_TMS9927_CHAR_WIDTH(8)

6
src/mame/drivers/ksys573.cpp
View File

@ -2125,11 +2125,7 @@ MACHINE_CONFIG_START(ksys573_state::konami573)
MCFG_DEVICE_ADD( "pccard1", PCCARD_SLOT, 0 )
MCFG_DEVICE_ADD( "pccard2", PCCARD_SLOT, 0 )
MCFG_DEVICE_ADD( m_flashbank, ADDRESS_MAP_BANK, 0 )
MCFG_DEVICE_PROGRAM_MAP( flashbank_map )
MCFG_ADDRESS_MAP_BANK_ENDIANNESS( ENDIANNESS_LITTLE )
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH( 16 )
MCFG_ADDRESS_MAP_BANK_STRIDE( 0x400000 )
ADDRESS_MAP_BANK( config, m_flashbank ).set_map( &ksys573_state::flashbank_map ).set_options( ENDIANNESS_LITTLE, 16, 32, 0x400000 );
/* video hardware */
MCFG_PSXGPU_ADD( "maincpu", "gpu", CXD8561Q, 0x200000, XTAL(53'693'175) )

24
src/mame/drivers/laser3k.cpp
View File

@ -987,26 +987,10 @@ MACHINE_CONFIG_START(laser3k_state::laser3k)
MCFG_PALETTE_INIT_OWNER(laser3k_state, laser3k)
/* memory banking */
MCFG_DEVICE_ADD("bank0", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(banks_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
MCFG_DEVICE_ADD("bank1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(banks_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
MCFG_DEVICE_ADD("bank2", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(banks_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
MCFG_DEVICE_ADD("bank3", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(banks_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
ADDRESS_MAP_BANK(config, "bank0").set_map(&laser3k_state::banks_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x4000);
ADDRESS_MAP_BANK(config, "bank1").set_map(&laser3k_state::banks_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x4000);
ADDRESS_MAP_BANK(config, "bank2").set_map(&laser3k_state::banks_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x4000);
ADDRESS_MAP_BANK(config, "bank3").set_map(&laser3k_state::banks_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x4000);
MCFG_RAM_ADD("mainram")
MCFG_RAM_DEFAULT_SIZE("192K")

7
src/mame/drivers/lethal.cpp
View File

@ -499,12 +499,7 @@ MACHINE_CONFIG_START(lethal_state::lethalen)
MCFG_DEVICE_ADD("soundcpu", Z80, MAIN_CLOCK/4) /* verified on pcb */
MCFG_DEVICE_PROGRAM_MAP(le_sound)
MCFG_DEVICE_ADD("bank4000", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank4000_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
ADDRESS_MAP_BANK(config, "bank4000").set_map(&lethal_state::bank4000_map).set_options(ENDIANNESS_BIG, 8, 16, 0x4000);
MCFG_DEVICE_ADD("eeprom", EEPROM_SERIAL_ER5911_8BIT)

15
src/mame/drivers/lynx.cpp
View File

@ -80,19 +80,8 @@ MACHINE_CONFIG_START(lynx_state::lynx)
MCFG_DEVICE_PROGRAM_MAP(lynx_mem)
MCFG_QUANTUM_TIME(attotime::from_hz(60))
MCFG_DEVICE_ADD("bank_fc00", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(lynx_fc00_mem)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(9)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x100)
MCFG_DEVICE_ADD("bank_fd00", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(lynx_fd00_mem)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(9)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x100)
ADDRESS_MAP_BANK(config, "bank_fc00").set_map(&lynx_state::lynx_fc00_mem).set_options(ENDIANNESS_LITTLE, 8, 9, 0x100);
ADDRESS_MAP_BANK(config, "bank_fd00").set_map(&lynx_state::lynx_fd00_mem).set_options(ENDIANNESS_LITTLE, 8, 9, 0x100);
/* video hardware */
MCFG_SCREEN_ADD("screen", LCD)

15
src/mame/drivers/majorpkr.cpp
View File

@ -1010,19 +1010,8 @@ MACHINE_CONFIG_START(majorpkr_state::majorpkr)
MCFG_DEVICE_IO_MAP(portmap)
MCFG_DEVICE_VBLANK_INT_DRIVER("screen", majorpkr_state, irq0_line_hold)
MCFG_DEVICE_ADD("palette_bank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(palettebanks)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(13)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x0800)
MCFG_DEVICE_ADD("vram_bank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vrambanks)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(13)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x0800)
ADDRESS_MAP_BANK(config, "palette_bank").set_map(&majorpkr_state::palettebanks).set_options(ENDIANNESS_LITTLE, 8, 13, 0x800);
ADDRESS_MAP_BANK(config, "vram_bank").set_map(&majorpkr_state::vrambanks).set_options(ENDIANNESS_LITTLE, 8, 13, 0x800);
MCFG_NVRAM_ADD_0FILL("nvram")

7
src/mame/drivers/mastboy.cpp
View File

@ -822,12 +822,7 @@ MACHINE_CONFIG_START(mastboy_state::mastboy)
m_outlatch->q_out_cb<3>().set("msm", FUNC(msm5205_device::reset_w));
m_outlatch->q_out_cb<4>().set("earom", FUNC(eeprom_parallel_28xx_device::oe_w));
MCFG_DEVICE_ADD("bank_c000", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank_c000_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
ADDRESS_MAP_BANK(config, "bank_c000").set_map(&mastboy_state::bank_c000_map).set_options(ENDIANNESS_LITTLE, 8, 22, 0x4000);
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)

6
src/mame/drivers/miniframe.cpp
View File

@ -235,11 +235,7 @@ MACHINE_CONFIG_START(miniframe_state::miniframe)
MCFG_RAM_EXTRA_OPTIONS("2M")
// RAM/ROM bank
MCFG_DEVICE_ADD("ramrombank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(ramrombank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x400000)
ADDRESS_MAP_BANK(config, "ramrombank").set_map(&miniframe_state::ramrombank_map).set_options(ENDIANNESS_BIG, 16, 32, 0x400000);
// floppy
MCFG_DEVICE_ADD("wd2797", WD2797, 1000000)

7
src/mame/drivers/mquake.cpp
View File

@ -319,12 +319,7 @@ MACHINE_CONFIG_START(mquake_state::mquake)
MCFG_DEVICE_ADD("maincpu", M68000, amiga_state::CLK_7M_NTSC)
MCFG_DEVICE_PROGRAM_MAP(main_map)
MCFG_DEVICE_ADD("overlay", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(overlay_512kb_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x200000)
ADDRESS_MAP_BANK(config, "overlay").set_map(&amiga_state::overlay_512kb_map).set_options(ENDIANNESS_BIG, 16, 22, 0x200000);
MCFG_NVRAM_ADD_0FILL("nvram")

13
src/mame/drivers/mstation.cpp
View File

@ -474,17 +474,8 @@ MACHINE_CONFIG_START(mstation_state::mstation)
MCFG_DEVICE_ADD("rtc", RP5C01, XTAL(32'768))
MCFG_RP5C01_OUT_ALARM_CB(WRITELINE(*this, mstation_state, rtc_irq))
MCFG_DEVICE_ADD("bank0", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(mstation_banked_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
MCFG_DEVICE_ADD("bank1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(mstation_banked_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
ADDRESS_MAP_BANK(config, "bank0").set_map(&mstation_state::mstation_banked_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x4000);
ADDRESS_MAP_BANK(config, "bank1").set_map(&mstation_state::mstation_banked_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x4000);
/* internal ram */
MCFG_RAM_ADD(RAM_TAG)

6
src/mame/drivers/mtouchxl.cpp
View File

@ -256,11 +256,7 @@ MACHINE_CONFIG_START(mtxl_state::at486)
MCFG_RAM_DEFAULT_SIZE("32M") // Early XL games had 8 MB RAM, 6000 and later require 32MB
/* bankdev for dxxxx */
MCFG_DEVICE_ADD("dbank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(dbank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x10000)
ADDRESS_MAP_BANK(config, "dbank").set_map(&mtxl_state::dbank_map).set_options(ENDIANNESS_LITTLE, 32, 32, 0x10000);
/* Flash ROM */
MCFG_AMD_29F040_ADD("flash")

21
src/mame/drivers/mz2500.cpp
View File

@ -1793,15 +1793,6 @@ static void mz2500_floppies(device_slot_interface &device)
device.option_add("dd", FLOPPY_35_DD);
}
#define MCFG_ADDRESS_BANK(tag) \
MCFG_DEVICE_ADD(tag, ADDRESS_MAP_BANK, 0) \
MCFG_DEVICE_PROGRAM_MAP(mz2500_bank_window_map) \
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE) \
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8) \
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(16+3) \
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
MACHINE_CONFIG_START(mz2500_state::mz2500)
/* basic machine hardware */
MCFG_DEVICE_ADD("maincpu", Z80, 6000000)
@ -1810,14 +1801,10 @@ MACHINE_CONFIG_START(mz2500_state::mz2500)
MCFG_DEVICE_VBLANK_INT_DRIVER("screen", mz2500_state, mz2500_vbl)
MCFG_DEVICE_IRQ_ACKNOWLEDGE_DRIVER(mz2500_state,mz2500_irq_ack)
MCFG_ADDRESS_BANK("rambank0")
MCFG_ADDRESS_BANK("rambank1")
MCFG_ADDRESS_BANK("rambank2")
MCFG_ADDRESS_BANK("rambank3")
MCFG_ADDRESS_BANK("rambank4")
MCFG_ADDRESS_BANK("rambank5")
MCFG_ADDRESS_BANK("rambank6")
MCFG_ADDRESS_BANK("rambank7")
for (int bank = 0; bank < 8; bank++)
{
ADDRESS_MAP_BANK(config, m_rambank[bank]).set_map(&mz2500_state::mz2500_bank_window_map).set_options(ENDIANNESS_LITTLE, 8, 16+3, 0x2000);
}
MCFG_DEVICE_ADD("i8255_0", I8255, 0)
MCFG_I8255_IN_PORTA_CB(READ8(*this, mz2500_state, mz2500_porta_r))

16
src/mame/drivers/mz700.cpp
View File

@ -377,12 +377,8 @@ MACHINE_CONFIG_START(mz_state::mz700)
MCFG_DEVICE_ADD("maincpu", Z80, XTAL(17'734'470)/5)
MCFG_DEVICE_PROGRAM_MAP(mz700_mem)
MCFG_DEVICE_IO_MAP(mz700_io)
MCFG_DEVICE_ADD("banke", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(mz700_banke)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
ADDRESS_MAP_BANK(config, "banke").set_map(&mz_state::mz700_banke).set_options(ENDIANNESS_LITTLE, 8, 16, 0x2000);
MCFG_MACHINE_RESET_OVERRIDE(mz_state, mz700)
@ -442,12 +438,8 @@ MACHINE_CONFIG_START(mz_state::mz800)
MCFG_DEVICE_MODIFY("maincpu")
MCFG_DEVICE_PROGRAM_MAP(mz800_mem)
MCFG_DEVICE_IO_MAP(mz800_io)
MCFG_DEVICE_ADD("bankf", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(mz800_bankf)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
ADDRESS_MAP_BANK(config, "bankf").set_map(&mz_state::mz800_bankf).set_options(ENDIANNESS_LITTLE, 8, 16, 0x2000);
MCFG_MACHINE_RESET_OVERRIDE(mz_state, mz800)
MCFG_GFXDECODE_MODIFY("gfxdecode", gfx_mz800)

13
src/mame/drivers/nds.cpp
View File

@ -979,17 +979,8 @@ MACHINE_CONFIG_START(nds_state::nds)
MCFG_DEVICE_PROGRAM_MAP(nds_arm9_map)
// WRAM
MCFG_DEVICE_ADD("nds7wram", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(nds7_wram_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x8000)
MCFG_DEVICE_ADD("nds9wram", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(nds9_wram_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x8000)
ADDRESS_MAP_BANK(config, "nds7wram").set_map(&nds_state::nds7_wram_map).set_options(ENDIANNESS_LITTLE, 32, 32, 0x8000);
ADDRESS_MAP_BANK(config, "nds9wram").set_map(&nds_state::nds9_wram_map).set_options(ENDIANNESS_LITTLE, 32, 32, 0x8000);
MACHINE_CONFIG_END
/* Help identifying the region and revisions of the set would be greatly appreciated! */

7
src/mame/drivers/nes_vt.cpp
View File

@ -1367,12 +1367,7 @@ MACHINE_CONFIG_START(nes_vt_state::nes_vt)
MCFG_PPU_VT03_READ_BG_CB(READ8(*this, nes_vt_state,chr_r))
MCFG_PPU_VT03_READ_SP_CB(READ8(*this, nes_vt_state,spr_r))
MCFG_DEVICE_ADD("prg", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(prg_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(15)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x8000)
ADDRESS_MAP_BANK(config, "prg").set_map(&nes_vt_state::prg_map).set_options(ENDIANNESS_LITTLE, 8, 15, 0x8000);
MCFG_NES_CONTROL_PORT_ADD("ctrl1", nes_control_port1_devices, "joypad")
//MCFG_NESCTRL_BRIGHTPIXEL_CB(nes_state, bright_pixel)

6
src/mame/drivers/octopus.cpp
View File

@ -1015,11 +1015,7 @@ MACHINE_CONFIG_START(octopus_state::octopus)
MCFG_DEVICE_ADDRESS_MAP(0, octopus_vram)
MCFG_VIDEO_SET_SCREEN("screen")
MCFG_DEVICE_ADD("z80_bank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(octopus_mem)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x10000)
ADDRESS_MAP_BANK(config, "z80_bank").set_map(&octopus_state::octopus_mem).set_options(ENDIANNESS_LITTLE, 8, 32, 0x10000);
MCFG_RAM_ADD("ram")
MCFG_RAM_DEFAULT_SIZE("256K")

15
src/mame/drivers/parodius.cpp
View File

@ -240,19 +240,8 @@ MACHINE_CONFIG_START(parodius_state::parodius)
MCFG_DEVICE_ADD("audiocpu", Z80, 3579545)
MCFG_DEVICE_PROGRAM_MAP(parodius_sound_map) /* NMIs are triggered by the 053260 */
MCFG_DEVICE_ADD("bank0000", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank0000_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(13)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x0800)
MCFG_DEVICE_ADD("bank2000", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank2000_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(12)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x0800)
ADDRESS_MAP_BANK(config, "bank0000").set_map(&parodius_state::bank0000_map).set_options(ENDIANNESS_BIG, 8, 13, 0x800);
ADDRESS_MAP_BANK(config, "bank2000").set_map(&parodius_state::bank2000_map).set_options(ENDIANNESS_BIG, 8, 12, 0x800);
MCFG_WATCHDOG_ADD("watchdog")

6
src/mame/drivers/pasogo.cpp
View File

@ -552,11 +552,7 @@ MACHINE_CONFIG_START(pasogo_state::pasogo)
MCFG_DEVICE_VBLANK_INT_DRIVER("screen", pasogo_state, pasogo_interrupt)
MCFG_DEVICE_IRQ_ACKNOWLEDGE_DEVICE("mb:pic8259", pic8259_device, inta_cb)
MCFG_DEVICE_ADD("ems", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(emsbank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
ADDRESS_MAP_BANK(config, "ems").set_map(&pasogo_state::emsbank_map).set_options(ENDIANNESS_LITTLE, 16, 32, 0x4000);
MCFG_IBM5160_MOTHERBOARD_ADD("mb", "maincpu")

7
src/mame/drivers/pc88va.cpp
View File

@ -1661,12 +1661,7 @@ MACHINE_CONFIG_START(pc88va_state::pc88va)
MCFG_PIT8253_CLK1(8000000) /* BEEP frequency setting */
MCFG_PIT8253_CLK2(8000000) /* RS232C baud rate setting */
MCFG_DEVICE_ADD("sysbank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(sysbank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(18+4)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x40000)
ADDRESS_MAP_BANK(config, "sysbank").set_map(&pc88va_state::sysbank_map).set_options(ENDIANNESS_LITTLE, 16, 18+4, 0x40000);
SPEAKER(config, "mono").front_center();
MCFG_DEVICE_ADD("ym", YM2203, 3993600) //unknown clock / divider

7
src/mame/drivers/pc9801.cpp
View File

@ -2428,12 +2428,7 @@ MACHINE_CONFIG_START(pc9801_state::pc9801rs)
pc9801_common(config);
MCFG_DEVICE_ADD("ipl_bank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(ipl_bank)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(18)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x18000)
ADDRESS_MAP_BANK(config, "ipl_bank").set_map(&pc9801_state::ipl_bank).set_options(ENDIANNESS_LITTLE, 16, 18, 0x18000);
MCFG_MACHINE_START_OVERRIDE(pc9801_state,pc9801rs)
MCFG_MACHINE_RESET_OVERRIDE(pc9801_state,pc9801rs)

7
src/mame/drivers/pcxt.cpp
View File

@ -507,12 +507,7 @@ MACHINE_CONFIG_START(pcxt_state::filetto)
MCFG_RAM_ADD(RAM_TAG)
MCFG_RAM_DEFAULT_SIZE("640K")
MCFG_DEVICE_ADD("bank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(18)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x10000)
ADDRESS_MAP_BANK(config, "bank").set_map(&pcxt_state::bank_map).set_options(ENDIANNESS_LITTLE, 8, 18, 0x10000);
MACHINE_CONFIG_END
MACHINE_CONFIG_START(pcxt_state::tetriskr)

32
src/mame/drivers/pengadvb.cpp
View File

@ -222,34 +222,10 @@ MACHINE_CONFIG_START(pengadvb_state::pengadvb)
MCFG_DEVICE_PROGRAM_MAP(program_mem)
MCFG_DEVICE_IO_MAP(io_mem)
// -_-;
MCFG_DEVICE_ADD("page0", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank_mem)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(18)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x10000)
MCFG_DEVICE_ADD("page1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank_mem)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(18)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x10000)
MCFG_DEVICE_ADD("page2", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank_mem)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(18)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x10000)
MCFG_DEVICE_ADD("page3", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank_mem)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(18)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x10000)
ADDRESS_MAP_BANK(config, "page0").set_map(&pengadvb_state::bank_mem).set_options(ENDIANNESS_LITTLE, 8, 18, 0x10000);
ADDRESS_MAP_BANK(config, "page1").set_map(&pengadvb_state::bank_mem).set_options(ENDIANNESS_LITTLE, 8, 18, 0x10000);
ADDRESS_MAP_BANK(config, "page2").set_map(&pengadvb_state::bank_mem).set_options(ENDIANNESS_LITTLE, 8, 18, 0x10000);
ADDRESS_MAP_BANK(config, "page3").set_map(&pengadvb_state::bank_mem).set_options(ENDIANNESS_LITTLE, 8, 18, 0x10000);
MCFG_DEVICE_ADD("ppi8255", I8255, 0)
MCFG_I8255_IN_PORTA_CB(READ8(*this, pengadvb_state, pengadvb_ppi_port_a_r))

7
src/mame/drivers/poly.cpp
View File

@ -253,12 +253,7 @@ MACHINE_CONFIG_START(poly_state::poly)
MCFG_DEVICE_ADD("maincpu", MC6809, 12.0576_MHz_XTAL / 3)
MCFG_DEVICE_PROGRAM_MAP(poly_mem)
MCFG_DEVICE_ADD("bankdev", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(poly_bank)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(17)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x10000)
ADDRESS_MAP_BANK(config, "bankdev").set_map(&poly_state::poly_bank).set_options(ENDIANNESS_LITTLE, 8, 17, 0x10000);
MCFG_INPUT_MERGER_ANY_HIGH("irqs")
MCFG_INPUT_MERGER_OUTPUT_HANDLER(INPUTLINE("maincpu", M6809_IRQ_LINE))

14
src/mame/drivers/psychic5.cpp
View File

@ -727,12 +727,7 @@ MACHINE_CONFIG_START(psychic5_state::psychic5)
MCFG_DEVICE_PROGRAM_MAP(psychic5_main_map)
MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", psychic5_state, scanline, "screen", 0, 1)
MCFG_DEVICE_ADD("vrambank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(psychic5_vrambank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(14)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
ADDRESS_MAP_BANK(config, "vrambank").set_map(&psychic5_state::psychic5_vrambank_map).set_options(ENDIANNESS_LITTLE, 8, 14, 0x2000);
MCFG_DEVICE_ADD("audiocpu", Z80, XTAL(5'000'000))
MCFG_DEVICE_PROGRAM_MAP(psychic5_sound_map)
@ -781,12 +776,7 @@ MACHINE_CONFIG_START(psychic5_state::bombsa)
MCFG_DEVICE_PROGRAM_MAP(bombsa_main_map)
MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", psychic5_state, scanline, "screen", 0, 1)
MCFG_DEVICE_ADD("vrambank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bombsa_vrambank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(14)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
ADDRESS_MAP_BANK(config, "vrambank").set_map(&psychic5_state::bombsa_vrambank_map).set_options(ENDIANNESS_LITTLE, 8, 14, 0x2000);
MCFG_DEVICE_ADD("audiocpu", Z80, XTAL(5'000'000) )
MCFG_DEVICE_PROGRAM_MAP(bombsa_sound_map)

7
src/mame/drivers/pwrview.cpp
View File

@ -434,12 +434,7 @@ MACHINE_CONFIG_START(pwrview_state::pwrview)
MCFG_MC6845_CHAR_WIDTH(32) // ??
MCFG_MC6845_UPDATE_ROW_CB(pwrview_state, update_row)
MCFG_DEVICE_ADD("bios_bank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bios_bank)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(17)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x8000)
ADDRESS_MAP_BANK(config, "bios_bank").set_map(&pwrview_state::bios_bank).set_options(ENDIANNESS_LITTLE, 16, 17, 0x8000);
MACHINE_CONFIG_END
ROM_START(pwrview)

7
src/mame/drivers/rad_eu3a05.cpp
View File

@ -1153,12 +1153,7 @@ MACHINE_CONFIG_START(radica_eu3a05_state::radicasi)
MCFG_DEVICE_PROGRAM_MAP(radicasi_map)
MCFG_DEVICE_VBLANK_INT_DRIVER("screen", radica_eu3a05_state, interrupt)
MCFG_DEVICE_ADD("bank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(radicasi_bank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(24)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x8000)
ADDRESS_MAP_BANK(config, "bank").set_map(&radica_eu3a05_state::radicasi_bank_map).set_options(ENDIANNESS_LITTLE, 8, 24, 0x8000);
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)

7
src/mame/drivers/rad_eu3a14.cpp
View File

@ -781,12 +781,7 @@ MACHINE_CONFIG_START(radica_eu3a14_state::radica_eu3a14)
MCFG_DEVICE_PROGRAM_MAP(radica_eu3a14_map)
MCFG_DEVICE_VBLANK_INT_DRIVER("screen", radica_eu3a14_state, interrupt)
MCFG_DEVICE_ADD("bank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(24)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x8000)
ADDRESS_MAP_BANK(config, "bank").set_map(&radica_eu3a14_state::bank_map).set_options(ENDIANNESS_LITTLE, 8, 24, 0x8000);
MCFG_DEVICE_ADD("gfxdecode", GFXDECODE, "palette", gfx_helper)

26
src/mame/drivers/rex6000.cpp
View File

@ -918,17 +918,8 @@ MACHINE_CONFIG_START(rex6000_state::rex6000)
MCFG_PALETTE_INIT_OWNER(rex6000_state, rex6000)
MCFG_DEVICE_ADD("gfxdecode", GFXDECODE, "palette", gfx_rex6000)
MCFG_DEVICE_ADD("bank0", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(rex6000_banked_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
MCFG_DEVICE_ADD("bank1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(rex6000_banked_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
ADDRESS_MAP_BANK(config, "bank0").set_map(&rex6000_state::rex6000_banked_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x2000);
ADDRESS_MAP_BANK(config, "bank1").set_map(&rex6000_state::rex6000_banked_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x2000);
MCFG_DEVICE_ADD( "ns16550", NS16550, XTAL(1'843'200) )
MCFG_INS8250_OUT_TX_CB(WRITELINE("serport", rs232_port_device, write_txd))
@ -1006,17 +997,8 @@ MACHINE_CONFIG_START(oz750_state::oz750)
MCFG_PALETTE_ADD("palette", 2)
MCFG_PALETTE_INIT_OWNER(rex6000_state, rex6000)
MCFG_DEVICE_ADD("bank0", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(oz750_banked_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
MCFG_DEVICE_ADD("bank1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(oz750_banked_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
ADDRESS_MAP_BANK(config, "bank0").set_map(&oz750_state::oz750_banked_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x2000);
ADDRESS_MAP_BANK(config, "bank1").set_map(&oz750_state::oz750_banked_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x2000);
/* quickload */
MCFG_QUICKLOAD_ADD("quickload", oz750_state, oz750, "wzd", 0)

15
src/mame/drivers/simpsons.cpp
View File

@ -333,19 +333,8 @@ MACHINE_CONFIG_START(simpsons_state::simpsons)
MCFG_DEVICE_ADD("audiocpu", Z80, XTAL(3'579'545)) /* verified on pcb */
MCFG_DEVICE_PROGRAM_MAP(z80_map) /* NMIs are generated by the 053260 */
MCFG_DEVICE_ADD("bank0000", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank0000_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(13)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000)
MCFG_DEVICE_ADD("bank2000", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank2000_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(14)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
ADDRESS_MAP_BANK(config, "bank0000").set_map(&simpsons_state::bank0000_map).set_options(ENDIANNESS_BIG, 8, 13, 0x1000);
ADDRESS_MAP_BANK(config, "bank2000").set_map(&simpsons_state::bank2000_map).set_options(ENDIANNESS_BIG, 8, 14, 0x2000);
MCFG_DEVICE_ADD("eeprom", EEPROM_SERIAL_ER5911_8BIT)

7
src/mame/drivers/sitcom.cpp
View File

@ -355,12 +355,7 @@ MACHINE_CONFIG_START(sitcom_state::sitcom)
MCFG_I8085A_SID(READLINE(*this, sitcom_state, sid_line))
MCFG_I8085A_SOD(WRITELINE(*this, sitcom_state, sod_led))
MCFG_DEVICE_ADD("bank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(sitcom_bank)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x8000)
ADDRESS_MAP_BANK(config, "bank").set_map(&sitcom_state::sitcom_bank).set_options(ENDIANNESS_LITTLE, 8, 16, 0x8000);
MCFG_CLOCK_ADD("100hz", 100)
MCFG_CLOCK_SIGNAL_HANDLER(INPUTLINE("maincpu", I8085_RST75_LINE))

6
src/mame/drivers/sk1.cpp
View File

@ -90,10 +90,8 @@ void sk1_state::sk1_memory(address_map &map)
MACHINE_CONFIG_START(sk1_state::sk1)
MCFG_DEVICE_ADD("dummy", ADDRESS_MAP_BANK, 0) // just to attach the memory map to something until I can work out what the CPU core is
MCFG_DEVICE_PROGRAM_MAP(sk1_memory)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(16)
// just to attach the memory map to something until I can work out what the CPU core is
ADDRESS_MAP_BANK(config, "dummy").set_map(&sk1_state::sk1_memory).set_data_width(8).set_addr_width(16);
MACHINE_CONFIG_END

6
src/mame/drivers/sm7238.cpp
View File

@ -369,11 +369,7 @@ MACHINE_CONFIG_START(sm7238_state::sm7238)
MCFG_DEVICE_IO_MAP(sm7238_io)
MCFG_DEVICE_IRQ_ACKNOWLEDGE_DEVICE("pic8259", pic8259_device, inta_cb)
MCFG_DEVICE_ADD("videobank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(videobank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
ADDRESS_MAP_BANK(config, "videobank").set_map(&sm7238_state::videobank_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x2000);
MCFG_NVRAM_ADD_0FILL("nvram")

47
src/mame/drivers/socrates.cpp
View File

@ -1480,23 +1480,9 @@ MACHINE_CONFIG_START(socrates_state::socrates)
MCFG_QUANTUM_TIME(attotime::from_hz(60))
MCFG_DEVICE_VBLANK_INT_DRIVER("screen", socrates_state, assert_irq)
MCFG_DEVICE_ADD("rombank1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(socrates_rombank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
MCFG_DEVICE_ADD("rambank1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(socrates_rambank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
MCFG_DEVICE_ADD("rambank2", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(socrates_rambank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
ADDRESS_MAP_BANK(config, "rombank1").set_map(&socrates_state::socrates_rombank_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x4000);
ADDRESS_MAP_BANK(config, "rambank1").set_map(&socrates_state::socrates_rambank_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x4000);
ADDRESS_MAP_BANK(config, "rambank2").set_map(&socrates_state::socrates_rambank_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x4000);
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
@ -1547,29 +1533,10 @@ MACHINE_CONFIG_START(iqunlimz_state::iqunlimz)
MCFG_DEVICE_IO_MAP(iqunlimz_io)
MCFG_DEVICE_VBLANK_INT_DRIVER("screen", iqunlimz_state, assert_irq)
MCFG_DEVICE_ADD("rombank1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(iqunlimz_rombank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
MCFG_DEVICE_ADD("rombank2", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(iqunlimz_rombank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
MCFG_DEVICE_ADD("rambank1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(iqunlimz_rambank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
MCFG_DEVICE_ADD("rambank2", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(iqunlimz_rambank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
ADDRESS_MAP_BANK(config, "rombank1").set_map(&iqunlimz_state::iqunlimz_rombank_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x4000);
ADDRESS_MAP_BANK(config, "rombank2").set_map(&iqunlimz_state::iqunlimz_rombank_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x4000);
ADDRESS_MAP_BANK(config, "rambank1").set_map(&iqunlimz_state::iqunlimz_rambank_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x4000);
ADDRESS_MAP_BANK(config, "rambank2").set_map(&iqunlimz_state::iqunlimz_rambank_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x4000);
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)

48
src/mame/drivers/sun2.cpp
View File

@ -622,32 +622,16 @@ MACHINE_CONFIG_START(sun2_state::sun2vme)
MCFG_RAM_DEFAULT_VALUE(0x00)
// MMU Type 0 device space
MCFG_DEVICE_ADD("type0", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype0space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000000)
ADDRESS_MAP_BANK(config, "type0").set_map(&sun2_state::vmetype0space_map).set_options(ENDIANNESS_BIG, 16, 32, 0x1000000);
// MMU Type 1 device space
MCFG_DEVICE_ADD("type1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype1space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000000)
ADDRESS_MAP_BANK(config, "type1").set_map(&sun2_state::vmetype1space_map).set_options(ENDIANNESS_BIG, 16, 32, 0x1000000);
// MMU Type 2 device space
MCFG_DEVICE_ADD("type2", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype2space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000000)
ADDRESS_MAP_BANK(config, "type2").set_map(&sun2_state::vmetype2space_map).set_options(ENDIANNESS_BIG, 16, 32, 0x1000000);
// MMU Type 3 device space
MCFG_DEVICE_ADD("type3", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype3space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000000)
ADDRESS_MAP_BANK(config, "type3").set_map(&sun2_state::vmetype3space_map).set_options(ENDIANNESS_BIG, 16, 32, 0x1000000);
MCFG_SCREEN_ADD("bwtwo", RASTER)
MCFG_SCREEN_UPDATE_DRIVER(sun2_state, bw2_update)
@ -694,32 +678,16 @@ MACHINE_CONFIG_START(sun2_state::sun2mbus)
MCFG_RAM_DEFAULT_VALUE(0x00)
// MMU Type 0 device space
MCFG_DEVICE_ADD("type0", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(mbustype0space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000000)
ADDRESS_MAP_BANK(config, "type0").set_map(&sun2_state::mbustype0space_map).set_options(ENDIANNESS_BIG, 16, 32, 0x1000000);
// MMU Type 1 device space
MCFG_DEVICE_ADD("type1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(mbustype1space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000000)
ADDRESS_MAP_BANK(config, "type1").set_map(&sun2_state::mbustype1space_map).set_options(ENDIANNESS_BIG, 16, 32, 0x1000000);
// MMU Type 2 device space
MCFG_DEVICE_ADD("type2", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(mbustype2space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000000)
ADDRESS_MAP_BANK(config, "type2").set_map(&sun2_state::mbustype2space_map).set_options(ENDIANNESS_BIG, 16, 32, 0x1000000);
// MMU Type 3 device space
MCFG_DEVICE_ADD("type3", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(mbustype3space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000000)
ADDRESS_MAP_BANK(config, "type3").set_map(&sun2_state::mbustype3space_map).set_options(ENDIANNESS_BIG, 16, 32, 0x1000000);
MCFG_SCREEN_ADD("bwtwo", RASTER)
MCFG_SCREEN_UPDATE_DRIVER(sun2_state, bw2_update)

48
src/mame/drivers/sun3.cpp
View File

@ -989,32 +989,16 @@ MACHINE_CONFIG_START(sun3_state::sun3)
MCFG_NVRAM_ADD_0FILL("nvram")
// MMU Type 0 device space
MCFG_DEVICE_ADD("type0", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype0space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
ADDRESS_MAP_BANK(config, "type0").set_map(&sun3_state::vmetype0space_map).set_options(ENDIANNESS_BIG, 32, 32, 0x80000000);
// MMU Type 1 device space
MCFG_DEVICE_ADD("type1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype1space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
ADDRESS_MAP_BANK(config, "type1").set_map(&sun3_state::vmetype1space_map).set_options(ENDIANNESS_BIG, 32, 32, 0x80000000);
// MMU Type 2 device space
MCFG_DEVICE_ADD("type2", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype2space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
ADDRESS_MAP_BANK(config, "type2").set_map(&sun3_state::vmetype2space_map).set_options(ENDIANNESS_BIG, 32, 32, 0x80000000);
// MMU Type 3 device space
MCFG_DEVICE_ADD("type3", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype3space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
ADDRESS_MAP_BANK(config, "type3").set_map(&sun3_state::vmetype3space_map).set_options(ENDIANNESS_BIG, 32, 32, 0x80000000);
MCFG_TIMER_DRIVER_ADD_PERIODIC("timer", sun3_state, sun3_timer, attotime::from_hz(100))
@ -1095,32 +1079,16 @@ MACHINE_CONFIG_START(sun3_state::sun3_50)
MCFG_RAM_DEFAULT_VALUE(0x00)
// MMU Type 0 device space
MCFG_DEVICE_ADD("type0", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype0space_novram_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
ADDRESS_MAP_BANK(config, "type0").set_map(&sun3_state::vmetype0space_novram_map).set_options(ENDIANNESS_BIG, 32, 32, 0x80000000);
// MMU Type 1 device space
MCFG_DEVICE_ADD("type1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype1space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
ADDRESS_MAP_BANK(config, "type1").set_map(&sun3_state::vmetype1space_map).set_options(ENDIANNESS_BIG, 32, 32, 0x80000000);
// MMU Type 2 device space
MCFG_DEVICE_ADD("type2", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype2space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
ADDRESS_MAP_BANK(config, "type2").set_map(&sun3_state::vmetype2space_map).set_options(ENDIANNESS_BIG, 32, 32, 0x80000000);
// MMU Type 3 device space
MCFG_DEVICE_ADD("type3", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype3space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
ADDRESS_MAP_BANK(config, "type3").set_map(&sun3_state::vmetype3space_map).set_options(ENDIANNESS_BIG, 32, 32, 0x80000000);
MCFG_DEVICE_ADD(SCC1_TAG, SCC8530N, 4.9152_MHz_XTAL)
MCFG_Z80SCC_OUT_TXDA_CB(WRITELINE(KEYBOARD_TAG, sun_keyboard_port_device, write_txd))

24
src/mame/drivers/sun4.cpp
View File

@ -1919,18 +1919,10 @@ MACHINE_CONFIG_START(sun4_state::sun4)
MCFG_FLOPPY_DRIVE_ADD("fdc:0", sun_floppies, "35hd", sun4_state::floppy_formats)
// MMU Type 0 device space
MCFG_DEVICE_ADD("type0", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(type0space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
ADDRESS_MAP_BANK(config, "type0").set_map(&sun4_state::type0space_map).set_options(ENDIANNESS_BIG, 32, 32, 0x80000000);
// MMU Type 1 device space
MCFG_DEVICE_ADD("type1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(type1space_s4_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
ADDRESS_MAP_BANK(config, "type1").set_map(&sun4_state::type1space_s4_map).set_options(ENDIANNESS_BIG, 32, 32, 0x80000000);
// Keyboard/mouse
MCFG_DEVICE_ADD(SCC1_TAG, SCC8530N, 4.9152_MHz_XTAL)
@ -1983,18 +1975,10 @@ MACHINE_CONFIG_START(sun4_state::sun4c)
MCFG_FLOPPY_DRIVE_ADD("fdc:0", sun_floppies, "35hd", sun4_state::floppy_formats)
// MMU Type 0 device space
MCFG_DEVICE_ADD("type0", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(type0space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
ADDRESS_MAP_BANK(config, "type0").set_map(&sun4_state::type0space_map).set_options(ENDIANNESS_BIG, 32, 32, 0x80000000);
// MMU Type 1 device space
MCFG_DEVICE_ADD("type1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(type1space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
ADDRESS_MAP_BANK(config, "type1").set_map(&sun4_state::type1space_map).set_options(ENDIANNESS_BIG, 32, 32, 0x80000000);
// Keyboard/mouse
MCFG_DEVICE_ADD(SCC1_TAG, SCC8530N, 4.9152_MHz_XTAL)

7
src/mame/drivers/surpratk.cpp
View File

@ -176,12 +176,7 @@ MACHINE_CONFIG_START(surpratk_state::surpratk)
MCFG_DEVICE_VBLANK_INT_DRIVER("screen", surpratk_state, surpratk_interrupt)
MCFG_KONAMICPU_LINE_CB(WRITE8(*this, surpratk_state, banking_callback))
MCFG_DEVICE_ADD("bank0000", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank0000_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(13)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x800)
ADDRESS_MAP_BANK(config, "bank0000").set_map(&surpratk_state::bank0000_map).set_options(ENDIANNESS_BIG, 8, 13, 0x800);
MCFG_WATCHDOG_ADD("watchdog")

6
src/mame/drivers/svi318.cpp
View File

@ -538,11 +538,7 @@ MACHINE_CONFIG_START(svi3x8_state::svi318)
MCFG_RAM_ADD(RAM_TAG)
MCFG_RAM_DEFAULT_SIZE("16K")
MCFG_DEVICE_ADD("io", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(svi3x8_io_bank)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(9)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x100)
ADDRESS_MAP_BANK(config, "io").set_map(&svi3x8_state::svi3x8_io_bank).set_data_width(8).set_addr_width(9).set_stride(0x100);
MCFG_DEVICE_ADD("ppi", I8255, 0)
MCFG_I8255_IN_PORTA_CB(READ8(*this, svi3x8_state, ppi_port_a_r))

16
src/mame/drivers/taito_l.cpp
View File

@ -1452,19 +1452,11 @@ WRITE8_MEMBER(fhawk_state::portA_w)
//logerror ("YM2203 bank change val=%02x %s\n", data & 0x03, machine().describe_context() );
}
#define TC0090LVC_BANK_ADD(_tag) \
MCFG_DEVICE_ADD(_tag, ADDRESS_MAP_BANK, 0) \
MCFG_DEVICE_PROGRAM_MAP(tc0090lvc_map) \
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE) \
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8) \
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(20) \
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000)
MACHINE_CONFIG_START(taitol_state::l_system_video)
TC0090LVC_BANK_ADD("rambank1")
TC0090LVC_BANK_ADD("rambank2")
TC0090LVC_BANK_ADD("rambank3")
TC0090LVC_BANK_ADD("rambank4")
for (int bank = 0; bank < 4; bank++)
{
ADDRESS_MAP_BANK(config, m_ram_bnks[bank]).set_map(&taitol_state::tc0090lvc_map).set_options(ENDIANNESS_LITTLE, 8, 20, 0x1000);
}
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_REFRESH_RATE(60)

6
src/mame/drivers/taitogn.cpp
View File

@ -729,11 +729,7 @@ MACHINE_CONFIG_START(taitogn_state::coh3002t)
MCFG_INTEL_TE28F160_ADD("sndflash1")
MCFG_INTEL_TE28F160_ADD("sndflash2")
MCFG_DEVICE_ADD("flashbank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(flashbank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x8000000)
ADDRESS_MAP_BANK(config, "flashbank").set_map(&taitogn_state::flashbank_map).set_options(ENDIANNESS_LITTLE, 16, 32, 0x8000000);
// 5MHz NEC uPD78081 MCU:
// we don't have a 78K0 emulation core yet..

7
src/mame/drivers/tandy1t.cpp
View File

@ -729,12 +729,7 @@ MACHINE_CONFIG_START(tandy1000_state::t1000rl)
tandy1000_101key(config);
MCFG_DEVICE_ADD("biosbank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(biosbank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(20)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x10000)
ADDRESS_MAP_BANK(config, "biosbank").set_map(&tandy1000_state::biosbank_map).set_options(ENDIANNESS_LITTLE, 16, 20, 0x10000);
MCFG_MACHINE_RESET_OVERRIDE(tandy1000_state,tandy1000rl)
MCFG_DEVICE_MODIFY(RAM_TAG)

11
src/mame/drivers/thunderx.cpp
View File

@ -648,12 +648,7 @@ MACHINE_CONFIG_START(thunderx_state::scontra)
MCFG_DEVICE_ADD("audiocpu", Z80, XTAL(3'579'545)) /* verified on pcb */
MCFG_DEVICE_PROGRAM_MAP(scontra_sound_map)
MCFG_DEVICE_ADD("bank5800", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(scontra_bank5800_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(12)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x0800)
ADDRESS_MAP_BANK(config, m_bank5800).set_map(&thunderx_state::scontra_bank5800_map).set_options(ENDIANNESS_BIG, 8, 12, 0x800);
MCFG_WATCHDOG_ADD("watchdog")
@ -712,9 +707,7 @@ MACHINE_CONFIG_START(thunderx_state::thunderx)
MCFG_DEVICE_MODIFY("audiocpu")
MCFG_DEVICE_PROGRAM_MAP(thunderx_sound_map)
MCFG_DEVICE_MODIFY("bank5800")
MCFG_DEVICE_PROGRAM_MAP(thunderx_bank5800_map)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(13)
m_bank5800->set_map(&thunderx_state::thunderx_bank5800_map).set_addr_width(13);
MCFG_DEVICE_REMOVE("k007232")
MACHINE_CONFIG_END

27
src/mame/drivers/ti85.cpp
View File

@ -701,29 +701,10 @@ MACHINE_CONFIG_START(ti85_state::ti83p)
MCFG_PALETTE_ENTRIES(2)
MCFG_PALETTE_INIT_OWNER(ti85_state, ti82 )
MCFG_DEVICE_ADD("membank1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(ti83p_banked_mem)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
MCFG_DEVICE_ADD("membank2", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(ti83p_banked_mem)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
MCFG_DEVICE_ADD("membank3", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(ti83p_banked_mem)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
MCFG_DEVICE_ADD("membank4", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(ti83p_banked_mem)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
ADDRESS_MAP_BANK(config, "membank1").set_map(&ti85_state::ti83p_banked_mem).set_options(ENDIANNESS_LITTLE, 8, 32, 0x4000);
ADDRESS_MAP_BANK(config, "membank2").set_map(&ti85_state::ti83p_banked_mem).set_options(ENDIANNESS_LITTLE, 8, 32, 0x4000);
ADDRESS_MAP_BANK(config, "membank3").set_map(&ti85_state::ti83p_banked_mem).set_options(ENDIANNESS_LITTLE, 8, 32, 0x4000);
ADDRESS_MAP_BANK(config, "membank4").set_map(&ti85_state::ti83p_banked_mem).set_options(ENDIANNESS_LITTLE, 8, 32, 0x4000);
MCFG_DEVICE_ADD("t6a04", T6A04, 0)
MCFG_T6A04_SIZE(96, 64)

6
src/mame/drivers/tk2000.cpp
View File

@ -599,11 +599,7 @@ MACHINE_CONFIG_START(tk2000_state::tk2000)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.00)
/* /INH banking */
MCFG_DEVICE_ADD(A2_UPPERBANK_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(inhbank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
ADDRESS_MAP_BANK(config, A2_UPPERBANK_TAG).set_map(&tk2000_state::inhbank_map).set_options(ENDIANNESS_LITTLE, 8, 32, 0x4000);
MCFG_RAM_ADD(RAM_TAG)
MCFG_RAM_DEFAULT_SIZE("64K")

12
src/mame/drivers/tnzs.cpp
View File

@ -887,14 +887,10 @@ void tnzs_base_state::mainbank_map(address_map &map)
map(0x08000, 0x1ffff).rom().region(":maincpu", 0x8000);
}
MACHINE_CONFIG_START(tnzs_base_state::tnzs_mainbank)
MCFG_DEVICE_ADD("mainbank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(mainbank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(17)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
MACHINE_CONFIG_END
void tnzs_base_state::tnzs_mainbank(machine_config &config)
{
ADDRESS_MAP_BANK(config, "mainbank").set_map(&tnzs_base_state::mainbank_map).set_options(ENDIANNESS_LITTLE, 8, 17, 0x4000);
}
#define COMMON_IN2\
PORT_START("IN2")\

7
src/mame/drivers/tosh1000.cpp
View File

@ -260,12 +260,7 @@ MACHINE_CONFIG_START(tosh1000_state::tosh1000)
MCFG_DEVICE_IO_MAP(tosh1000_io)
MCFG_DEVICE_IRQ_ACKNOWLEDGE_DEVICE("mb:pic8259", pic8259_device, inta_cb)
MCFG_DEVICE_ADD("bankdev", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(tosh1000_romdos)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(20)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x10000)
ADDRESS_MAP_BANK(config, "bankdev").set_map(&tosh1000_state::tosh1000_romdos).set_options(ENDIANNESS_LITTLE, 8, 20, 0x10000);
MCFG_MACHINE_RESET_OVERRIDE(tosh1000_state, tosh1000)

6
src/mame/drivers/unixpc.cpp
View File

@ -379,11 +379,7 @@ MACHINE_CONFIG_START(unixpc_state::unixpc)
MCFG_RAM_EXTRA_OPTIONS("2M")
// RAM/ROM bank
MCFG_DEVICE_ADD("ramrombank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(ramrombank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x400000)
ADDRESS_MAP_BANK(config, "ramrombank").set_map(&unixpc_state::ramrombank_map).set_options(ENDIANNESS_BIG, 16, 32, 0x400000);
// floppy
MCFG_DEVICE_ADD("wd2797", WD2797, 40_MHz_XTAL / 40) // 1PCK (CPU clock) divided by custom DMA chip

7
src/mame/drivers/upscope.cpp
View File

@ -271,12 +271,7 @@ MACHINE_CONFIG_START(upscope_state::upscope)
MCFG_DEVICE_ADD("maincpu", M68000, amiga_state::CLK_7M_NTSC)
MCFG_DEVICE_PROGRAM_MAP(main_map)
MCFG_DEVICE_ADD("overlay", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(overlay_512kb_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x200000)
ADDRESS_MAP_BANK(config, "overlay").set_map(&amiga_state::overlay_512kb_map).set_options(ENDIANNESS_BIG, 16, 22, 0x200000);
MCFG_NVRAM_ADD_0FILL("nvram")

6
src/mame/drivers/vcs80.cpp
View File

@ -237,11 +237,7 @@ MACHINE_CONFIG_START(vcs80_state::vcs80)
MCFG_RAM_DEFAULT_SIZE("1K")
/* bankdev */
MCFG_DEVICE_ADD("bdmem", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vcs80_bd_mem)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x10000)
ADDRESS_MAP_BANK(config, "bdmem").set_map(&vcs80_state::vcs80_bd_mem).set_options(ENDIANNESS_BIG, 8, 32, 0x10000);
MACHINE_CONFIG_END
/* ROMs */

15
src/mame/drivers/vendetta.cpp
View File

@ -435,19 +435,8 @@ MACHINE_CONFIG_START(vendetta_state::vendetta)
MCFG_DEVICE_VBLANK_INT_DRIVER("screen", vendetta_state, irq)
MCFG_KONAMICPU_LINE_CB(WRITE8(*this, vendetta_state, banking_callback))
MCFG_DEVICE_ADD("videobank0", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(videobank0_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(13)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000)
MCFG_DEVICE_ADD("videobank1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(videobank1_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(13)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000)
ADDRESS_MAP_BANK(config, "videobank0").set_map(&vendetta_state::videobank0_map).set_options(ENDIANNESS_BIG, 8, 13, 0x1000);
ADDRESS_MAP_BANK(config, "videobank1").set_map(&vendetta_state::videobank1_map).set_options(ENDIANNESS_BIG, 8, 13, 0x1000);
MCFG_DEVICE_ADD("audiocpu", Z80, XTAL(3'579'545)) /* verified with PCB */
MCFG_DEVICE_PROGRAM_MAP(sound_map)

7
src/mame/drivers/vt240.cpp
View File

@ -666,12 +666,7 @@ MACHINE_CONFIG_START(vt240_state::vt240)
MCFG_I8085A_SOD(WRITELINE(*this, vt240_state, i8085_rdy_w))
MCFG_I8085A_SID(READLINE(*this, vt240_state, i8085_sid_r))
MCFG_DEVICE_ADD("bank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(20)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000)
ADDRESS_MAP_BANK(config, "bank").set_map(&vt240_state::bank_map).set_options(ENDIANNESS_LITTLE, 16, 20, 0x1000);
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_RAW_PARAMS(XTAL(16'097'280), 1024, 0, 800, 629, 0, 480)

7
src/mame/drivers/wardner.cpp
View File

@ -385,12 +385,7 @@ MACHINE_CONFIG_START(wardner_state::wardner)
MCFG_DEVICE_PROGRAM_MAP(main_program_map)
MCFG_DEVICE_IO_MAP(main_io_map)
MCFG_DEVICE_ADD("membank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(main_bank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(18)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x8000)
ADDRESS_MAP_BANK(config, "membank").set_map(&wardner_state::main_bank_map).set_options(ENDIANNESS_LITTLE, 8, 18, 0x8000);
MCFG_DEVICE_ADD("audiocpu", Z80, XTAL(14'000'000)/4) /* 3.5MHz */
MCFG_DEVICE_PROGRAM_MAP(sound_program_map)

14
src/mame/drivers/williams.cpp
View File

@ -1554,12 +1554,7 @@ MACHINE_CONFIG_START(williams_state::defender)
MCFG_DEVICE_MODIFY("soundcpu")
MCFG_DEVICE_PROGRAM_MAP(defender_sound_map)
MCFG_DEVICE_ADD("bankc000", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(defender_bankc000_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000)
ADDRESS_MAP_BANK(config, "bankc000").set_map(&williams_state::defender_bankc000_map).set_options(ENDIANNESS_BIG, 8, 16, 0x1000);
MCFG_MACHINE_START_OVERRIDE(williams_state,defender)
MCFG_MACHINE_RESET_OVERRIDE(williams_state,defender)
@ -1751,12 +1746,7 @@ MACHINE_CONFIG_START(williams2_state::williams2)
MCFG_DEVICE_ADD("soundcpu", M6808, MASTER_CLOCK/3) /* yes, this is different from the older games */
MCFG_DEVICE_PROGRAM_MAP(williams2_sound_map)
MCFG_DEVICE_ADD("bank8000", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(williams2_bank8000_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(12)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x0800)
ADDRESS_MAP_BANK(config, "bank8000").set_map(&williams2_state::williams2_bank8000_map).set_options(ENDIANNESS_BIG, 8, 12, 0x800);
MCFG_MACHINE_START_OVERRIDE(williams2_state,williams2)
MCFG_MACHINE_RESET_OVERRIDE(williams2_state,williams2)

7
src/mame/drivers/wmg.cpp
View File

@ -526,12 +526,7 @@ MACHINE_CONFIG_START(wmg_state::wmg)
MCFG_NVRAM_ADD_0FILL("nvram")
MCFG_DEVICE_ADD("bankc000", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(wmg_banked_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000)
ADDRESS_MAP_BANK(config, "bankc000").set_map(&wmg_state::wmg_banked_map).set_options(ENDIANNESS_BIG, 8, 16, 0x1000);
// set a timer to go off every 32 scanlines, to toggle the VA11 line and update the screen
MCFG_TIMER_DRIVER_ADD_SCANLINE("scan_timer", williams_state, williams_va11_callback, "screen", 0, 32)

7
src/mame/drivers/x1.cpp
View File

@ -2206,12 +2206,7 @@ MACHINE_CONFIG_START(x1_state::x1)
MCFG_DEVICE_IO_MAP(x1_io)
MCFG_Z80_DAISY_CHAIN(x1_daisy)
MCFG_DEVICE_ADD("iobank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(x1_io_banks)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(17)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x10000)
ADDRESS_MAP_BANK(config, "iobank").set_map(&x1_state::x1_io_banks).set_options(ENDIANNESS_LITTLE, 8, 17, 0x10000);
MCFG_DEVICE_ADD("ctc", Z80CTC, MAIN_CLOCK/4)
MCFG_Z80CTC_INTR_CB(INPUTLINE("x1_cpu", INPUT_LINE_IRQ0))

7
src/mame/drivers/x1twin.cpp
View File

@ -417,12 +417,7 @@ MACHINE_CONFIG_START(x1twin_state::x1twin)
MCFG_DEVICE_IO_MAP(x1_io)
MCFG_Z80_DAISY_CHAIN(x1_daisy)
MCFG_DEVICE_ADD("iobank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(x1_io_banks)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(17)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x10000)
ADDRESS_MAP_BANK(config, "iobank").set_map(&x1_state::x1_io_banks).set_options(ENDIANNESS_LITTLE, 8, 17, 0x10000);
MCFG_DEVICE_ADD("ctc", Z80CTC, MAIN_CLOCK/4)
MCFG_Z80CTC_INTR_CB(INPUTLINE("x1_cpu", INPUT_LINE_IRQ0))

7
src/mame/drivers/xavix.cpp
View File

@ -638,12 +638,7 @@ MACHINE_CONFIG_START(xavix_state::xavix)
MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", xavix_state, scanline_cb, "screen", 0, 1)
MCFG_DEVICE_ADD("lowbus", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(xavix_lowbus_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(24)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x8000)
ADDRESS_MAP_BANK(config, "lowbus").set_map(&xavix_state::xavix_lowbus_map).set_options(ENDIANNESS_LITTLE, 8, 24, 0x8000);
/* video hardware */

7
src/mame/drivers/zn.cpp
View File

@ -2200,12 +2200,7 @@ MACHINE_CONFIG_START(zn_state::nbajamex)
MCFG_MACHINE_START_OVERRIDE(zn_state, nbajamex)
MCFG_MACHINE_RESET_OVERRIDE(zn_state, nbajamex)
MCFG_DEVICE_ADD("nbajamex_bankmap", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(nbajamex_bank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(24)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x800000)
ADDRESS_MAP_BANK(config, "nbajamex_bankmap").set_map(&zn_state::nbajamex_bank_map).set_options(ENDIANNESS_LITTLE, 32, 24, 0x800000);
MCFG_DEVICE_ADD("rax", ACCLAIM_RAX, 0)
MACHINE_CONFIG_END

7
src/mame/machine/cedar_magnet_sprite.cpp
View File

@ -227,12 +227,7 @@ MACHINE_CONFIG_START(cedar_magnet_sprite_device::device_add_mconfig)
// MCFG_Z80PIO_IN_PB_CB(READ8(*this, cedar_magnet_sprite_device, pio2_pb_r))
MCFG_Z80PIO_OUT_PB_CB(WRITE8(*this, cedar_magnet_sprite_device, pio2_pb_w))
MCFG_DEVICE_ADD("sp_sub_ram", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(cedar_magnet_sprite_sub_ram_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(18)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x10000)
ADDRESS_MAP_BANK(config, "sp_sub_ram").set_map(&cedar_magnet_sprite_device::cedar_magnet_sprite_sub_ram_map).set_options(ENDIANNESS_LITTLE, 8, 18, 0x10000);
MACHINE_CONFIG_END

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