mirror of
https://github.com/holub/mame
synced 2025-06-25 22:04:15 +03:00
mips3 -- Added routine for clearing fastram region so that dynamic ram allocation can be mapped to fastram.
atahle -- Added clear cache command. iteagle -- Re-arrange inputs for different games. voodoo_pci -- Add pre-fetchable flag to BAR. iteagle_fpga -- Added memory for eagle1 boards and map gun input. vrc4373 -- Split memory space mapping routines for CPU and PCI spaces and added fastram for CPU.
This commit is contained in:
ted green
parent
7b886584dc
commit
71afdc9758
@ -297,7 +297,7 @@ public:
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TIMER_CALLBACK_MEMBER(compare_int_callback);
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void add_fastram(offs_t start, offs_t end, UINT8 readonly, void *base);
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void clear_fastram(UINT32 select_start);
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void mips3drc_set_options(UINT32 options);
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void mips3drc_add_hotspot(offs_t pc, UINT32 opcode, UINT32 cycles);
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@ -154,6 +154,20 @@ void mips3_device::mips3drc_set_options(UINT32 options)
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m_drcoptions = options;
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}
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/*-------------------------------------------------
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mips3drc_clears_fastram - clears fastram
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region starting at index select_start
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-------------------------------------------------*/
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void mips3_device::clear_fastram(UINT32 select_start)
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{
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for (int i=select_start; i<MIPS3_MAX_FASTRAM; i++) {
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m_fastram[i].start = 0;
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m_fastram[i].end = 0;
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m_fastram[i].readonly = false;
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m_fastram[i].base = NULL;
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}
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m_fastram_select=select_start;
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}
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/*-------------------------------------------------
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mips3drc_add_fastram - add a new fastram
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@ -197,6 +197,10 @@ void ata_hle_device::process_command()
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start_busy(MINIMUM_COMMAND_TIME, PARAM_COMMAND);
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break;
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case IDE_COMMAND_CACHE_FLUSH:
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start_busy(MINIMUM_COMMAND_TIME, PARAM_COMMAND);
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break;
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default:
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LOGPRINT(("IDE unknown command (%02X)\n", m_command));
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m_status |= IDE_STATUS_ERR;
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@ -229,6 +233,10 @@ void ata_hle_device::finished_command()
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set_irq(ASSERT_LINE);
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break;
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case IDE_COMMAND_CACHE_FLUSH:
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m_status |= IDE_STATUS_DRDY;
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break;
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default:
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logerror( "finished_command() unhandled command %02x\n", m_command );
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break;
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@ -125,6 +125,7 @@ protected:
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IDE_COMMAND_WRITE_DMA = 0xca,
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IDE_COMMAND_IDLE_IMMEDIATE = 0xe1,
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IDE_COMMAND_IDLE = 0xe3,
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IDE_COMMAND_CACHE_FLUSH = 0xe7,
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IDE_COMMAND_IDENTIFY_DEVICE = 0xec,
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IDE_COMMAND_SET_FEATURES = 0xef,
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IDE_COMMAND_SECURITY_UNLOCK = 0xf2,
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@ -32,6 +32,7 @@ vrc4373_device::vrc4373_device(const machine_config &mconfig, const char *tag, d
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: pci_host_device(mconfig, VRC4373, "NEC VRC4373 System Controller", tag, owner, clock, "vrc4373", __FILE__),
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m_mem_config("memory_space", ENDIANNESS_LITTLE, 32, 32),
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m_io_config("io_space", ENDIANNESS_LITTLE, 32, 32)
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{
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}
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@ -43,7 +44,7 @@ const address_space_config *vrc4373_device::memory_space_config(address_spacenum
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void vrc4373_device::device_start()
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{
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pci_host_device::device_start();
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m_cpu = machine().device<cpu_device>(cpu_tag);
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m_cpu = machine().device<mips3_device>(cpu_tag);
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m_cpu_space = &m_cpu->space(AS_PROGRAM);
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memory_space = &space(AS_DATA);
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io_space = &space(AS_IO);
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@ -61,39 +62,49 @@ void vrc4373_device::device_start()
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m_ram_base = 0;
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m_simm_size = 1<<21;
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m_simm_base = 0;
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regenerate_config_mapping();
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// ROM size = 1 MB
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m_cpu_space->install_rom (0x1fc00000, 0x1fcfffff, m_region->base());
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m_cpu_space->install_device(0x0f000000, 0x0f0000ff, *static_cast<vrc4373_device *>(this), &vrc4373_device::cpu_map);
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// PCI Configuration also mapped at 0x0f000100
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m_cpu_space->install_device(0x0f000100, 0x0f0001ff, *static_cast<vrc4373_device *>(this), &vrc4373_device::config_map);
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// MIPS drc
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m_cpu->add_fastram(0x1fc00000, 0x1fcfffff, TRUE, m_region->base());
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}
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void vrc4373_device::device_reset()
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{
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pci_device::device_reset();
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memset(m_cpu_regs, 0, sizeof(m_cpu_regs));
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remap_cb();
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regenerate_config_mapping();
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}
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void vrc4373_device::map_extra(UINT64 memory_window_start, UINT64 memory_window_end, UINT64 memory_offset, address_space *memory_space,
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UINT64 io_window_start, UINT64 io_window_end, UINT64 io_offset, address_space *io_space)
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void vrc4373_device::map_cpu_space()
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{
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m_cpu_space->unmap_readwrite(0x00000000, 0xffffffff);
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m_cpu_space->install_rom (0x1fc00000, 0x1fcfffff, m_region->base());
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m_cpu_space->install_device(0x0f000000, 0x0f0000ff, *static_cast<vrc4373_device *>(this), &vrc4373_device::cpu_map);
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// PCI Configuration also mapped at 0x0f000100
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m_cpu_space->install_device(0x0f000100, 0x0f0001ff, *static_cast<vrc4373_device *>(this), &vrc4373_device::config_map);
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UINT32 winStart, winEnd, winSize;
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// VRC4373 is at 0x0f000000 to 0x0f0001ff
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// ROM region starts at 0x1f000000
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m_cpu_space->unmap_readwrite(0x00000000, 0x0effffff);
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m_cpu_space->unmap_readwrite(0x0f000200, 0x1effffff);
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// Clear fastram regions in cpu after rom
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m_cpu->clear_fastram(1);
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if (m_cpu_regs[NREG_BMCR]&0x8) {
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m_cpu_space->install_ram (m_ram_base, m_ram_base+m_ram_size-1, &m_ram[0]);
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m_cpu_space->install_ram(m_ram_base, m_ram_base+m_ram_size-1, &m_ram[0]);
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m_cpu->add_fastram(m_ram_base, m_ram_size-1, FALSE, &m_ram[0]);
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if (LOG_NILE)
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logerror("%s: map_extra ram_size=%08X ram_base=%08X\n", tag(),m_ram_size,m_ram_base);
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logerror("%s: map_cpu_space ram_size=%08X ram_base=%08X\n", tag(),m_ram_size,m_ram_base);
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}
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if (m_cpu_regs[NREG_SIMM1]&0x8) {
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m_cpu_space->install_ram (m_simm_base, m_simm_base+m_simm_size-1, &m_simm[0]);
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m_cpu_space->install_ram(m_simm_base, m_simm_base+m_simm_size-1, &m_simm[0]);
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//m_cpu->add_fastram(m_simm_base, m_simm_size-1, FALSE, &m_simm[0]);
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if (LOG_NILE)
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logerror("%s: map_extra simm_size=%08X simm_base=%08X\n", tag(),m_simm_size,m_simm_base);
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logerror("%s: map_cpu_space simm_size=%08X simm_base=%08X\n", tag(),m_simm_size,m_simm_base);
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}
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// PCI Master Window 1
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if (m_cpu_regs[NREG_PCIMW1]&0x1000) {
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winStart = m_cpu_regs[NREG_PCIMW1]&0xff000000;
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@ -102,7 +113,7 @@ void vrc4373_device::map_extra(UINT64 memory_window_start, UINT64 memory_window_
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m_cpu_space->install_read_handler(winStart, winEnd, 0, 0, read32_delegate(FUNC(vrc4373_device::master1_r), this));
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m_cpu_space->install_write_handler(winStart, winEnd, 0, 0, write32_delegate(FUNC(vrc4373_device::master1_w), this));
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if (LOG_NILE)
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logerror("%s: map_extra Master Window 1 start=%08X end=%08X size=%08X laddr=%08X\n", tag(), winStart, winEnd, winSize, m_pci1_laddr);
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logerror("%s: map_cpu_space Master Window 1 start=%08X end=%08X size=%08X laddr=%08X\n", tag(), winStart, winEnd, winSize, m_pci1_laddr);
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}
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// PCI Master Window 2
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if (m_cpu_regs[NREG_PCIMW2]&0x1000) {
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@ -112,7 +123,7 @@ void vrc4373_device::map_extra(UINT64 memory_window_start, UINT64 memory_window_
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m_cpu_space->install_read_handler(winStart, winEnd, 0, 0, read32_delegate(FUNC(vrc4373_device::master2_r), this));
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m_cpu_space->install_write_handler(winStart, winEnd, 0, 0, write32_delegate(FUNC(vrc4373_device::master2_w), this));
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if (LOG_NILE)
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logerror("%s: map_extra Master Window 2 start=%08X end=%08X size=%08X laddr=%08X\n", tag(), winStart, winEnd, winSize, m_pci2_laddr);
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logerror("%s: map_cpu_space Master Window 2 start=%08X end=%08X size=%08X laddr=%08X\n", tag(), winStart, winEnd, winSize, m_pci2_laddr);
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}
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// PCI IO Window
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if (m_cpu_regs[NREG_PCIMIOW]&0x1000) {
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@ -122,8 +133,15 @@ void vrc4373_device::map_extra(UINT64 memory_window_start, UINT64 memory_window_
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m_cpu_space->install_read_handler(winStart, winEnd, 0, 0, read32_delegate(FUNC(vrc4373_device::master_io_r), this));
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m_cpu_space->install_write_handler(winStart, winEnd, 0, 0, write32_delegate(FUNC(vrc4373_device::master_io_w), this));
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if (LOG_NILE)
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logerror("%s: map_extra IO Window start=%08X end=%08X size=%08X laddr=%08X\n", tag(), winStart, winEnd, winSize, m_pci_io_laddr);
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logerror("%s: map_cpu_space IO Window start=%08X end=%08X size=%08X laddr=%08X\n", tag(), winStart, winEnd, winSize, m_pci_io_laddr);
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}
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}
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void vrc4373_device::map_extra(UINT64 memory_window_start, UINT64 memory_window_end, UINT64 memory_offset, address_space *memory_space,
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UINT64 io_window_start, UINT64 io_window_end, UINT64 io_offset, address_space *io_space)
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{
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UINT32 winStart, winEnd, winSize;
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// PCI Target Window 1
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if (m_cpu_regs[NREG_PCITW1]&0x1000) {
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winStart = m_cpu_regs[NREG_PCITW1]&0xffe00000;
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@ -306,21 +324,23 @@ WRITE32_MEMBER(vrc4373_device::cpu_if_w)
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switch (offset) {
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case NREG_PCIMW1:
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m_pci1_laddr = (data&0xff)<<24;
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remap_cb();
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map_cpu_space();
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break;
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case NREG_PCIMW2:
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m_pci2_laddr = (data&0xff)<<24;
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remap_cb();
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map_cpu_space();
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break;
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case NREG_PCIMIOW:
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m_pci_io_laddr = (data&0xff)<<24;
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remap_cb();
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map_cpu_space();
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break;
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case NREG_PCITW1:
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m_target1_laddr = (data&0x7FF)<<21;
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m_target1_laddr = 0x00000000 | ((data&0x7FF)<<21);
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remap_cb();
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break;
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case NREG_PCITW2:
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m_target2_laddr = (data&0x7FF)<<21;
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m_target2_laddr = 0x00000000 | ((data&0x7FF)<<21);
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remap_cb();
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break;
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case NREG_PCICAR:
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// Bits in reserved area are used for device selection of type 0 config transactions
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@ -374,7 +394,7 @@ WRITE32_MEMBER(vrc4373_device::cpu_if_w)
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m_ram.resize(m_ram_size/4);
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m_ram_base = (data & 0x0fc00000);
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}
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remap_cb();
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map_cpu_space();
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break;
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case NREG_SIMM1:
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if ((data>>3)&0x1) {
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@ -386,7 +406,7 @@ WRITE32_MEMBER(vrc4373_device::cpu_if_w)
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m_simm.resize(m_simm_size/4);
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m_simm_base = (data & 0x0fe00000);
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}
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remap_cb();
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map_cpu_space();
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break;
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default:
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break;
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@ -6,6 +6,7 @@
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#define VRC4373_H
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#include "pci.h"
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#include "cpu/mips/mips3.h"
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#define MCFG_VRC4373_ADD(_tag, _cpu_tag) \
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MCFG_PCI_HOST_ADD(_tag, VRC4373, 0x005B1033, 0x00, 0x00000000) \
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@ -66,7 +67,6 @@ public:
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virtual void map_extra(UINT64 memory_window_start, UINT64 memory_window_end, UINT64 memory_offset, address_space *memory_space,
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UINT64 io_window_start, UINT64 io_window_end, UINT64 io_offset, address_space *io_space);
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void set_cpu_tag(const char *tag);
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virtual DECLARE_ADDRESS_MAP(config_map, 32);
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@ -102,13 +102,15 @@ protected:
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void dma_transfer(int which);
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private:
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cpu_device *m_cpu;
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mips3_device *m_cpu;
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const char *cpu_tag;
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address_space_config m_mem_config, m_io_config;
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DECLARE_ADDRESS_MAP(cpu_map, 32);
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void map_cpu_space();
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UINT32 m_ram_size;
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UINT32 m_ram_base;
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std::vector<UINT32> m_ram;
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@ -117,7 +119,6 @@ private:
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UINT32 m_simm_base;
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std::vector<UINT32> m_simm;
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UINT32 m_cpu_regs[0x7c];
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UINT32 m_pci1_laddr, m_pci2_laddr, m_pci_io_laddr;
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@ -105,7 +105,7 @@ void voodoo_pci_device::device_start()
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}
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pci_device::device_start();
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if (m_type<=TYPE_VOODOO_2) {
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add_map(16*1024*1024, M_MEM, FUNC(voodoo_pci_device::voodoo_reg_map));
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add_map(16*1024*1024, M_MEM | M_PREF, FUNC(voodoo_pci_device::voodoo_reg_map));
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} else {
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add_map(32*1024*1024, M_MEM, FUNC(voodoo_pci_device::banshee_reg_map));
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add_map(32*1024*1024, M_MEM, FUNC(voodoo_pci_device::lfb_map));
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@ -155,7 +155,7 @@ static MACHINE_CONFIG_START( iteagle, iteagle_state )
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/* basic machine hardware */
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MCFG_CPU_ADD("maincpu", VR4310LE, 166666666)
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MCFG_MIPS3_ICACHE_SIZE(16384)
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MCFG_MIPS3_DCACHE_SIZE(16384)
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MCFG_MIPS3_DCACHE_SIZE(8192)
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MCFG_PCI_ROOT_ADD( ":pci")
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MCFG_VRC4373_ADD( ":pci:00.0", ":maincpu")
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@ -171,7 +171,7 @@ static MACHINE_CONFIG_START( iteagle, iteagle_state )
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MCFG_ITEAGLE_EEPROM_ADD( PCI_ID_EEPROM)
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MCFG_SCREEN_ADD("screen", RASTER)
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MCFG_SCREEN_REFRESH_RATE(59)
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MCFG_SCREEN_REFRESH_RATE(60)
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MCFG_SCREEN_SIZE(512, 384)
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MCFG_SCREEN_UPDATE_DEVICE(PCI_ID_VIDEO, voodoo_pci_device, screen_update)
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@ -268,14 +268,14 @@ static INPUT_PORTS_START( iteagle )
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PORT_START("IN1")
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PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
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PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_START1 )
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PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME( "Left/Trigger" )
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PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME( "Right/Pump" )
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PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME( "Left" )
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PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME( "Right" )
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PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_NAME( "Fly By" )
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PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME( "Backspin" )
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PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_UNUSED )
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PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNUSED )
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PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_COIN2 )
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PORT_BIT( 0xfe00, IP_ACTIVE_LOW, IPT_UNUSED )
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PORT_BIT( 0xfe00, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_START("SYSTEM")
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PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_TILT ) PORT_NAME( "Test" )
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@ -287,12 +287,14 @@ static INPUT_PORTS_START( iteagle )
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PORT_DIPNAME( 0x0020, 0x00, "SW51-2" )
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PORT_DIPSETTING(0x00, "On" )
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PORT_DIPSETTING(0x20, "Off" )
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PORT_DIPNAME( 0x00c0, 0x00, "SW51-34" )
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PORT_DIPNAME( 0xc0, 0x00, "SW51-34" )
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PORT_DIPSETTING(0x00, "On" )
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PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_VOLUME_UP )
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PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_VOLUME_DOWN )
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PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_BILL1 )
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PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_UNUSED )
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PORT_BIT( 0x3000, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_UNUSED )
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PORT_BIT( 0x2000, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_DIPNAME( 0xC000, 0xC000, "Voltage" )
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PORT_DIPSETTING(0xC000, "OK" )
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PORT_DIPSETTING(0x8000, "Low" )
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@ -306,13 +308,49 @@ static INPUT_PORTS_START( iteagle )
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PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_Y ) PORT_SENSITIVITY(25) PORT_KEYDELTA(32) PORT_REVERSE PORT_PLAYER(1)
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||||
|
||||
PORT_START("GUNX1")
|
||||
PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_X ) PORT_SENSITIVITY(50) PORT_KEYDELTA(5)
|
||||
PORT_BIT( 0x1ff, 0x100, IPT_LIGHTGUN_X )
|
||||
PORT_SENSITIVITY(50) PORT_KEYDELTA(10)
|
||||
|
||||
PORT_START("GUNY1")
|
||||
PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_Y ) PORT_SENSITIVITY(50) PORT_KEYDELTA(5)
|
||||
PORT_BIT( 0x1ff, 0x100, IPT_LIGHTGUN_Y )
|
||||
PORT_SENSITIVITY(50) PORT_KEYDELTA(10) PORT_MINMAX(0, 383)
|
||||
|
||||
INPUT_PORTS_END
|
||||
|
||||
static INPUT_PORTS_START( virtpool )
|
||||
PORT_INCLUDE( iteagle )
|
||||
|
||||
PORT_MODIFY("IN1")
|
||||
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME( "English" )
|
||||
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME( "Aim" )
|
||||
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
|
||||
PORT_MODIFY("SYSTEM")
|
||||
PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME( "Slop" )
|
||||
|
||||
INPUT_PORTS_END
|
||||
|
||||
static INPUT_PORTS_START( bbhcotw )
|
||||
PORT_INCLUDE( iteagle )
|
||||
|
||||
PORT_MODIFY("IN1")
|
||||
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME( "Trigger" )
|
||||
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME( "Pump" )
|
||||
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
|
||||
PORT_MODIFY("GUNX1")
|
||||
PORT_BIT( 0x1ff, 0x100, IPT_LIGHTGUN_X )
|
||||
PORT_SENSITIVITY(50) PORT_KEYDELTA(10)
|
||||
PORT_CROSSHAIR(X, 1.0, 0.0, 0)
|
||||
|
||||
PORT_MODIFY("GUNY1")
|
||||
PORT_BIT( 0x1ff, 0x100, IPT_LIGHTGUN_Y )
|
||||
PORT_SENSITIVITY(50) PORT_KEYDELTA(10) PORT_MINMAX(0, 383)
|
||||
PORT_CROSSHAIR(Y, 1.0, 0.0, 0)
|
||||
|
||||
INPUT_PORTS_END
|
||||
|
||||
/*************************************
|
||||
*
|
||||
@ -517,19 +555,19 @@ ROM_END
|
||||
*
|
||||
*************************************/
|
||||
|
||||
GAME( 2000, iteagle, 0, iteagle, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Eagle BIOS", GAME_IS_BIOS_ROOT )
|
||||
GAME( 1998, virtpool, iteagle, virtpool, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Virtual Pool", GAME_NOT_WORKING )
|
||||
GAME( 2002, carnking, iteagle, carnking, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Carnival King (v1.00.11)", GAME_NOT_WORKING )
|
||||
GAME( 2000, gtfore01, iteagle, gtfore01, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! (v1.00.25)", 0 )
|
||||
GAME( 2001, gtfore02, iteagle, gtfore02, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2002 (v2.01.06)", 0 )
|
||||
GAME( 2002, gtfore03, iteagle, gtfore03, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2003 (v3.00.10)", 0 )
|
||||
GAME( 2002, gtfore03a, gtfore03, gtfore03, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2003 (v3.00.09)", 0 )
|
||||
GAME( 2003, gtfore04, iteagle, gtfore04, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2004 Extra (v4.00.08)", 0 )
|
||||
GAME( 2003, gtfore04a, gtfore04, gtfore04, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2004 (v4.00.00)", 0 )
|
||||
GAME( 2004, gtfore05, iteagle, gtfore05, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2005 Extra (v5.01.06)", 0 )
|
||||
GAME( 2004, gtfore05a, gtfore05, gtfore05, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2005 Extra (v5.01.02)", 0 )
|
||||
GAME( 2004, gtfore05b, gtfore05, gtfore05, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2005 Extra (v5.01.00)", 0 )
|
||||
GAME( 2004, gtfore05c, gtfore05, gtfore05, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2005 Extra (v5.00.00)", 0 )
|
||||
GAME( 2005, gtfore06, iteagle, gtfore06, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2006 Complete (v6.00.01)", 0 )
|
||||
GAME( 2002, bbhsc, iteagle, bbhsc, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Big Buck Hunter - Shooter's Challenge (v1.50.07)", GAME_NOT_WORKING )
|
||||
GAME( 2006, bbhcotw, iteagle, bbhcotw, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Big Buck Hunter Call of the Wild (v3.02.5)", GAME_NOT_WORKING )
|
||||
GAME( 2000, iteagle, 0, iteagle, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Eagle BIOS", GAME_IS_BIOS_ROOT )
|
||||
GAME( 1998, virtpool, iteagle, virtpool, virtpool, driver_device, 0, ROT0, "Incredible Technologies", "Virtual Pool", GAME_NOT_WORKING )
|
||||
GAME( 2002, carnking, iteagle, carnking, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Carnival King (v1.00.11)", GAME_NOT_WORKING )
|
||||
GAME( 2000, gtfore01, iteagle, gtfore01, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! (v1.00.25)", 0 )
|
||||
GAME( 2001, gtfore02, iteagle, gtfore02, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2002 (v2.01.06)", 0 )
|
||||
GAME( 2002, gtfore03, iteagle, gtfore03, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2003 (v3.00.10)", 0 )
|
||||
GAME( 2002, gtfore03a, gtfore03, gtfore03, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2003 (v3.00.09)", 0 )
|
||||
GAME( 2003, gtfore04, iteagle, gtfore04, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2004 Extra (v4.00.08)", 0 )
|
||||
GAME( 2003, gtfore04a, gtfore04, gtfore04, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2004 (v4.00.00)", 0 )
|
||||
GAME( 2004, gtfore05, iteagle, gtfore05, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2005 Extra (v5.01.06)", 0 )
|
||||
GAME( 2004, gtfore05a, gtfore05, gtfore05, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2005 Extra (v5.01.02)", 0 )
|
||||
GAME( 2004, gtfore05b, gtfore05, gtfore05, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2005 Extra (v5.01.00)", 0 )
|
||||
GAME( 2004, gtfore05c, gtfore05, gtfore05, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2005 Extra (v5.00.00)", 0 )
|
||||
GAME( 2005, gtfore06, iteagle, gtfore06, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2006 Complete (v6.00.01)", 0 )
|
||||
GAME( 2002, bbhsc, iteagle, bbhsc, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Big Buck Hunter - Shooter's Challenge (v1.50.07)", GAME_NOT_WORKING )
|
||||
GAME( 2006, bbhcotw, iteagle, bbhcotw, bbhcotw, driver_device, 0, ROT0, "Incredible Technologies", "Big Buck Hunter Call of the Wild (v3.02.5)", 0 )
|
||||
|
||||
@ -5,6 +5,7 @@
|
||||
|
||||
#define LOG_FPGA (0)
|
||||
#define LOG_RTC (0)
|
||||
#define LOG_RAM (0)
|
||||
#define LOG_EEPROM (0)
|
||||
#define LOG_IDE (0)
|
||||
#define LOG_IDE_CTRL (0)
|
||||
@ -20,6 +21,10 @@ DEVICE_ADDRESS_MAP_START(rtc_map, 32, iteagle_fpga_device)
|
||||
AM_RANGE(0x000, 0x7ff) AM_READWRITE(rtc_r, rtc_w)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
DEVICE_ADDRESS_MAP_START(ram_map, 32, iteagle_fpga_device)
|
||||
AM_RANGE(0x00000, 0x1ffff) AM_READWRITE(ram_r, ram_w)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
iteagle_fpga_device::iteagle_fpga_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
|
||||
: pci_device(mconfig, ITEAGLE_FPGA, "ITEagle FPGA", tag, owner, clock, "iteagle_fpga", __FILE__),
|
||||
device_nvram_interface(mconfig, *this), m_version(0), m_seq_init(0)
|
||||
@ -40,14 +45,17 @@ void iteagle_fpga_device::device_start()
|
||||
// RTC defaults to base address 0x000c0000
|
||||
bank_infos[1].adr = 0x000c0000 & (~(bank_infos[1].size - 1));
|
||||
|
||||
add_map(sizeof(m_ram), M_MEM, FUNC(iteagle_fpga_device::ram_map));
|
||||
// RAM defaults to base address 0x000e0000
|
||||
bank_infos[2].adr = 0x000e0000 & (~(bank_infos[2].size - 1));
|
||||
|
||||
m_timer = timer_alloc(0, NULL);
|
||||
m_timer->adjust(attotime::zero, 0, attotime::from_hz(25));
|
||||
}
|
||||
|
||||
void iteagle_fpga_device::device_reset()
|
||||
{
|
||||
remap_cb();
|
||||
m_cpu = machine().device<cpu_device>(m_cpu_tag);
|
||||
pci_device::device_reset();
|
||||
memset(m_fpga_regs, 0, sizeof(m_fpga_regs));
|
||||
m_seq = m_seq_init;
|
||||
m_seq_rem1 = 0;
|
||||
@ -58,10 +66,17 @@ void iteagle_fpga_device::device_reset()
|
||||
m_fpga_regs[0x04/4] = 0x00000000; // Nibble starting at bit 20 is resolution, byte 0 is atmel response
|
||||
m_prev_reg = 0;
|
||||
|
||||
m_serial_str.clear();
|
||||
m_serial_idx = 0;
|
||||
m_serial_data = false;
|
||||
m_serial_reg1c[0] = 0x2c;
|
||||
m_serial_reg1d[0] = 0x2c;
|
||||
memset(m_serial_com1, 0, sizeof(m_serial_com1));
|
||||
memset(m_serial_com2, 0, sizeof(m_serial_com2));
|
||||
memset(m_serial_com3, 0, sizeof(m_serial_com3));
|
||||
memset(m_serial_com4, 0, sizeof(m_serial_com4));
|
||||
m_serial_com1[0] = 0x2c;
|
||||
m_serial_com2[0] = 0x2c;
|
||||
m_serial_com3[0] = 0x2c;
|
||||
m_serial_com4[0] = 0x2c;
|
||||
}
|
||||
|
||||
void iteagle_fpga_device::update_sequence(UINT32 data)
|
||||
@ -101,8 +116,8 @@ void iteagle_fpga_device::device_timer(emu_timer &timer, device_timer_id tid, in
|
||||
{
|
||||
if (m_fpga_regs[0x4/4]&0x01000000) {
|
||||
//m_fpga_regs[0x04/4] |= 0x02080000;
|
||||
m_fpga_regs[0x04/4] |= 0x00000000;
|
||||
//m_cpu->set_input_line(m_irq_num, ASSERT_LINE);
|
||||
m_fpga_regs[0x04/4] |= 0x00080000;
|
||||
m_cpu->set_input_line(m_irq_num, ASSERT_LINE);
|
||||
if (LOG_FPGA)
|
||||
logerror("%s:fpga device_timer Setting interrupt(%i)\n", machine().describe_context(), m_irq_num);
|
||||
}
|
||||
@ -126,29 +141,31 @@ READ32_MEMBER( iteagle_fpga_device::fpga_r )
|
||||
break;
|
||||
|
||||
case 0x08/4:
|
||||
//result = ((machine().root_device().ioport("GUNY1")->read()&0xff)<<8) | ((machine().root_device().ioport("GUNX1")->read()&0xff)<<0);
|
||||
result = ((machine().root_device().ioport("TRACKY1")->read()&0xff)<<8) | (machine().root_device().ioport("TRACKX1")->read()&0xff);
|
||||
if (LOG_FPGA && m_prev_reg!=offset)
|
||||
logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
break;
|
||||
// case 0x0c/4: // 1d = modem byte
|
||||
// result = (result & 0xFFFF0000) | 0x2c2c;
|
||||
// if (LOG_FPGA)
|
||||
// logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
// break;
|
||||
case 0x14/4: // Interrupt & 0x4==0x00080000
|
||||
result = 0x00000000;
|
||||
case 0x14/4: // GUN1-- Interrupt & 0x4==0x00080000
|
||||
result = ((machine().root_device().ioport("GUNY1")->read())<<16) | (machine().root_device().ioport("GUNX1")->read());
|
||||
if (LOG_FPGA)
|
||||
logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
break;
|
||||
case 0x18/4: // Interrupt & 0x4==0x02000000
|
||||
result = 0x00000000;
|
||||
result = 0;
|
||||
if (LOG_FPGA)
|
||||
logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
break;
|
||||
case 0x0c/4: // 1d = modem byte
|
||||
result = (result & 0xFFFF0000) | ((m_serial_com2[m_serial_idx]&0xff)<<8) | (m_serial_com1[m_serial_idx]&0xff);
|
||||
if (ACCESSING_BITS_0_15) {
|
||||
m_serial_data = false;
|
||||
m_serial_idx = 0;
|
||||
}
|
||||
if (LOG_FPGA)
|
||||
logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
break;
|
||||
case 0x1c/4: // 1d = modem byte
|
||||
result = (result & 0xFFFF0000) | ((m_serial_reg1d[m_serial_idx]&0xff)<<8) | (m_serial_reg1c[m_serial_idx]&0xff);
|
||||
result = (result & 0xFFFF0000) | ((m_serial_com4[m_serial_idx]&0xff)<<8) | (m_serial_com3[m_serial_idx]&0xff);
|
||||
if (ACCESSING_BITS_0_15) {
|
||||
m_serial_data = false;
|
||||
m_serial_idx = 0;
|
||||
@ -180,6 +197,8 @@ WRITE32_MEMBER( iteagle_fpga_device::fpga_w )
|
||||
// Interrupt clear/enable
|
||||
if (ACCESSING_BITS_24_31 && (data & 0x01000000)) {
|
||||
m_cpu->set_input_line(m_irq_num, CLEAR_LINE);
|
||||
// Not sure what value to use here, needed for lightgun
|
||||
m_timer->adjust(attotime::from_hz(25));
|
||||
if (LOG_FPGA)
|
||||
logerror("%s:fpga_w offset %04X = %08X & %08X Clearing interrupt(%i)\n", machine().describe_context(), offset*4, data, mem_mask, m_irq_num);
|
||||
} else {
|
||||
@ -202,12 +221,11 @@ WRITE32_MEMBER( iteagle_fpga_device::fpga_w )
|
||||
logerror("%s:fpga_w offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
break;
|
||||
case 0x0c/4:
|
||||
case 0x1c/4:
|
||||
if (ACCESSING_BITS_0_7) {
|
||||
if (!m_serial_data) {
|
||||
m_serial_idx = data&0xf;
|
||||
} else {
|
||||
m_serial_reg1c[m_serial_idx] = data&0xff;
|
||||
m_serial_com1[m_serial_idx] = data&0xff;
|
||||
m_serial_idx = 0;
|
||||
}
|
||||
m_serial_data = !m_serial_data;
|
||||
@ -216,10 +234,67 @@ WRITE32_MEMBER( iteagle_fpga_device::fpga_w )
|
||||
if (!m_serial_data) {
|
||||
m_serial_idx = (data&0x0f00)>>8;
|
||||
} else {
|
||||
m_serial_reg1d[m_serial_idx] = (data&0xff00)>>8;
|
||||
m_serial_com2[m_serial_idx] = (data&0xff00)>>8;
|
||||
}
|
||||
m_serial_data = !m_serial_data;
|
||||
}
|
||||
if (ACCESSING_BITS_16_23) {
|
||||
if (m_serial_str.size()==0)
|
||||
m_serial_str = "com1: ";
|
||||
m_serial_str += (data>>16)&0xff;
|
||||
if (((data>>16)&0xff)==0xd) {
|
||||
osd_printf_debug("%s\n", m_serial_str.c_str());
|
||||
m_serial_str.clear();
|
||||
}
|
||||
}
|
||||
if (ACCESSING_BITS_24_31) {
|
||||
if (m_serial_str.size()==0)
|
||||
m_serial_str = "com2: ";
|
||||
m_serial_str += (data>>24)&0xff;
|
||||
if (1 || ((data>>24)&0xff)==0xd) {
|
||||
osd_printf_debug("%s\n", m_serial_str.c_str());
|
||||
m_serial_str.clear();
|
||||
}
|
||||
}
|
||||
if (LOG_FPGA)
|
||||
logerror("%s:fpga_w offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
break;
|
||||
case 0x1c/4:
|
||||
if (ACCESSING_BITS_0_7) {
|
||||
if (!m_serial_data) {
|
||||
m_serial_idx = data&0xf;
|
||||
} else {
|
||||
m_serial_com3[m_serial_idx] = data&0xff;
|
||||
m_serial_idx = 0;
|
||||
}
|
||||
m_serial_data = !m_serial_data;
|
||||
}
|
||||
if (ACCESSING_BITS_8_15) {
|
||||
if (!m_serial_data) {
|
||||
m_serial_idx = (data&0x0f00)>>8;
|
||||
} else {
|
||||
m_serial_com4[m_serial_idx] = (data&0xff00)>>8;
|
||||
}
|
||||
m_serial_data = !m_serial_data;
|
||||
}
|
||||
if (ACCESSING_BITS_16_23) {
|
||||
if (m_serial_str.size()==0)
|
||||
m_serial_str = "com3: ";
|
||||
m_serial_str += (data>>16)&0xff;
|
||||
if (1 || ((data>>16)&0xff)==0xd) {
|
||||
osd_printf_debug("%s\n", m_serial_str.c_str());
|
||||
m_serial_str.clear();
|
||||
}
|
||||
}
|
||||
if (ACCESSING_BITS_24_31) {
|
||||
if (m_serial_str.size()==0)
|
||||
m_serial_str = "com4: ";
|
||||
m_serial_str += (data>>24)&0xff;
|
||||
if (((data>>24)&0xff)==0xd) {
|
||||
osd_printf_debug("%s\n", m_serial_str.c_str());
|
||||
m_serial_str.clear();
|
||||
}
|
||||
}
|
||||
if (LOG_FPGA)
|
||||
logerror("%s:fpga_w offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
break;
|
||||
@ -310,6 +385,24 @@ WRITE32_MEMBER( iteagle_fpga_device::rtc_w )
|
||||
|
||||
}
|
||||
|
||||
//*************************************
|
||||
//* FPGA RAM -- Eagle 1 only
|
||||
//*************************************
|
||||
READ32_MEMBER( iteagle_fpga_device::ram_r )
|
||||
{
|
||||
UINT32 result = m_ram[offset];
|
||||
if (LOG_RAM)
|
||||
logerror("%s:FPGA ram_r from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
return result;
|
||||
}
|
||||
|
||||
WRITE32_MEMBER( iteagle_fpga_device::ram_w )
|
||||
{
|
||||
COMBINE_DATA(&m_ram[offset]);
|
||||
if (LOG_RAM)
|
||||
logerror("%s:FPGA ram_w to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
}
|
||||
|
||||
//************************************
|
||||
// Attached serial EEPROM
|
||||
//************************************
|
||||
@ -377,6 +470,12 @@ void iteagle_eeprom_device::device_reset()
|
||||
pci_device::device_reset();
|
||||
}
|
||||
|
||||
void iteagle_eeprom_device::map_extra(UINT64 memory_window_start, UINT64 memory_window_end, UINT64 memory_offset, address_space *memory_space,
|
||||
UINT64 io_window_start, UINT64 io_window_end, UINT64 io_offset, address_space *io_space)
|
||||
{
|
||||
m_memory_space = memory_space;
|
||||
}
|
||||
|
||||
READ32_MEMBER( iteagle_eeprom_device::eeprom_r )
|
||||
{
|
||||
UINT32 result = 0;
|
||||
@ -386,9 +485,9 @@ READ32_MEMBER( iteagle_eeprom_device::eeprom_r )
|
||||
if (ACCESSING_BITS_16_23) {
|
||||
result = m_eeprom->do_read()<<(16+3);
|
||||
if (LOG_EEPROM)
|
||||
logerror("%s:eeprom read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
logerror("%s:eeprom_r from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
} else {
|
||||
logerror("%s:eeprom read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
logerror("%s:eeprom_r from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
@ -401,16 +500,23 @@ READ32_MEMBER( iteagle_eeprom_device::eeprom_r )
|
||||
WRITE32_MEMBER( iteagle_eeprom_device::eeprom_w )
|
||||
{
|
||||
switch (offset) {
|
||||
case 0x8/4: // 8255x PORT command
|
||||
if ((data&0xf)==0x1) {
|
||||
// Self test for ethernet controller
|
||||
m_memory_space->write_dword((data&0xfffffff0) | 0x4, 0x0);
|
||||
logerror("%s:eeprom_w to offset %04X = %08X & %08X Self Test\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
}
|
||||
break;
|
||||
case 0xC/4: // I2C Handler
|
||||
if (ACCESSING_BITS_16_23) {
|
||||
m_eeprom->di_write((data & 0x040000) >> (16+2));
|
||||
m_eeprom->cs_write((data & 0x020000) ? ASSERT_LINE : CLEAR_LINE);
|
||||
m_eeprom->clk_write((data & 0x010000) ? ASSERT_LINE : CLEAR_LINE);
|
||||
if (LOG_EEPROM)
|
||||
logerror("%s:eeprom write to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
logerror("%s:eeprom_w to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
} else {
|
||||
//if (LOG_EEPROM)
|
||||
logerror("%s:eeprom write to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
logerror("%s:eeprom_w to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
@ -427,7 +533,7 @@ WRITE32_MEMBER( iteagle_eeprom_device::eeprom_w )
|
||||
const device_type ITEAGLE_IDE = &device_creator<iteagle_ide_device>;
|
||||
|
||||
DEVICE_ADDRESS_MAP_START(ctrl_map, 32, iteagle_ide_device)
|
||||
AM_RANGE(0x000, 0x02f) AM_READWRITE(ctrl_r, ctrl_w)
|
||||
AM_RANGE(0x000, 0x0cf) AM_READWRITE(ctrl_r, ctrl_w)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
|
||||
@ -499,16 +605,42 @@ void iteagle_ide_device::device_reset()
|
||||
pci_device::device_reset();
|
||||
memset(m_ctrl_regs, 0, sizeof(m_ctrl_regs));
|
||||
m_ctrl_regs[0x10/4] = 0x00000000; // 0x6=No SIMM, 0x2, 0x1, 0x0 = SIMM . Top 16 bits are compared to 0x3.
|
||||
memset(m_rtc_regs, 0, sizeof(m_rtc_regs));
|
||||
}
|
||||
|
||||
READ32_MEMBER( iteagle_ide_device::ctrl_r )
|
||||
{
|
||||
system_time systime;
|
||||
UINT32 result = m_ctrl_regs[offset];
|
||||
switch (offset) {
|
||||
case 0x0/4:
|
||||
if (LOG_IDE_REG)
|
||||
logerror("%s:fpga ctrl_r from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
break;
|
||||
case 0x70/4:
|
||||
if (ACCESSING_BITS_8_15) {
|
||||
// get the current date/time from the core
|
||||
machine().current_datetime(systime);
|
||||
m_rtc_regs[0] = dec_2_bcd(systime.local_time.second);
|
||||
m_rtc_regs[1] = 0x00; // Seconds Alarm
|
||||
m_rtc_regs[2] = dec_2_bcd(systime.local_time.minute);
|
||||
m_rtc_regs[3] = 0x00; // Minutes Alarm
|
||||
m_rtc_regs[4] = dec_2_bcd(systime.local_time.hour);
|
||||
m_rtc_regs[5] = 0x00; // Hours Alarm
|
||||
|
||||
m_rtc_regs[6] = dec_2_bcd((systime.local_time.weekday != 0) ? systime.local_time.weekday : 7);
|
||||
m_rtc_regs[7] = dec_2_bcd(systime.local_time.mday);
|
||||
m_rtc_regs[8] = dec_2_bcd(systime.local_time.month + 1);
|
||||
m_rtc_regs[9] = dec_2_bcd(systime.local_time.year - 1900); // Epoch is 1900
|
||||
m_rtc_regs[0xa] &= ~0x10; // Reg A Status
|
||||
//m_ctrl_regs[0xb] &= 0x10; // Reg B Status
|
||||
//m_ctrl_regs[0xc] &= 0x10; // Reg C Interupt Status
|
||||
m_rtc_regs[0xd] = 0x80; // Reg D Valid time/ram Status
|
||||
result = (result & 0xffff00ff) | (m_rtc_regs[m_ctrl_regs[0x70/4]&0xff]<<8);
|
||||
}
|
||||
if (LOG_IDE_REG)
|
||||
logerror("%s:fpga ctrl_r from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
break;
|
||||
default:
|
||||
if (LOG_IDE_REG)
|
||||
logerror("%s:fpga ctrl_r from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
@ -535,6 +667,10 @@ WRITE32_MEMBER( iteagle_ide_device::ctrl_w )
|
||||
logerror("%s:fpga ctrl_w to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
}
|
||||
break;
|
||||
case 0x70/4:
|
||||
if (ACCESSING_BITS_8_15) {
|
||||
m_rtc_regs[m_ctrl_regs[0x70/4]&0xff] = (data>>8)&0xff;
|
||||
}
|
||||
default:
|
||||
if (LOG_IDE_REG)
|
||||
logerror("%s:fpga ctrl_w to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
|
||||
@ -55,14 +55,18 @@ private:
|
||||
cpu_device *m_cpu;
|
||||
int m_irq_num;
|
||||
|
||||
UINT32 m_fpga_regs[0x20];
|
||||
UINT32 m_rtc_regs[0x200];
|
||||
UINT32 m_fpga_regs[0x20/4];
|
||||
UINT32 m_rtc_regs[0x800/4];
|
||||
UINT32 m_ram[0x20000/4];
|
||||
UINT32 m_prev_reg;
|
||||
|
||||
std::string m_serial_str;
|
||||
UINT8 m_serial_idx;
|
||||
bool m_serial_data;
|
||||
UINT8 m_serial_reg1c[0x10];
|
||||
UINT8 m_serial_reg1d[0x10];
|
||||
UINT8 m_serial_com1[0x10];
|
||||
UINT8 m_serial_com2[0x10];
|
||||
UINT8 m_serial_com3[0x10];
|
||||
UINT8 m_serial_com4[0x10];
|
||||
|
||||
UINT32 m_version;
|
||||
UINT32 m_seq_init;
|
||||
@ -72,11 +76,15 @@ private:
|
||||
|
||||
DECLARE_ADDRESS_MAP(rtc_map, 32);
|
||||
DECLARE_ADDRESS_MAP(fpga_map, 32);
|
||||
DECLARE_ADDRESS_MAP(ram_map, 32);
|
||||
|
||||
DECLARE_READ32_MEMBER( fpga_r );
|
||||
DECLARE_WRITE32_MEMBER( fpga_w );
|
||||
DECLARE_READ32_MEMBER( rtc_r );
|
||||
DECLARE_WRITE32_MEMBER( rtc_w );
|
||||
|
||||
DECLARE_READ32_MEMBER( ram_r );
|
||||
DECLARE_WRITE32_MEMBER( ram_w );
|
||||
};
|
||||
|
||||
class iteagle_eeprom_device : public pci_device {
|
||||
@ -84,6 +92,8 @@ public:
|
||||
iteagle_eeprom_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
// optional information overrides
|
||||
virtual machine_config_constructor device_mconfig_additions() const;
|
||||
virtual void map_extra(UINT64 memory_window_start, UINT64 memory_window_end, UINT64 memory_offset, address_space *memory_space,
|
||||
UINT64 io_window_start, UINT64 io_window_end, UINT64 io_offset, address_space *io_space);
|
||||
|
||||
required_device<eeprom_serial_93cxx_device> m_eeprom;
|
||||
|
||||
@ -93,6 +103,7 @@ protected:
|
||||
virtual void device_reset();
|
||||
|
||||
private:
|
||||
address_space *m_memory_space;
|
||||
UINT16 m_sw_version;
|
||||
UINT8 m_hw_version;
|
||||
|
||||
@ -122,7 +133,8 @@ private:
|
||||
cpu_device *m_cpu;
|
||||
int m_irq_num;
|
||||
|
||||
UINT32 m_ctrl_regs[0x30];
|
||||
UINT32 m_ctrl_regs[0xd0/4];
|
||||
UINT8 m_rtc_regs[0x100];
|
||||
|
||||
DECLARE_ADDRESS_MAP(ctrl_map, 32);
|
||||
DECLARE_ADDRESS_MAP(ide_map, 32);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user