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srcclean (nw)

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This commit is contained in:
Vas Crabb 2016-11-27 09:56:49 +11:00
parent 1637c91a5c
commit 7238415d1f
164 changed files with 2707 additions and 2705 deletions
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92
hash/bbcb_flop.xml
View File

@ -50,11 +50,11 @@
</dataarea>
</part>
<!--
<part name="rom" interface="bbc_rom">
<dataarea name="rom" size="16384">
<rom name="alps.rom" size="16384" crc="75e5219e" sha1="bb03788d7f58e222795f460767bcdf198c21140a" offset="0"/>
</dataarea>
</part>
<part name="rom" interface="bbc_rom">
<dataarea name="rom" size="16384">
<rom name="alps.rom" size="16384" crc="75e5219e" sha1="bb03788d7f58e222795f460767bcdf198c21140a" offset="0"/>
</dataarea>
</part>
-->
</software>
@ -360,12 +360,12 @@
</dataarea>
</part>
<!--
<part name="rom1" interface="bbc_rom">
<feature name="part_id" value="Dragon ROM"/>
<dataarea name="rom" size="16384">
<rom name="dragon_rom.bin" size="16384" crc="6d92ca4f" sha1="1f5df3ffb0b982881e52bbf00b29f52e5e32d868" offset="0" />
</dataarea>
</part>
<part name="rom1" interface="bbc_rom">
<feature name="part_id" value="Dragon ROM"/>
<dataarea name="rom" size="16384">
<rom name="dragon_rom.bin" size="16384" crc="6d92ca4f" sha1="1f5df3ffb0b982881e52bbf00b29f52e5e32d868" offset="0" />
</dataarea>
</part>
-->
</software>
@ -1074,11 +1074,11 @@
</dataarea>
</part>
<!--
<part name="rom" interface="bbc_rom">
<dataarea name="rom" size="16384">
<rom name="viewspell v1.0 (1985)(acornsoft).bin" size="16384" crc="224a0fbc" sha1="251ffce5b169d8e09d89f38b7eee4176533f8e8d" offset="0"/>
</dataarea>
</part>
<part name="rom" interface="bbc_rom">
<dataarea name="rom" size="16384">
<rom name="viewspell v1.0 (1985)(acornsoft).bin" size="16384" crc="224a0fbc" sha1="251ffce5b169d8e09d89f38b7eee4176533f8e8d" offset="0"/>
</dataarea>
</part>
-->
</software>
@ -1299,11 +1299,11 @@
</dataarea>
</part>
<!--
<part name="rom" interface="bbc_rom">
<dataarea name="rom" size="16384">
<rom name="bcpl v7.0 (1982)(richards computer products).bin" size="16384" crc="81c373b2" sha1="09ff6358ff4c58046f4531abe739a888898cb8d3" offset="0"/>
</dataarea>
</part>
<part name="rom" interface="bbc_rom">
<dataarea name="rom" size="16384">
<rom name="bcpl v7.0 (1982)(richards computer products).bin" size="16384" crc="81c373b2" sha1="09ff6358ff4c58046f4531abe739a888898cb8d3" offset="0"/>
</dataarea>
</part>
-->
</software>
@ -1342,16 +1342,16 @@
</dataarea>
</part>
<!--
<part name="rom1" interface="bbc_rom">
<dataarea name="rom" size="16384">
<rom name="pascal v1.1-1 (19xx)(-).bin" size="16384" crc="ed1a7497" sha1="44cfe2d7fb0895a6c8858f09aaf5a96bcdcc3767" offset="0"/>
</dataarea>
</part>
<part name="rom2" interface="bbc_rom">
<dataarea name="rom" size="16384">
<rom name="pascal v1.1-2 (19xx)(-).bin" size="16384" crc="73455b67" sha1="0e2354e8d93d9858dbd9d24dfa0aa96a206b0b25" offset="0"/>
</dataarea>
</part>
<part name="rom1" interface="bbc_rom">
<dataarea name="rom" size="16384">
<rom name="pascal v1.1-1 (19xx)(-).bin" size="16384" crc="ed1a7497" sha1="44cfe2d7fb0895a6c8858f09aaf5a96bcdcc3767" offset="0"/>
</dataarea>
</part>
<part name="rom2" interface="bbc_rom">
<dataarea name="rom" size="16384">
<rom name="pascal v1.1-2 (19xx)(-).bin" size="16384" crc="73455b67" sha1="0e2354e8d93d9858dbd9d24dfa0aa96a206b0b25" offset="0"/>
</dataarea>
</part>
-->
</software>
@ -1367,16 +1367,16 @@
</dataarea>
</part>
<!--
<part name="rom1" interface="bbc_rom">
<dataarea name="rom" size="16384">
<rom name="logo 1.rom" size="16384" crc="a0defcf9" sha1="57fdd30894679400cb7c10b331cefd1a2362aeae" offset="0"/>
</dataarea>
</part>
<part name="rom2" interface="bbc_rom">
<dataarea name="rom" size="16384">
<rom name="logo 2.rom" size="16384" crc="753ab82e" sha1="9a22a865ae594a91f0c3c4a88861ae6050d025c3" offset="0"/>
</dataarea>
</part>
<part name="rom1" interface="bbc_rom">
<dataarea name="rom" size="16384">
<rom name="logo 1.rom" size="16384" crc="a0defcf9" sha1="57fdd30894679400cb7c10b331cefd1a2362aeae" offset="0"/>
</dataarea>
</part>
<part name="rom2" interface="bbc_rom">
<dataarea name="rom" size="16384">
<rom name="logo 2.rom" size="16384" crc="753ab82e" sha1="9a22a865ae594a91f0c3c4a88861ae6050d025c3" offset="0"/>
</dataarea>
</part>
-->
</software>
@ -1390,11 +1390,11 @@
</dataarea>
</part>
<!--
<part name="rom" interface="bbc_rom">
<dataarea name="rom" size="16384">
<rom name="oxford pascal v2.1 (19xx)(oxford computers).bin" size="16384" crc="771cd1da" sha1="898229668f03f0c5cdb73a0e59687175553c1692" offset="0"/>
</dataarea>
</part>
<part name="rom" interface="bbc_rom">
<dataarea name="rom" size="16384">
<rom name="oxford pascal v2.1 (19xx)(oxford computers).bin" size="16384" crc="771cd1da" sha1="898229668f03f0c5cdb73a0e59687175553c1692" offset="0"/>
</dataarea>
</part>
-->
</software>

2
hash/megadriv.xml
View File

@ -1681,7 +1681,7 @@ Info on Sega chip labels (from Sunbeam / Digital Corruption)
</dataarea>
</part>
</software>
<software name="coolspotp" cloneof="coolspot">
<description>Cool Spot (Euro, Prototype)</description>
<year>1993</year>

16
hash/pico.xml
View File

@ -662,7 +662,7 @@ Published by Others (T-yyy*** serial codes, for yyy depending on the publisher)
<rom name="9k0-0001a-rv.ic1" size="2097152" crc="b94f7d54" sha1="dabeb440adbb7477cc880c51fb0cfc1e5f99d23b" offset="000000" loadflag="load16_word_swap" />
</dataarea>
</part>
</software>
</software>
<software name="cookpicok" cloneof="cookpico">
<description>Cooking Pico (Kor)</description>
@ -675,7 +675,7 @@ Published by Others (T-yyy*** serial codes, for yyy depending on the publisher)
</dataarea>
</part>
</software>
<software name="crayola">
<description>Crayola - Create a World (USA)</description>
<year>19??</year>
@ -4757,8 +4757,8 @@ But how do later protos fit with this theory? Maybe the later protos were from t
<rom name="samsung pico-toy2.u1" size="2097152" crc="27ef458e" sha1="e4f908d235d25d21390a8965416a34c91b880b63" offset="000000" loadflag="load16_word_swap" />
</dataarea>
</part>
</software>
</software>
<software name="ultraher">
<description>UltraHero (Jpn)</description>
<year>1995</year>
@ -5151,8 +5151,8 @@ But how do later protos fit with this theory? Maybe the later protos were from t
<rom name="mpr-17620-s.u1" size="524288" crc="25639a73" sha1="d0a768236e21d05ea1734691ab9031ea7a4b3e47" offset="000000" loadflag="load16_word_swap" />
</dataarea>
</part>
</software>
</software>
<software name="hkiinkaip" cloneof="hkiinkai">
<description>Heisei Kyouiku Iinkai Jr. (Jpn, Prototype)</description>
<year>1995</year>
@ -6057,7 +6057,7 @@ But how do later protos fit with this theory? Maybe the later protos were from t
<rom name="samsung km23c8100dg pico-9837g.u1" size="1048576" crc="70b7440e" sha1="d6f7b9c9e5714afebfdb116480f73976eae23d17" offset="000000" loadflag="load16_word_swap" />
</dataarea>
</part>
</software>
</software>
<software name="muattago">
<description>Muat Tago Galka (Kor)</description>
@ -6069,7 +6069,7 @@ But how do later protos fit with this theory? Maybe the later protos were from t
<rom name="samsung km23c8100dg pico-9840g.u1" size="1048576" crc="9974d421" sha1="7026dec346ce459ad5e81f3c4d209e2480d6626c" offset="000000" loadflag="load16_word_swap" />
</dataarea>
</part>
</software>
</software>
<software name="drmtour">
<description>Dreamland Tour (Kor)</description>

4
hash/sawatte.xml
View File

@ -29,7 +29,7 @@
</dataarea>
</part>
</software>
<software name="mickkuda">
<description>Mickey no Kudamonoya-san</description>
<year>1996</year>
@ -102,7 +102,7 @@
</dataarea>
</part>
</software>
<software name="micknatk">
<description>Tokyo Disneyland - Mickey no Nakayoshi Tankentai</description>
<year>1998</year>

4
hash/sms.xml
View File

@ -7600,10 +7600,10 @@
<rom name="SG11004A 79ST0086END 9045" size="0x080000" crc="cdbfe86e" sha1="83d6f261471dca20f8d2e33b9807d670e9b4eb9c" offset="000000" />
</dataarea>
<dataarea name="ram" size="16384">
</dataarea>
</dataarea>
</part>
</software>
<!-- The next items have been compiled from original source code written by Jeroen Tel.
It is unsure if Probe has ever written any game code for these licensed titles -->

2
hash/snes.xml
View File

@ -2907,7 +2907,7 @@ Beyond that last category are the roms waiting to be classified.
</dataarea>
</part>
</software>
<software name="tecmonbaup" cloneof="tecmonba">
<!-- i2a2n2 -->
<description>Tecmo Super NBA Basketball (USA, Prototype 19921026)</description>

2
plugins/README.md
View File

@ -1,3 +1,3 @@
# **Plugins** #
LUA plugins contains code from various sources so license is per file.
LUA plugins contains code from various sources so license is per file.

6
plugins/cheat/plugin.json
View File

@ -1,9 +1,9 @@
{
"plugin": {
"name": "cheat",
"name": "cheat",
"description": "Cheat plugin",
"version": "0.0.1",
"author": "Carl",
"version": "0.0.1",
"author": "Carl",
"type": "plugin",
"start": "false"
}

6
plugins/cheatfind/plugin.json
View File

@ -1,9 +1,9 @@
{
"plugin": {
"name": "cheatfind",
"name": "cheatfind",
"description": "Cheat finder helper library",
"version": "0.0.1",
"author": "Carl",
"version": "0.0.1",
"author": "Carl",
"type": "plugin",
"start": "false"
}

6
plugins/console/plugin.json
View File

@ -1,9 +1,9 @@
{
"plugin": {
"name": "console",
"name": "console",
"description": "Console plugin",
"version": "0.0.1",
"author": "Carl",
"version": "0.0.1",
"author": "Carl",
"type": "plugin",
"start": "false"
}

2
plugins/data/load_dat.lua
View File

@ -49,7 +49,7 @@ function datfile.open(file, vertag, fixupcb)
dbver = stmt:get_value(0)
end
stmt:finalize()
if not dbver then
db:exec("CREATE TABLE \"" .. file .. [[_idx" (
type VARCHAR NOT NULL,

6
plugins/data/plugin.json
View File

@ -1,9 +1,9 @@
{
"plugin": {
"name": "data",
"name": "data",
"description": "Data plugin",
"version": "0.0.1",
"author": "Carl",
"version": "0.0.1",
"author": "Carl",
"type": "plugin",
"start": "true"
}

8
plugins/dummy/plugin.json
View File

@ -1,10 +1,10 @@
{
"plugin": {
"name": "dummy",
"name": "dummy",
"description": "Dummy test plugin",
"version": "0.0.1",
"author": "Miodrag Milanovic",
"version": "0.0.1",
"author": "Miodrag Milanovic",
"type": "plugin",
"start": "false"
}
}
}

8
plugins/hiscore/plugin.json
View File

@ -1,10 +1,10 @@
{
"plugin": {
"name": "hiscore",
"name": "hiscore",
"description": "Hiscore support",
"version": "1.0.0",
"author": "borgar@borgar.net",
"version": "1.0.0",
"author": "borgar@borgar.net",
"type": "plugin",
"start": "false"
}
}
}

8
plugins/json/plugin.json
View File

@ -1,9 +1,9 @@
{
"plugin": {
"name": "json",
"name": "json",
"description": "json library",
"version": "2.5.0",
"author": "David Kolf",
"version": "2.5.0",
"author": "David Kolf",
"type": "library"
}
}
}

6
plugins/layout/plugin.json
View File

@ -1,9 +1,9 @@
{
"plugin": {
"name": "layout",
"name": "layout",
"description": "Layout helper plugin",
"version": "0.0.1",
"author": "Carl",
"version": "0.0.1",
"author": "Carl",
"type": "plugin",
"start": "false"
}

22
plugins/timer/init.lua
View File

@ -23,18 +23,18 @@ function timer.startplugin()
total_time = total_time + (os.time() - start_time)
local db = assert(sqlite3.open(timer_db))
local insert_stmt = assert( db:prepare("INSERT OR IGNORE INTO timer VALUES (?, ?, 0, 0)") )
insert_stmt:bind_values(emu.romname(), emu.softname())
insert_stmt:step()
insert_stmt:reset()
local update_stmt = assert( db:prepare("UPDATE timer SET total_time=?, play_count=? WHERE driver=? AND software=?") )
update_stmt:bind_values(total_time, play_count,emu.romname(), emu.softname())
update_stmt:step()
update_stmt:reset()
assert(db:close() == sqlite3.OK)
assert(db:close() == sqlite3.OK)
end
@ -48,13 +48,13 @@ function timer.startplugin()
local db = assert(sqlite3.open(timer_db))
local found=false
db:exec([[select * from sqlite_master where name='timer';]], function(...) found=true return 0 end)
if not found then
if not found then
db:exec[[ CREATE TABLE timer (
driver VARCHAR(32) PRIMARY KEY,
software VARCHAR(40),
total_time INTEGER NOT NULL,
play_count INTEGER NOT NULL
); ]]
driver VARCHAR(32) PRIMARY KEY,
software VARCHAR(40),
total_time INTEGER NOT NULL,
play_count INTEGER NOT NULL
); ]]
end
local stmt, row
@ -69,7 +69,7 @@ function timer.startplugin()
total_time = 0
end
assert(db:close() == sqlite3.OK)
assert(db:close() == sqlite3.OK)
start_time = os.time()
play_count = play_count + 1

6
plugins/timer/plugin.json
View File

@ -1,9 +1,9 @@
{
"plugin": {
"name": "timer",
"name": "timer",
"description": "Timer plugin",
"version": "0.0.1",
"author": "Carl",
"version": "0.0.1",
"author": "Carl",
"type": "plugin",
"start": "false"
}

6
scripts/src/3rdparty.lua
View File

@ -587,7 +587,7 @@ end
forcedincludes {
MAME_DIR .. "src/osd/uwp/uwpcompat.h"
}
configuration {}
files {
@ -1521,12 +1521,12 @@ end
"-Wno-discarded-qualifiers",
"-Wno-unused-but-set-variable",
}
configuration { "mingw-clang"}
buildoptions_c {
"-Wno-incompatible-pointer-types-discards-qualifiers"
}
configuration { "osx*"}
buildoptions {
"-Wno-undef",

4
scripts/src/main.lua
View File

@ -86,7 +86,7 @@ end
}
configuration "**/scripts/resources/uwp/assets/*.png"
flags { "DeploymentContent" }
-- Effects and Shaders
configuration { "winstore*" }
files {
@ -233,7 +233,7 @@ end
}
if (STANDALONE~=true) then
links {
"frontend",
"frontend",
}
end
if (MACHINES["NETLIST"]~=null) then

12
scripts/src/osd/uwp.lua
View File

@ -43,10 +43,10 @@ project ("osd_" .. _OPTIONS["osd"])
removeflags {
"SingleOutputDir",
}
dofile("uwp_cfg.lua")
osdmodulesbuild()
includedirs {
MAME_DIR .. "src/emu",
MAME_DIR .. "src/devices", -- accessing imagedev from debugger
@ -80,17 +80,17 @@ project ("osd_" .. _OPTIONS["osd"])
MAME_DIR .. "src/osd/uwp/uwpcompat.h",
MAME_DIR .. "src/osd/osdepend.h",
}
project ("ocore_" .. _OPTIONS["osd"])
uuid (os.uuid("ocore_" .. _OPTIONS["osd"]))
kind (LIBTYPE)
removeflags {
"SingleOutputDir",
"SingleOutputDir",
}
dofile("uwp_cfg.lua")
includedirs {
MAME_DIR .. "3rdparty",
MAME_DIR .. "src/emu",
@ -99,7 +99,7 @@ project ("ocore_" .. _OPTIONS["osd"])
MAME_DIR .. "src/lib",
MAME_DIR .. "src/lib/util",
}
files {
MAME_DIR .. "src/osd/osdcomm.h",
MAME_DIR .. "src/osd/osdcore.cpp",

2
scripts/src/tests.lua
View File

@ -63,7 +63,7 @@ project("mametests")
configuration { "rpi" }
targetextension ""
configuration { }
links {

2
scripts/target/mame/arcade.lua
View File

@ -4575,7 +4575,7 @@ files {
MAME_DIR .. "src/mame/drivers/quizo.cpp",
MAME_DIR .. "src/mame/drivers/quizpun2.cpp",
MAME_DIR .. "src/mame/audio/rax.cpp",
MAME_DIR .. "src/mame/audio/rax.h",
MAME_DIR .. "src/mame/audio/rax.h",
MAME_DIR .. "src/mame/drivers/rbmk.cpp",
MAME_DIR .. "src/mame/drivers/rcorsair.cpp",
MAME_DIR .. "src/mame/drivers/re900.cpp",

14
src/devices/bus/hp9845_io/98034.cpp
View File

@ -2,14 +2,14 @@
// copyright-holders: F. Ulivi
/*********************************************************************
98034.cpp
98034.cpp
98034 module (HPIB interface)
98034 module (HPIB interface)
TODO: Implement Parallel Poll response
TODO: Implement Parallel Poll response
The main reference for this module is:
HP 98034-90001, 98034 Installation and Service Manual
The main reference for this module is:
HP 98034-90001, 98034 Installation and Service Manual
*********************************************************************/
@ -146,8 +146,8 @@ WRITE16_MEMBER(hp98034_io_card::reg_w)
// ==========
// 7-4 1
// 3-2 ~offset
// 1 0
// 0 1
// 1 0
// 0 1
m_mode_reg = (uint8_t)((offset << 2) ^ 0xfd);
m_force_flg = true;

56
src/devices/bus/hp9845_io/98035.cpp
View File

@ -93,16 +93,16 @@
#define BIT_SET(w , n) ((w) |= BIT_MASK(n))
// Frequency of digit multiplexing in clock chip
#define DIGIT_MUX_FREQ (XTAL_32_768kHz / 64)
#define DIGIT_MUX_FREQ (XTAL_32_768kHz / 64)
// Duration of key presses
#define KEY_PRESS_SHORT 1 // 1.95 ms
#define KEY_PRESS_LONG 512 // 1 s
#define KEY_PRESS_SHORT 1 // 1.95 ms
#define KEY_PRESS_LONG 512 // 1 s
// Mask of keys in m_clock_keys
#define KEY_READ_MASK 1
#define KEY_SET_MASK 2
#define KEY_CHG_MASK 4
#define KEY_READ_MASK 1
#define KEY_SET_MASK 2
#define KEY_CHG_MASK 4
// Timers
enum {
@ -112,33 +112,33 @@ enum {
// 7-segment display
// Mapping of 7 segments on NP input port is as follows:
// Bit Segment
// Bit Segment
// ============
// 7 N/U (1)
// 6 N/U (1)
// 5 Seg "G"
// 4 Seg "F"
// 3 Seg "E"
// 2 Seg "C"
// 1 Seg "B"
// 0 Seg "A"
// 7 N/U (1)
// 6 N/U (1)
// 5 Seg "G"
// 4 Seg "F"
// 3 Seg "E"
// 2 Seg "C"
// 1 Seg "B"
// 0 Seg "A"
//
// Segment "D" is not mapped as it's not needed to tell decimal digits apart.
// A segment is ON when its bit is "0".
#define SEVEN_SEG_OFF 0xff // All segments off
#define SEVEN_SEG_A 0xc0 // "A"
#define SEVEN_SEG_P 0xc4 // "P"
#define SEVEN_SEG_OFF 0xff // All segments off
#define SEVEN_SEG_A 0xc0 // "A"
#define SEVEN_SEG_P 0xc4 // "P"
static const uint8_t dec_2_seven_segs[] = {
0xe0, // 0
0xf9, // 1
0xd4, // 2
0xd8, // 3
0xc9, // 4
0xca, // 5
0xc2, // 6
0xf8, // 7
0xc0, // 8
0xc8 // 9
0xe0, // 0
0xf9, // 1
0xd4, // 2
0xd8, // 3
0xc9, // 4
0xca, // 5
0xc2, // 6
0xf8, // 7
0xc0, // 8
0xc8 // 9
};
hp98035_io_card::hp98035_io_card(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)

14
src/devices/bus/hp9845_io/98035.h
View File

@ -83,13 +83,13 @@ private:
// Clock chip emulation
typedef enum {
CLOCK_OFF, // Display OFF
CLOCK_HHMM, // Show HH:mm
CLOCK_SS, // Show :SS
CLOCK_HH, // Show HH: A/P
CLOCK_MIN, // Show :mm
CLOCK_MON, // Show MM:
CLOCK_DOM, // Show :DD
CLOCK_OFF, // Display OFF
CLOCK_HHMM, // Show HH:mm
CLOCK_SS, // Show :SS
CLOCK_HH, // Show HH: A/P
CLOCK_MIN, // Show :mm
CLOCK_MON, // Show MM:
CLOCK_DOM, // Show :DD
} clock_state_t;
emu_timer *m_clock_timer;

4
src/devices/bus/hp9845_io/hp9845_io.h
View File

@ -21,9 +21,9 @@
#define HP9845_IO_FIRST_SC 1 // Lowest SC used by I/O cards
#define MCFG_HP9845_IO_SC(_default_sc) \
#define MCFG_HP9845_IO_SC(_default_sc) \
PORT_START("SC") \
PORT_CONFNAME(0xf , (_default_sc) - HP9845_IO_FIRST_SC , "Select Code") \
PORT_CONFNAME(0xf , (_default_sc) - HP9845_IO_FIRST_SC , "Select Code") \
PORT_CONFSETTING(0 , "1")\
PORT_CONFSETTING(1 , "2")\
PORT_CONFSETTING(2 , "3")\

2
src/devices/cpu/arc/arcdasm.cpp
View File

@ -180,7 +180,7 @@ static const char *regnames[0x40] =
#define ARC_REGOP_SHIMM ((op & 0x000001ff) >> 0 ) // aka D
CPU_DISASSEMBLE(arc)
CPU_DISASSEMBLE(arc)
{
uint32_t op = oprom[0] | (oprom[1] << 8) | (oprom[2] << 16) | (oprom[3] << 24);
op = big_endianize_int32(op);

2
src/devices/cpu/arm/arm.cpp
View File

@ -1182,7 +1182,7 @@ void arm_cpu_device::HandleMemBlock( uint32_t insn )
}
else
result = loadDec( insn&0xffff, rbp, insn&INSN_BDT_S, &deferredR15, &defer );
if (insn & INSN_BDT_W)
{
if (rb==0xf)

2
src/devices/cpu/asap/asapdasm.cpp
View File

@ -141,6 +141,6 @@ CPU_DISASSEMBLE(asap)
util::stream_format(stream, "jmp%s %s[%s]", setcond[cond], reg[rsrc1], src2(op,2));
break;
case 0x1f: util::stream_format(stream, "trap $1f"); flags = DASMFLAG_STEP_OVER; break;
}
}
return 4 | flags | DASMFLAG_SUPPORTED;
}

2
src/devices/cpu/dsp16/dsp16dis.cpp
View File

@ -339,7 +339,7 @@ CPU_DISASSEMBLE(dsp16a)
std::string fString = disasmF1Field(F1, D, S);
std::string xString = (X ? "*pt++i" : "*pt++");
std::string aString = (opcode == 0x19) ? "a0" : "a1";
if (Y != 0x00)
util::stream_format(stream, "UNKNOWN");
else

6
src/devices/cpu/dsp32/dsp32dis.cpp
View File

@ -313,13 +313,13 @@ static unsigned dasm_dsp32(std::ostream &stream, unsigned pc, uint32_t op)
util::stream_format(stream, "a%d = %s(%s)",
(op >> 21) & 3, // aN
functable[(op >> 23) & 15], // G
dasm_XYZ((op >> 7) & 0x7f)); // Y
dasm_XYZ((op >> 7) & 0x7f)); // Y
else
util::stream_format(stream, "%s = a%d = %s(%s)",
dasm_XYZ((op >> 0) & 0x7f), // Z
dasm_XYZ((op >> 0) & 0x7f), // Z
(op >> 21) & 3, // aN
functable[(op >> 23) & 15], // G
dasm_XYZ((op >> 7) & 0x7f)); // Y
dasm_XYZ((op >> 7) & 0x7f)); // Y
break;
/* CA formats 0/1 */

2
src/devices/cpu/h6280/6280dasm.cpp
View File

@ -249,6 +249,6 @@ CPU_DISASSEMBLE(h6280)
default:
util::stream_format(stream, "%-5s$%02X", token[opc], OP >> 1);
}
}
return (PC - pc) | flags | DASMFLAG_SUPPORTED;
}

1312
src/devices/cpu/m6809/6x09dasm.cpp
View File

File diff suppressed because it is too large Load Diff

2
src/devices/cpu/mips/mips3.h
View File

@ -767,7 +767,7 @@ private:
/***************************************************************************
DISASSEMBLING
DISASSEMBLING
***************************************************************************/
unsigned dasmmips3(std::ostream &stream, unsigned pc, uint32_t op);

2
src/devices/cpu/mips/mips3drc.cpp
View File

@ -4090,7 +4090,7 @@ void mips3_device::log_opcode_desc(drcuml_state *drcuml, const opcode_desc *desc
}
else
buffer << "???";
const std::string buffer_string = buffer.str();
drcuml->log_printf("%08X [%08X] t:%08X f:%s: %-30s", desclist->pc, desclist->physpc, desclist->targetpc, log_desc_flags_to_string(desclist->flags), buffer_string.c_str());

6
src/devices/cpu/nanoprocessor/nanoprocessor.cpp
View File

@ -37,9 +37,9 @@ enum {
#define BIT_SET(w , n) ((w) |= BIT_MASK(n))
// Bits in m_flags
#define NANO_DC0_BIT 0 // DC0
#define NANO_E_BIT (NANO_DC0_BIT + HP_NANO_DC_NO) // Extend flag
#define NANO_I_BIT (NANO_E_BIT + 1) // Interrupt flag
#define NANO_DC0_BIT 0 // DC0
#define NANO_E_BIT (NANO_DC0_BIT + HP_NANO_DC_NO) // Extend flag
#define NANO_I_BIT (NANO_E_BIT + 1) // Interrupt flag
const device_type HP_NANOPROCESSOR = &device_creator<hp_nanoprocessor_device>;

24
src/devices/cpu/nanoprocessor/nanoprocessor.h
View File

@ -53,21 +53,21 @@
#ifndef _NANOPROCESSOR_H_
#define _NANOPROCESSOR_H_
#define HP_NANO_REGS 16 // Number of GP registers
#define HP_NANO_PC_MASK 0x7ff // Mask of PC meaningful bits: 11 bits available
#define HP_NANO_DC_NO 8 // Number of direct control lines (DC7 is typically used as interrupt mask)
#define HP_NANO_IE_DC 7 // DC line used as interrupt enable/mask (DC7)
#define HP_NANO_REGS 16 // Number of GP registers
#define HP_NANO_PC_MASK 0x7ff // Mask of PC meaningful bits: 11 bits available
#define HP_NANO_DC_NO 8 // Number of direct control lines (DC7 is typically used as interrupt mask)
#define HP_NANO_IE_DC 7 // DC line used as interrupt enable/mask (DC7)
// DC changed callback
// The callback receives a 8-bit word holding the state of all DC lines.
// DC0 is in bit 0, DC1 in bit 1 and so on.
// Keep in mind that DC7 usually masks the interrupt signal.
#define MCFG_HP_NANO_DC_CHANGED(_devcb) \
#define MCFG_HP_NANO_DC_CHANGED(_devcb) \
hp_nanoprocessor_device::set_dc_changed_func(*device , DEVCB_##_devcb);
// Callback to read the input state of DC lines
// All lines that are not in input are to be reported at "1"
#define MCFG_HP_NANO_READ_DC_CB(_devcb) \
#define MCFG_HP_NANO_READ_DC_CB(_devcb) \
hp_nanoprocessor_device::set_read_dc_func(*device , DEVCB_##_devcb);
class hp_nanoprocessor_device : public cpu_device
@ -110,12 +110,12 @@ private:
int m_icount;
// State of processor
uint8_t m_reg_A; // Accumulator
uint8_t m_reg_R[ HP_NANO_REGS ]; // General purpose registers
uint16_t m_reg_PA; // Program counter ("Program Address" in HP doc)
uint16_t m_reg_SSR; // Subroutine stack register
uint16_t m_reg_ISR; // Interrupt stack register
uint16_t m_flags; // Flags: extend flag (E) & direct control lines (DC0-7)
uint8_t m_reg_A; // Accumulator
uint8_t m_reg_R[ HP_NANO_REGS ]; // General purpose registers
uint16_t m_reg_PA; // Program counter ("Program Address" in HP doc)
uint16_t m_reg_SSR; // Subroutine stack register
uint16_t m_reg_ISR; // Interrupt stack register
uint16_t m_flags; // Flags: extend flag (E) & direct control lines (DC0-7)
address_space_config m_program_config;
address_space_config m_io_config;

4
src/devices/cpu/nanoprocessor/nanoprocessor_dasm.cpp
View File

@ -114,9 +114,9 @@ static const dis_entry_t dis_table[] = {
CPU_DISASSEMBLE(hp_nanoprocessor)
{
const uint8_t opcode = *oprom;
const uint8_t opcode = *oprom;
opram++;
opram++;
for (const dis_entry_t& ent : dis_table) {
if ((opcode & ent.m_op_mask) == ent.m_opcode) {

2
src/devices/cpu/rsp/rsp.cpp
View File

@ -735,7 +735,7 @@ void rsp_device::execute_run()
{
int i, l;
static uint32_t prev_regs[32];
util::ovectorstream string;
rsp_dasm_one(string, m_ppc, op);
string.put('\0');

6
src/devices/cpu/sh4/sh4.cpp
View File

@ -198,8 +198,8 @@ void sh4_base_device::LDTLB(const uint16_t opcode)
// these come from PTEH
m_utlb[replace].VPN = (m_m[PTEH] & 0xfffffc00) >> 10;
// m_utlb[replace].D = (m_m[PTEH] & 0x00000200) >> 9; // from PTEL
// m_utlb[replace].V = (m_m[PTEH] & 0x00000100) >> 8; // from PTEL
// m_utlb[replace].D = (m_m[PTEH] & 0x00000200) >> 9; // from PTEL
// m_utlb[replace].V = (m_m[PTEH] & 0x00000100) >> 8; // from PTEL
m_utlb[replace].ASID = (m_m[PTEH] & 0x000000ff) >> 0;
// these come from PTEL
m_utlb[replace].PPN = (m_m[PTEL] & 0x1ffffc00) >> 10;
@ -4070,7 +4070,7 @@ void sh34_base_device::execute_run()
debugger_instruction_hook(this, m_pc & AM);
uint16_t opcode;
if (!m_sh4_mmu_enabled) opcode = m_direct->read_word(m_pc & AM, WORD2_XOR_LE(0));
else opcode = RW(m_pc); // should probably use a different function as this needs to go through the ITLB

2
src/devices/cpu/sh4/sh4.h
View File

@ -137,7 +137,7 @@ struct sh4_ddt_dma
};
// ASID [7:0] | VPN [31:10] | V | | PPN [28:10] | SZ[1:0] | SH | C | PR[1:0] | D | WT | SA[2:0] | TC
// ASID [7:0] | VPN [31:10] | V | | PPN [28:10] | SZ[1:0] | SH | C | PR[1:0] | D | WT | SA[2:0] | TC
struct sh4_utlb
{

62
src/devices/cpu/sh4/sh4comn.cpp
View File

@ -676,17 +676,17 @@ WRITE32_MEMBER( sh4_base_device::sh4_internal_w )
// printf("sh4_internal_w: Write %08x (%x), %08x @ %08x\n", 0xfe000000+((offset & 0x3fc0) << 11)+((offset & 0x3f) << 2), offset, data, mem_mask);
switch( offset )
switch( offset )
{
case PTEH: // for use with LDTLB opcode
m_m[PTEH] &= 0xffffffff;
/*
NNNN NNNN NNNN NNNN NNNN NN-- AAAA AAAA
NNNN NNNN NNNN NNNN NNNN NN-- AAAA AAAA
N = VPM = Virtual Page Number
A = ASID = Address Space Identifier
N = VPM = Virtual Page Number
A = ASID = Address Space Identifier
same as the address table part of the utlb but with 2 unused bits (these are sourced from PTEL instead when LDTLB is called)
same as the address table part of the utlb but with 2 unused bits (these are sourced from PTEL instead when LDTLB is called)
*/
@ -695,18 +695,18 @@ WRITE32_MEMBER( sh4_base_device::sh4_internal_w )
case PTEL:
m_m[PTEL] &= 0xffffffff;
/*
---P PPPP PPPP PPPP PPPP PP-V zRRz CDHW
---P PPPP PPPP PPPP PPPP PP-V zRRz CDHW
same format as data array 1 of the utlb
same format as data array 1 of the utlb
*/
break;
case PTEA:
m_m[PTEA] &= 0xffffffff;
/*
---- ---- ---- ---- ---- ---- ---- TSSS
---- ---- ---- ---- ---- ---- ---- TSSS
same format as data array 2 of the utlb
same format as data array 2 of the utlb
*/
break;
@ -725,18 +725,18 @@ WRITE32_MEMBER( sh4_base_device::sh4_internal_w )
logerror("%s: MMUCR %08x\n", machine().describe_context(), data);
m_m[MMUCR] &= 0xffffffff;
/*
LLLL LL-- BBBB BB-- CCCC CCQV ---- -T-A
LLLL LL-- BBBB BB-- CCCC CCQV ---- -T-A
L = LRUI = Least recently used ITLB
B = URB = UTLB replace boundary
C = URC = UTLB replace counter
Q = SQMD = Store Queue Mode Bit
V = SV = Single Virtual Mode Bit
T = TI = TLB invaldiate
A = AT = Address translation bit (enable)
L = LRUI = Least recently used ITLB
B = URB = UTLB replace boundary
C = URC = UTLB replace counter
Q = SQMD = Store Queue Mode Bit
V = SV = Single Virtual Mode Bit
T = TI = TLB invaldiate
A = AT = Address translation bit (enable)
*/
if (data & MMUCR_AT)
{
@ -750,7 +750,7 @@ WRITE32_MEMBER( sh4_base_device::sh4_internal_w )
printf("The MMU emulation is a hack specific to that system\n");
}
if (m_mmuhack == 2)
{
for (int i = 0;i < 64;i++)
@ -1322,16 +1322,16 @@ uint32_t sh4_base_device::sh4_getsqremap(uint32_t address)
WRITE64_MEMBER( sh4_base_device::sh4_utlb_address_array_w )
{
/* uses bits 13:8 of address to select which UTLB entry we're addressing
/* uses bits 13:8 of address to select which UTLB entry we're addressing
bit 7 of the address enables 'associative' mode, causing a search
operation rather than a direct write.
operation rather than a direct write.
NNNN NNNN NNNN NNNN NNNN NNDV AAAA AAAA
NNNN NNNN NNNN NNNN NNNN NNDV AAAA AAAA
N = VPN = Virtual Page Number
D = Dirty Bit
V = Validity Bit
A = ASID = Address Space Identifier
N = VPN = Virtual Page Number
D = Dirty Bit
V = Validity Bit
A = ASID = Address Space Identifier
*/
logerror("sh4_utlb_address_array_w %08x %08x\n", offset, data);
@ -1433,11 +1433,11 @@ WRITE64_MEMBER( sh4_base_device::sh4_utlb_data_array2_w )
{
/* uses bits 13:8 of address to select which UTLB entry we're addressing
---- ---- ---- ---- ---- ---- ---- TSSS
---- ---- ---- ---- ---- ---- ---- TSSS
T = TC = Timing Control
S = SA = Space attributes
- = unused (should be 0)
T = TC = Timing Control
S = SA = Space attributes
- = unused (should be 0)
*/
@ -1462,4 +1462,4 @@ READ64_MEMBER(sh4_base_device::sh4_utlb_data_array2_r)
ret |= m_utlb[i].SA << 0;
return ret;
}
}

32
src/devices/cpu/tlcs90/tlcs90.cpp
View File

@ -998,11 +998,11 @@ bool tlcs90_device::stream_arg(std::ostream &stream, uint32_t pc, const char *pr
{
case MODE_NONE: return false;
case MODE_BIT8: util::stream_format(stream, "%s%d", pre, r ); return true;
case MODE_I8: util::stream_format(stream, "%s$%02X", pre, r ); return true;
case MODE_D8: util::stream_format(stream, "%s$%04X", pre, (pc+2+(r&0x7f)-(r&0x80))&0xffff ); return true;
case MODE_I16: util::stream_format(stream, "%s$%04X", pre, r ); return true;
case MODE_D16: util::stream_format(stream, "%s$%04X", pre, (pc+2+(r&0x7fff)-(r&0x8000))&0xffff ); return true;
case MODE_BIT8: util::stream_format(stream, "%s%d", pre, r ); return true;
case MODE_I8: util::stream_format(stream, "%s$%02X", pre, r ); return true;
case MODE_D8: util::stream_format(stream, "%s$%04X", pre, (pc+2+(r&0x7f)-(r&0x80))&0xffff ); return true;
case MODE_I16: util::stream_format(stream, "%s$%04X", pre, r ); return true;
case MODE_D16: util::stream_format(stream, "%s$%04X", pre, (pc+2+(r&0x7fff)-(r&0x8000))&0xffff ); return true;
case MODE_MI16:
reg_name = internal_registers_names(r);
if (reg_name)
@ -1010,17 +1010,17 @@ bool tlcs90_device::stream_arg(std::ostream &stream, uint32_t pc, const char *pr
else
util::stream_format(stream, "%s($%04X)", pre, r );
return true;
case MODE_R8: util::stream_format(stream, "%s%s", pre, r8_names[r] ); return true;
case MODE_R16: util::stream_format(stream, "%s%s", pre, r16_names[r] ); return true;
case MODE_MR16: util::stream_format(stream, "%s(%s)", pre, r16_names[r] ); return true;
case MODE_R8: util::stream_format(stream, "%s%s", pre, r8_names[r] ); return true;
case MODE_R16: util::stream_format(stream, "%s%s", pre, r16_names[r] ); return true;
case MODE_MR16: util::stream_format(stream, "%s(%s)", pre, r16_names[r] ); return true;
case MODE_MR16R8: util::stream_format(stream, "%s(%s+%s)", pre, r16_names[r], r8_names[rb] ); return true;
case MODE_MR16D8: util::stream_format(stream, "%s(%s%c$%02X)", pre, r16_names[r], (rb&0x80)?'-':'+', (rb&0x80)?((rb^0xff)+1):rb ); return true;
case MODE_MR16R8: util::stream_format(stream, "%s(%s+%s)", pre, r16_names[r], r8_names[rb] ); return true;
case MODE_MR16D8: util::stream_format(stream, "%s(%s%c$%02X)", pre, r16_names[r], (rb&0x80)?'-':'+', (rb&0x80)?((rb^0xff)+1):rb ); return true;
case MODE_CC: util::stream_format(stream, "%s%s", pre, cc_names[r] ); return true;
case MODE_CC: util::stream_format(stream, "%s%s", pre, cc_names[r] ); return true;
case MODE_R16R8: util::stream_format(stream, "%s%s+%s", pre, r16_names[r], r8_names[rb] ); return true;
case MODE_R16D8: util::stream_format(stream, "%s%s%c$%02X", pre, r16_names[r], (rb&0x80)?'-':'+', (rb&0x80)?((rb^0xff)+1):rb ); return true;
case MODE_R16R8: util::stream_format(stream, "%s%s+%s", pre, r16_names[r], r8_names[rb] ); return true;
case MODE_R16D8: util::stream_format(stream, "%s%s%c$%02X", pre, r16_names[r], (rb&0x80)?'-':'+', (rb&0x80)?((rb^0xff)+1):rb ); return true;
default:
fatalerror("%04x: unimplemented addr mode = %d\n",pc,mode);
@ -1037,9 +1037,9 @@ offs_t tlcs90_device::disasm_disassemble(std::ostream &stream, offs_t pc, const
decode();
m_op &= ~OP_16;
util::stream_format (stream, "%-5s", op_names[ m_op ] ); // strlen("callr") == 5
bool streamed = stream_arg (stream, pc, " ", m_mode1, m_r1, m_r1b );
stream_arg (stream, pc, streamed ?",":"", m_mode2, m_r2, m_r2b );
util::stream_format (stream, "%-5s", op_names[ m_op ] ); // strlen("callr") == 5
bool streamed = stream_arg (stream, pc, " ", m_mode1, m_r1, m_r1b );
stream_arg (stream, pc, streamed ?",":"", m_mode2, m_r2, m_r2b );
return (m_addr - pc) | DASMFLAG_SUPPORTED;
}

2
src/devices/cpu/tms34010/34010dsm.cpp
View File

@ -34,7 +34,7 @@ static void print_reg(std::ostream &stream, uint8_t reg)
{
if (reg != 0x0f)
{
util::stream_format(stream, "%c%d", rf, reg);
util::stream_format(stream, "%c%d", rf, reg);
}
else
{

8
src/devices/cpu/tms9900/tms9900.cpp
View File

@ -101,10 +101,10 @@
- State save
- HOLD state should be tested; I don't have test cases yet
Previous implementation with valuable info inside:
https://github.com/mamedev/mame/blob/677ec78eb50decdc40fad3d30daa3560feaff3cc/src/devices/cpu/tms9900/99xxcore.h
Previous implementation with valuable info inside:
https://github.com/mamedev/mame/blob/677ec78eb50decdc40fad3d30daa3560feaff3cc/src/devices/cpu/tms9900/99xxcore.h
Michael Zapf, June 2012
*/

8
src/devices/machine/68230pit.cpp
View File

@ -28,8 +28,8 @@
#define VERBOSE 0
#define LOGPRINT(x) { do { if (VERBOSE) logerror x; } while (0); }
#define LOG(x) {} LOGPRINT(x)
#define LOGR(x) {} LOGPRINT(x)
#define LOG(x) {} LOGPRINT(x)
#define LOGR(x) {} LOGPRINT(x)
#define LOGINT(x) {} LOGPRINT(x)
#define LOGSETUP(x) {} LOGPRINT(x)
#if VERBOSE > 1
@ -237,8 +237,8 @@ void pit68230_device::wr_pitreg_pgcr(uint8_t data)
LOG(("%s(%02x) \"%s\": %s - %02x\n", FUNCNAME, data, tag(), FUNCNAME, data));
LOGSETUP(("PGCR - Mode %d,", (data >> 6) & 3 ));
LOGSETUP((" H34:%s, H12:%s,", (data & 0x20) ? "enabled" : "disabled", (data & 0x10) ? "enabled" : "disabled" ));
LOGSETUP((" Sense assert H4:%s, H3:%s, H2:%s, H1:%s\n",
data & 0x04 ? "Hi" : "Lo", data & 0x03 ? "Hi" : "Lo",
LOGSETUP((" Sense assert H4:%s, H3:%s, H2:%s, H1:%s\n",
data & 0x04 ? "Hi" : "Lo", data & 0x03 ? "Hi" : "Lo",
data & 0x02 ? "Hi" : "Lo", data & 0x01 ? "Hi" : "Lo"));
m_pgcr = data;
}

2
src/devices/machine/7400.cpp
View File

@ -2,7 +2,7 @@
// copyright-holders:Ryan Holtz
/*****************************************************************************
7400 Quad 2-Input NAND Gate
7400 Quad 2-Input NAND Gate
*****************************************************************************/

28
src/devices/machine/7400.h
View File

@ -2,11 +2,11 @@
// copyright-holders:Ryan Holtz
/*****************************************************************************
7400 Quad 2-Input NAND Gate
7400 Quad 2-Input NAND Gate
***********************************************************************
Connection Diagram:
Connection Diagram:
___ ___
1A 1 |* u | 14 Vcc
1B 2 | | 13 4B
@ -16,15 +16,15 @@
2Y 6 | | 9 3A
GND 7 |_______| 8 3Y
Truth Table:
___________
| A | B | Y |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
|___|___|___|
Truth Table:
___________
| A | B | Y |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
|___|___|___|
**********************************************************************/
@ -97,11 +97,11 @@ private:
devcb_write_line m_y4_func;
// inputs
uint8_t m_a; // pins 1,4,9,12
uint8_t m_b; // pins 2,5,10,13
uint8_t m_a; // pins 1,4,9,12
uint8_t m_b; // pins 2,5,10,13
// outputs
uint8_t m_y; // pins 3,6,8,11
uint8_t m_y; // pins 3,6,8,11
};
// device type definition

2
src/devices/machine/7404.cpp
View File

@ -2,7 +2,7 @@
// copyright-holders:Ryan Holtz
/*****************************************************************************
5/7404 Hex Inverters
5/7404 Hex Inverters
*****************************************************************************/

50
src/devices/machine/7404.h
View File

@ -2,16 +2,16 @@
// copyright-holders:Ryan Holtz
/*****************************************************************************
5/7404 Hex Inverters
5/7404 Hex Inverters
***********************************************************************
Connection Diagram:
Connection Diagram:
SN5404 J Package
SN54LS04, SN54S04 J or W Package
SN7404 D, DB, N or NS Package
SN74S04 D or N Package
SN5404 J Package
SN54LS04, SN54S04 J or W Package
SN7404 D, DB, N or NS Package
SN74S04 D or N Package
___ ___
1A 1 |* u | 14 Vcc
1Y 2 | | 13 6A
@ -22,7 +22,7 @@
GND 7 |_______| 8 4Y
SN5404 W Package
SN5404 W Package
___ ___
1A 1 |* u | 14 1Y
2Y 2 | | 13 6A
@ -33,25 +33,25 @@
4A 7 |_______| 8 4Y
SN54LS04, SN54S04 FK Package
SN54LS04, SN54S04 FK Package
1Y 1A NC Vcc 6A
_______________________
/ |_| |_| |_| |_| |_| |
|_ 3 2 1 20 19 _|
2A |_| 18|_| 6Y
|_ _|
NC |_| 17|_| NC
|_ _|
2Y |_| 16|_| 5A
|_ _|
NC |_| 15|_| NC
|_ _|
3A |_| 14|_| 5Y
| 9 10 11 12 13 |
|__|=|_|=|_|=|_|=|_|=|__|
_______________________
/ |_| |_| |_| |_| |_| |
|_ 3 2 1 20 19 _|
2A |_| 18|_| 6Y
|_ _|
NC |_| 17|_| NC
|_ _|
2Y |_| 16|_| 5A
|_ _|
NC |_| 15|_| NC
|_ _|
3A |_| 14|_| 5Y
| 9 10 11 12 13 |
|__|=|_|=|_|=|_|=|_|=|__|
3Y GND NC 4Y 4A
3Y GND NC 4Y 4A
**********************************************************************/
@ -133,10 +133,10 @@ private:
devcb_write_line m_y6_func;
// inputs
uint8_t m_a; // pins 1,3,5,9,11,13
uint8_t m_a; // pins 1,3,5,9,11,13
// outputs
uint8_t m_y; // pins 2,4,6,8,10,12
uint8_t m_y; // pins 2,4,6,8,10,12
};
// device type definition

2
src/devices/machine/74161.cpp
View File

@ -2,7 +2,7 @@
// copyright-holders:Ryan Holtz
/*****************************************************************************
54/74161 4-bit binary counter
54/74161 4-bit binary counter
*****************************************************************************/

72
src/devices/machine/74161.h
View File

@ -2,11 +2,11 @@
// copyright-holders:Ryan Holtz
/*****************************************************************************
5/74160..3 BCD decade counter / 4-bit binary counter
5/74160..3 BCD decade counter / 4-bit binary counter
***********************************************************************
Connection Diagram:
Connection Diagram:
___ ___
*R 1 |* u | 16 Vcc
CP 2 | | 15 TC
@ -17,38 +17,38 @@
CEP 7 | | 10 CET
GND 8 |_______| 9 /PE
*MR for 160 and 161
*SR for 162 and 163
*MR for 160 and 161
*SR for 162 and 163
Logic Symbol:
Logic Symbol:
9 3 4 5 6
| | | | |
____|___|___|___|___|____
| |
| PE P0 P1 P2 P3 |
7 ---| CEP |
| |
10 ---| CET TC |--- 15
| |
2 ---| CP |
| MR Q0 Q1 Q2 Q3 |
|_________________________|
| | | | |
| | | | |
9 3 4 5 6
| | | | |
____|___|___|___|___|____
| |
| PE P0 P1 P2 P3 |
7 ---| CEP |
| |
10 ---| CET TC |--- 15
| |
2 ---| CP |
| MR Q0 Q1 Q2 Q3 |
|_________________________|
| | | | |
| | | | |
1 14 13 12 11
***********************************************************************
Mode Select Table:
Mode Select Table:
MR PE CET CEP Action on clock edge
L X X X Reset (clear)
H L X X Load Pn..Qn
H H H H Count (increment)
H H L X No change (hold)
H H X L No change (hold)
MR PE CET CEP Action on clock edge
L X X X Reset (clear)
H L X X Load Pn..Qn
H H H H Count (increment)
H H L X No change (hold)
H H X L No change (hold)
**********************************************************************/
@ -137,19 +137,19 @@ private:
devcb_write_line m_tc_func;
// inputs
uint8_t m_clear; // pin 1
uint8_t m_pe; // pin 9
uint8_t m_cet; // pin 10
uint8_t m_cep; // pin 7
uint8_t m_clock; // pin 2
uint8_t m_p; // pins 3-6 from LSB to MSB
uint8_t m_clear; // pin 1
uint8_t m_pe; // pin 9
uint8_t m_cet; // pin 10
uint8_t m_cep; // pin 7
uint8_t m_clock; // pin 2
uint8_t m_p; // pins 3-6 from LSB to MSB
// outputs
uint8_t m_out; // pins 14-11 from LSB to MSB
uint8_t m_tc; // pin 15
uint8_t m_out; // pins 14-11 from LSB to MSB
uint8_t m_tc; // pin 15
const bool m_synchronous_reset;
const uint8_t m_limit;
const bool m_synchronous_reset;
const uint8_t m_limit;
};
class ttl74160_device : public ttl7416x_device

4
src/devices/machine/74175.cpp
View File

@ -2,7 +2,7 @@
// copyright-holders:Ryan Holtz
/*****************************************************************************
5/74174/5 Hex/Quad D Flip-Flops with Clear
5/74174/5 Hex/Quad D Flip-Flops with Clear
*****************************************************************************/
@ -245,4 +245,4 @@ void ttl74175_device::tick()
m_not_q3_func(m_q3 ^ 1);
if (last_q4 != m_q1)
m_not_q4_func(m_q4 ^ 1);
}
}

58
src/devices/machine/74175.h
View File

@ -2,43 +2,43 @@
// copyright-holders:Ryan Holtz
/**********************************************************************
5/74174/5 Hex/Quad D Flip-Flops with Clear
5/74174/5 Hex/Quad D Flip-Flops with Clear
***********************************************************************
Connection Diagram:
___ ___ ___ ___
CLEAR 1 |* u | 16 Vcc CLEAR 1 |* u | 16 Vcc
Q1 2 | | 15 Q6 Q1 2 | | 15 Q4
D1 3 | | 14 D6 /Q1 3 | | 14 /Q4
D2 4 | | 13 D5 D1 4 | | 13 D4
Q2 5 | | 12 Q5 D2 5 | | 12 D3
D3 6 | | 11 D4 /Q2 6 | | 11 /Q3
Q3 7 | | 10 Q4 Q2 7 | | 10 Q3
GND 8 |_______| 9 CLOCK GND 8 |_______| 9 CLOCK
Connection Diagram:
___ ___ ___ ___
CLEAR 1 |* u | 16 Vcc CLEAR 1 |* u | 16 Vcc
Q1 2 | | 15 Q6 Q1 2 | | 15 Q4
D1 3 | | 14 D6 /Q1 3 | | 14 /Q4
D2 4 | | 13 D5 D1 4 | | 13 D4
Q2 5 | | 12 Q5 D2 5 | | 12 D3
D3 6 | | 11 D4 /Q2 6 | | 11 /Q3
Q3 7 | | 10 Q4 Q2 7 | | 10 Q3
GND 8 |_______| 9 CLOCK GND 8 |_______| 9 CLOCK
5/74174 5/74175
5/74174 5/74175
***********************************************************************
Function Table:
_________________________________
| Inputs | Outputs* |
|---------------------|-----------|
| Clear | Clock | D | Q | /Q |
|-------|-------|-----|-----|-----|
| L | X | X | L | H |
| H | ^ | H | H | L |
| H | ^ | L | L | H |
| H | L | X | Q0 | Q0 |
|_______|_______|_____|_____|_____|
Function Table:
_________________________________
| Inputs | Outputs* |
|---------------------|-----------|
| Clear | Clock | D | Q | /Q |
|-------|-------|-----|-----|-----|
| L | X | X | L | H |
| H | ^ | H | H | L |
| H | ^ | L | L | H |
| H | L | X | Q0 | Q0 |
|_______|_______|_____|_____|_____|
H = High Level (steady state)
L = Low Level (steady state)
X = Don't Care
^ = Transition from low to high level
Q0 = The level of Q before the indicated steady-state input conditions were established.
* = 175 only
H = High Level (steady state)
L = Low Level (steady state)
X = Don't Care
^ = Transition from low to high level
Q0 = The level of Q before the indicated steady-state input conditions were established.
* = 175 only
**********************************************************************/

2
src/devices/machine/82s129.cpp
View File

@ -2,7 +2,7 @@
// copyright-holders:Ryan Holtz
/*****************************************************************************
(DM)9334 8-Bit Addressable Latch
(DM)9334 8-Bit Addressable Latch
*****************************************************************************/

48
src/devices/machine/82s129.h
View File

@ -2,13 +2,13 @@
// copyright-holders:Ryan Holtz
/*****************************************************************************
82S129/6 1K-bit TTL bipolar PROM
82S129/6 1K-bit TTL bipolar PROM
******************************************************************************
Connection Diagrams:
Connection Diagrams:
N Package
N Package
___ ___
A6 1 |* u | 16 Vcc
A5 2 | | 15 A7
@ -22,21 +22,21 @@
A Package
3 2 1 20 19
| | | | |
/---------------------|
| A5 A6 NC Vcc A7 |
| |
4 -| A4 /CE2 |- 18
5 -| A3 /CE1 |- 17
6 -| A0 O1 |- 16
7 -| A1 NC |- 15
8 -| A2 O2 |- 14
| |
| NC GND NC O4 O3 |
|_____________________|
| | | | |
9 10 11 12 13
3 2 1 20 19
| | | | |
/---------------------|
| A5 A6 NC Vcc A7 |
| |
4 -| A4 /CE2 |- 18
5 -| A3 /CE1 |- 17
6 -| A0 O1 |- 16
7 -| A1 NC |- 15
8 -| A2 O2 |- 14
| |
| NC GND NC O4 O3 |
|_____________________|
| | | | |
9 10 11 12 13
**********************************************************************/
@ -127,7 +127,7 @@ private:
void init();
void update();
required_memory_region m_region;
required_memory_region m_region;
// callbacks
devcb_write_line m_out_func;
@ -137,15 +137,15 @@ private:
devcb_write_line m_o4_func;
// inputs
uint8_t m_ce1; // pin 13
uint8_t m_ce2; // pin 14
uint8_t m_a; // pins 5,6,7,4,3,2,1,15 from LSB to MSB
uint8_t m_ce1; // pin 13
uint8_t m_ce2; // pin 14
uint8_t m_a; // pins 5,6,7,4,3,2,1,15 from LSB to MSB
// outputs
uint8_t m_out; // pins 12-9 from LSB to MSB
uint8_t m_out; // pins 12-9 from LSB to MSB
// data
std::unique_ptr<uint8_t[]> m_data;
std::unique_ptr<uint8_t[]> m_data;
static const uint32_t PROM_SIZE;
};

2
src/devices/machine/aakart.cpp
View File

@ -136,7 +136,7 @@ void aakart_device::device_timer(emu_timer &timer, device_timer_id id, int param
m_queue_size--;
for(int i=0; i<m_queue_size; i++)
m_queue[i] = m_queue[i + 1];
}
}
break;
case 0xfd:
m_rx = 0xfd;

38
src/devices/machine/am2847.h
View File

@ -4,16 +4,16 @@
AMD Am2847/Am2896 Quad 80/96-Bit Static Shift Registers
Pin-compatible with:
* 2532B
* TMS3120
* TMS3409
* MK1007
* 3347
Pin-compatible with:
* 2532B
* TMS3120
* TMS3409
* MK1007
* 3347
***********************************************************************
Connection Diagram:
Connection Diagram:
___ ___
OUT A 1 |* u | 16 Vss
RC A 2 | | 15 IN D
@ -24,18 +24,18 @@
OUT C 7 | | 10 IN C
Vdd 8 |_______| 9 RC C
Logic Symbol:
Logic Symbol:
2 5 9 14
| | | |
_____|______|______|______|_____
| RC A RC B RC C RC D |
3 ---| IN A OUT A |--- 1
6 ---| IN A OUT B |--- 4
10 ---| IN A OUT C |--- 7
15 ---| IN A OUT D |--- 13
11 ---| CP |
|________________________________|
2 5 9 14
| | | |
_____|______|______|______|_____
| RC A RC B RC C RC D |
3 ---| IN A OUT A |--- 1
6 ---| IN A OUT B |--- 4
10 ---| IN A OUT C |--- 7
15 ---| IN A OUT D |--- 13
11 ---| CP |
|________________________________|
**********************************************************************/
@ -131,4 +131,4 @@ extern const device_type AM2847;
extern const device_type AM2849;
extern const device_type TMS3409;
#endif // AM2847_H
#endif // AM2847_H

4
src/devices/machine/com8116.h
View File

@ -4,8 +4,8 @@
COM8116 Dual Baud Rate Generator (Programmable Divider) emulation
COM5016 is a mostly-compatible clone of this chip, with +12V on
pin 9 rather than NC.
COM5016 is a mostly-compatible clone of this chip, with +12V on
pin 9 rather than NC.
**********************************************************************
_____ _____

2
src/devices/machine/dm9334.cpp
View File

@ -2,7 +2,7 @@
// copyright-holders:Ryan Holtz
/*****************************************************************************
(DM)9334 8-Bit Addressable Latch
(DM)9334 8-Bit Addressable Latch
*****************************************************************************/

94
src/devices/machine/dm9334.h
View File

@ -2,11 +2,11 @@
// copyright-holders:Ryan Holtz
/*****************************************************************************
(DM)9334 8-Bit Addressable Latch
(DM)9334 8-Bit Addressable Latch
******************************************************************************
Connection Diagram:
Connection Diagram:
___ ___
A0 1 |* u | 16 Vcc
A1 2 | | 15 /C
@ -19,49 +19,49 @@
***********************************************************************
Function Tables:
Function Tables:
/E /C Mode
L H Addressable Latch
H H Memory
L L Active High Eight
Channel Demultiplexer
H L Clear
/E /C Mode
L H Addressable Latch
H H Memory
L L Active High Eight
Channel Demultiplexer
H L Clear
___________________________________________________________________________________________
| Inputs | Present Output States | |
|---------------------------|-------------------------------------------------| Mode |
| /C /E | D | A0 A1 A2 | Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 | |
|---------|---|-------------|-------------------------------------------------|-------------|
| L H | X | X X X | L L L L L L L L | Clear |
|---------|---|-------------|-------------------------------------------------|-------------|
| L L | L | L L L | L L L L L L L L | |
| L L | H | L L L | H L L L L L L L | |
| L L | L | H L L | L L L L L L L L | |
| L L | H | H L L | L H L L L L L L | |
| * * | * | * | * | Demultiplex |
| * * | * | * | * | |
| * * | * | * | * | |
| * * | * | * | * | |
| L L | H | H H H | L L L L L L L H | |
|---------|---|-------------|-------------------------------------------------|-------------|
| H H | X | X X X | Qn-1 | Memory |
|---------|---|-------------|-------------------------------------------------|-------------|
| H L | L | L L L | L Qn-1 Qn-1 Qn-1 | |
| H L | H | L L L | H Qn-1 Qn-1 | |
| H L | L | H L L | Qn-1 L Qn-1 | |
| H L | H | H L L | Qn-1 H Qn-1 | |
| * * | * | * | * | |
| * * | * | * | * | |
| * * | * | * | * | |
| H L | L | H H H | Qn-1 Qn-1 L | |
| H L | H | H H H | Qn-1 Qn-1 H | |
|---------|---|-------------|-------------------------------------------------|-------------|
___________________________________________________________________________________________
| Inputs | Present Output States | |
|---------------------------|-------------------------------------------------| Mode |
| /C /E | D | A0 A1 A2 | Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 | |
|---------|---|-------------|-------------------------------------------------|-------------|
| L H | X | X X X | L L L L L L L L | Clear |
|---------|---|-------------|-------------------------------------------------|-------------|
| L L | L | L L L | L L L L L L L L | |
| L L | H | L L L | H L L L L L L L | |
| L L | L | H L L | L L L L L L L L | |
| L L | H | H L L | L H L L L L L L | |
| * * | * | * | * | Demultiplex |
| * * | * | * | * | |
| * * | * | * | * | |
| * * | * | * | * | |
| L L | H | H H H | L L L L L L L H | |
|---------|---|-------------|-------------------------------------------------|-------------|
| H H | X | X X X | Qn-1 | Memory |
|---------|---|-------------|-------------------------------------------------|-------------|
| H L | L | L L L | L Qn-1 Qn-1 Qn-1 | |
| H L | H | L L L | H Qn-1 Qn-1 | |
| H L | L | H L L | Qn-1 L Qn-1 | |
| H L | H | H L L | Qn-1 H Qn-1 | |
| * * | * | * | * | |
| * * | * | * | * | |
| * * | * | * | * | |
| H L | L | H H H | Qn-1 Qn-1 L | |
| H L | H | H H H | Qn-1 Qn-1 H | |
|---------|---|-------------|-------------------------------------------------|-------------|
X = Don't Care Condition
L = Low Voltage Level
H = High Voltage Level
Qn-1 = Previous Output State
X = Don't Care Condition
L = Low Voltage Level
H = High Voltage Level
Qn-1 = Previous Output State
**********************************************************************/
@ -168,13 +168,13 @@ private:
devcb_write_line m_q7_func;
// inputs
uint8_t m_e; // pin 14
uint8_t m_c; // pin 15
uint8_t m_d; // pin 13
uint8_t m_a; // pins 1-3 from LSB to MSB
uint8_t m_e; // pin 14
uint8_t m_c; // pin 15
uint8_t m_d; // pin 13
uint8_t m_a; // pins 1-3 from LSB to MSB
// outputs
uint8_t m_out; // pins 4-7 and 9-12 from LSB to MSB
uint8_t m_out; // pins 4-7 and 9-12 from LSB to MSB
};
// device type definition

14
src/devices/machine/fga002.cpp
View File

@ -34,13 +34,13 @@
#define VERBOSE 0
#define LOGPRINT(x) { do { if (VERBOSE) logerror x; } while (0); }
#define LOG(x) {} LOGPRINT(x)
#define LOGR(x) {} LOGPRINT(x)
#define LOGSETUP(x) {} LOGPRINT(x)
#define LOGINT(x) {} LOGPRINT(x)
#define LOGVEC(x) {} LOGPRINT(x)
#define LOGLVL(x) {} LOGPRINT(x)
#define LOGIACK(x) {} LOGPRINT(x)
#define LOG(x) {} LOGPRINT(x)
#define LOGR(x) {} LOGPRINT(x)
#define LOGSETUP(x) {} LOGPRINT(x)
#define LOGINT(x) {} LOGPRINT(x)
#define LOGVEC(x) {} LOGPRINT(x)
#define LOGLVL(x) {} LOGPRINT(x)
#define LOGIACK(x) {} LOGPRINT(x)
#if VERBOSE == 2
#define logerror printf

78
src/devices/machine/i82371sb.cpp
View File

@ -39,7 +39,7 @@ DEVICE_ADDRESS_MAP_START(internal_io_map, 32, i82371sb_isa_device)
AM_RANGE(0x0070, 0x007f) AM_DEVREADWRITE8("rtc", ds12885_device, read, write, 0xffffffff);
AM_RANGE(0x0080, 0x009f) AM_READWRITE8(at_page8_r, at_page8_w, 0xffffffff);
AM_RANGE(0x00a0, 0x00bf) AM_DEVREADWRITE8("pic8259_slave", pic8259_device, read, write, 0xffffffff)
AM_RANGE(0x00c0, 0x00df) AM_READWRITE8(at_dma8237_2_r, at_dma8237_2_w, 0xffffffff);
AM_RANGE(0x00c0, 0x00df) AM_READWRITE8(at_dma8237_2_r, at_dma8237_2_w, 0xffffffff);
AM_RANGE(0x00e0, 0x00ef) AM_NOP
// VGA-HACK
@ -109,43 +109,43 @@ static MACHINE_CONFIG_FRAGMENT( southbridge )
MCFG_MC146818_IRQ_HANDLER(DEVWRITELINE("pic8259_slave", pic8259_device, ir0_w))
MCFG_MC146818_CENTURY_INDEX(0x32)
// MCFG_BUS_MASTER_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", nullptr, false)
// MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("pic8259_slave", pic8259_device, ir6_w))
// MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE(":maincpu", AS_PROGRAM)
// MCFG_BUS_MASTER_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", nullptr, false)
// MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("pic8259_slave", pic8259_device, ir6_w))
// MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE(":maincpu", AS_PROGRAM)
//
// MCFG_BUS_MASTER_IDE_CONTROLLER_ADD("ide2", ata_devices, "cdrom", nullptr, false)
// MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("pic8259_slave", pic8259_device, ir7_w))
// MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE(":maincpu", AS_PROGRAM)
// MCFG_BUS_MASTER_IDE_CONTROLLER_ADD("ide2", ata_devices, "cdrom", nullptr, false)
// MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("pic8259_slave", pic8259_device, ir7_w))
// MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE(":maincpu", AS_PROGRAM)
/* sound hardware */
MCFG_SPEAKER_STANDARD_MONO("mono")
MCFG_SOUND_ADD("speaker", SPEAKER_SOUND, 0)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
//
// MCFG_DEVICE_ADD("isabus", ISA16, 0)
// MCFG_ISA16_CPU(":maincpu")
// MCFG_ISA_OUT_IRQ2_CB(DEVWRITELINE("pic8259_slave", pic8259_device, ir2_w)) // in place of irq 2 on at irq 9 is used
// MCFG_ISA_OUT_IRQ3_CB(DEVWRITELINE("pic8259_master", pic8259_device, ir3_w))
// MCFG_ISA_OUT_IRQ4_CB(DEVWRITELINE("pic8259_master", pic8259_device, ir4_w))
// MCFG_ISA_OUT_IRQ5_CB(DEVWRITELINE("pic8259_master", pic8259_device, ir5_w))
// MCFG_ISA_OUT_IRQ6_CB(DEVWRITELINE("pic8259_master", pic8259_device, ir6_w))
// MCFG_ISA_OUT_IRQ7_CB(DEVWRITELINE("pic8259_master", pic8259_device, ir7_w))
// MCFG_ISA_OUT_IRQ10_CB(DEVWRITELINE("pic8259_slave", pic8259_device, ir3_w))
// MCFG_ISA_OUT_IRQ11_CB(DEVWRITELINE("pic8259_slave", pic8259_device, ir4_w))
// MCFG_ISA_OUT_IRQ12_CB(DEVWRITELINE("pic8259_slave", pic8259_device, ir5_w))
// MCFG_ISA_OUT_IRQ14_CB(DEVWRITELINE("pic8259_slave", pic8259_device, ir6_w))
// MCFG_ISA_OUT_IRQ15_CB(DEVWRITELINE("pic8259_slave", pic8259_device, ir7_w))
// MCFG_ISA_OUT_DRQ0_CB(DEVWRITELINE("dma8237_1", am9517a_device, dreq0_w))
// MCFG_ISA_OUT_DRQ1_CB(DEVWRITELINE("dma8237_1", am9517a_device, dreq1_w))
// MCFG_ISA_OUT_DRQ2_CB(DEVWRITELINE("dma8237_1", am9517a_device, dreq2_w))
// MCFG_ISA_OUT_DRQ3_CB(DEVWRITELINE("dma8237_1", am9517a_device, dreq3_w))
// MCFG_ISA_OUT_DRQ5_CB(DEVWRITELINE("dma8237_2", am9517a_device, dreq1_w))
// MCFG_ISA_OUT_DRQ6_CB(DEVWRITELINE("dma8237_2", am9517a_device, dreq2_w))
// MCFG_ISA_OUT_DRQ7_CB(DEVWRITELINE("dma8237_2", am9517a_device, dreq3_w))
// // on board devices
// MCFG_ISA16_SLOT_ADD("isabus","board1", pc_isa_onboard, "fdcsmc", true)
// MCFG_ISA16_SLOT_ADD("isabus","board2", pc_isa_onboard, "comat", true)
// MCFG_ISA16_SLOT_ADD("isabus","board3", pc_isa_onboard, "lpt", true)
// MCFG_DEVICE_ADD("isabus", ISA16, 0)
// MCFG_ISA16_CPU(":maincpu")
// MCFG_ISA_OUT_IRQ2_CB(DEVWRITELINE("pic8259_slave", pic8259_device, ir2_w)) // in place of irq 2 on at irq 9 is used
// MCFG_ISA_OUT_IRQ3_CB(DEVWRITELINE("pic8259_master", pic8259_device, ir3_w))
// MCFG_ISA_OUT_IRQ4_CB(DEVWRITELINE("pic8259_master", pic8259_device, ir4_w))
// MCFG_ISA_OUT_IRQ5_CB(DEVWRITELINE("pic8259_master", pic8259_device, ir5_w))
// MCFG_ISA_OUT_IRQ6_CB(DEVWRITELINE("pic8259_master", pic8259_device, ir6_w))
// MCFG_ISA_OUT_IRQ7_CB(DEVWRITELINE("pic8259_master", pic8259_device, ir7_w))
// MCFG_ISA_OUT_IRQ10_CB(DEVWRITELINE("pic8259_slave", pic8259_device, ir3_w))
// MCFG_ISA_OUT_IRQ11_CB(DEVWRITELINE("pic8259_slave", pic8259_device, ir4_w))
// MCFG_ISA_OUT_IRQ12_CB(DEVWRITELINE("pic8259_slave", pic8259_device, ir5_w))
// MCFG_ISA_OUT_IRQ14_CB(DEVWRITELINE("pic8259_slave", pic8259_device, ir6_w))
// MCFG_ISA_OUT_IRQ15_CB(DEVWRITELINE("pic8259_slave", pic8259_device, ir7_w))
// MCFG_ISA_OUT_DRQ0_CB(DEVWRITELINE("dma8237_1", am9517a_device, dreq0_w))
// MCFG_ISA_OUT_DRQ1_CB(DEVWRITELINE("dma8237_1", am9517a_device, dreq1_w))
// MCFG_ISA_OUT_DRQ2_CB(DEVWRITELINE("dma8237_1", am9517a_device, dreq2_w))
// MCFG_ISA_OUT_DRQ3_CB(DEVWRITELINE("dma8237_1", am9517a_device, dreq3_w))
// MCFG_ISA_OUT_DRQ5_CB(DEVWRITELINE("dma8237_2", am9517a_device, dreq1_w))
// MCFG_ISA_OUT_DRQ6_CB(DEVWRITELINE("dma8237_2", am9517a_device, dreq2_w))
// MCFG_ISA_OUT_DRQ7_CB(DEVWRITELINE("dma8237_2", am9517a_device, dreq3_w))
// // on board devices
// MCFG_ISA16_SLOT_ADD("isabus","board1", pc_isa_onboard, "fdcsmc", true)
// MCFG_ISA16_SLOT_ADD("isabus","board2", pc_isa_onboard, "comat", true)
// MCFG_ISA16_SLOT_ADD("isabus","board3", pc_isa_onboard, "lpt", true)
// VGA-HACK
MCFG_FRAGMENT_ADD( pcvideo_vga );
// end-VGA-HACK
@ -177,7 +177,7 @@ i82371sb_isa_device::i82371sb_isa_device(const machine_config &mconfig, const ch
m_ds12885(*this, "rtc"),
m_pc_kbdc(*this, "pc_kbdc")
, m_at_spkrdata(0), m_pit_out2(0), m_dma_channel(0), m_cur_eop(false), m_dma_high_byte(0), m_at_speaker(0), m_refresh(false), m_channel_check(0), m_nmi_enabled(0)
// VGA-HACK
// VGA-HACK
,m_vga_region(*this, ":ibm_vga")
// end-VGA-HACK
{
@ -210,9 +210,9 @@ void i82371sb_isa_device::device_reset()
smireq = 0x0000;
ctlmtr = 0x00;
cthmtr = 0x00;
m_at_spkrdata = 0;
m_pit_out2 = 1;
m_dma_channel = -1;
@ -427,7 +427,7 @@ void i82371sb_isa_device::map_extra(uint64_t memory_window_start, uint64_t memor
{
map_bios(memory_space, 0xfffc0000, 0xffffffff);
map_bios(memory_space, 0x000e0000, 0x000fffff);
// VGA-HACK
// VGA-HACK
vga_device *m_vga = subdevice<vga_device>("vga");
memory_space->install_rom(0x000c0000, 0x000c7fff, m_vga_region->base());
memory_space->install_readwrite_handler(0xa0000,0xbffff,read8_delegate(FUNC(vga_device::mem_r),m_vga),write8_delegate(FUNC(vga_device::mem_w),m_vga),0xffffffff);
@ -683,7 +683,7 @@ WRITE_LINE_MEMBER( i82371sb_isa_device::at_dma8237_out_eop )
{
m_cur_eop = state == ASSERT_LINE;
//if(m_dma_channel != -1)
// m_isabus->eop_w(m_dma_channel, m_cur_eop ? ASSERT_LINE : CLEAR_LINE );
// m_isabus->eop_w(m_dma_channel, m_cur_eop ? ASSERT_LINE : CLEAR_LINE );
}
void i82371sb_isa_device::pc_select_dma_channel(int channel, bool state)
@ -691,12 +691,12 @@ void i82371sb_isa_device::pc_select_dma_channel(int channel, bool state)
if(!state) {
m_dma_channel = channel;
//if(m_cur_eop)
// m_isabus->eop_w(channel, ASSERT_LINE );
// m_isabus->eop_w(channel, ASSERT_LINE );
} else if(m_dma_channel == channel) {
m_dma_channel = -1;
//if(m_cur_eop)
// m_isabus->eop_w(channel, CLEAR_LINE );
// m_isabus->eop_w(channel, CLEAR_LINE );
}
}

8
src/devices/machine/i82371sb.h
View File

@ -84,7 +84,7 @@ public:
DECLARE_WRITE8_MEMBER (ctltmr_w);
DECLARE_READ8_MEMBER (cthtmr_r);
DECLARE_WRITE8_MEMBER (cthtmr_w);
// southbridge
DECLARE_READ8_MEMBER(at_page8_r);
DECLARE_WRITE8_MEMBER(at_page8_w);
@ -131,7 +131,7 @@ public:
DECLARE_WRITE8_MEMBER(pc_dma_write_byte);
DECLARE_READ8_MEMBER(pc_dma_read_word);
DECLARE_WRITE8_MEMBER(pc_dma_write_word);
protected:
virtual void device_start() override;
virtual void device_reset() override;
@ -145,7 +145,7 @@ private:
uint8_t dlc, smicntl, ftmr, ctlmtr, cthmtr;
void map_bios(address_space *memory_space, uint32_t start, uint32_t end);
//southbridge
required_device<cpu_device> m_maincpu;
@ -158,7 +158,7 @@ private:
required_device<speaker_sound_device> m_speaker;
required_device<ds12885_device> m_ds12885;
required_device<pc_kbdc_device> m_pc_kbdc;
uint8_t m_at_spkrdata;
uint8_t m_pit_out2;
int m_dma_channel;

12
src/devices/machine/scnxx562.cpp
View File

@ -88,12 +88,12 @@ DONE (x) (p=partly) NMOS CMOS
#define VERBOSE 0
#define LOGPRINT(x) { do { if (VERBOSE) logerror x; } while (0); }
#define LOG(x) {}
#define LOGR(x) {}
#define LOGTX(x) {}
#define LOGRX(x) {}
#define LOGSETUP(x) {} LOGPRINT(x)
#define LOGINT(x) {}
#define LOG(x) {}
#define LOGR(x) {}
#define LOGTX(x) {}
#define LOGRX(x) {}
#define LOGSETUP(x) {} LOGPRINT(x)
#define LOGINT(x) {}
#if VERBOSE > 1
#define logerror printf

4
src/devices/machine/z80dart.cpp
View File

@ -537,8 +537,8 @@ void z80dart_channel::device_start()
// state saving
save_item(NAME(m_rr));
save_item(NAME(m_wr));
// save_item(NAME(m_rx_data_fifo));
// save_item(NAME(m_rx_error_fifo));
// save_item(NAME(m_rx_data_fifo));
// save_item(NAME(m_rx_error_fifo));
save_item(NAME(m_rx_clock));
save_item(NAME(m_rx_first));
save_item(NAME(m_rx_break));

46
src/devices/machine/z80scc.cpp
View File

@ -295,30 +295,30 @@ conditions. In addition, there are four sources per channel: 0) Transmitt 1) Ext
which affects the way the interrupt vector is formed. The sources in more detail
INT_RECEIVE: The sources of receive interrupts consist of Receive Character Available and Special Receive Condition.
The Special Receive Condition can be subdivided into Receive Overrun, Framing Error (Asynchronous) or
End of Frame (SDLC). In addition, a parity error can be a special receive condition by programming
The Special Receive Condition can be subdivided into Receive Overrun, Framing Error (Asynchronous) or
End of Frame (SDLC). In addition, a parity error can be a special receive condition by programming
INT_EXTERNAL: The External/status interrupts have several sources which may be individually enabled in WR15.
The sources are zero count, /DCD, Sync/Hunt, /CTS, transmitter under-run/EOM and Break/Abort.
INT_TRANSMIT: The NMOS/CMOS version of the SCC only has a one byte deep transmit buffer. The status of the
transmit buffer can be determined through TBE bit in RR0, bit D2, which shows whether the
transmit buffer is empty or not. After a hardware reset (including a hardware reset by software), or
a channel reset, this bit is set to 1.
While transmit interrupts are enabled, the NMOS/CMOS version sets the Transmit Interrupt Pending
(TxIP) bit whenever the transmit buffer becomes empty. This means that the transmit buffer
must be full before the TxIP can be set. Thus, when transmit interrupts are first enabled, the TxIP
will not be set until after the first character is written to the NMOS/CMOS.
transmit buffer can be determined through TBE bit in RR0, bit D2, which shows whether the
transmit buffer is empty or not. After a hardware reset (including a hardware reset by software), or
a channel reset, this bit is set to 1.
While transmit interrupts are enabled, the NMOS/CMOS version sets the Transmit Interrupt Pending
(TxIP) bit whenever the transmit buffer becomes empty. This means that the transmit buffer
must be full before the TxIP can be set. Thus, when transmit interrupts are first enabled, the TxIP
will not be set until after the first character is written to the NMOS/CMOS.
INT_SPECIAL: This mode allows the receiver to interrupt only on
characters with a special receive condition. When an interrupt occurs, the data containing the error
is held in the Receive FIFO until an Error Reset command is issued. When using this mode in conjunction
with a DMA, the DMA is initialized and enabled before any characters have been
received by the ESCC. This eliminates the time-critical section of code required in the Receive
Interrupt on First Character or Special Condition mode. Hence, all data can be transferred via the
DMA so that the CPU need not handle the first received character as a special case. In SDLC
mode, if the SDLC Frame Status FIFO is enabled and an EOF is received, an interrupt with vector
for receive data available is generated and the Receive FIFO is not locked.
is held in the Receive FIFO until an Error Reset command is issued. When using this mode in conjunction
with a DMA, the DMA is initialized and enabled before any characters have been
received by the ESCC. This eliminates the time-critical section of code required in the Receive
Interrupt on First Character or Special Condition mode. Hence, all data can be transferred via the
DMA so that the CPU need not handle the first received character as a special case. In SDLC
mode, if the SDLC Frame Status FIFO is enabled and an EOF is received, an interrupt with vector
for receive data available is generated and the Receive FIFO is not locked.
To allow for control over the daisy chain, the SCC has a Disable Lower Chain (DLC) software command (WR9 bit 2)
that pulls IEO Low. This selectively deactivates parts of the daisy chain regardless of the interrupt status.
@ -1847,9 +1847,9 @@ void z80scc_channel::do_sccreg_wr4(uint8_t data)
m_wr4 = data;
LOG(("- Parity : %s\n", (data & WR4_PARITY_ENABLE) ? ((data & WR4_PARITY_EVEN) ? "Even" : "Odd") : "None"));
LOG(("- Stop Bits : %s\n", data & WR4_STOP_BITS_MASK ? stop_bits_tostring(get_stop_bits()) : "not used, sync modes enabled" ));
LOG(("- Sync Mode : %s\n", !(data & WR4_STOP_BITS_MASK) ?
(data & WR4_BIT5 ?
(data & WR4_BIT4 ? "External Sync Mode - /SYNC is used as input!" : "SDLC - not implemented")
LOG(("- Sync Mode : %s\n", !(data & WR4_STOP_BITS_MASK) ?
(data & WR4_BIT5 ?
(data & WR4_BIT4 ? "External Sync Mode - /SYNC is used as input!" : "SDLC - not implemented")
: (data & WR4_BIT4 ? "16 bit" : "8 bit"))
: "Disabled"));
LOG(("- Clock Mode: %uX\n", get_clock_mode()));
@ -1946,7 +1946,7 @@ void z80scc_channel::do_sccreg_wr9(uint8_t data)
}
}
/* WR10 contains miscellaneous control bits for both the receiver and the transmitter.
/* WR10 contains miscellaneous control bits for both the receiver and the transmitter.
On the ESCC and 85C30 with the Extended Read option enabled, this register may be read as RR11.*/
void z80scc_channel::do_sccreg_wr10(uint8_t data)
{
@ -2420,7 +2420,7 @@ void z80scc_channel::data_write(uint8_t data)
}
}
else
{
{
LOGTX(("- Transmitter disabled\n"));
}
/* "While transmit interrupts are enabled, the nmos/cmos version sets the transmit interrupt pending
@ -2520,7 +2520,7 @@ WRITE_LINE_MEMBER( z80scc_channel::cts_w )
if (state) m_rr0 |= RR0_CTS; else m_rr0 &= ~RR0_CTS; // Raw pin/status value
if (m_extint_latch == 0 && (m_wr1 & WR1_EXT_INT_ENABLE) && (m_wr15 & WR15_CTS))
{
{
// trigger interrupt
LOGCTS((" - Trigger CTS interrupt\n"));
m_uart->trigger_interrupt(m_index, INT_EXTERNAL);
@ -2755,7 +2755,7 @@ void z80scc_channel::update_serial()
parity = PARITY_ODD;
}
else
{
{
parity = PARITY_NONE;
}

68
src/devices/machine/z80scc.h
View File

@ -310,10 +310,10 @@ protected:
{
REG_WR0_COMMAND_REGPT = 0,
REG_WR1_INT_DMA_ENABLE = 1,
REG_WR2_INT_VECTOR = 2,
REG_WR3_RX_CONTROL = 3,
REG_WR4_RX_TX_MODES = 4,
REG_WR5_TX_CONTROL = 5,
REG_WR2_INT_VECTOR = 2,
REG_WR3_RX_CONTROL = 3,
REG_WR4_RX_TX_MODES = 4,
REG_WR5_TX_CONTROL = 5,
REG_WR6_SYNC_OR_SDLC_A = 6,
REG_WR7_SYNC_OR_SDLC_F = 7,
REG_WR8_TRANSMIT_DATA = 8,
@ -322,30 +322,30 @@ protected:
REG_WR11_CLOCK_MODES = 11,
REG_WR12_LO_BAUD_GEN = 12,
REG_WR13_HI_BAUD_GEN = 13,
REG_WR14_MISC_CTRL = 14,
REG_WR14_MISC_CTRL = 14,
REG_WR15_EXT_ST_INT_CTRL= 15
};
enum
{
RR0_RX_CHAR_AVAILABLE = 0x01,
RR0_ZC = 0x02,
RR0_TX_BUFFER_EMPTY = 0x04,
RR0_DCD = 0x08,
RR0_SYNC_HUNT = 0x10,
RR0_CTS = 0x20,
RR0_TX_UNDERRUN = 0x40,
RR0_BREAK_ABORT = 0x80
RR0_ZC = 0x02,
RR0_TX_BUFFER_EMPTY = 0x04,
RR0_DCD = 0x08,
RR0_SYNC_HUNT = 0x10,
RR0_CTS = 0x20,
RR0_TX_UNDERRUN = 0x40,
RR0_BREAK_ABORT = 0x80
};
enum
{
RR1_ALL_SENT = 0x01,
RR1_ALL_SENT = 0x01,
RR1_RESIDUE_CODE_MASK = 0x0e,
RR1_PARITY_ERROR = 0x10,
RR1_PARITY_ERROR = 0x10,
RR1_RX_OVERRUN_ERROR = 0x20,
RR1_CRC_FRAMING_ERROR = 0x40,
RR1_END_OF_FRAME = 0x80
RR1_END_OF_FRAME = 0x80
};
enum
@ -413,17 +413,17 @@ protected:
WR1_RX_INT_ALL = 0x18,
WR1_WRDY_ON_RX_TX = 0x20,
WR1_WRDY_FUNCTION = 0x40,
WR1_WRDY_ENABLE = 0x80
WR1_WRDY_ENABLE = 0x80
};
enum
{
WR3_RX_ENABLE = 0x01,
WR3_RX_ENABLE = 0x01,
WR3_SYNC_CHAR_LOAD_INHIBIT = 0x02,
WR3_ADDRESS_SEARCH_MODE = 0x04,
WR3_RX_CRC_ENABLE = 0x08,
WR3_RX_CRC_ENABLE = 0x08,
WR3_ENTER_HUNT_MODE = 0x10,
WR3_AUTO_ENABLES = 0x20,
WR3_AUTO_ENABLES = 0x20,
WR3_RX_WORD_LENGTH_MASK = 0xc0,
WR3_RX_WORD_LENGTH_5 = 0x00,
WR3_RX_WORD_LENGTH_7 = 0x40,
@ -442,9 +442,9 @@ protected:
WR4_SYNC_MODE_MASK = 0x30,
WR4_SYNC_MODE_8_BIT = 0x00,
WR4_SYNC_MODE_16_BIT = 0x10,
WR4_BIT4 = 0x10,
WR4_BIT4 = 0x10,
WR4_SYNC_MODE_SDLC = 0x20,
WR4_BIT5 = 0x20,
WR4_BIT5 = 0x20,
WR4_SYNC_MODE_EXT = 0x30,
WR4_CLOCK_RATE_MASK = 0xc0,
WR4_CLOCK_RATE_X1 = 0x00,
@ -455,11 +455,11 @@ protected:
enum
{
WR5_TX_CRC_ENABLE = 0x01,
WR5_RTS = 0x02,
WR5_CRC16 = 0x04,
WR5_TX_ENABLE = 0x08,
WR5_SEND_BREAK = 0x10,
WR5_TX_CRC_ENABLE = 0x01,
WR5_RTS = 0x02,
WR5_CRC16 = 0x04,
WR5_TX_ENABLE = 0x08,
WR5_SEND_BREAK = 0x10,
WR5_TX_WORD_LENGTH_MASK = 0x60,
WR5_TX_WORD_LENGTH_5 = 0x00,
WR5_TX_WORD_LENGTH_6 = 0x40,
@ -481,27 +481,27 @@ protected:
WR9_CMD_CHNB_RESET = 0x40,
WR9_CMD_CHNA_RESET = 0x80,
WR9_CMD_HW_RESET = 0xC0,
WR9_BIT_VIS = 0x01,
WR9_BIT_NV = 0x02,
WR9_BIT_DLC = 0x04,
WR9_BIT_MIE = 0x08,
WR9_BIT_VIS = 0x01,
WR9_BIT_NV = 0x02,
WR9_BIT_DLC = 0x04,
WR9_BIT_MIE = 0x08,
WR9_BIT_SHSL = 0x10,
WR9_BIT_IACK = 0x20
};
enum
{
WR10_8_6_BIT_SYNC = 0x01,
WR10_LOOP_MODE = 0x02,
WR10_8_6_BIT_SYNC = 0x01,
WR10_LOOP_MODE = 0x02,
WR10_ABORT_FLAG_UNDERRUN = 0x04,
WR10_MARK_FLAG_IDLE = 0x08,
WR10_GO_ACTIVE_ON_POLL = 0x10,
WR10_ENCODING_MASK = 0x60,
WR10_NRZ_ENCODING = 0x00,
WR10_NRZI_ENCODING = 0x20,
WR10_BIT5 = 0x20,
WR10_BIT5 = 0x20,
WR10_FM1_ENCODING = 0x40,
WR10_BIT6 = 0x40,
WR10_BIT6 = 0x40,
WR10_FM0_ENCODING = 0x60,
WR10_CRC_PRESET = 0x80
};

12
src/devices/machine/z80sio.cpp
View File

@ -1085,12 +1085,12 @@ void z80sio_channel::control_write(uint8_t data)
switch (reg)
{
case REG_WR0_COMMAND_REGPT: do_sioreg_wr0(data); break;
case REG_WR1_INT_DMA_ENABLE: do_sioreg_wr1(data); m_uart->check_interrupts(); break;
case REG_WR2_INT_VECTOR: do_sioreg_wr2(data); break;
case REG_WR3_RX_CONTROL: do_sioreg_wr3(data); update_serial(); break;
case REG_WR4_RX_TX_MODES: do_sioreg_wr4(data); update_serial(); break;
case REG_WR5_TX_CONTROL: do_sioreg_wr5(data); update_serial(); update_rts(); break;
case REG_WR0_COMMAND_REGPT: do_sioreg_wr0(data); break;
case REG_WR1_INT_DMA_ENABLE: do_sioreg_wr1(data); m_uart->check_interrupts(); break;
case REG_WR2_INT_VECTOR: do_sioreg_wr2(data); break;
case REG_WR3_RX_CONTROL: do_sioreg_wr3(data); update_serial(); break;
case REG_WR4_RX_TX_MODES: do_sioreg_wr4(data); update_serial(); break;
case REG_WR5_TX_CONTROL: do_sioreg_wr5(data); update_serial(); update_rts(); break;
case REG_WR6_SYNC_OR_SDLC_A: do_sioreg_wr6(data); break;
case REG_WR7_SYNC_OR_SDLC_F: do_sioreg_wr7(data); break;
default:

4
src/devices/machine/z80sio.h
View File

@ -493,8 +493,8 @@ protected:
enum
{
TYPE_Z80SIO = 0x001,
TYPE_UPD7201 = 0x002
TYPE_Z80SIO = 0x001,
TYPE_UPD7201 = 0x002
};
enum

12
src/devices/video/stvvdp2.cpp
View File

@ -2145,7 +2145,7 @@ void saturn_state::stv_vdp2_fill_rotation_parameter_table( uint8_t rot_parameter
stv_current_rotation_parameter_table.dkast= (m_vdp2_vram[address/4 + 22] & 0x03ffffc0) | ((m_vdp2_vram[address/4 + 22] & 0x02000000) ? 0xfc000000 : 0x00000000 );
stv_current_rotation_parameter_table.dkax = (m_vdp2_vram[address/4 + 23] & 0x03ffffc0) | ((m_vdp2_vram[address/4 + 23] & 0x02000000) ? 0xfc000000 : 0x00000000 );
// check rotation parameter read control, override if specific bits are disabled
// check rotation parameter read control, override if specific bits are disabled
// (Batman Forever The Riddler stage relies on this)
switch(rot_parameter)
{
@ -2155,7 +2155,7 @@ void saturn_state::stv_vdp2_fill_rotation_parameter_table( uint8_t rot_parameter
if(!STV_VDP2_RAYSTRE)
stv_current_rotation_parameter_table.yst = 0;
if(!STV_VDP2_RAKASTRE)
stv_current_rotation_parameter_table.dkax = 0;
@ -2166,13 +2166,13 @@ void saturn_state::stv_vdp2_fill_rotation_parameter_table( uint8_t rot_parameter
if(!STV_VDP2_RBYSTRE)
stv_current_rotation_parameter_table.yst = 0;
if(!STV_VDP2_RBKASTRE)
stv_current_rotation_parameter_table.dkax = 0;
break;
}
#define RP stv_current_rotation_parameter_table
if(LOG_ROZ == 1) logerror( "Rotation parameter table (%d)\n", rot_parameter );
@ -4806,7 +4806,7 @@ void saturn_state::stv_vdp2_copy_roz_bitmap(bitmap_rgb32 &bitmap,
}
}
else
{
{
for (hcnt = cliprect.min_x; hcnt <= cliprect.max_x; hcnt++ )
{
switch( coeff_table_size )

6
src/emu/addrmap.cpp
View File

@ -311,7 +311,7 @@ bool address_map_entry::unitmask_is_appropriate(u8 width, u64 unitmask, const ch
address_map::address_map(device_t &device, address_spacenum spacenum)
: m_spacenum(spacenum),
m_device(&device),
m_device(&device),
m_databits(0xff),
m_unmapval(0),
m_globalmask(0)
@ -357,7 +357,7 @@ address_map::address_map(device_t &device, address_spacenum spacenum)
address_map::address_map(device_t &device, address_map_entry *entry)
: m_spacenum(AS_PROGRAM),
m_device(&device),
m_device(&device),
m_databits(0xff),
m_unmapval(0),
m_globalmask(0)
@ -375,7 +375,7 @@ address_map::address_map(device_t &device, address_map_entry *entry)
address_map::address_map(const address_space &space, offs_t start, offs_t end, int bits, u64 unitmask, device_t &device, address_map_delegate submap_delegate)
: m_spacenum(space.spacenum()),
m_device(&device),
m_device(&device),
m_databits(space.data_width()),
m_unmapval(space.unmap()),
m_globalmask(space.bytemask())

2
src/emu/inpttype.h
View File

@ -156,7 +156,7 @@ inline void construct_core_types_P2(simple_list<input_type_entry> &typelist)
INPUT_PORT_DIGITAL_TYPE( 2, PLAYER2, JOYSTICK_DOWN, "P2 Down", input_seq(KEYCODE_F, input_seq::or_code, JOYCODE_Y_DOWN_SWITCH_INDEXED(1)) )
INPUT_PORT_DIGITAL_TYPE( 2, PLAYER2, JOYSTICK_LEFT, "P2 Left", input_seq(KEYCODE_D, input_seq::or_code, JOYCODE_X_LEFT_SWITCH_INDEXED(1)) )
INPUT_PORT_DIGITAL_TYPE( 2, PLAYER2, JOYSTICK_RIGHT, "P2 Right", input_seq(KEYCODE_G, input_seq::or_code, JOYCODE_X_RIGHT_SWITCH_INDEXED(1)) )
INPUT_PORT_DIGITAL_TYPE( 2, PLAYER2, JOYSTICKRIGHT_UP, "P2 Right Stick/Up", input_seq() )
INPUT_PORT_DIGITAL_TYPE( 2, PLAYER2, JOYSTICKRIGHT_UP, "P2 Right Stick/Up", input_seq() )
INPUT_PORT_DIGITAL_TYPE( 2, PLAYER2, JOYSTICKRIGHT_DOWN, "P2 Right Stick/Down", input_seq() )
INPUT_PORT_DIGITAL_TYPE( 2, PLAYER2, JOYSTICKRIGHT_LEFT, "P2 Right Stick/Left", input_seq() )
INPUT_PORT_DIGITAL_TYPE( 2, PLAYER2, JOYSTICKRIGHT_RIGHT, "P2 Right Stick/Right", input_seq() )

2
src/emu/layout/README.md
View File

@ -3,4 +3,4 @@
Layouts files are definiton files to describe look and fell of emulated machines, and are product
of many different contributors.
Licensed under [CC0 1.0 Universal (CC0 1.0)](https://creativecommons.org/publicdomain/zero/1.0/)
Licensed under [CC0 1.0 Universal (CC0 1.0)](https://creativecommons.org/publicdomain/zero/1.0/)

4
src/frontend/mame/luaengine.cpp
View File

@ -64,7 +64,7 @@ namespace sol
lua_setfield(L, LUA_REGISTRYINDEX, "sol::buffer_temp");
}
else
lua_pop(L, -1);
lua_pop(L, -1);
luaL_pushresultsize(&buff, len);
}
@ -814,7 +814,7 @@ void lua_engine::initialize()
auto ret = func();
if (ret.valid()) {
const char *tmp = ret.get<const char *>();
if (tmp != nullptr)
if (tmp != nullptr)
ctx.result = tmp;
else
exit(0);

4
src/frontend/mame/ui/pluginopt.h
View File

@ -25,9 +25,9 @@ class menu_plugin : public menu
{
public:
menu_plugin(mame_ui_manager &mui, render_container &container);
static void show_menu(mame_ui_manager &mui, render_container &container, char *menu);
virtual ~menu_plugin();
private:

6
src/lib/util/delegate.h
View File

@ -181,7 +181,7 @@ struct delegate_traits
using static_func_type = _ReturnType(*)(_ClassType *, Params...);
using static_ref_func_type = _ReturnType(*)(_ClassType &, Params...);
using member_func_type = _ReturnType(_ClassType::*)(Params...);
using const_member_func_type = _ReturnType(_ClassType::*)(Params...) const;
using const_member_func_type = _ReturnType(_ClassType::*)(Params...) const;
};
@ -507,7 +507,7 @@ public:
m_raw_function(nullptr),
m_std_func(funcptr)
{
}
// copy operator
@ -588,7 +588,7 @@ protected:
late_bind_func m_latebinder; // late binding helper
generic_static_func m_raw_function; // raw static function pointer
delegate_mfp m_raw_mfp; // raw member function pointer
functional_type m_std_func; // std::function pointer
functional_type m_std_func; // std::function pointer
};

60
src/mame/audio/rax.cpp
View File

@ -3,7 +3,7 @@
/***************************************************************************
Acclaim RAX Sound Board
****************************************************************************/
#include "emu.h"
@ -93,7 +93,7 @@ READ16_MEMBER( acclaim_rax_device::adsp_control_r )
WRITE16_MEMBER( acclaim_rax_device::adsp_control_w )
{
m_control_regs[offset] = data;
switch (offset)
{
case 0x1:
@ -116,9 +116,9 @@ WRITE16_MEMBER( acclaim_rax_device::adsp_control_w )
uint32_t dir = (m_control_regs[BDMA_CONTROL_REG] >> 2) & 1;
uint32_t type = m_control_regs[BDMA_CONTROL_REG] & 3;
uint32_t src_addr = (page << 14) | m_control_regs[BDMA_EXT_ADDR_REG];
uint32_t count = m_control_regs[BDMA_WORD_COUNT_REG];
address_space* addr_space = (type == 0 ? m_program : m_data);
if (dir == 0)
@ -139,7 +139,7 @@ WRITE16_MEMBER( acclaim_rax_device::adsp_control_w )
else if (type == 1)
{
while (count)
{
{
uint16_t src_word = (adsp_rom[src_addr + 0] << 8) | adsp_rom[src_addr + 1];
addr_space->write_word(m_control_regs[BDMA_INT_ADDR_REG] * 2, src_word);
@ -152,9 +152,9 @@ WRITE16_MEMBER( acclaim_rax_device::adsp_control_w )
else
{
int shift = type == 2 ? 8 : 0;
while (count)
{
{
uint16_t src_word = adsp_rom[src_addr] << shift;
addr_space->write_word(m_control_regs[BDMA_INT_ADDR_REG] * 2, src_word);
@ -176,7 +176,7 @@ WRITE16_MEMBER( acclaim_rax_device::adsp_control_w )
break;
}
case S1_AUTOBUF_REG:
/* autobuffer off: nuke the timer, and disable the DAC */
if ((data & 0x0002) == 0)
@ -184,7 +184,7 @@ WRITE16_MEMBER( acclaim_rax_device::adsp_control_w )
dmadac_enable(&m_dmadac[1], 1, 0);
}
break;
case S0_AUTOBUF_REG:
/* autobuffer off: nuke the timer, and disable the DAC */
if ((data & 0x0002) == 0)
@ -193,7 +193,7 @@ WRITE16_MEMBER( acclaim_rax_device::adsp_control_w )
m_reg_timer[0]->reset();
}
break;
case S1_CONTROL_REG:
if (((data >> 4) & 3) == 2)
fatalerror("DCS: Oh no!, the data is compressed with u-law encoding\n");
@ -220,7 +220,7 @@ TIMER_DEVICE_CALLBACK_MEMBER( acclaim_rax_device::dma_timer_callback )
m_control_regs[BDMA_EXT_ADDR_REG] = param & 0x3fff;
m_control_regs[BDMA_CONTROL_REG] &= ~0xff00;
m_control_regs[BDMA_CONTROL_REG] |= ((param >> 14) & 0xff) << 8;
if (m_control_regs[BDMA_CONTROL_REG] & 8)
m_cpu->set_input_line(INPUT_LINE_RESET, PULSE_LINE);
else
@ -298,10 +298,10 @@ void acclaim_rax_device::device_start()
m_dmadac[0] = subdevice<dmadac_sound_device>("dacl");
m_dmadac[1] = subdevice<dmadac_sound_device>("dacr");
m_reg_timer[0] = subdevice<timer_device>("adsp_reg_timer0");
m_dma_timer = subdevice<timer_device>("adsp_dma_timer");
// 1 bank for internal
membank("databank")->configure_entries(0, 5, auto_alloc_array(machine(), uint16_t, 0x2000 * 5), 0x2000*sizeof(uint16_t));
}
@ -322,15 +322,15 @@ void acclaim_rax_device::device_reset()
m_adsp_snd_pf0 = 1;
m_rom_bank = 0;
/* initialize our state structure and install the transmit callback */
m_size[0] = 0;
m_incs[0] = 0;
m_ireg[0] = 0;
/* initialize the ADSP control regs */
memset(m_control_regs, 0, sizeof(m_control_regs));
m_dmovlay_val = 0;
m_data_bank = 0;
update_data_ram_bank();
@ -344,10 +344,10 @@ void acclaim_rax_device::adsp_irq(int which)
/* get the index register */
int reg = m_cpu->state_int(ADSP2100_I0 + m_ireg[which]);
/* copy the current data into the buffer */
int count = m_size[which] / (4 * (m_incs[which] ? m_incs[which] : 1));
int16_t buffer[0x100];
for (uint32_t i = 0; i < count; i++)
@ -378,15 +378,15 @@ TIMER_DEVICE_CALLBACK_MEMBER( acclaim_rax_device::adsp_irq0 )
void acclaim_rax_device::recompute_sample_rate(int which)
{
/* calculate how long until we generate an interrupt */
/* frequency the time per each bit sent */
attotime sample_period = attotime::from_hz(m_cpu->unscaled_clock()) * (1 * (m_control_regs[which ? S1_SCLKDIV_REG : S0_SCLKDIV_REG] + 1));
/* now put it down to samples, so we know what the channel frequency has to be */
sample_period = sample_period * (16 * 1);
dmadac_set_frequency(&m_dmadac[0], 2, ATTOSECONDS_TO_HZ(sample_period.attoseconds()));
dmadac_enable(&m_dmadac[0], 2, 1);
/* fire off a timer which will hit every half-buffer */
if (m_incs[which])
{
@ -398,7 +398,7 @@ void acclaim_rax_device::recompute_sample_rate(int which)
WRITE32_MEMBER(acclaim_rax_device::adsp_sound_tx_callback)
{
int which = offset;
if (which != 0)
return;
@ -413,27 +413,27 @@ WRITE32_MEMBER(acclaim_rax_device::adsp_sound_tx_callback)
/* get the autobuffer registers */
int mreg, lreg;
uint16_t source;
m_ireg[which] = (m_control_regs[autobuf_reg] >> 9) & 7;
mreg = (m_control_regs[autobuf_reg] >> 7) & 3;
mreg |= m_ireg[which] & 0x04; /* msb comes from ireg */
lreg = m_ireg[which];
/* now get the register contents in a more legible format */
/* we depend on register indexes to be continuous (which is the case in our core) */
source = m_cpu->state_int(ADSP2100_I0 + m_ireg[which]);
m_incs[which] = m_cpu->state_int(ADSP2100_M0 + mreg);
m_size[which] = m_cpu->state_int(ADSP2100_L0 + lreg);
/* get the base value, since we need to keep it around for wrapping */
source -= m_incs[which];
/* make it go back one so we dont lose the first sample */
m_cpu->set_state_int(ADSP2100_I0 + m_ireg[which], source);
/* save it as it is now */
m_ireg_base[which] = source;
/* recompute the sample rate and timer */
recompute_sample_rate(which);
return;
@ -441,10 +441,10 @@ WRITE32_MEMBER(acclaim_rax_device::adsp_sound_tx_callback)
else
logerror( "ADSP SPORT1: trying to transmit and autobuffer not enabled!\n" );
}
/* if we get there, something went wrong. Disable playing */
dmadac_enable(&m_dmadac[0], 2, 0);
/* remove timer */
m_reg_timer[which]->reset();
}

58
src/mame/audio/rax.h
View File

@ -22,31 +22,31 @@ public:
READ16_MEMBER( data_r );
WRITE16_MEMBER( data_w );
READ16_MEMBER(adsp_control_r);
WRITE16_MEMBER(adsp_control_w);
WRITE16_MEMBER(ram_bank_w);
WRITE16_MEMBER(rom_bank_w);
READ16_MEMBER(host_r);
WRITE16_MEMBER(host_w);
void update_data_ram_bank();
void adsp_irq(int which);
void recompute_sample_rate(int which);
WRITE32_MEMBER(adsp_sound_tx_callback);
TIMER_DEVICE_CALLBACK_MEMBER(adsp_irq0);
TIMER_DEVICE_CALLBACK_MEMBER(sport0_irq);
WRITE32_MEMBER(dmovlay_callback);
required_device<adsp2181_device> m_cpu;
required_shared_ptr<uint32_t> m_adsp_pram;
required_memory_bank m_adsp_data_bank;
required_shared_ptr<uint32_t> m_adsp_pram;
required_memory_bank m_adsp_data_bank;
uint32_t m_adsp_snd_pf0;
struct
{
uint16_t bdma_internal_addr;
@ -54,38 +54,38 @@ public:
uint16_t bdma_control;
uint16_t bdma_word_count;
} m_adsp_regs;
address_space *m_program;
address_space *m_data;
uint16_t m_control_regs[32];
uint8_t* m_rom;
uint16_t m_control_regs[32];
uint8_t* m_rom;
/* sound output */
uint16_t m_size[2];
uint16_t m_incs[2];
dmadac_sound_device *m_dmadac[2];
timer_device *m_reg_timer[2];
timer_device *m_sport_timer;
uint32_t m_ireg[2];
uint16_t m_ireg_base[2];
uint32_t m_data_bank;
uint32_t m_rom_bank;
uint32_t m_dmovlay_val;
uint16_t m_size[2];
uint16_t m_incs[2];
dmadac_sound_device *m_dmadac[2];
timer_device *m_reg_timer[2];
timer_device *m_sport_timer;
uint32_t m_ireg[2];
uint16_t m_ireg_base[2];
uint32_t m_data_bank;
uint32_t m_rom_bank;
uint32_t m_dmovlay_val;
required_device<generic_latch_16_device> m_data_in;
required_device<generic_latch_16_device> m_data_out;
timer_device *m_dma_timer;
TIMER_DEVICE_CALLBACK_MEMBER( dma_timer_callback );
protected:
// device-level overrides
virtual void device_start() override;
virtual void device_reset() override;
virtual machine_config_constructor device_mconfig_additions() const override;
virtual machine_config_constructor device_mconfig_additions() const override;
};
// device type definition

6
src/mame/drivers/amusco.cpp
View File

@ -230,7 +230,7 @@ WRITE8_MEMBER(amusco_state::output_a_w)
output().set_lamp_value(4, (data >> 4) & 1); // Lamp 4 (Hold/Disc 2)
output().set_lamp_value(5, (data >> 5) & 1); // Lamp 5 (Hold/Disc 4)
// logerror("Writing %02Xh to PPI output A\n", data);
// logerror("Writing %02Xh to PPI output A\n", data);
}
WRITE8_MEMBER(amusco_state::output_b_w)
@ -251,12 +251,12 @@ WRITE8_MEMBER(amusco_state::output_b_w)
//machine().bookkeeping().coin_counter_w(0, ~data & 0x10); // Probably not coin-related
// logerror("Writing %02Xh to PPI output B\n", data);
// logerror("Writing %02Xh to PPI output B\n", data);
}
WRITE8_MEMBER(amusco_state::output_c_w)
{
// logerror("Writing %02Xh to PPI output C\n", data);
// logerror("Writing %02Xh to PPI output C\n", data);
}
WRITE8_MEMBER(amusco_state::vram_w)

1224
src/mame/drivers/aristmk5.cpp
View File

File diff suppressed because it is too large Load Diff

4
src/mame/drivers/aristmk6.cpp
View File

@ -46,7 +46,7 @@ public:
u8 irl0pend, irl0en;
u8 irl1pend, irl1en;
u8 irl2pend, irl2en; // UARTs ?
u8 irl2pend, irl2en; // UARTs ?
u8 irl3pend0, irl3en0;
u8 irl3pend1, irl3en1;
void testIrq();
@ -168,7 +168,7 @@ uint32_t aristmk6_state::screen_update_aristmk6(screen_device &screen, bitmap_rg
uint32_t pix1;
int col;
pix1 = pix & 0xffffffff;
col = 0;
if (pix1) col = 1;

4
src/mame/drivers/bionicc.cpp
View File

@ -20,7 +20,7 @@
Horizontal scan rate: 15.606kHz
Vertical scan rate: 60.024Hz
pixel clock: 6.000MHz, 166ns per pixel
htotal: 64.076us, 386 pixels
@ -373,7 +373,7 @@ static MACHINE_CONFIG_START( bionicc, bionicc_state )
MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", bionicc_state, bionicc_scanline, "screen", 0, 1)
/* Protection MCU Intel C8751H-88 runs at 24MHz / 4 = 6MHz */
MCFG_CPU_ADD("audiocpu", Z80, XTAL_14_31818MHz / 4) /* EXO3 C,B=GND, A=5V ==> Divisor 2^2 */
MCFG_CPU_PROGRAM_MAP(sound_map)
/* FIXME: interrupt timing

2
src/mame/drivers/clshroad.cpp
View File

@ -372,7 +372,7 @@ MACHINE_CONFIG_END
* 2 x NEC D780C
** 18.??? MHz clock
***************************************************************************/
ROM_START( firebatl )

6
src/mame/drivers/concept.cpp
View File

@ -306,10 +306,10 @@ ROM_START( concept )
// the source code)
ROM_LOAD16_WORD("cc.prm", 0x010000, 0x2000, CRC(b5a87dab) SHA1(0da59af6cfeeb38672f71731527beac323d9c3d6))
#endif
ROM_REGION16_BE(0x2000, "macsbug", 0)
ROM_LOAD16_BYTE( "mb20h.bin", 0x000000, 0x001000, CRC(aa357112) SHA1(88211e5f59887928c557c27cdea674f48bf8eaf7) )
ROM_LOAD16_BYTE( "mb20l.bin", 0x000001, 0x001000, CRC(b4b59de9) SHA1(3e8b8b5950b5359203c054f94af1fc5b8f0495b9) )
ROM_LOAD16_BYTE( "mb20h.bin", 0x000000, 0x001000, CRC(aa357112) SHA1(88211e5f59887928c557c27cdea674f48bf8eaf7) )
ROM_LOAD16_BYTE( "mb20l.bin", 0x000001, 0x001000, CRC(b4b59de9) SHA1(3e8b8b5950b5359203c054f94af1fc5b8f0495b9) )
ROM_END
/* YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY FULLNAME */

24
src/mame/drivers/crystal.cpp
View File

@ -403,7 +403,7 @@ void crystal_state::TimerStart(int which)
attotime period = attotime::from_hz(43000000) * ((PD + 1) * (TCV + 1));
m_Timer[which]->adjust(period);
// printf("timer %d start, PD = %x TCV = %x period = %s\n", which, PD, TCV, period.as_string());
// printf("timer %d start, PD = %x TCV = %x period = %s\n", which, PD, TCV, period.as_string());
}
TIMER_CALLBACK_MEMBER(crystal_state::Timercb)
@ -438,7 +438,7 @@ void crystal_state::Timer_w( address_space &space, int which, uint32_t data, uin
{
// Timer stop
m_Timer[which]->adjust(attotime::never);
// printf("timer %d stop\n", which);
// printf("timer %d stop\n", which);
}
}
}
@ -720,15 +720,15 @@ READ32_MEMBER(crystal_state::crzyddz2_key_r)
uint8_t data = 0x3f;
for (int i = 0; i < sizeof(key_names)/sizeof(key_names[0]); ++i)
if (!BIT(mux,i))
data = ioport(key_names[i])->read();
data = ioport(key_names[i])->read();
/*
crzyddz2 in out
00 40
40 00
c0 80
crzyddz2 in out
00 40
40 00
c0 80
*/
// m_crzyddz2_prot = (m_PIO >> 8) & 0xc0) ^ 0x40;
// m_crzyddz2_prot = (m_PIO >> 8) & 0xc0) ^ 0x40;
m_crzyddz2_prot = (machine().rand() & 0xc0);
return 0xffffff00 | data | m_crzyddz2_prot;
@ -1242,7 +1242,7 @@ INPUT_PORTS_END
static INPUT_PORTS_START(crzyddz2)
PORT_START("P1_P2") // 1500002 & 1500000
PORT_START("P1_P2") // 1500002 & 1500000
PORT_BIT( 0x00000001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) // up
PORT_BIT( 0x00000002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) // down (next secret code)
PORT_BIT( 0x00000004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) // left (inc secret code)
@ -1515,8 +1515,8 @@ ROM_START( crzyddz2 )
ROM_LOAD( "rom.u48", 0x000000, 0x1000000, CRC(0f3a1987) SHA1(6cad943846c79db31226676c7391f32216cfff79) )
ROM_REGION( 0x1000000, "maincpu", ROMREGION_ERASEFF )
ROM_COPY( "user1", 0x000000, 0x000000, 0x1000000 ) // copy flash here
ROM_LOAD( "27c322.u49", 0x000000, 0x0200000, CRC(b3177f39) SHA1(2a28bf8045bd2e053d88549b79fbc11f30ef9a32) ) // 1ST AND 2ND HALF IDENTICAL
ROM_COPY( "user1", 0x000000, 0x000000, 0x1000000 ) // copy flash here
ROM_LOAD( "27c322.u49", 0x000000, 0x0200000, CRC(b3177f39) SHA1(2a28bf8045bd2e053d88549b79fbc11f30ef9a32) ) // 1ST AND 2ND HALF IDENTICAL
ROM_CONTINUE( 0x000000, 0x0200000 )
ROM_REGION( 0x4280, "pic", 0 ) // hy04
@ -1539,7 +1539,7 @@ ROM_START( menghong )
ROM_LOAD( "rom.u48", 0x000000, 0x1000000, CRC(e24257c4) SHA1(569d79a61ff6d35100ba5727069363146df9e0b7) )
ROM_REGION( 0x1000000, "maincpu", 0 )
ROM_COPY( "user1", 0x000000, 0x000000, 0x1000000 ) // copy flash here
ROM_COPY( "user1", 0x000000, 0x000000, 0x1000000 ) // copy flash here
ROM_LOAD( "060511_08-01-18.u49", 0x000000, 0x0200000, CRC(b0c12107) SHA1(b1753757bbdb7d996df563ac6abdc6b46676704b) ) // 27C160
ROM_REGION( 0x4280, "pic", 0 ) // hy04

90
src/mame/drivers/didact.cpp
View File

@ -9,12 +9,12 @@
* Esselte 100 and the Candela computer for the swedish schools to educate the students in assembly programming
* and BASIC for electro mechanical applications such as stepper motors, simple process control, buttons
* and LED:s. Didact designs were marketed by Esselte Studium to the swedish schools. The Candela computer
* was designed to be the big breakthough and developed by Candela Data AB, "a Didact Company". The Candela
* system was based around a main unit that could run OS-9 or Flex and a terminal unit that had a propietary
* was designed to be the big breakthough and developed by Candela Data AB, "a Didact Company". The Candela
* system was based around a main unit that could run OS-9 or Flex and a terminal unit that had a propietary
* software including CDBASIC. The Candela system lost the battle of the swedish schools to
* the Compis computer by TeleNova which was based on CP/M initially. Later both lost to IBM PC as we know.
* Candela Data continued to sell their system to the swedish industry without major successes despite great
* innovation and spririt.
* innovation and spririt.
*
* The Esselte 1000 was an educational package based on Apple II plus software and litterature
* but the relation to Didact is at this point unknown so it is probably a pure Esselte software production.
@ -30,10 +30,10 @@
* TODO:
* Didact designs: mp68a, md6802, Modulab, Esselte 100, can09t, can09
* --------------------------------------------------------------------------
* - Add PCB layouts OK OK OK OK
* - Dump ROM:s, OK OK rev2 OK OK
* - Keyboard OK OK rev2
* - Display/CRT OK OK OK
* - Add PCB layouts OK OK OK OK
* - Dump ROM:s, OK OK rev2 OK OK
* - Keyboard OK OK rev2
* - Display/CRT OK OK OK
* - Clickable Artwork RQ RQ
* - Sound NA NA
* - Cassette i/f OK
@ -53,7 +53,7 @@
#include "video/mc6845.h" // For candela
#include "machine/wd_fdc.h" // For candela
#include "machine/clock.h" // For candela
#include "machine/ram.h" // For candela
#include "machine/ram.h" // For candela
#include "video/dm9368.h" // For the mp68a
#include "machine/74145.h" // For the md6802 and e100
// Features
@ -66,7 +66,7 @@
#define VERBOSE 0
#define LOGPRINT(x) do { if (VERBOSE) logerror x; } while (0)
#define LOG(x) LOGPRINT(x)
#define LOG(x) LOGPRINT(x)
#define LOGSCAN(x) {}
#define LOGSER(x) {}
#define LOGSCREEN(x) {}
@ -839,7 +839,7 @@ ADDRESS_MAP_END
* +----------------------------------+-------+------------------+ +----------+-------+-------+---------+--+----------+-------+
*
*/
/*
/*
* Candela Terminal
* TODO:
* - Map additional PIA:s on the ROM board
@ -991,15 +991,15 @@ protected:
};
void can09_state::machine_reset()
{
LOG(("%s()\n", FUNCNAME));
{
LOG(("%s()\n", FUNCNAME));
m_bank1->set_entry(0);
}
void can09_state::machine_start()
{
LOG(("%s()\n", FUNCNAME));
m_bank1->configure_entries(0, 8, m_ram->pointer(), 0x8000);
{
LOG(("%s()\n", FUNCNAME));
m_bank1->configure_entries(0, 8, m_ram->pointer(), 0x8000);
}
uint32_t can09_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
@ -1012,7 +1012,7 @@ uint32_t can09_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap,
#endif
LOGSCREEN(("%s()\n", FUNCNAME));
// vramad = 0;
// vramad = 0;
for (int row = 0; row < 72 * 8; row += 8)
{
for (int col = 0; col < 64 * 8; col += 8)
@ -1026,17 +1026,17 @@ uint32_t can09_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap,
/* plot the character */
for (y = 0; y < 8; y++)
{
// if (VERBOSE && charcode != 0x20 && charcode != 0) LOGSCREEN(("\n %02x: ", *chardata));
// if (VERBOSE && charcode != 0x20 && charcode != 0) LOGSCREEN(("\n %02x: ", *chardata));
for (x = 0; x < 8; x++)
{
// if (VERBOSE && charcode != 0x20 && charcode != 0) LOGSCREEN((" %02x: ", *chardata));
// if (VERBOSE && charcode != 0x20 && charcode != 0) LOGSCREEN((" %02x: ", *chardata));
bitmap.pix16(row + y, col + x) = x & 1; //(*chardata & (1 << x)) ? 1 : 0;
}
// chardata++;
// chardata++;
}
// vramad++;
// vramad++;
}
// if (VERBOSE && charcode != 0x20 && charcode != 0) LOGSCREEN(("\n"));
// if (VERBOSE && charcode != 0x20 && charcode != 0) LOGSCREEN(("\n"));
}
return 0;
@ -1061,9 +1061,9 @@ READ8_MEMBER( can09_state::pia1_B_r )
WRITE8_MEMBER( can09_state::pia1_B_w )
{
// UINT8 *RAM = memregion("maincpu")->base();
// UINT8 *RAM = memregion("maincpu")->base();
LOG(("%s(%02x)\n", FUNCNAME, data));
// membank("bank1")->set_entry((data & 0x70) >> 4);
// membank("bank1")->set_entry((data & 0x70) >> 4);
m_bank1->set_entry((data & 0x70) >> 4);
#if 0
switch (data & 0x70){
@ -1099,10 +1099,10 @@ static ADDRESS_MAP_START( can09_map, AS_PROGRAM, 8, can09_state )
/*
* Port A=0x18 B=0x20 erase 0-7fff
* Port A=0x18 B=0x30 erase 0-7fff
* Port A=0x18 B=0x00
* Port A=0x18 B=0x00
* Port A=0x10 B=
*/
// AM_RANGE(0x0000, 0x7fff) AM_RAM
// AM_RANGE(0x0000, 0x7fff) AM_RAM
AM_RANGE(0x0000, 0x7fff) AM_RAM AM_RAMBANK("bank1")
AM_RANGE(0xe020, 0xe020) AM_DEVWRITE("crtc", h46505_device, address_w)
AM_RANGE(0xe021, 0xe021) AM_DEVWRITE("crtc", h46505_device, register_w)
@ -1408,25 +1408,25 @@ static MACHINE_CONFIG_START( can09, can09_state )
MCFG_MC6845_CHAR_WIDTH(8)
MCFG_MC6845_UPDATE_ROW_CB(can09_state, crtc_update_row)
#endif
/* Setup loop from data table in ROM: 0xFFCB 0xE020 (CRTC register number), 0xFFD0 0xE021 (CRTC register value)
Reg Value Comment
0x00 0x55 Horizontal Total number of characters,
0x01 0x40 Horizontal Displayed number of characters
0x02 0x43 Horizontal Sync Position, character number
0x03 0x03 Horizontal Sync width, number of charcters
0x04 0x50 Vertical Total number of characters
0x05 0x09 Vertical Total Adjust number of characters
0x06 0x48 Vertical Displayed number of characters
0x07 0x4B Vertical Sync Position, character number
0x08 0x00 Interlace Mode/Scew, Non-Interlaced
0x09 0x03 Max Scan Line Address Register
0x0A 0x00 Cursor Start
0x0B 0x0A Cursor End
0x0C 0x00 Start Address hi
0x0D 0x00 Start Address lo
0x0E 0x00 Cursor hi
0x0F 0x00 Cursor lo
Note - no init of Light Pen registers
/* Setup loop from data table in ROM: 0xFFCB 0xE020 (CRTC register number), 0xFFD0 0xE021 (CRTC register value)
Reg Value Comment
0x00 0x55 Horizontal Total number of characters,
0x01 0x40 Horizontal Displayed number of characters
0x02 0x43 Horizontal Sync Position, character number
0x03 0x03 Horizontal Sync width, number of charcters
0x04 0x50 Vertical Total number of characters
0x05 0x09 Vertical Total Adjust number of characters
0x06 0x48 Vertical Displayed number of characters
0x07 0x4B Vertical Sync Position, character number
0x08 0x00 Interlace Mode/Scew, Non-Interlaced
0x09 0x03 Max Scan Line Address Register
0x0A 0x00 Cursor Start
0x0B 0x0A Cursor End
0x0C 0x00 Start Address hi
0x0D 0x00 Start Address lo
0x0E 0x00 Cursor hi
0x0F 0x00 Cursor lo
Note - no init of Light Pen registers
*/
@ -1629,7 +1629,7 @@ ROM_START( can09t )
ROM_LOAD( "ic2-mon58b-c8d7.bin", 0x0000, 0x8000, CRC(7eabfec6) SHA1(e08e2349035389b441227df903aa54f4c1e4a337) )
/* Programmable logic for the CAN09 1.4 PCB */
ROM_REGION(0x1000, "plas", 0)
ROM_LOAD( "ic10-21.1.bin", 0x0000, 0x20, CRC(b75ac72d) SHA1(689363200035b11a823d17a8d717f313eeefc3bf) )
ROM_LOAD( "ic10-21.1.bin", 0x0000, 0x20, CRC(b75ac72d) SHA1(689363200035b11a823d17a8d717f313eeefc3bf) )
ROM_END
ROM_START( can09 )

2
src/mame/drivers/dynduke.cpp
View File

@ -19,7 +19,7 @@
There is a country code byte in the program to select between
Seibu Kaihatsu/Fabtek/Taito licenses.
The Double Dynamites is an updated co-op version sporting different
The Double Dynamites is an updated co-op version sporting different
enemy patterns and drops.
Emulation by Bryan McPhail, mish@tendril.co.uk

70
src/mame/drivers/fccpu30.cpp
View File

@ -201,11 +201,11 @@
#define VERBOSE 0
#define LOGPRINT(x) { do { if (VERBOSE) logerror x; } while (0); }
#define LOG(x) {} LOGPRINT(x)
#define LOGINIT(x) {} LOGPRINT(x)
#define LOGR(x) {}
#define LOGSETUP(x) {}
#define LOGINT(x) {}
#define LOG(x) {} LOGPRINT(x)
#define LOGINIT(x) {} LOGPRINT(x)
#define LOGR(x) {}
#define LOGSETUP(x) {}
#define LOGINT(x) {}
#if VERBOSE >= 2
#define logerror printf
#endif
@ -306,16 +306,16 @@ static ADDRESS_MAP_START (cpu30_mem, AS_PROGRAM, 32, cpu30_state)
ADDRESS_MAP_UNMAP_HIGH
AM_RANGE (0x00000000, 0x00000007) AM_ROM AM_READ (bootvect_r) /* ROM mirror just during reset */
AM_RANGE (0x00000000, 0x00000007) AM_RAM AM_WRITE (bootvect_w) /* After first write we act as RAM */
// AM_RANGE (0x00000008, 0x003fffff) AM_RAM /* RAM installed in machine start */
// AM_RANGE (0x00000008, 0x003fffff) AM_RAM /* RAM installed in machine start */
AM_RANGE (0xff000000, 0xff7fffff) AM_ROM AM_REGION("roms", 0x000000)
AM_RANGE (0xff800c00, 0xff800dff) AM_DEVREADWRITE8("pit1", pit68230_device, read, write, 0xffffffff)
AM_RANGE (0xff800e00, 0xff800fff) AM_DEVREADWRITE8("pit2", pit68230_device, read, write, 0xffffffff)
AM_RANGE (0xff802000, 0xff8021ff) AM_DEVREADWRITE8("duscc", duscc68562_device, read, write, 0xffffffff) /* Port 1&2 - Dual serial port DUSCC */
AM_RANGE (0xff802200, 0xff8023ff) AM_DEVREADWRITE8("duscc2", duscc68562_device, read, write, 0xffffffff) /* Port 3&4 - Dual serial port DUSCC */
AM_RANGE (0xff803000, 0xff8031ff) AM_DEVREADWRITE8("rtc", rtc72423_device, read, write, 0xffffffff)
// AM_RANGE (0xff803400, 0xff8035ff) AM_DEVREADWRITE8("scsi", mb87033_device, read, write, 0xffffffff) /* TODO: implement MB87344 SCSI device */
// AM_RANGE (0xff803400, 0xff8035ff) AM_DEVREADWRITE8("scsi", mb87033_device, read, write, 0xffffffff) /* TODO: implement MB87344 SCSI device */
AM_RANGE (0xff803400, 0xff8035ff) AM_READWRITE8(scsi_r, scsi_w, 0x000000ff) /* mock driver to log calls to device */
// AM_RANGE (0xff803800, 0xff80397f) AM_DEVREADWRITE8("fdc", wd37c65c_device, read, write, 0xffffffff) /* TODO: implement WD3/C65C fdc controller */
// AM_RANGE (0xff803800, 0xff80397f) AM_DEVREADWRITE8("fdc", wd37c65c_device, read, write, 0xffffffff) /* TODO: implement WD3/C65C fdc controller */
AM_RANGE (0xff803800, 0xff80397f) AM_READWRITE8(fdc_r, fdc_w, 0x000000ff) /* mock driver to log calls to device */
AM_RANGE (0xff803980, 0xff8039ff) AM_READ8(slot1_status_r, 0x000000ff)
AM_RANGE (0xffc00000, 0xffcfffff) AM_RAM AM_SHARE ("nvram") /* On-board SRAM with battery backup (nvram) */
@ -354,7 +354,7 @@ void cpu30_state::machine_reset ()
m_sysrom = (uint32_t*)(memregion ("roms")->base () + 0x800000);
}
/* setup board ID */
/* setup board ID */
DRIVER_INIT_MEMBER( cpu30_state, cpu30x ) { LOGINIT(("%s\n", FUNCNAME)); m_board_id = 0x50; }
DRIVER_INIT_MEMBER( cpu30_state, cpu30xa ) { LOGINIT(("%s\n", FUNCNAME)); m_board_id = 0x50; }
DRIVER_INIT_MEMBER( cpu30_state, cpu30za ) { LOGINIT(("%s\n", FUNCNAME)); m_board_id = 0x50; }
@ -363,7 +363,7 @@ DRIVER_INIT_MEMBER( cpu30_state, cpu30be8 ) { LOGINIT(("%s\n", FUNCNAME)); m_
DRIVER_INIT_MEMBER( cpu30_state, cpu30be16 ) { LOGINIT(("%s\n", FUNCNAME)); m_board_id = 0x50; }
DRIVER_INIT_MEMBER( cpu30_state, cpu30lite4 ) { LOGINIT(("%s\n", FUNCNAME)); m_board_id = 0x50; }
DRIVER_INIT_MEMBER( cpu30_state, cpu30lite8 ) { LOGINIT(("%s\n", FUNCNAME)); m_board_id = 0x50; }
DRIVER_INIT_MEMBER( cpu30_state, cpu33 ) { LOGINIT(("%s\n", FUNCNAME)); m_board_id = 0x68; } // 0x60 skips FGA prompt
DRIVER_INIT_MEMBER( cpu30_state, cpu33 ) { LOGINIT(("%s\n", FUNCNAME)); m_board_id = 0x68; } // 0x60 skips FGA prompt
/* Mock FDC driver */
READ8_MEMBER (cpu30_state::fdc_r){
@ -524,13 +524,13 @@ READ8_MEMBER (cpu30_state::board_mem_id_rd)
{
case (1024 * 1024 * 32): sz = 0; break;
case (1024 * 1024 * 16): sz = 1; break;
case (1024 * 1024 * 8): sz = 2; break;
case (1024 * 1024 * 4): sz = 3; break;
case (1024 * 1024 * 2): sz = 4; break;
case (1024 * 1024 * 1): sz = 5; break;
case (1024 * 512 * 1): sz = 6; break;
case (1024 * 256 * 1): sz = 7; break;
default:
case (1024 * 1024 * 8): sz = 2; break;
case (1024 * 1024 * 4): sz = 3; break;
case (1024 * 1024 * 2): sz = 4; break;
case (1024 * 1024 * 1): sz = 5; break;
case (1024 * 512 * 1): sz = 6; break;
case (1024 * 256 * 1): sz = 7; break;
default:
logerror("No supported RAM size, telling VMEPROM 4Mb\n");
sz = 4;
}
@ -550,13 +550,13 @@ READ8_MEMBER (cpu30_state::board_mem_id_rd)
// return 0x56;// CPU-30, 1Mb, 36MHz
// return 0x53;// CPU-30, 4Mb, 36MHz
// return 0x57;// CPU-30, 4Mb, 36MHz
// return 0x48 + sz;// none
// return 0x38 + sz;// none
// return 0x28 + sz;// none
// return 0x18 + sz;// CPU-23 p1
// return 0x10 + sz;// CPU-22 p4
// return 0x20 + sz;// p1: Wait until hard disk is up to speed
// printf("SIZE:%02x\n", sz);
// return 0x48 + sz;// none
// return 0x38 + sz;// none
// return 0x28 + sz;// none
// return 0x18 + sz;// CPU-23 p1
// return 0x10 + sz;// CPU-22 p4
// return 0x20 + sz;// p1: Wait until hard disk is up to speed
// printf("SIZE:%02x\n", sz);
LOG(("- Board ID:%02x Size:%02x\n", m_board_id, sz));
return m_board_id + sz;
}
@ -730,7 +730,7 @@ static MACHINE_CONFIG_DERIVED( cpu30x, cpu30 )
MCFG_DEVICE_MODIFY("maincpu")
MCFG_DEVICE_CLOCK(XTAL_16_777216MHz) /* 16.7 MHz from description, crystal needs verification */
// MCFG_DEVICE_REMOVE("")
// MCFG_DEVICE_REMOVE("")
// dual ported ram
MCFG_RAM_MODIFY(RAM_TAG)
@ -796,10 +796,10 @@ MACHINE_CONFIG_END
/* SYS68K/CPU-30Lite/4 68030 CPU, 25 MHz, 4 Mbyte shared DRAM, 4 Mbyte Flash, 4 serial ports, 32-bit VMEbus interface, VMEPROM firmware. */
static MACHINE_CONFIG_DERIVED( cpu30lite4, cpu30zbe )
// Enable these when added to main config
// MCFG_DEVICE_REMOVE("fpu")
// MCFG_DEVICE_REMOVE("scsi")
// MCFG_DEVICE_REMOVE("eth")
// MCFG_DEVICE_REMOVE("fdc")
// MCFG_DEVICE_REMOVE("fpu")
// MCFG_DEVICE_REMOVE("scsi")
// MCFG_DEVICE_REMOVE("eth")
// MCFG_DEVICE_REMOVE("fdc")
// dual ported ram
MCFG_RAM_MODIFY(RAM_TAG)
MCFG_RAM_DEFAULT_SIZE("4M")
@ -842,12 +842,12 @@ ROM_START (nodump)
ROM_END
/* These needs reality check as they has 1Mb of RAM which is not a suitable size for later CPU_30:s */
#define rom_fccpu30x rom_fccpu30
#define rom_fccpu30xa rom_fccpu30
#define rom_fccpu30za rom_fccpu30
#define rom_fccpu30x rom_fccpu30
#define rom_fccpu30xa rom_fccpu30
#define rom_fccpu30za rom_fccpu30
#define rom_fccpu30zbe rom_fccpu30
#define rom_fccpu30be8 rom_fccpu30
#define rom_fccpu30zbe rom_fccpu30
#define rom_fccpu30be8 rom_fccpu30
#define rom_fccpu30be16 rom_fccpu30
/* These needs dumps */
@ -855,7 +855,7 @@ ROM_END
#define rom_fccpu30lite8 rom_nodump
/* These are most likelly wrong, needs dump */
#define rom_fccpu30senr rom_nodump
#define rom_fccpu30senr rom_nodump
#define rom_fccpu30senr501 rom_nodump
/*

2
src/mame/drivers/fcscsi.cpp
View File

@ -138,7 +138,7 @@ static ADDRESS_MAP_START (fcscsi1_mem, AS_PROGRAM, 16, fcscsi1_state)
AM_RANGE (0x002000, 0x01ffff) AM_RAM /* Dual Ported RAM */
AM_RANGE (0xe00000, 0xe7ffff) AM_ROM /* System EPROM Area 32Kb DEBUGGER supplied */
AM_RANGE (0xd00000, 0xd0003f) AM_DEVREADWRITE8 ("pit", pit68230_device, read, write, 0x00ff)
// AM_RANGE (0xc40000, 0xc4001f) AM_DEVREADWRITE8("scsi", ncr5386_device, read, write, 0x00ff) /* SCSI Controller interface - device support not yet available*/
// AM_RANGE (0xc40000, 0xc4001f) AM_DEVREADWRITE8("scsi", ncr5386_device, read, write, 0x00ff) /* SCSI Controller interface - device support not yet available*/
AM_RANGE (0xc40000, 0xc4001f) AM_READWRITE8 (scsi_r, scsi_w, 0x00ff)
AM_RANGE (0xc80000, 0xc800ff) AM_DEVREADWRITE("mc68450", hd63450_device, read, write) /* DMA Controller interface */
AM_RANGE (0xcc0000, 0xcc0007) AM_DEVREADWRITE8("fdc", wd1772_t, read, write, 0x00ff) /* Floppy Controller interface */

6
src/mame/drivers/fidel6502.cpp
View File

@ -424,7 +424,7 @@ public:
TIMER_DEVICE_CALLBACK_MEMBER(irq_on) { m_maincpu->set_input_line(M6502_IRQ_LINE, ASSERT_LINE); }
TIMER_DEVICE_CALLBACK_MEMBER(irq_off) { m_maincpu->set_input_line(M6502_IRQ_LINE, CLEAR_LINE); }
// CSC, SU9, RSC
void csc_prepare_display();
DECLARE_READ8_MEMBER(csc_speech_r);
@ -879,7 +879,7 @@ READ8_MEMBER(fidel6502_state::fexcel_ttl_r)
WRITE8_MEMBER(fidel6502_state::fdesdis_control_w)
{
uint8_t q3_old = m_led_select & 8;
// a0-a2,d7: 74259
uint8_t mask = 1 << offset;
m_led_select = (m_led_select & ~mask) | ((data & 0x80) ? mask : 0);
@ -904,7 +904,7 @@ WRITE8_MEMBER(fidel6502_state::fdesdis_control_w)
for (int i = 0; i < 4; i++)
m_display_state[i+2] = m_7seg_data >> (8*i) & 0xff;
}
m_display_maxy += 4;
set_display_segmask(0x3c, 0x7f);
display_update();

248
src/mame/drivers/hazeltin.cpp
View File

@ -2,16 +2,16 @@
// copyright-holders:Ryan Holtz
/***************************************************************************
Hazeltine 1500
original machine (c) 1977 Hazeltine Corporation
Hazeltine 1500
original machine (c) 1977 Hazeltine Corporation
perliminary driver by Ryan Holtz
perliminary driver by Ryan Holtz
TODO:
- pretty much everything
References:
[1]: Hazeltine_1500_Series_Maintenance_Manual_Dec77.pdf, on Bitsavers
[1]: Hazeltine_1500_Series_Maintenance_Manual_Dec77.pdf, on Bitsavers
****************************************************************************/
@ -30,39 +30,39 @@ References:
#include "machine/dm9334.h"
#include "machine/kb3600.h"
#define CPU_TAG "maincpu"
#define UART_TAG "uart"
#define BAUDGEN_TAG "baudgen"
#define KBDC_TAG "ay53600"
#define CHARRAM_TAG "chrram"
#define CHARROM_TAG "chargen"
#define BAUDPORT_TAG "baud"
#define MISCPORT_TAG "misc"
#define MISCKEYS_TAG "misc_keys"
#define SCREEN_TAG "screen"
#define TMS3409A_TAG "u67"
#define TMS3409B_TAG "u57"
#define DOTCLK_TAG "dotclk"
#define DOTCLK_DISP_TAG "dotclk_dispatch"
#define CPU_TAG "maincpu"
#define UART_TAG "uart"
#define BAUDGEN_TAG "baudgen"
#define KBDC_TAG "ay53600"
#define CHARRAM_TAG "chrram"
#define CHARROM_TAG "chargen"
#define BAUDPORT_TAG "baud"
#define MISCPORT_TAG "misc"
#define MISCKEYS_TAG "misc_keys"
#define SCREEN_TAG "screen"
#define TMS3409A_TAG "u67"
#define TMS3409B_TAG "u57"
#define DOTCLK_TAG "dotclk"
#define DOTCLK_DISP_TAG "dotclk_dispatch"
#define CHAR_CTR_CLK_TAG "ch_bucket_ctr_clk"
#define U58_TAG "u58"
#define U59_TAG "u59"
#define U58_TAG "u58"
#define U59_TAG "u59"
#define VID_PROM_ADDR_RESET_TAG "u59_y5"
#define U61_TAG "u61"
#define U68_TAG "u68"
#define U69_PROMMSB_TAG "u69"
#define U70_PROMLSB_TAG "u70"
#define U61_TAG "u61"
#define U68_TAG "u68"
#define U69_PROMMSB_TAG "u69"
#define U70_PROMLSB_TAG "u70"
#define U70_TC_LINE_TAG "u70_tc"
#define U71_PROM_TAG "u71"
#define U72_PROMDEC_TAG "u72"
#define U81_TAG "u81"
#define U83_TAG "u83"
#define U84_DIV11_TAG "u84"
#define U71_PROM_TAG "u71"
#define U72_PROMDEC_TAG "u72"
#define U81_TAG "u81"
#define U83_TAG "u83"
#define U84_DIV11_TAG "u84"
#define U85_VERT_DR_UB_TAG "u85"
#define U87_TAG "u87"
#define U88_DIV9_TAG "u88"
#define U90_DIV14_TAG "u90"
#define BAUD_PROM_TAG "u39"
#define U87_TAG "u87"
#define U88_DIV9_TAG "u88"
#define U90_DIV14_TAG "u90"
#define BAUD_PROM_TAG "u39"
// Number of cycles to burn when fetching the next row of characters into the line buffer:
// CPU clock is 18MHz / 9
@ -74,26 +74,26 @@ References:
// 2*9*80 1 1440 * XTAL_2MHz
// -------------- divided by --------- = ---------------- = 86.5 main CPU cycles per line fetch
// XTAL_33_264MHz XTAL_2MHz XTAL_33_264MHz
#define LINE_FETCH_CYCLES (87)
#define LINE_FETCH_CYCLES (87)
#define SR2_FULL_DUPLEX (0x01)
#define SR2_UPPER_ONLY (0x08)
#define SR2_FULL_DUPLEX (0x01)
#define SR2_UPPER_ONLY (0x08)
#define SR3_PB_RESET (0x04)
#define SR3_PB_RESET (0x04)
#define KBD_STATUS_KBDR (0x01)
#define KBD_STATUS_TV_UB (0x40)
#define KBD_STATUS_TV_INT (0x80)
#define KBD_STATUS_KBDR (0x01)
#define KBD_STATUS_TV_UB (0x40)
#define KBD_STATUS_TV_INT (0x80)
#define SCREEN_HTOTAL (9*100)
#define SCREEN_HDISP (9*80)
#define SCREEN_HSTART (9*5)
#define SCREEN_HTOTAL (9*100)
#define SCREEN_HDISP (9*80)
#define SCREEN_HSTART (9*5)
#define SCREEN_VTOTAL (28*11)
#define SCREEN_VDISP (24*11)
#define SCREEN_VSTART (0)
#define SCREEN_VTOTAL (28*11)
#define SCREEN_VDISP (24*11)
#define SCREEN_VSTART (0)
#define VERT_UB_LINE (24*11+8)
#define VERT_UB_LINE (24*11+8)
class hazl1500_state : public driver_device
{
@ -131,11 +131,11 @@ public:
, m_scanline_timer(nullptr)
, m_status_reg_3(0)
, m_kbd_status_latch(0)
, m_refresh_address(0)
, m_refresh_address(0)
, m_vpos(0)
, m_hblank(false)
, m_vblank(false)
, m_delayed_vblank(false)
, m_hblank(false)
, m_vblank(false)
, m_delayed_vblank(false)
{
}
@ -161,7 +161,7 @@ public:
DECLARE_READ_LINE_MEMBER(ay3600_control_r);
DECLARE_WRITE_LINE_MEMBER(ay3600_data_ready_w);
DECLARE_WRITE8_MEMBER(refresh_address_w);
DECLARE_WRITE8_MEMBER(refresh_address_w);
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override;
static const device_timer_id TIMER_HBLANK = 0;
@ -211,7 +211,7 @@ private:
uint8_t m_status_reg_3;
uint8_t m_kbd_status_latch;
uint8_t m_refresh_address;
uint8_t m_refresh_address;
uint16_t m_vpos;
bool m_hblank;
bool m_vblank;
@ -230,7 +230,7 @@ void hazl1500_state::machine_start()
save_item(NAME(m_status_reg_3));
save_item(NAME(m_kbd_status_latch));
save_item(NAME(m_refresh_address));
save_item(NAME(m_refresh_address));
save_item(NAME(m_vpos));
save_item(NAME(m_hblank));
save_item(NAME(m_vblank));
@ -242,8 +242,8 @@ void hazl1500_state::machine_reset()
m_status_reg_3 = 0;
m_kbd_status_latch = 0;
m_refresh_address = 0;
m_screen->reset_origin(0, 0);
m_refresh_address = 0;
m_screen->reset_origin(0, 0);
m_vpos = m_screen->vpos();
m_vblank = (m_vpos >= SCREEN_VDISP);
m_delayed_vblank = m_vpos < VERT_UB_LINE;
@ -369,21 +369,21 @@ void hazl1500_state::device_timer(emu_timer &timer, device_timer_id id, int para
WRITE8_MEMBER(hazl1500_state::refresh_address_w)
{
m_refresh_address = data;
//printf("m_refresh_address %x, vpos %d, screen vpos %d\n", m_refresh_address, m_vpos, m_screen->vpos());
m_refresh_address = data;
//printf("m_refresh_address %x, vpos %d, screen vpos %d\n", m_refresh_address, m_vpos, m_screen->vpos());
}
void hazl1500_state::check_tv_interrupt()
{
uint8_t char_row = m_vpos % 11;
uint8_t char_row = m_vpos % 11;
bool bit_match = char_row == 2 || char_row == 3;
bool tv_interrupt = bit_match && !m_delayed_vblank;
bool tv_interrupt = bit_match && !m_delayed_vblank;
//printf("interrupt for line %d (%d): %s\n", m_vpos, char_row, tv_interrupt ? "yes" : "no");
m_kbd_status_latch &= ~KBD_STATUS_TV_INT;
m_kbd_status_latch |= tv_interrupt ? KBD_STATUS_TV_INT : 0;
m_kbd_status_latch &= ~KBD_STATUS_TV_INT;
m_kbd_status_latch |= tv_interrupt ? KBD_STATUS_TV_INT : 0;
m_maincpu->set_input_line(INPUT_LINE_IRQ0, tv_interrupt ? ASSERT_LINE : CLEAR_LINE);
m_maincpu->set_input_line(INPUT_LINE_IRQ0, tv_interrupt ? ASSERT_LINE : CLEAR_LINE);
}
void hazl1500_state::update_tv_unblank()
@ -525,12 +525,12 @@ static INPUT_PORTS_START( hazl1500 )
// X2 |BAKSP| 2 | 4 | 6 | 8 | 9 | -= | | | |
PORT_START("X2")
PORT_BIT(0x001, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_BACKSPACE) PORT_NAME("Backspace")
PORT_BIT(0x002, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_2) PORT_CHAR('2') PORT_CHAR('\"')
PORT_BIT(0x004, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_4) PORT_CHAR('4') PORT_CHAR('$')
PORT_BIT(0x008, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_6) PORT_CHAR('6') PORT_CHAR('&')
PORT_BIT(0x010, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_8) PORT_CHAR('8') PORT_CHAR('(')
PORT_BIT(0x020, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_9) PORT_CHAR('9') PORT_CHAR(')')
PORT_BIT(0x001, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_BACKSPACE) PORT_NAME("Backspace")
PORT_BIT(0x002, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_2) PORT_CHAR('2') PORT_CHAR('\"')
PORT_BIT(0x004, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_4) PORT_CHAR('4') PORT_CHAR('$')
PORT_BIT(0x008, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_6) PORT_CHAR('6') PORT_CHAR('&')
PORT_BIT(0x010, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_8) PORT_CHAR('8') PORT_CHAR('(')
PORT_BIT(0x020, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_9) PORT_CHAR('9') PORT_CHAR(')')
PORT_BIT(0x040, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_MINUS) PORT_CHAR('-') PORT_CHAR('=')
PORT_BIT(0x080, IP_ACTIVE_HIGH, IPT_UNUSED)
PORT_BIT(0x100, IP_ACTIVE_HIGH, IPT_UNUSED)
@ -539,79 +539,79 @@ static INPUT_PORTS_START( hazl1500 )
// X3 | | ESC | W | R | Y | 0 | `@ | CLR |NP , |NP 9 |
PORT_START("X3")
PORT_BIT(0x001, IP_ACTIVE_HIGH, IPT_UNUSED)
PORT_BIT(0x002, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_ESC) PORT_NAME("Esc")
PORT_BIT(0x004, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_W) PORT_CHAR('W') PORT_CHAR('w')
PORT_BIT(0x008, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_R) PORT_CHAR('R') PORT_CHAR('r')
PORT_BIT(0x010, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_Y) PORT_CHAR('Y') PORT_CHAR('y')
PORT_BIT(0x020, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_0) PORT_CHAR('0')
PORT_BIT(0x040, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_OPENBRACE) PORT_CHAR('@') PORT_CHAR('`')
PORT_BIT(0x080, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_DEL) PORT_NAME("Clr")
PORT_BIT(0x002, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_ESC) PORT_NAME("Esc")
PORT_BIT(0x004, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_W) PORT_CHAR('W') PORT_CHAR('w')
PORT_BIT(0x008, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_R) PORT_CHAR('R') PORT_CHAR('r')
PORT_BIT(0x010, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_Y) PORT_CHAR('Y') PORT_CHAR('y')
PORT_BIT(0x020, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_0) PORT_CHAR('0')
PORT_BIT(0x040, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_OPENBRACE) PORT_CHAR('@') PORT_CHAR('`')
PORT_BIT(0x080, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_DEL) PORT_NAME("Clr")
PORT_BIT(0x100, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_DEL_PAD)
PORT_BIT(0x200, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_9_PAD) PORT_CHAR(UCHAR_MAMEKEY(9_PAD))
PORT_BIT(0x200, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_9_PAD) PORT_CHAR(UCHAR_MAMEKEY(9_PAD))
// X4 | | Q | E | T | U | O | {[ | |\ |NP 7 |NP 6 |
PORT_START("X4")
PORT_BIT(0x001, IP_ACTIVE_HIGH, IPT_UNUSED)
PORT_BIT(0x002, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_Q) PORT_CHAR('Q') PORT_CHAR('q')
PORT_BIT(0x004, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_E) PORT_CHAR('E') PORT_CHAR('e')
PORT_BIT(0x008, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_T) PORT_CHAR('T') PORT_CHAR('t')
PORT_BIT(0x010, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_U) PORT_CHAR('U') PORT_CHAR('u')
PORT_BIT(0x020, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_O) PORT_CHAR('O') PORT_CHAR('o')
PORT_BIT(0x040, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_OPENBRACE) PORT_CHAR('[') PORT_CHAR('{')
PORT_BIT(0x080, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_BACKSLASH) PORT_CHAR('\\') PORT_CHAR('|')
PORT_BIT(0x100, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_7_PAD) PORT_CHAR(UCHAR_MAMEKEY(7_PAD))
PORT_BIT(0x200, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_6_PAD) PORT_CHAR(UCHAR_MAMEKEY(6_PAD))
PORT_BIT(0x002, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_Q) PORT_CHAR('Q') PORT_CHAR('q')
PORT_BIT(0x004, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_E) PORT_CHAR('E') PORT_CHAR('e')
PORT_BIT(0x008, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_T) PORT_CHAR('T') PORT_CHAR('t')
PORT_BIT(0x010, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_U) PORT_CHAR('U') PORT_CHAR('u')
PORT_BIT(0x020, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_O) PORT_CHAR('O') PORT_CHAR('o')
PORT_BIT(0x040, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_OPENBRACE) PORT_CHAR('[') PORT_CHAR('{')
PORT_BIT(0x080, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_BACKSLASH) PORT_CHAR('\\') PORT_CHAR('|')
PORT_BIT(0x100, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_7_PAD) PORT_CHAR(UCHAR_MAMEKEY(7_PAD))
PORT_BIT(0x200, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_6_PAD) PORT_CHAR(UCHAR_MAMEKEY(6_PAD))
// X5 |HOME | A | D | G | I | P | *: | LF |NP 8 |NP 5 |
PORT_START("X5")
PORT_BIT(0x001, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_HOME) PORT_NAME("Home")
PORT_BIT(0x002, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_A) PORT_CHAR('A') PORT_CHAR('a')
PORT_BIT(0x004, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_D) PORT_CHAR('D') PORT_CHAR('d')
PORT_BIT(0x008, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_G) PORT_CHAR('G') PORT_CHAR('g')
PORT_BIT(0x010, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_I) PORT_CHAR('I') PORT_CHAR('i')
PORT_BIT(0x020, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_P) PORT_CHAR('P') PORT_CHAR('p')
PORT_BIT(0x040, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_QUOTE) PORT_CHAR(':') PORT_CHAR('*')
PORT_BIT(0x080, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_PGDN) PORT_NAME("Line Feed")
PORT_BIT(0x100, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_8_PAD) PORT_CHAR(UCHAR_MAMEKEY(8_PAD))
PORT_BIT(0x200, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_5_PAD) PORT_CHAR(UCHAR_MAMEKEY(5_PAD))
PORT_BIT(0x001, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_HOME) PORT_NAME("Home")
PORT_BIT(0x002, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_A) PORT_CHAR('A') PORT_CHAR('a')
PORT_BIT(0x004, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_D) PORT_CHAR('D') PORT_CHAR('d')
PORT_BIT(0x008, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_G) PORT_CHAR('G') PORT_CHAR('g')
PORT_BIT(0x010, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_I) PORT_CHAR('I') PORT_CHAR('i')
PORT_BIT(0x020, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_P) PORT_CHAR('P') PORT_CHAR('p')
PORT_BIT(0x040, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_QUOTE) PORT_CHAR(':') PORT_CHAR('*')
PORT_BIT(0x080, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_PGDN) PORT_NAME("Line Feed")
PORT_BIT(0x100, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_8_PAD) PORT_CHAR(UCHAR_MAMEKEY(8_PAD))
PORT_BIT(0x200, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_5_PAD) PORT_CHAR(UCHAR_MAMEKEY(5_PAD))
// X6 | | S | F | H | J | +; | }] | DEL |NP 4 |NP 2 |
PORT_START("X6")
PORT_BIT(0x001, IP_ACTIVE_HIGH, IPT_UNUSED)
PORT_BIT(0x002, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_S) PORT_CHAR('S') PORT_CHAR('s')
PORT_BIT(0x004, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_F) PORT_CHAR('F') PORT_CHAR('f')
PORT_BIT(0x008, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_H) PORT_CHAR('H') PORT_CHAR('h')
PORT_BIT(0x010, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_J) PORT_CHAR('J') PORT_CHAR('j')
PORT_BIT(0x020, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_COLON) PORT_CHAR(';') PORT_CHAR('+')
PORT_BIT(0x002, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_S) PORT_CHAR('S') PORT_CHAR('s')
PORT_BIT(0x004, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_F) PORT_CHAR('F') PORT_CHAR('f')
PORT_BIT(0x008, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_H) PORT_CHAR('H') PORT_CHAR('h')
PORT_BIT(0x010, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_J) PORT_CHAR('J') PORT_CHAR('j')
PORT_BIT(0x020, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_COLON) PORT_CHAR(';') PORT_CHAR('+')
PORT_BIT(0x040, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_BACKSLASH) PORT_CHAR(']') PORT_CHAR('}')
PORT_BIT(0x080, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_DEL) PORT_NAME("Del")
PORT_BIT(0x100, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_4_PAD) PORT_CHAR(UCHAR_MAMEKEY(4_PAD))
PORT_BIT(0x200, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_2_PAD) PORT_CHAR(UCHAR_MAMEKEY(2_PAD))
PORT_BIT(0x080, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_DEL) PORT_NAME("Del")
PORT_BIT(0x100, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_4_PAD) PORT_CHAR(UCHAR_MAMEKEY(4_PAD))
PORT_BIT(0x200, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_2_PAD) PORT_CHAR(UCHAR_MAMEKEY(2_PAD))
// X7 | | Z | C | B | K | L | <, | CR |NP 1 |NP 3 |
PORT_START("X7")
PORT_BIT(0x001, IP_ACTIVE_HIGH, IPT_UNUSED)
PORT_BIT(0x002, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_Z) PORT_CHAR('Z') PORT_CHAR('z')
PORT_BIT(0x004, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_C) PORT_CHAR('C') PORT_CHAR('c')
PORT_BIT(0x008, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_B) PORT_CHAR('B') PORT_CHAR('b')
PORT_BIT(0x010, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_K) PORT_CHAR('K') PORT_CHAR('k')
PORT_BIT(0x020, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_L) PORT_CHAR('L') PORT_CHAR('l')
PORT_BIT(0x040, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',') PORT_CHAR('<')
PORT_BIT(0x080, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_ENTER) PORT_CHAR(13) PORT_NAME("Return")
PORT_BIT(0x100, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_1_PAD) PORT_CHAR(UCHAR_MAMEKEY(1_PAD))
PORT_BIT(0x200, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_3_PAD) PORT_CHAR(UCHAR_MAMEKEY(3_PAD))
PORT_BIT(0x002, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_Z) PORT_CHAR('Z') PORT_CHAR('z')
PORT_BIT(0x004, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_C) PORT_CHAR('C') PORT_CHAR('c')
PORT_BIT(0x008, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_B) PORT_CHAR('B') PORT_CHAR('b')
PORT_BIT(0x010, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_K) PORT_CHAR('K') PORT_CHAR('k')
PORT_BIT(0x020, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_L) PORT_CHAR('L') PORT_CHAR('l')
PORT_BIT(0x040, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',') PORT_CHAR('<')
PORT_BIT(0x080, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_ENTER) PORT_CHAR(13) PORT_NAME("Return")
PORT_BIT(0x100, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_1_PAD) PORT_CHAR(UCHAR_MAMEKEY(1_PAD))
PORT_BIT(0x200, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_3_PAD) PORT_CHAR(UCHAR_MAMEKEY(3_PAD))
// X8 | | X | V | N |SPACE| M | >. | ?/ |NP 0 |NP . |
PORT_START("X8")
PORT_BIT(0x001, IP_ACTIVE_HIGH, IPT_UNUSED)
PORT_BIT(0x002, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_X) PORT_CHAR('X') PORT_CHAR('x')
PORT_BIT(0x004, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_V) PORT_CHAR('V') PORT_CHAR('v')
PORT_BIT(0x008, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_N) PORT_CHAR('N') PORT_CHAR('n')
PORT_BIT(0x010, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ')
PORT_BIT(0x020, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_M) PORT_CHAR('M') PORT_CHAR('m')
PORT_BIT(0x040, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_STOP) PORT_CHAR('.') PORT_CHAR('>')
PORT_BIT(0x080, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_SLASH) PORT_CHAR('/') PORT_CHAR('?')
PORT_BIT(0x100, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_0_PAD) PORT_CHAR(UCHAR_MAMEKEY(0_PAD))
PORT_BIT(0x002, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_X) PORT_CHAR('X') PORT_CHAR('x')
PORT_BIT(0x004, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_V) PORT_CHAR('V') PORT_CHAR('v')
PORT_BIT(0x008, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_N) PORT_CHAR('N') PORT_CHAR('n')
PORT_BIT(0x010, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ')
PORT_BIT(0x020, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_M) PORT_CHAR('M') PORT_CHAR('m')
PORT_BIT(0x040, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_STOP) PORT_CHAR('.') PORT_CHAR('>')
PORT_BIT(0x080, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_SLASH) PORT_CHAR('/') PORT_CHAR('?')
PORT_BIT(0x100, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_0_PAD) PORT_CHAR(UCHAR_MAMEKEY(0_PAD))
PORT_BIT(0x200, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_ENTER_PAD) PORT_CHAR(UCHAR_MAMEKEY(DEL_PAD))
PORT_START(MISCKEYS_TAG)
@ -676,7 +676,7 @@ static MACHINE_CONFIG_START( hazl1500, hazl1500_state )
MCFG_CPU_ADD(CPU_TAG, I8080, XTAL_18MHz/9) // 18MHz crystal on schematics, using an i8224 clock gen/driver IC
MCFG_CPU_PROGRAM_MAP(hazl1500_mem)
MCFG_CPU_IO_MAP(hazl1500_io)
MCFG_QUANTUM_PERFECT_CPU(CPU_TAG)
MCFG_QUANTUM_PERFECT_CPU(CPU_TAG)
/* video hardware */
MCFG_SCREEN_ADD_MONOCHROME(SCREEN_TAG, RASTER, rgb_t::green())
@ -795,5 +795,5 @@ ROM_END
/* Driver */
/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */
COMP( 1977, hazl1500, 0, 0, hazl1500, hazl1500, driver_device, 0, "Hazeltine Corporation", "Hazeltine 1500", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW)
/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */
COMP( 1977, hazl1500, 0, 0, hazl1500, hazl1500, driver_device, 0, "Hazeltine Corporation", "Hazeltine 1500", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW)

6
src/mame/drivers/hh_tms1k.cpp
View File

@ -710,7 +710,7 @@ MACHINE_CONFIG_END
Bandai System Control Car: Cheetah 「システムコントロールカー チーター」
* TMS1000NLL MP0915 (die label 1000B, MP0915)
* 2 motors (one for back axis, one for steering), no sound
It's a programmable buggy, like Big Track but much simpler. To add a command
step in program-mode, press a direction key and one of the time delay number
keys at the same time. To run the program(max 24 steps), switch to run-mode
@ -2557,7 +2557,7 @@ MACHINE_CONFIG_END
Entex Space Battle
* TMS1000 EN-6004 MP0920 (die label 1000B, MP0920)
* 2 7seg LEDs, and other LEDs behind bezel, 1-bit sound
The Japanese version was published by Gakken, same name.
led translation table: led zz from game PCB = MAME y.x:
@ -6397,7 +6397,7 @@ MACHINE_CONFIG_END
(Tandy) Radio Shack Monkey See (1982 version)
* TMS1000 MP0271 (die label 1000E, MP0271), only half of ROM space used
* 2 LEDs(one red, one green), 1-bit sound
This is the TMS1000 version, the one from 1977 has a MM5780.
To play, enter an equation followed by the ?-key, and the calculator will
tell you if it was right(green) or wrong(red). For example 1+2=3?

16
src/mame/drivers/indy_indigo2.cpp
View File

@ -63,14 +63,14 @@
#define PI1_TAG "pi1"
#define KBDC_TAG "kbdc"
#define PIT_TAG "pit"
#define RS232A_TAG "rs232a"
#define RS232B_TAG "rs232b"
#define RS232A_TAG "rs232a"
#define RS232B_TAG "rs232b"
#define SCC_PCLK XTAL_10MHz
#define SCC_RXA_CLK XTAL_3_6864MHz // Needs verification
#define SCC_TXA_CLK 0
#define SCC_RXB_CLK XTAL_3_6864MHz // Needs verification
#define SCC_TXB_CLK 0
#define SCC_PCLK XTAL_10MHz
#define SCC_RXA_CLK XTAL_3_6864MHz // Needs verification
#define SCC_TXA_CLK 0
#define SCC_RXB_CLK XTAL_3_6864MHz // Needs verification
#define SCC_TXB_CLK 0
#define MCFG_IOC2_GUINNESS_ADD(_tag) \
MCFG_DEVICE_ADD(_tag, SGI_IOC2_GUINNESS, 0)
@ -103,7 +103,7 @@ protected:
required_device<mips3_device> m_maincpu;
required_device<scc85230_device> m_scc;
required_device<pc_lpt_device> m_pi1; // we assume standard parallel port (SPP) mode
required_device<pc_lpt_device> m_pi1; // we assume standard parallel port (SPP) mode
// TODO: SGI parallel port (SGIPP), HP BOISE high speed parallel port (HPBPP), and Ricoh scanner modes
required_device<kbdc8042_device> m_kbdc;
required_device<pit8254_device> m_pit;

2
src/mame/drivers/jangou.cpp
View File

@ -763,7 +763,7 @@ static INPUT_PORTS_START( roylcrdn )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_NAME("Note In") /* Note In */
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MEMORY_RESET ) PORT_TOGGLE PORT_CODE(KEYCODE_9) /* Memory Reset */
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_TOGGLE PORT_CODE(KEYCODE_0) PORT_NAME("Analyzer") /* Analyzer */
PORT_SERVICE( 0x10, IP_ACTIVE_LOW ) /* Test Mode */
PORT_SERVICE( 0x10, IP_ACTIVE_LOW ) /* Test Mode */
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_NAME("Coin In") /* Coin In */
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_GAMBLE_KEYOUT ) PORT_NAME("Credit Clear") /* Credit Clear */
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED ) /* Spare 1 */

22
src/mame/drivers/kron.cpp
View File

@ -136,15 +136,15 @@ kron180_state(const machine_config &mconfig, device_type type, const char *tag)
uint8_t *m_vram;
uint32_t screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
DECLARE_WRITE_LINE_MEMBER(keyb_interrupt);
DECLARE_WRITE8_MEMBER( sn74259_w ){ LOGIO(("%s %02x = %02x\n", FUNCNAME, offset & 0x07, offset & 0x08 ? 1 : 0)); }
DECLARE_WRITE8_MEMBER( ap5_w ){ LOGIO(("%s %02x = %02x\n", FUNCNAME, offset, data)); }
DECLARE_READ8_MEMBER( ap5_r ){ LOGIO(("%s() %02x = %02x\n", FUNCNAME, offset, 1)); return 1; }
DECLARE_WRITE8_MEMBER( wkb_w ){ LOGIO(("%s %02x = %02x\n", FUNCNAME, offset, data)); }
DECLARE_WRITE8_MEMBER( sn74299_w ){ LOGIO(("%s %02x = %02x\n", FUNCNAME, offset, data)); }
DECLARE_READ8_MEMBER( sn74299_r ){ LOGIO(("%s() %02x = %02x\n", FUNCNAME, offset, 1)); return 1; }
DECLARE_WRITE8_MEMBER( txen_w ){ LOGIO(("%s %02x = %02x\n", FUNCNAME, offset, data)); }
DECLARE_WRITE8_MEMBER( kbd_reset_w ){ LOGIO(("%s %02x = %02x\n", FUNCNAME, offset, data)); }
DECLARE_WRITE8_MEMBER( dreq_w ){ LOGIO(("%s %02x = %02x\n", FUNCNAME, offset, data)); }
DECLARE_WRITE8_MEMBER( sn74259_w ){ LOGIO(("%s %02x = %02x\n", FUNCNAME, offset & 0x07, offset & 0x08 ? 1 : 0)); }
DECLARE_WRITE8_MEMBER( ap5_w ){ LOGIO(("%s %02x = %02x\n", FUNCNAME, offset, data)); }
DECLARE_READ8_MEMBER( ap5_r ){ LOGIO(("%s() %02x = %02x\n", FUNCNAME, offset, 1)); return 1; }
DECLARE_WRITE8_MEMBER( wkb_w ){ LOGIO(("%s %02x = %02x\n", FUNCNAME, offset, data)); }
DECLARE_WRITE8_MEMBER( sn74299_w ){ LOGIO(("%s %02x = %02x\n", FUNCNAME, offset, data)); }
DECLARE_READ8_MEMBER( sn74299_r ){ LOGIO(("%s() %02x = %02x\n", FUNCNAME, offset, 1)); return 1; }
DECLARE_WRITE8_MEMBER( txen_w ){ LOGIO(("%s %02x = %02x\n", FUNCNAME, offset, data)); }
DECLARE_WRITE8_MEMBER( kbd_reset_w ){ LOGIO(("%s %02x = %02x\n", FUNCNAME, offset, data)); }
DECLARE_WRITE8_MEMBER( dreq_w ){ LOGIO(("%s %02x = %02x\n", FUNCNAME, offset, data)); }
protected:
required_device<cpu_device> m_maincpu;
required_shared_ptr<uint8_t> m_videoram;
@ -320,5 +320,5 @@ ROM_START (kron180)
ROM_END
/* Driver */
/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */
COMP (1995, kron180, 0, 0, kron180, kron180, driver_device, 0, "Kron Ltd", "Kron K-180", MACHINE_NOT_WORKING | MACHINE_NO_SOUND )
/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */
COMP (1995, kron180, 0, 0, kron180, kron180, driver_device, 0, "Kron Ltd", "Kron K-180", MACHINE_NOT_WORKING | MACHINE_NO_SOUND )

2
src/mame/drivers/lsasquad.cpp
View File

@ -735,7 +735,7 @@ ROM_START( lsasquad )
ROM_REGION( 0x0400, "prio_prom", 0 )
ROM_LOAD( "a64-06.9", 0x0000, 0x0400, CRC(7ced30ba) SHA1(f22de13d4fd49b7b2ffd06032eb5e14fbdeec91c) ) /* priority */
ROM_REGION( 0x0200, "plds", 0 )
ROM_LOAD( "pal16l8a.14", 0x0000, 0x0104, CRC(a7cc157d) SHA1(f06f750636d59a610e0b0eda8cb791780ebc57a5) )
ROM_END

120
src/mame/drivers/mac128.cpp
View File

@ -4,9 +4,9 @@
drivers/mac128.cpp
Original-style Macintosh family emulation
The cutoff here is Macs with 128k-style video and audio and no ADB
Nate Woods, Raphael Nabet, R. Belmont
0x000000 - 0x3fffff RAM/ROM (switches based on overlay)
@ -36,7 +36,7 @@
SCC:
PB_EXT (DCDB) from mouse Y circuitry
PA_EXT (DCDA) from mouse X circuitry
SCC Init:
Control B:
@ -130,10 +130,10 @@ enum mac128model_t
#define MAC_ALT_SND_BUF_OFFSET (0x5F00>>1)
#define LOG_KEYBOARD 0
#define LOG_GENERAL 0
#define LOG_MAC_IWM 0
#define LOG_VIA 0
#define LOG_MEMORY 0
#define LOG_GENERAL 0
#define LOG_MAC_IWM 0
#define LOG_VIA 0
#define LOG_MEMORY 0
class mac128_state : public driver_device
{
@ -235,7 +235,7 @@ public:
DECLARE_WRITE16_MEMBER ( macplus_scsi_w );
DECLARE_WRITE_LINE_MEMBER(mac_scsi_irq);
DECLARE_WRITE_LINE_MEMBER(set_scc_interrupt);
TIMER_DEVICE_CALLBACK_MEMBER(mac_scanline);
DECLARE_DRIVER_INIT(mac128k512k);
DECLARE_DRIVER_INIT(mac512ke);
@ -348,7 +348,7 @@ void mac128_state::field_interrupts()
take_interrupt = 1;
}
// printf("field_interrupts: take %d\n", take_interrupt);
// printf("field_interrupts: take %d\n", take_interrupt);
if (m_last_taken_interrupt > -1)
{
@ -365,7 +365,7 @@ void mac128_state::field_interrupts()
WRITE_LINE_MEMBER(mac128_state::set_scc_interrupt)
{
// printf("SCC IRQ: %d\n", state);
// printf("SCC IRQ: %d\n", state);
m_scc_interrupt = state;
field_interrupts();
}
@ -474,59 +474,59 @@ void mac128_state::scc_mouse_irq(int x, int y)
if (x && y)
{
if (m_last_was_x)
if (m_last_was_x)
{
if(x == 2)
if(x == 2)
{
if(lastx)
if(lastx)
{
m_scc->dcda_w(CLEAR_LINE);
m_mouse_bit_x = 0;
}
else
}
else
{
m_scc->dcda_w(ASSERT_LINE);
m_mouse_bit_x = 1;
}
}
else
}
else
{
if(lastx)
if(lastx)
{
m_scc->dcda_w(CLEAR_LINE);
m_mouse_bit_x = 1;
}
else
}
else
{
m_scc->dcda_w(ASSERT_LINE);
m_mouse_bit_x = 0;
}
}
lastx = !lastx;
}
else
}
else
{
if(y == 2)
if(y == 2)
{
if(lasty)
if(lasty)
{
m_scc->dcdb_w(CLEAR_LINE);
m_mouse_bit_y = 0;
}
else
}
else
{
m_scc->dcdb_w(ASSERT_LINE);
m_mouse_bit_y = 1;
}
}
else
}
else
{
if(lasty)
if(lasty)
{
m_scc->dcdb_w(CLEAR_LINE);
m_mouse_bit_y = 1;
}
else
}
else
{
m_scc->dcdb_w(ASSERT_LINE);
m_mouse_bit_y = 0;
@ -539,59 +539,59 @@ void mac128_state::scc_mouse_irq(int x, int y)
}
else
{
if (x)
if (x)
{
if(x == 2)
if(x == 2)
{
if(lastx)
if(lastx)
{
m_scc->dcda_w(CLEAR_LINE);
m_mouse_bit_x = 0;
}
else
}
else
{
m_scc->dcda_w(ASSERT_LINE);
m_mouse_bit_x = 1;
}
}
else
}
else
{
if(lastx)
if(lastx)
{
m_scc->dcda_w(CLEAR_LINE);
m_mouse_bit_x = 1;
}
else
}
else
{
m_scc->dcda_w(ASSERT_LINE);
m_mouse_bit_x = 0;
}
}
lastx = !lastx;
}
else
}
else
{
if(y == 2)
if(y == 2)
{
if(lasty)
if(lasty)
{
m_scc->dcdb_w(CLEAR_LINE);
m_mouse_bit_y = 0;
}
else
}
else
{
m_scc->dcdb_w(ASSERT_LINE);
m_mouse_bit_y = 1;
}
}
else
}
else
{
if(lasty)
if(lasty)
{
m_scc->dcdb_w(CLEAR_LINE);
m_mouse_bit_y = 1;
}
else
}
else
{
m_scc->dcdb_w(ASSERT_LINE);
m_mouse_bit_y = 0;
@ -740,7 +740,7 @@ WRITE8_MEMBER(mac128_state::mac_via_out_a)
/* Early Mac models had VIA A4 control overlaying. In the Mac SE (and
* possibly later models), overlay was set on reset, but cleared on the
* first access to the ROM. */
if (((data & 0x10) >> 4) != m_overlay)
{
m_overlay = (data & 0x10) >> 4;
@ -1336,7 +1336,7 @@ static MACHINE_CONFIG_START( mac512ke, mac128_state )
/* internal ram */
MCFG_RAM_ADD(RAM_TAG)
MCFG_RAM_DEFAULT_SIZE("512K")
// software list
MCFG_SOFTWARE_LIST_ADD("flop35_list","mac_flop")
MCFG_SOFTWARE_LIST_ADD("hdd_list", "mac_hdd")
@ -1554,7 +1554,7 @@ ROM_END
* 04 <- 20 x1 clock, Sync Modes Enable, SDLC Mode (01111110 Flag)
* 0a <- e0 CRC preset to '1's, FM0 encoding scheme
* 06 <- 00 Receiver SDLC ADR0-ADR7 bits
* 07 <- 7e Receiver SDLC Flag character (0x7e as expected)
* 07 <- 7e Receiver SDLC Flag character (0x7e as expected)
* 0c <- 06 Low baudrate divider
* 0d <- 00 Hi baudrate divider
* 0e <- c0 Set FM Mode Command
@ -1562,10 +1562,10 @@ ROM_END
* 02 <- 00 Interrupt vector
* 0f <- 08 External/Status Control: DCD interrupts enabled
* 01 <- 09 Enable External Interrupts + Rx Int On First Character or Special Condition
* 09 <- 0a Master Interrupt Control: No vector and Interrupts enabled!
* 09 <- 0a Master Interrupt Control: No vector and Interrupts enabled!
* 0b <- 70 Rx Clock is DPLL Output, Tx Clock is BRG output + TTL Clock on RTxC
* 0e <- 21 Enter Search Mode Command + BRG enable + RTxC as BRG clock
* 05 <- 60 Tx 8 bit, Tx disable, SDLC CRC Polynomial selected, Tx CRC disabled
* 05 <- 60 Tx 8 bit, Tx disable, SDLC CRC Polynomial selected, Tx CRC disabled
* 06 <- 01 Receiver SDLC ADR0-ADR7 bits updated
* 0f <- 88 External/Status Control: Abort/Break and DCD interrupts enabled
*/
@ -1580,7 +1580,7 @@ ROM_START( macplus )
ROM_REGION16_BE(0x100000, "bootrom", 0)
ROM_SYSTEM_BIOS(0, "v3", "Loud Harmonicas")
ROMX_LOAD( "macplus.rom", 0x00000, 0x20000, CRC(b2102e8e) SHA1(7d2f808a045aa3a1b242764f0e2c7d13e288bf1f), ROM_GROUPWORD | ROM_BIOS(1) )
ROM_FILL(0x20000, 0x2, 0xff) // ROM checks for same contents at 20000 and 40000 to determine if SCSI is present
ROM_FILL(0x20000, 0x2, 0xff) // ROM checks for same contents at 20000 and 40000 to determine if SCSI is present
ROM_FILL(0x40000, 0x2, 0xaa)
ROM_SYSTEM_BIOS(1, "v2", "Lonely Heifers")
ROMX_LOAD( "23512-1007__342-0342-a.rom-lo.u7d", 0x000000, 0x010000, CRC(5aaa4a2f) SHA1(5dfbfbe279ddadfae691c95f552fd9db41e3ed90), ROM_SKIP(1) | ROM_BIOS(2) )
@ -1594,8 +1594,8 @@ ROM_START( macplus )
ROM_SYSTEM_BIOS(3, "romdisk", "mac68k.info self-boot (1/1/2015)")
ROMX_LOAD( "modplus-harp2.bin", 0x000000, 0x028000, CRC(ba56078d) SHA1(debdf328ac73e1662d274a044d8750224f47edef), ROM_GROUPWORD | ROM_BIOS(4) )
ROM_SYSTEM_BIOS(4, "romdisk2", "bigmessofwires.com ROMinator (2/25/2015)")
ROMX_LOAD( "rominator-20150225-lo.bin", 0x000001, 0x080000, CRC(62cf2a0b) SHA1(f78ebb0919dd9e094bef7952b853b70e66d05e01), ROM_SKIP(1) | ROM_BIOS(5) )
ROMX_LOAD( "rominator-20150225-hi.bin", 0x000000, 0x080000, CRC(a28ba8ec) SHA1(9ddcf500727955c60db0ff24b5ca2458f53fd89a), ROM_SKIP(1) | ROM_BIOS(5) )
ROMX_LOAD( "rominator-20150225-lo.bin", 0x000001, 0x080000, CRC(62cf2a0b) SHA1(f78ebb0919dd9e094bef7952b853b70e66d05e01), ROM_SKIP(1) | ROM_BIOS(5) )
ROMX_LOAD( "rominator-20150225-hi.bin", 0x000000, 0x080000, CRC(a28ba8ec) SHA1(9ddcf500727955c60db0ff24b5ca2458f53fd89a), ROM_SKIP(1) | ROM_BIOS(5) )
ROM_END
/* YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY FULLNAME */

54
src/mame/drivers/micro20.cpp
View File

@ -4,9 +4,9 @@
micro20.cpp
GMX Micro 20 single-board computer
68020 + 68881 FPU
800a5e = end of initial 68020 torture test
****************************************************************************/
@ -21,9 +21,9 @@
#define MAINCPU_TAG "maincpu"
#define DUART_A_TAG "duarta"
#define DUART_B_TAG "duartb"
#define RTC_TAG "rtc"
#define FDC_TAG "fdc"
#define PIT_TAG "pit"
#define RTC_TAG "rtc"
#define FDC_TAG "fdc"
#define PIT_TAG "pit"
class micro20_state : public driver_device
{
@ -41,12 +41,12 @@ public:
required_memory_region m_rom;
required_shared_ptr<uint32_t> m_mainram;
required_device<pit68230_device> m_pit;
virtual void machine_start() override;
virtual void machine_reset() override;
DECLARE_WRITE_LINE_MEMBER(m68k_reset_callback);
private:
};
@ -59,11 +59,11 @@ void micro20_state::machine_reset()
{
uint32_t *pROM = (uint32_t *)m_rom->base();
uint32_t *pRAM = (uint32_t *)m_mainram.target();
pRAM[0] = pROM[0];
pRAM[1] = pROM[1];
m_maincpu->reset();
m_maincpu->set_reset_callback(write_line_delegate(FUNC(micro20_state::m68k_reset_callback),this));
}
@ -80,12 +80,12 @@ WRITE_LINE_MEMBER(micro20_state::m68k_reset_callback)
static ADDRESS_MAP_START(micro20_map, AS_PROGRAM, 32, micro20_state )
AM_RANGE(0x00000000, 0x001fffff) AM_RAM AM_SHARE("mainram")
AM_RANGE(0x00800000, 0x0083ffff) AM_ROM AM_REGION("bootrom", 0)
AM_RANGE(0xffff8000, 0xffff8003) AM_DEVREADWRITE8(FDC_TAG, wd1772_t, status_r, cmd_w, 0xff000000)
AM_RANGE(0xffff8000, 0xffff8003) AM_DEVREADWRITE8(FDC_TAG, wd1772_t, track_r, track_w, 0x00ff0000)
AM_RANGE(0xffff8000, 0xffff8003) AM_DEVREADWRITE8(FDC_TAG, wd1772_t, sector_r, sector_w, 0x0000ff00)
AM_RANGE(0xffff8000, 0xffff8003) AM_DEVREADWRITE8(FDC_TAG, wd1772_t, data_r, data_w, 0x000000ff)
AM_RANGE(0xffff8000, 0xffff8003) AM_DEVREADWRITE8(FDC_TAG, wd1772_t, status_r, cmd_w, 0xff000000)
AM_RANGE(0xffff8000, 0xffff8003) AM_DEVREADWRITE8(FDC_TAG, wd1772_t, track_r, track_w, 0x00ff0000)
AM_RANGE(0xffff8000, 0xffff8003) AM_DEVREADWRITE8(FDC_TAG, wd1772_t, sector_r, sector_w, 0x0000ff00)
AM_RANGE(0xffff8000, 0xffff8003) AM_DEVREADWRITE8(FDC_TAG, wd1772_t, data_r, data_w, 0x000000ff)
AM_RANGE(0xffff8080, 0xffff808f) AM_DEVREADWRITE8(DUART_A_TAG, mc68681_device, read, write, 0xffffffff)
AM_RANGE(0xffff80a0, 0xffff80af) AM_DEVREADWRITE8(DUART_B_TAG, mc68681_device, read, write, 0xffffffff)
AM_RANGE(0xffff80a0, 0xffff80af) AM_DEVREADWRITE8(DUART_B_TAG, mc68681_device, read, write, 0xffffffff)
AM_RANGE(0xffff80c0, 0xffff80df) AM_DEVREADWRITE8(PIT_TAG, pit68230_device, read, write, 0xffffffff)
ADDRESS_MAP_END
@ -93,19 +93,19 @@ static MACHINE_CONFIG_START( micro20, micro20_state )
/* basic machine hardware */
MCFG_CPU_ADD(MAINCPU_TAG, M68020, XTAL_16_67MHz)
MCFG_CPU_PROGRAM_MAP(micro20_map)
MCFG_MC68681_ADD(DUART_A_TAG, XTAL_3_6864MHz)
// MCFG_MC68681_IRQ_CALLBACK(WRITELINE(vt240_state, irq13_w))
// MCFG_MC68681_A_TX_CALLBACK(DEVWRITELINE("host", rs232_port_device, write_txd))
// MCFG_MC68681_B_TX_CALLBACK(DEVWRITELINE("printer", rs232_port_device, write_txd))
// MCFG_MC68681_OUTPORT_CALLBACK(WRITE8(vt240_state, duartout_w))
// MCFG_MC68681_IRQ_CALLBACK(WRITELINE(vt240_state, irq13_w))
// MCFG_MC68681_A_TX_CALLBACK(DEVWRITELINE("host", rs232_port_device, write_txd))
// MCFG_MC68681_B_TX_CALLBACK(DEVWRITELINE("printer", rs232_port_device, write_txd))
// MCFG_MC68681_OUTPORT_CALLBACK(WRITE8(vt240_state, duartout_w))
MCFG_MC68681_ADD(DUART_B_TAG, XTAL_3_6864MHz)
MCFG_DEVICE_ADD(RTC_TAG, MSM58321, XTAL_32_768kHz)
MCFG_WD1772_ADD(FDC_TAG, XTAL_16_67MHz / 2)
MCFG_DEVICE_ADD(PIT_TAG, PIT68230, XTAL_16_67MHz / 2)
MACHINE_CONFIG_END
@ -121,10 +121,10 @@ INPUT_PORTS_END
ROM_START( micro20 )
ROM_REGION32_BE(0x40000, "bootrom", 0)
ROM_LOAD32_BYTE( "d00-07_u6_6791.bin", 0x000003, 0x010000, CRC(63d66ea1) SHA1(c5dfbc4d81920e1d2e981c52c1af3d486d382a35) )
ROM_LOAD32_BYTE( "d08-15_u8_0dc6.bin", 0x000002, 0x010000, CRC(d62ef21f) SHA1(2779d430b1a0b835807627e707d46547b29ef579) )
ROM_LOAD32_BYTE( "d16-23_u10_e5b0.bin", 0x000001, 0x010000, CRC(cd7acf86) SHA1(db994ed714a1079fbb66616355e8f18d2d1a2005) )
ROM_LOAD32_BYTE( "d24-31_u13_d115.bin", 0x000000, 0x010000, CRC(3646d943) SHA1(97ee54063e2fe49fef2ff68d0f2e39345a75eac5) )
ROM_LOAD32_BYTE( "d00-07_u6_6791.bin", 0x000003, 0x010000, CRC(63d66ea1) SHA1(c5dfbc4d81920e1d2e981c52c1af3d486d382a35) )
ROM_LOAD32_BYTE( "d08-15_u8_0dc6.bin", 0x000002, 0x010000, CRC(d62ef21f) SHA1(2779d430b1a0b835807627e707d46547b29ef579) )
ROM_LOAD32_BYTE( "d16-23_u10_e5b0.bin", 0x000001, 0x010000, CRC(cd7acf86) SHA1(db994ed714a1079fbb66616355e8f18d2d1a2005) )
ROM_LOAD32_BYTE( "d24-31_u13_d115.bin", 0x000000, 0x010000, CRC(3646d943) SHA1(97ee54063e2fe49fef2ff68d0f2e39345a75eac5) )
ROM_END
COMP( 1984, micro20, 0, 0, micro20, micro20, driver_device, 0, "GMX", "Micro 20", MACHINE_NOT_WORKING | MACHINE_NO_SOUND )

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