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Removed index and clock parameters from CPU_INIT function.

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This commit is contained in:
Aaron Giles 2008-12-18 10:11:10 +00:00
parent aa7e2482e2
commit 72b283a0d1
26 changed files with 104 additions and 106 deletions
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14
src/emu/cpu/adsp2100/adsp2100.c
View File

@ -544,7 +544,7 @@ static void set_irq_line(adsp2100_state *adsp, int irqline, int state)
INITIALIZATION AND SHUTDOWN
***************************************************************************/
static adsp2100_state *adsp21xx_init(const device_config *device, int index, int clock, cpu_irq_callback irqcallback)
static adsp2100_state *adsp21xx_init(const device_config *device, cpu_irq_callback irqcallback)
{
adsp2100_state *adsp = device->token;
@ -2034,7 +2034,7 @@ static void adsp21xx_load_boot_data(UINT8 *srcdata, UINT32 *dstdata)
static CPU_INIT( adsp2100 )
{
adsp2100_state *adsp = adsp21xx_init(device, index, clock, irqcallback);
adsp2100_state *adsp = adsp21xx_init(device, irqcallback);
adsp->chip_type = CHIP_TYPE_ADSP2100;
adsp->mstat_mask = 0x0f;
adsp->imask_mask = 0x0f;
@ -2091,7 +2091,7 @@ CPU_GET_INFO( adsp2100 )
static CPU_INIT( adsp2101 )
{
adsp2100_state *adsp = adsp21xx_init(device, index, clock, irqcallback);
adsp2100_state *adsp = adsp21xx_init(device, irqcallback);
adsp->chip_type = CHIP_TYPE_ADSP2101;
adsp->mstat_mask = 0x7f;
adsp->imask_mask = 0x3f;
@ -2161,7 +2161,7 @@ CPU_GET_INFO( adsp2101 )
static CPU_INIT( adsp2104 )
{
adsp2100_state *adsp = adsp21xx_init(device, index, clock, irqcallback);
adsp2100_state *adsp = adsp21xx_init(device, irqcallback);
adsp->chip_type = CHIP_TYPE_ADSP2104;
adsp->mstat_mask = 0x7f;
adsp->imask_mask = 0x3f;
@ -2236,7 +2236,7 @@ CPU_GET_INFO( adsp2104 )
static CPU_INIT( adsp2105 )
{
adsp2100_state *adsp = adsp21xx_init(device, index, clock, irqcallback);
adsp2100_state *adsp = adsp21xx_init(device, irqcallback);
adsp->chip_type = CHIP_TYPE_ADSP2105;
adsp->mstat_mask = 0x7f;
adsp->imask_mask = 0x3f;
@ -2305,7 +2305,7 @@ CPU_GET_INFO( adsp2105 )
static CPU_INIT( adsp2115 )
{
adsp2100_state *adsp = adsp21xx_init(device, index, clock, irqcallback);
adsp2100_state *adsp = adsp21xx_init(device, irqcallback);
adsp->chip_type = CHIP_TYPE_ADSP2115;
adsp->mstat_mask = 0x7f;
adsp->imask_mask = 0x3f;
@ -2380,7 +2380,7 @@ CPU_GET_INFO( adsp2115 )
static CPU_INIT( adsp2181 )
{
adsp2100_state *adsp = adsp21xx_init(device, index, clock, irqcallback);
adsp2100_state *adsp = adsp21xx_init(device, irqcallback);
adsp->chip_type = CHIP_TYPE_ADSP2181;
adsp->mstat_mask = 0x7f;
adsp->imask_mask = 0x3ff;

2
src/emu/cpu/cop400/cop410.c
View File

@ -200,7 +200,7 @@ static CPU_INIT( cop410 )
/* allocate serial timer */
cop400->serial_timer = timer_alloc(device->machine, cop400_serial_tick, cop400);
timer_adjust_periodic(cop400->serial_timer, attotime_zero, index, ATTOTIME_IN_HZ(clock));
timer_adjust_periodic(cop400->serial_timer, attotime_zero, 0, ATTOTIME_IN_HZ(device->clock / 16));
/* initialize instruction length array */

8
src/emu/cpu/cop400/cop420.c
View File

@ -203,24 +203,24 @@ static CPU_INIT( cop420 )
/* allocate serial timer */
cop400->serial_timer = timer_alloc(device->machine, cop400_serial_tick, cop400);
timer_adjust_periodic(cop400->serial_timer, attotime_zero, 0, ATTOTIME_IN_HZ(clock));
timer_adjust_periodic(cop400->serial_timer, attotime_zero, 0, ATTOTIME_IN_HZ(device->clock / 16));
/* allocate counter timer */
cop400->counter_timer = timer_alloc(device->machine, cop400_counter_tick, cop400);
timer_adjust_periodic(cop400->counter_timer, attotime_zero, 0, ATTOTIME_IN_HZ(clock / 4));
timer_adjust_periodic(cop400->counter_timer, attotime_zero, 0, ATTOTIME_IN_HZ(device->clock / 16 / 4));
/* allocate IN latch timer */
cop400->inil_timer = timer_alloc(device->machine, cop400_inil_tick, cop400);
timer_adjust_periodic(cop400->inil_timer, attotime_zero, 0, ATTOTIME_IN_HZ(clock));
timer_adjust_periodic(cop400->inil_timer, attotime_zero, 0, ATTOTIME_IN_HZ(device->clock / 16));
/* allocate Microbus timer */
if (cop400->intf->microbus == COP400_MICROBUS_ENABLED)
{
cop400->microbus_timer = timer_alloc(device->machine, cop400_microbus_tick, cop400);
timer_adjust_periodic(cop400->microbus_timer, attotime_zero, 0, ATTOTIME_IN_HZ(clock));
timer_adjust_periodic(cop400->microbus_timer, attotime_zero, 0, ATTOTIME_IN_HZ(device->clock / 16));
}
/* initialize instruction length array */

8
src/emu/cpu/cop400/cop440.c
View File

@ -215,24 +215,24 @@ static CPU_INIT( cop444 )
/* allocate serial timer */
cop400->serial_timer = timer_alloc(device->machine, cop400_serial_tick, cop400);
timer_adjust_periodic(cop400->serial_timer, attotime_zero, index, ATTOTIME_IN_HZ(clock));
timer_adjust_periodic(cop400->serial_timer, attotime_zero, 0, ATTOTIME_IN_HZ(device->clock / 16));
/* allocate counter timer */
cop400->counter_timer = timer_alloc(device->machine, cop400_counter_tick, cop400);
timer_adjust_periodic(cop400->counter_timer, attotime_zero, index, ATTOTIME_IN_HZ(clock / 4));
timer_adjust_periodic(cop400->counter_timer, attotime_zero, 0, ATTOTIME_IN_HZ(device->clock / 16 / 4));
/* allocate IN latch timer */
cop400->inil_timer = timer_alloc(device->machine, cop400_inil_tick, cop400);
timer_adjust_periodic(cop400->inil_timer, attotime_zero, index, ATTOTIME_IN_HZ(clock));
timer_adjust_periodic(cop400->inil_timer, attotime_zero, 0, ATTOTIME_IN_HZ(device->clock / 16));
/* allocate Microbus timer */
if (cop400->intf->microbus == COP400_MICROBUS_ENABLED)
{
cop400->microbus_timer = timer_alloc(device->machine, cop400_microbus_tick, cop400);
timer_adjust_periodic(cop400->microbus_timer, attotime_zero, index, ATTOTIME_IN_HZ(clock));
timer_adjust_periodic(cop400->microbus_timer, attotime_zero, 0, ATTOTIME_IN_HZ(device->clock / 16));
}
/* initialize instruction length array */

6
src/emu/cpu/dsp56k/dsp56k.c
View File

@ -150,9 +150,9 @@ static CPU_INIT( dsp56k )
dsp56k_core* cpustate = device->token;
// Call specific module inits
pcu_init(cpustate, index);
// agu_init(cpustate, index);
// alu_init(cpustate, index);
pcu_init(cpustate);
// agu_init(cpustate);
// alu_init(cpustate);
// HACK - You're not in bootstrap mode upon bootup
cpustate->bootstrap_mode = BOOTSTRAP_OFF;

2
src/emu/cpu/dsp56k/dsp56pcu.c
View File

@ -113,7 +113,7 @@ UINT8 dsp56k_operating_mode(dsp56k_core* cpustate)
}
static void pcu_init(dsp56k_core* cpustate, int index)
static void pcu_init(dsp56k_core* cpustate)
{
// Init the irq table
dsp56k_irq_table_init();

38
src/emu/cpu/e132xs/e132xs.c
View File

@ -1521,7 +1521,7 @@ static void set_irq_line(hyperstone_state *cpustate, int irqline, int state)
ISR &= ~(1 << irqline);
}
static void hyperstone_init(const device_config *device, int index, int clock, cpu_irq_callback irqcallback, int scale_mask)
static void hyperstone_init(const device_config *device, cpu_irq_callback irqcallback, int scale_mask)
{
hyperstone_state *cpustate = device->token;
@ -1544,10 +1544,10 @@ static void hyperstone_init(const device_config *device, int index, int clock, c
}
#if (HAS_E116T || HAS_E116XT || HAS_E116XS || HAS_E116XSR || HAS_GMS30C2116 || HAS_GMS30C2216)
static void e116_init(const device_config *device, int index, int clock, cpu_irq_callback irqcallback, int scale_mask)
static void e116_init(const device_config *device, cpu_irq_callback irqcallback, int scale_mask)
{
hyperstone_state *cpustate = device->token;
hyperstone_init(device, index, clock, irqcallback, scale_mask);
hyperstone_init(device, irqcallback, scale_mask);
cpustate->opcodexor = 0;
}
#endif
@ -1555,50 +1555,50 @@ static void e116_init(const device_config *device, int index, int clock, cpu_irq
#if (HAS_E116T)
static CPU_INIT( e116t )
{
e116_init(device, index, clock, irqcallback, 0);
e116_init(device, irqcallback, 0);
}
#endif
#if (HAS_E116XT)
static CPU_INIT( e116xt )
{
e116_init(device, index, clock, irqcallback, 3);
e116_init(device, irqcallback, 3);
}
#endif
#if (HAS_E116XS)
static CPU_INIT( e116xs )
{
e116_init(device, index, clock, irqcallback, 7);
e116_init(device, irqcallback, 7);
}
#endif
#if (HAS_E116XSR)
static CPU_INIT( e116xsr )
{
e116_init(device, index, clock, irqcallback, 7);
e116_init(device, irqcallback, 7);
}
#endif
#if (HAS_GMS30C2116)
static CPU_INIT( gms30c2116 )
{
e116_init(device, index, clock, irqcallback, 0);
e116_init(device, irqcallback, 0);
}
#endif
#if (HAS_GMS30C2216)
static CPU_INIT( gms30c2216 )
{
e116_init(device, index, clock, irqcallback, 0);
e116_init(device, irqcallback, 0);
}
#endif
#if (HAS_E132N || HAS_E132T || HAS_E132XN || HAS_E132XT || HAS_E132XS || HAS_E132XSR || HAS_GMS30C2132 || HAS_GMS30C2232)
static void e132_init(const device_config *device, int index, int clock, cpu_irq_callback irqcallback, int scale_mask)
static void e132_init(const device_config *device, cpu_irq_callback irqcallback, int scale_mask)
{
hyperstone_state *cpustate = device->token;
hyperstone_init(device, index, clock, irqcallback, scale_mask);
hyperstone_init(device, irqcallback, scale_mask);
cpustate->opcodexor = WORD_XOR_BE(0);
}
#endif
@ -1606,56 +1606,56 @@ static void e132_init(const device_config *device, int index, int clock, cpu_irq
#if (HAS_E132N)
static CPU_INIT( e132n )
{
e132_init(device, index, clock, irqcallback, 0);
e132_init(device, irqcallback, 0);
}
#endif
#if (HAS_E132T)
static CPU_INIT( e132t )
{
e132_init(device, index, clock, irqcallback, 0);
e132_init(device, irqcallback, 0);
}
#endif
#if (HAS_E132XN)
static CPU_INIT( e132xn )
{
e132_init(device, index, clock, irqcallback, 3);
e132_init(device, irqcallback, 3);
}
#endif
#if (HAS_E132XT)
static CPU_INIT( e132xt )
{
e132_init(device, index, clock, irqcallback, 3);
e132_init(device, irqcallback, 3);
}
#endif
#if (HAS_E132XS)
static CPU_INIT( e132xs )
{
e132_init(device, index, clock, irqcallback, 7);
e132_init(device, irqcallback, 7);
}
#endif
#if (HAS_E132XSR)
static CPU_INIT( e132xsr )
{
e132_init(device, index, clock, irqcallback, 7);
e132_init(device, irqcallback, 7);
}
#endif
#if (HAS_GMS30C2132)
static CPU_INIT( gms30c2132 )
{
e132_init(device, index, clock, irqcallback, 0);
e132_init(device, irqcallback, 0);
}
#endif
#if (HAS_GMS30C2232)
static CPU_INIT( gms30c2232 )
{
e132_init(device, index, clock, irqcallback, 0);
e132_init(device, irqcallback, 0);
}
#endif

14
src/emu/cpu/m6502/m6502.c
View File

@ -130,7 +130,7 @@ static void default_wdmem_id(const address_space *space, offs_t offset, UINT8 da
*
*****************************************************************************/
static void m6502_common_init(const device_config *device, int index, int clock, cpu_irq_callback irqcallback, UINT8 subtype, void (*const *insn)(m6502_Regs *cpustate), const char *type)
static void m6502_common_init(const device_config *device, cpu_irq_callback irqcallback, UINT8 subtype, void (*const *insn)(m6502_Regs *cpustate), const char *type)
{
m6502_Regs *cpustate = device->token;
@ -165,7 +165,7 @@ static void m6502_common_init(const device_config *device, int index, int clock,
static CPU_INIT( m6502 )
{
m6502_common_init(device, index, clock, irqcallback, SUBTYPE_6502, insn6502, "m6502");
m6502_common_init(device, irqcallback, SUBTYPE_6502, insn6502, "m6502");
}
static CPU_RESET( m6502 )
@ -313,7 +313,7 @@ static void m6502_set_irq_line(m6502_Regs *cpustate, int irqline, int state)
static CPU_INIT( n2a03 )
{
m6502_common_init(device, index, clock, irqcallback, SUBTYPE_2A03, insn2a03, "n2a03");
m6502_common_init(device, irqcallback, SUBTYPE_2A03, insn2a03, "n2a03");
}
/* The N2A03 is integrally tied to its PSG (they're on the same die).
@ -336,7 +336,7 @@ void n2a03_irq(const device_config *device)
static CPU_INIT( m6510 )
{
m6502_common_init(device, index, clock, irqcallback, SUBTYPE_6510, insn6510, "m6510");
m6502_common_init(device, irqcallback, SUBTYPE_6510, insn6510, "m6510");
}
static CPU_RESET( m6510 )
@ -404,7 +404,7 @@ ADDRESS_MAP_END
static CPU_INIT( m65c02 )
{
m6502_common_init(device, index, clock, irqcallback, SUBTYPE_65C02, insn65c02, "m65c02");
m6502_common_init(device, irqcallback, SUBTYPE_65C02, insn65c02, "m65c02");
}
static CPU_RESET( m65c02 )
@ -510,7 +510,7 @@ static void m65c02_set_irq_line(m6502_Regs *cpustate, int irqline, int state)
#if (HAS_M65SC02)
static CPU_INIT( m65sc02 )
{
m6502_common_init(device, index, clock, irqcallback, SUBTYPE_65SC02, insn65sc02, "m65sc02");
m6502_common_init(device, irqcallback, SUBTYPE_65SC02, insn65sc02, "m65sc02");
}
#endif
@ -522,7 +522,7 @@ static CPU_INIT( m65sc02 )
static CPU_INIT( deco16 )
{
m6502_Regs *cpustate = device->token;
m6502_common_init(device, index, clock, irqcallback, SUBTYPE_DECO16, insndeco16, "deco16");
m6502_common_init(device, irqcallback, SUBTYPE_DECO16, insndeco16, "deco16");
cpustate->io = memory_find_address_space(device, ADDRESS_SPACE_IO);
}

6
src/emu/cpu/m6800/m6800.c
View File

@ -1287,7 +1287,7 @@ static CPU_INIT( m6801 )
cpustate->data = cpu_get_address_space(device, ADDRESS_SPACE_DATA);
cpustate->io = cpu_get_address_space(device, ADDRESS_SPACE_IO);
cpustate->clock = clock;
cpustate->clock = device->clock / 4;
cpustate->m6800_rx_timer = timer_alloc(device->machine, m6800_rx_tick, cpustate);
cpustate->m6800_tx_timer = timer_alloc(device->machine, m6800_tx_tick, cpustate);
@ -1333,7 +1333,7 @@ static CPU_INIT( m6803 )
cpustate->data = cpu_get_address_space(device, ADDRESS_SPACE_DATA);
cpustate->io = cpu_get_address_space(device, ADDRESS_SPACE_IO);
cpustate->clock = clock;
cpustate->clock = device->clock / 4;
cpustate->m6800_rx_timer = timer_alloc(device->machine, m6800_rx_tick, cpustate);
cpustate->m6800_tx_timer = timer_alloc(device->machine, m6800_tx_tick, cpustate);
@ -1695,7 +1695,7 @@ static CPU_INIT( hd63701 )
cpustate->data = cpu_get_address_space(device, ADDRESS_SPACE_DATA);
cpustate->io = cpu_get_address_space(device, ADDRESS_SPACE_IO);
cpustate->clock = clock;
cpustate->clock = device->clock / 4;
cpustate->m6800_rx_timer = timer_alloc(device->machine, m6800_rx_tick, cpustate);
cpustate->m6800_tx_timer = timer_alloc(device->machine, m6800_tx_tick, cpustate);

2
src/emu/cpu/mb86233/mb86233.c
View File

@ -97,8 +97,6 @@ static CPU_INIT( mb86233 )
{
mb86233_state *cpustate = device->token;
mb86233_cpu_core * _config = (mb86233_cpu_core *)device->static_config;
(void)index;
(void)clock;
(void)irqcallback;
memset(cpustate, 0, sizeof( *cpustate ) );

10
src/emu/cpu/mcs48/mcs48.c
View File

@ -693,7 +693,7 @@ static const mcs48_opcode opcode_table[256]=
mcs48_init - generic MCS-48 initialization
-------------------------------------------------*/
static void mcs48_init(const device_config *device, int index, int clock, cpu_irq_callback irqcallback, UINT16 romsize)
static void mcs48_init(const device_config *device, cpu_irq_callback irqcallback, UINT16 romsize)
{
mcs48_state *cpustate = device->token;
@ -747,7 +747,7 @@ static void mcs48_init(const device_config *device, int index, int clock, cpu_ir
#if (HAS_I8035 || HAS_MB8884)
static CPU_INIT( i8035 )
{
mcs48_init(device, index, clock, irqcallback, 0x0);
mcs48_init(device, irqcallback, 0x0);
}
#endif
@ -761,7 +761,7 @@ static CPU_INIT( i8035 )
#if (HAS_I8048 || HAS_I8648 || HAS_I8748 || HAS_N7751)
static CPU_INIT( i8048 )
{
mcs48_init(device, index, clock, irqcallback, 0x400);
mcs48_init(device, irqcallback, 0x400);
}
#endif
@ -775,7 +775,7 @@ static CPU_INIT( i8048 )
#if (HAS_I8039)
static CPU_INIT( i8039 )
{
mcs48_init(device, index, clock, irqcallback, 0x0);
mcs48_init(device, irqcallback, 0x0);
}
#endif
@ -789,7 +789,7 @@ static CPU_INIT( i8039 )
#if (HAS_I8049 || HAS_I8749 || HAS_M58715)
static CPU_INIT( i8049 )
{
mcs48_init(device, index, clock, irqcallback, 0x800);
mcs48_init(device, irqcallback, 0x800);
}
#endif

4
src/emu/cpu/mips/mips3com.c
View File

@ -70,7 +70,7 @@ INLINE int tlb_entry_is_global(const mips3_tlb_entry *entry)
structure based on the configured type
-------------------------------------------------*/
void mips3com_init(mips3_state *mips, mips3_flavor flavor, int bigendian, const device_config *device, int index, int clock, cpu_irq_callback irqcallback)
void mips3com_init(mips3_state *mips, mips3_flavor flavor, int bigendian, const device_config *device, cpu_irq_callback irqcallback)
{
const mips3_config *config = device->static_config;
int tlbindex;
@ -79,7 +79,7 @@ void mips3com_init(mips3_state *mips, mips3_flavor flavor, int bigendian, const
memset(mips, 0, sizeof(*mips));
mips->flavor = flavor;
mips->bigendian = bigendian;
mips->cpu_clock = clock;
mips->cpu_clock = device->clock;
mips->irq_callback = irqcallback;
mips->device = device;
mips->program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);

2
src/emu/cpu/mips/mips3com.h
View File

@ -225,7 +225,7 @@ struct _mips3_state
FUNCTION PROTOTYPES
***************************************************************************/
void mips3com_init(mips3_state *mips, mips3_flavor flavor, int bigendian, const device_config *device, int index, int clock, cpu_irq_callback irqcallback);
void mips3com_init(mips3_state *mips, mips3_flavor flavor, int bigendian, const device_config *device, cpu_irq_callback irqcallback);
void mips3com_exit(mips3_state *mips);
void mips3com_reset(mips3_state *mips);

28
src/emu/cpu/mips/mips3drc.c
View File

@ -340,7 +340,7 @@ INLINE void save_fast_iregs(mips3_state *mips3, drcuml_block *block)
mips3_init - initialize the processor
-------------------------------------------------*/
static void mips3_init(mips3_flavor flavor, int bigendian, const device_config *device, int index, int clock, cpu_irq_callback irqcallback)
static void mips3_init(mips3_flavor flavor, int bigendian, const device_config *device, cpu_irq_callback irqcallback)
{
drcfe_config feconfig =
{
@ -365,7 +365,7 @@ static void mips3_init(mips3_flavor flavor, int bigendian, const device_config *
memset(mips3, 0, sizeof(*mips3));
/* initialize the core */
mips3com_init(mips3, flavor, bigendian, device, index, clock, irqcallback);
mips3com_init(mips3, flavor, bigendian, device, irqcallback);
/* allocate the implementation-specific state from the full cache */
mips3->impstate = drccache_memory_alloc_near(cache, sizeof(*mips3->impstate));
@ -3625,12 +3625,12 @@ static void log_opcode_desc(drcuml_state *drcuml, const opcode_desc *desclist, i
#if (HAS_R4600)
static CPU_INIT( r4600be )
{
mips3_init(MIPS3_TYPE_R4600, TRUE, device, index, clock, irqcallback);
mips3_init(MIPS3_TYPE_R4600, TRUE, device, irqcallback);
}
static CPU_INIT( r4600le )
{
mips3_init(MIPS3_TYPE_R4600, FALSE, device, index, clock, irqcallback);
mips3_init(MIPS3_TYPE_R4600, FALSE, device, irqcallback);
}
CPU_GET_INFO( r4600be )
@ -3679,12 +3679,12 @@ CPU_GET_INFO( r4600le )
#if (HAS_R4650)
static CPU_INIT( r4650be )
{
mips3_init(MIPS3_TYPE_R4650, TRUE, device, index, clock, irqcallback);
mips3_init(MIPS3_TYPE_R4650, TRUE, device, irqcallback);
}
static CPU_INIT( r4650le )
{
mips3_init(MIPS3_TYPE_R4650, FALSE, device, index, clock, irqcallback);
mips3_init(MIPS3_TYPE_R4650, FALSE, device, irqcallback);
}
CPU_GET_INFO( r4650be )
@ -3733,12 +3733,12 @@ CPU_GET_INFO( r4650le )
#if (HAS_R4700)
static CPU_INIT( r4700be )
{
mips3_init(MIPS3_TYPE_R4700, TRUE, device, index, clock, irqcallback);
mips3_init(MIPS3_TYPE_R4700, TRUE, device, irqcallback);
}
static CPU_INIT( r4700le )
{
mips3_init(MIPS3_TYPE_R4700, FALSE, device, index, clock, irqcallback);
mips3_init(MIPS3_TYPE_R4700, FALSE, device, irqcallback);
}
CPU_GET_INFO( r4700be )
@ -3787,12 +3787,12 @@ CPU_GET_INFO( r4700le )
#if (HAS_R5000)
static CPU_INIT( r5000be )
{
mips3_init(MIPS3_TYPE_R5000, TRUE, device, index, clock, irqcallback);
mips3_init(MIPS3_TYPE_R5000, TRUE, device, irqcallback);
}
static CPU_INIT( r5000le )
{
mips3_init(MIPS3_TYPE_R5000, FALSE, device, index, clock, irqcallback);
mips3_init(MIPS3_TYPE_R5000, FALSE, device, irqcallback);
}
CPU_GET_INFO( r5000be )
@ -3841,12 +3841,12 @@ CPU_GET_INFO( r5000le )
#if (HAS_QED5271)
static CPU_INIT( qed5271be )
{
mips3_init(MIPS3_TYPE_QED5271, TRUE, device, index, clock, irqcallback);
mips3_init(MIPS3_TYPE_QED5271, TRUE, device, irqcallback);
}
static CPU_INIT( qed5271le )
{
mips3_init(MIPS3_TYPE_QED5271, FALSE, device, index, clock, irqcallback);
mips3_init(MIPS3_TYPE_QED5271, FALSE, device, irqcallback);
}
CPU_GET_INFO( qed5271be )
@ -3895,12 +3895,12 @@ CPU_GET_INFO( qed5271le )
#if (HAS_RM7000)
static CPU_INIT( rm7000be )
{
mips3_init(MIPS3_TYPE_RM7000, TRUE, device, index, clock, irqcallback);
mips3_init(MIPS3_TYPE_RM7000, TRUE, device, irqcallback);
}
static CPU_INIT( rm7000le )
{
mips3_init(MIPS3_TYPE_RM7000, FALSE, device, index, clock, irqcallback);
mips3_init(MIPS3_TYPE_RM7000, FALSE, device, irqcallback);
}
CPU_GET_INFO( rm7000be )

8
src/emu/cpu/nec/nec.c
View File

@ -1087,7 +1087,7 @@ static CPU_DISASSEMBLE( nec )
return necv_dasm_one(buffer, pc, oprom, nec_state->config);
}
static void nec_init(const device_config *device, int index, int clock, cpu_irq_callback irqcallback, int type)
static void nec_init(const device_config *device, cpu_irq_callback irqcallback, int type)
{
const nec_config *config = device->static_config ? device->static_config : &default_config;
nec_state_t *nec_state = device->token;
@ -1212,7 +1212,7 @@ static CPU_INIT( v20 )
{
nec_state_t *nec_state = device->token;
nec_init(device, index, clock, irqcallback, 0);
nec_init(device, irqcallback, 0);
configure_memory_8bit(nec_state);
nec_state->chip_type=V20;
nec_state->prefetch_size = 4; /* 3 words */
@ -1225,7 +1225,7 @@ static CPU_INIT( v30 )
{
nec_state_t *nec_state = device->token;
nec_init(device, index, clock, irqcallback, 1);
nec_init(device, irqcallback, 1);
configure_memory_16bit(nec_state);
nec_state->chip_type=V30;
nec_state->prefetch_size = 6; /* 3 words */
@ -1239,7 +1239,7 @@ static CPU_INIT( v33 )
{
nec_state_t *nec_state = device->token;
nec_init(device, index, clock, irqcallback, 2);
nec_init(device, irqcallback, 2);
nec_state->chip_type=V33;
nec_state->prefetch_size = 6;
/* FIXME: Need information about prefetch size and cycles for V33.

6
src/emu/cpu/pdp1/tx0.c
View File

@ -118,7 +118,7 @@ static void tx0_write(tx0_state *cpustate, offs_t address, int data)
;
}
static void tx0_init_common(int is_64kw, const device_config *device, int index, int clock, cpu_irq_callback irqcallback)
static void tx0_init_common(int is_64kw, const device_config *device, cpu_irq_callback irqcallback)
{
tx0_state *cpustate = device->token;
@ -134,12 +134,12 @@ static void tx0_init_common(int is_64kw, const device_config *device, int index,
static CPU_INIT( tx0_64kw )
{
tx0_init_common(1, device, index, clock, irqcallback);
tx0_init_common(1, device, irqcallback);
}
static CPU_INIT( tx0_8kw)
{
tx0_init_common(0, device, index, clock, irqcallback);
tx0_init_common(0, device, irqcallback);
}
static CPU_RESET( tx0 )

8
src/emu/cpu/powerpc/ppccom.c
View File

@ -184,7 +184,7 @@ INLINE void set_decrementer(powerpc_state *ppc, UINT32 newdec)
structure based on the configured type
-------------------------------------------------*/
void ppccom_init(powerpc_state *ppc, powerpc_flavor flavor, UINT8 cap, int tb_divisor, const device_config *device, int index, int clock, cpu_irq_callback irqcallback)
void ppccom_init(powerpc_state *ppc, powerpc_flavor flavor, UINT8 cap, int tb_divisor, const device_config *device, cpu_irq_callback irqcallback)
{
const powerpc_config *config = device->static_config;
@ -194,12 +194,12 @@ void ppccom_init(powerpc_state *ppc, powerpc_flavor flavor, UINT8 cap, int tb_di
ppc->cap = cap;
ppc->cache_line_size = 32;
ppc->tb_divisor = tb_divisor;
ppc->cpu_clock = clock;
ppc->cpu_clock = device->clock;
ppc->irq_callback = irqcallback;
ppc->device = device;
ppc->program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
ppc->system_clock = (config != NULL) ? config->bus_frequency : clock;
ppc->tb_divisor = (ppc->tb_divisor * clock + ppc->system_clock / 2 - 1) / ppc->system_clock;
ppc->system_clock = (config != NULL) ? config->bus_frequency : device->clock;
ppc->tb_divisor = (ppc->tb_divisor * device->clock + ppc->system_clock / 2 - 1) / ppc->system_clock;
/* allocate the virtual TLB */
ppc->vtlb = vtlb_alloc(device, ADDRESS_SPACE_PROGRAM, (cap & PPCCAP_603_MMU) ? PPC603_FIXED_TLB_ENTRIES : 0, POWERPC_TLB_ENTRIES);

2
src/emu/cpu/powerpc/ppccom.h
View File

@ -572,7 +572,7 @@ struct _powerpc_state
FUNCTION PROTOTYPES
***************************************************************************/
void ppccom_init(powerpc_state *ppc, powerpc_flavor flavor, UINT8 cap, int tb_divisor, const device_config *device, int index, int clock, cpu_irq_callback irqcallback);
void ppccom_init(powerpc_state *ppc, powerpc_flavor flavor, UINT8 cap, int tb_divisor, const device_config *device, cpu_irq_callback irqcallback);
void ppccom_exit(powerpc_state *ppc);
void ppccom_reset(powerpc_state *ppc);

22
src/emu/cpu/powerpc/ppcdrc.c
View File

@ -531,7 +531,7 @@ INLINE UINT32 compute_spr(UINT32 spr)
ppcdrc_init - initialize the processor
-------------------------------------------------*/
static void ppcdrc_init(powerpc_flavor flavor, UINT8 cap, int tb_divisor, const device_config *device, int index, int clock, cpu_irq_callback irqcallback)
static void ppcdrc_init(powerpc_flavor flavor, UINT8 cap, int tb_divisor, const device_config *device, cpu_irq_callback irqcallback)
{
drcfe_config feconfig =
{
@ -556,7 +556,7 @@ static void ppcdrc_init(powerpc_flavor flavor, UINT8 cap, int tb_divisor, const
memset(ppc, 0, sizeof(*ppc));
/* initialize the core */
ppccom_init(ppc, flavor, cap, tb_divisor, device, index, clock, irqcallback);
ppccom_init(ppc, flavor, cap, tb_divisor, device, irqcallback);
/* allocate the implementation-specific state from the full cache */
ppc->impstate = drccache_memory_alloc_near(cache, sizeof(*ppc->impstate));
@ -4228,7 +4228,7 @@ static CPU_SET_INFO( ppcdrc4xx )
static CPU_INIT( ppc403ga )
{
ppcdrc_init(PPC_MODEL_403GA, PPCCAP_4XX, 1, device, index, clock, irqcallback);
ppcdrc_init(PPC_MODEL_403GA, PPCCAP_4XX, 1, device, irqcallback);
}
@ -4267,7 +4267,7 @@ CPU_GET_INFO( ppc403ga )
static CPU_INIT( ppc403gcx )
{
ppcdrc_init(PPC_MODEL_403GCX, PPCCAP_4XX, 1, device, index, clock, irqcallback);
ppcdrc_init(PPC_MODEL_403GCX, PPCCAP_4XX, 1, device, irqcallback);
}
@ -4311,7 +4311,7 @@ CPU_GET_INFO( ppc403gcx )
static CPU_INIT( ppc601 )
{
ppcdrc_init(PPC_MODEL_601, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED, 0/* no TB */, device, index, clock, irqcallback);
ppcdrc_init(PPC_MODEL_601, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED, 0/* no TB */, device, irqcallback);
}
@ -4349,7 +4349,7 @@ CPU_GET_INFO( ppc601 )
static CPU_INIT( ppc602 )
{
ppcdrc_init(PPC_MODEL_602, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED | PPCCAP_603_MMU, 4, device, index, clock, irqcallback);
ppcdrc_init(PPC_MODEL_602, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED | PPCCAP_603_MMU, 4, device, irqcallback);
}
@ -4387,7 +4387,7 @@ CPU_GET_INFO( ppc602 )
static CPU_INIT( ppc603 )
{
ppcdrc_init(PPC_MODEL_603, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED | PPCCAP_603_MMU, 4, device, index, clock, irqcallback);
ppcdrc_init(PPC_MODEL_603, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED | PPCCAP_603_MMU, 4, device, irqcallback);
}
@ -4425,7 +4425,7 @@ CPU_GET_INFO( ppc603 )
static CPU_INIT( ppc603e )
{
ppcdrc_init(PPC_MODEL_603E, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED | PPCCAP_603_MMU, 4, device, index, clock, irqcallback);
ppcdrc_init(PPC_MODEL_603E, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED | PPCCAP_603_MMU, 4, device, irqcallback);
}
@ -4463,7 +4463,7 @@ CPU_GET_INFO( ppc603e )
static CPU_INIT( ppc603r )
{
ppcdrc_init(PPC_MODEL_603R, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED | PPCCAP_603_MMU, 4, device, index, clock, irqcallback);
ppcdrc_init(PPC_MODEL_603R, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED | PPCCAP_603_MMU, 4, device, irqcallback);
}
@ -4501,7 +4501,7 @@ CPU_GET_INFO( ppc603r )
static CPU_INIT( ppc604 )
{
ppcdrc_init(PPC_MODEL_604, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED, 4, device, index, clock, irqcallback);
ppcdrc_init(PPC_MODEL_604, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED, 4, device, irqcallback);
}
@ -4544,7 +4544,7 @@ CPU_GET_INFO( ppc604 )
static CPU_INIT( mpc8240 )
{
ppcdrc_init(PPC_MODEL_MPC8240, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED, 4/* unknown */, device, index, clock, irqcallback);
ppcdrc_init(PPC_MODEL_MPC8240, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED, 4/* unknown */, device, irqcallback);
}

2
src/emu/cpu/sh2/sh2.c
View File

@ -2251,7 +2251,7 @@ static CPU_INIT( sh2 )
memset(sh2, 0, sizeof(SH2));
/* initialize the common core parts */
sh2_common_init(sh2, device, index, clock, irqcallback);
sh2_common_init(sh2, device, irqcallback);
}
/**************************************************************************

2
src/emu/cpu/sh2/sh2comn.c
View File

@ -696,7 +696,7 @@ void sh2_exception(SH2 *sh2, const char *message, int irqline)
#endif
}
void sh2_common_init(SH2 *sh2, const device_config *device, int index, int clock, cpu_irq_callback irqcallback)
void sh2_common_init(SH2 *sh2, const device_config *device, cpu_irq_callback irqcallback)
{
const sh2_cpu_core *conf = device->static_config;

2
src/emu/cpu/sh2/sh2comn.h
View File

@ -174,7 +174,7 @@ typedef struct
TIMER_CALLBACK( sh2_timer_callback );
TIMER_CALLBACK( sh2_dmac_callback );
void sh2_common_init(SH2 *sh2, const device_config *device, int index, int clock, cpu_irq_callback irqcallback);
void sh2_common_init(SH2 *sh2, const device_config *device, cpu_irq_callback irqcallback);
void sh2_recalc_irq(SH2 *sh2);
void sh2_set_irq_line(SH2 *sh2, int irqline, int state);
void sh2_set_frt_input(const device_config *device, int state);

2
src/emu/cpu/sh2/sh2drc.c
View File

@ -685,7 +685,7 @@ static CPU_INIT( sh2 )
memset(sh2, 0, sizeof(SH2));
/* initialize the common core parts */
sh2_common_init(sh2, device, index, clock, irqcallback);
sh2_common_init(sh2, device, irqcallback);
/* allocate the implementation-specific state from the full cache */
sh2->cache = cache;

4
src/emu/cpu/v30mz/v30mz.c
View File

@ -913,7 +913,7 @@ static CPU_DISASSEMBLE( nec )
return necv_dasm_one(buffer, pc, oprom);
}
static void nec_init(const device_config *device, int index, int clock, cpu_irq_callback irqcallback, int type)
static void nec_init(const device_config *device, cpu_irq_callback irqcallback, int type)
{
v30mz_state *cpustate = device->token;
@ -942,7 +942,7 @@ static void nec_init(const device_config *device, int index, int clock, cpu_irq_
cpustate->io = memory_find_address_space(device, ADDRESS_SPACE_IO);
}
static CPU_INIT( v30mz ) { nec_init(device, index, clock, irqcallback, 3); }
static CPU_INIT( v30mz ) { nec_init(device, irqcallback, 3); }
static CPU_EXECUTE( v30mz )
{
v30mz_state *cpustate = device->token;

2
src/emu/cpuexec.c
View File

@ -418,7 +418,7 @@ static DEVICE_START( cpu )
/* initialize this CPU */
num_regs = state_save_get_reg_count(device->machine);
init = (cpu_init_func)device_get_info_fct(device, CPUINFO_PTR_INIT);
(*init)(device, index, classdata->clock, standard_irq_callback);
(*init)(device, standard_irq_callback);
num_regs = state_save_get_reg_count(device->machine) - num_regs;
/* fetch post-initialization data */

6
src/emu/cpuintrf.h
View File

@ -224,8 +224,8 @@ enum
#define CPU_SET_INFO_CALL(name) CPU_SET_INFO_NAME(name)(device, state, info)
#define CPU_INIT_NAME(name) cpu_init_##name
#define CPU_INIT(name) void CPU_INIT_NAME(name)(const device_config *device, int index, int clock, cpu_irq_callback irqcallback)
#define CPU_INIT_CALL(name) CPU_INIT_NAME(name)(device, index, clock, irqcallback)
#define CPU_INIT(name) void CPU_INIT_NAME(name)(const device_config *device, cpu_irq_callback irqcallback)
#define CPU_INIT_CALL(name) CPU_INIT_NAME(name)(device, irqcallback)
#define CPU_RESET_NAME(name) cpu_reset_##name
#define CPU_RESET(name) void CPU_RESET_NAME(name)(const device_config *device)
@ -334,7 +334,7 @@ typedef int (*cpu_irq_callback)(const device_config *device, int irqnum);
typedef void (*cpu_get_info_func)(const device_config *device, UINT32 state, cpuinfo *info);
typedef void (*cpu_set_info_func)(const device_config *device, UINT32 state, cpuinfo *info);
typedef void (*cpu_init_func)(const device_config *device, int index, int clock, cpu_irq_callback irqcallback);
typedef void (*cpu_init_func)(const device_config *device, cpu_irq_callback irqcallback);
typedef void (*cpu_reset_func)(const device_config *device);
typedef void (*cpu_exit_func)(const device_config *device);
typedef int (*cpu_execute_func)(const device_config *device, int cycles);