diff --git a/scripts/src/machine.lua b/scripts/src/machine.lua index 63bec113de8..13be57aa125 100644 --- a/scripts/src/machine.lua +++ b/scripts/src/machine.lua @@ -1872,6 +1872,8 @@ if (MACHINES["PCI"]~=null) then MAME_DIR .. "src/devices/machine/i6300esb.h", MAME_DIR .. "src/devices/machine/i82439hx.cpp", MAME_DIR .. "src/devices/machine/i82439hx.h", + MAME_DIR .. "src/devices/machine/i82439tx.cpp", + MAME_DIR .. "src/devices/machine/i82439tx.h", MAME_DIR .. "src/devices/machine/i82371sb.cpp", MAME_DIR .. "src/devices/machine/i82371sb.h", MAME_DIR .. "src/devices/machine/lpc.cpp", diff --git a/src/devices/machine/i82371sb.cpp b/src/devices/machine/i82371sb.cpp index df4360bdf1c..745a9196824 100644 --- a/src/devices/machine/i82371sb.cpp +++ b/src/devices/machine/i82371sb.cpp @@ -5,7 +5,9 @@ #include "i82371sb.h" #include "cpu/i386/i386.h" #include "bus/pc_kbd/keyboards.h" - +// VGA-HACK +#include "video/pc_vga.h" +// end-VGA-HACK const device_type I82371SB_ISA = &device_creator; DEVICE_ADDRESS_MAP_START(config_map, 32, i82371sb_isa_device) @@ -38,7 +40,13 @@ DEVICE_ADDRESS_MAP_START(internal_io_map, 32, i82371sb_isa_device) AM_RANGE(0x0080, 0x009f) AM_READWRITE8(at_page8_r, at_page8_w, 0xffffffff); AM_RANGE(0x00a0, 0x00bf) AM_DEVREADWRITE8("pic8259_slave", pic8259_device, read, write, 0xffffffff) AM_RANGE(0x00c0, 0x00df) AM_READWRITE8(at_dma8237_2_r, at_dma8237_2_w, 0xffffffff); - AM_RANGE(0x00ec, 0x00ef) AM_WRITE8 (nop_w, 0x0000ff00) // Non-existing, used for delays by the bios/os + AM_RANGE(0x00e0, 0x00ef) AM_NOP + + // VGA-HACK + AM_RANGE(0x3b0, 0x3bf) AM_DEVREADWRITE8("vga",vga_device,port_03b0_r, port_03b0_w, 0xffffffff); + AM_RANGE(0x3c0, 0x3cf) AM_DEVREADWRITE8("vga",vga_device,port_03c0_r, port_03c0_w, 0xffffffff); + AM_RANGE(0x3d0, 0x3df) AM_DEVREADWRITE8("vga",vga_device,port_03d0_r, port_03d0_w, 0xffffffff); + // end-VGA-HACK ADDRESS_MAP_END static MACHINE_CONFIG_FRAGMENT( southbridge ) @@ -138,6 +146,9 @@ static MACHINE_CONFIG_FRAGMENT( southbridge ) // MCFG_ISA16_SLOT_ADD("isabus","board1", pc_isa_onboard, "fdcsmc", true) // MCFG_ISA16_SLOT_ADD("isabus","board2", pc_isa_onboard, "comat", true) // MCFG_ISA16_SLOT_ADD("isabus","board3", pc_isa_onboard, "lpt", true) + // VGA-HACK + MCFG_FRAGMENT_ADD( pcvideo_vga ); + // end-VGA-HACK MACHINE_CONFIG_END //------------------------------------------------- @@ -166,6 +177,9 @@ i82371sb_isa_device::i82371sb_isa_device(const machine_config &mconfig, const ch m_ds12885(*this, "rtc"), m_pc_kbdc(*this, "pc_kbdc") , m_at_spkrdata(0), m_pit_out2(0), m_dma_channel(0), m_cur_eop(false), m_dma_high_byte(0), m_at_speaker(0), m_refresh(false), m_channel_check(0), m_nmi_enabled(0) + // VGA-HACK + ,m_vga_region(*this, ":ibm_vga") + // end-VGA-HACK { } @@ -413,7 +427,11 @@ void i82371sb_isa_device::map_extra(uint64_t memory_window_start, uint64_t memor { map_bios(memory_space, 0xfffc0000, 0xffffffff); map_bios(memory_space, 0x000e0000, 0x000fffff); - + // VGA-HACK + vga_device *m_vga = subdevice("vga"); + memory_space->install_rom(0x000c0000, 0x000c7fff, m_vga_region->base()); + memory_space->install_readwrite_handler(0xa0000,0xbffff,read8_delegate(FUNC(vga_device::mem_r),m_vga),write8_delegate(FUNC(vga_device::mem_w),m_vga),0xffffffff); + // end-VGA-HACK io_space->install_device(0, 0xffff, *this, &i82371sb_isa_device::internal_io_map); #if 0 diff --git a/src/devices/machine/i82371sb.h b/src/devices/machine/i82371sb.h index 87147ac9f58..18a7005c318 100644 --- a/src/devices/machine/i82371sb.h +++ b/src/devices/machine/i82371sb.h @@ -174,7 +174,8 @@ private: uint8_t m_nmi_enabled; void pc_select_dma_channel(int channel, bool state); - + // VGA-HACK + optional_memory_region m_vga_region; }; extern const device_type I82371SB_ISA; diff --git a/src/devices/machine/i82439tx.cpp b/src/devices/machine/i82439tx.cpp new file mode 100644 index 00000000000..c0e92a230dc --- /dev/null +++ b/src/devices/machine/i82439tx.cpp @@ -0,0 +1,308 @@ +// license:BSD-3-Clause +// copyright-holders:Olivier Galibert +#include "i82439tx.h" + +const device_type I82439TX_NEW = &device_creator; + +DEVICE_ADDRESS_MAP_START(config_map, 32, i82439tx_host_device) + AM_RANGE(0x50, 0x53) AM_READWRITE8(pcon_r, pcon_w, 0x000000ff) + AM_RANGE(0x50, 0x53) AM_READWRITE8(cc_r, cc_w, 0x00ff0000) + AM_RANGE(0x54, 0x57) AM_READWRITE8(dramec_r, dramec_w, 0x00ff0000) + AM_RANGE(0x54, 0x57) AM_READWRITE8(dramc_r, dramc_w, 0xff000000) + AM_RANGE(0x58, 0x5b) AM_READWRITE8(dramt_r, dramt_w, 0x000000ff) + AM_RANGE(0x58, 0x5b) AM_READWRITE8(pam0_r, pam0_w, 0xffffff00) + AM_RANGE(0x5c, 0x5f) AM_READWRITE8(pam3_r, pam3_w, 0xffffffff) + AM_RANGE(0x60, 0x67) AM_READWRITE8(drb_r, drb_w, 0xffffffff) + AM_RANGE(0x68, 0x6b) AM_READWRITE8(drt_r, drt_w, 0x000000ff) + AM_RANGE(0x68, 0x6b) AM_READWRITE8(drat_r, drat_w, 0x0000ff00) + AM_RANGE(0x70, 0x73) AM_READWRITE8(smram_r, smram_w, 0x00ff0000) + AM_RANGE(0x90, 0x93) AM_READWRITE8(errcmd_r, errcmd_w, 0x000000ff) + AM_RANGE(0x90, 0x93) AM_READWRITE8(errsts_r, errsts_w, 0x0000ff00) + AM_RANGE(0x90, 0x93) AM_READ8 (errsyn_r, 0x00ff0000) + + + AM_INHERIT_FROM(pci_host_device::config_map) +ADDRESS_MAP_END + +i82439tx_host_device::i82439tx_host_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) + : pci_host_device(mconfig, I82439TX_NEW, "i82439tx northbridge", tag, owner, clock, "i82439tx", __FILE__) +{ +} + +void i82439tx_host_device::set_cpu_tag(const char *_cpu_tag) +{ + cpu_tag = _cpu_tag; +} + +void i82439tx_host_device::set_ram_size(int _ram_size) +{ + ram_size = _ram_size; +} + +void i82439tx_host_device::device_start() +{ + pci_host_device::device_start(); + cpu = machine().device(cpu_tag); + memory_space = &cpu->space(AS_PROGRAM); + io_space = &cpu->space(AS_IO); + + memory_window_start = 0; + memory_window_end = 0xffffffff; + memory_offset = 0; + io_window_start = 0; + io_window_end = 0xffff; + io_offset = 0; + status = 0x0010; + + ram.resize(ram_size/4); +} + +void i82439tx_host_device::reset_all_mappings() +{ + pci_host_device::reset_all_mappings(); +} + +void i82439tx_host_device::device_reset() +{ + pci_host_device::device_reset(); + + pcon = 0x00; + cc = 0xa2; + dramec = 0x00; + dramc = 0x01; + dramt = 0x00; + memset(pam, 0x00, sizeof(pam)); + memset(drb, 0x02, sizeof(drb)); + drt = 0x00; + drat = 0x00; + smram = 0x02; + errcmd = 0x00; + errsts = 0x00; + errsyn = 0x00; +} + +void i82439tx_host_device::map_extra(uint64_t memory_window_start, uint64_t memory_window_end, uint64_t memory_offset, address_space *memory_space, + uint64_t io_window_start, uint64_t io_window_end, uint64_t io_offset, address_space *io_space) +{ + io_space->install_device(0, 0xffff, *static_cast(this), &pci_host_device::io_configuration_access_map); + + if((dramc & 0xc0) == 0x40) + memory_space->install_ram (0x00000000, 0x0007ffff, &ram[0x00000000/4]); + else + memory_space->install_ram (0x00000000, 0x0009ffff, &ram[0x00000000/4]); + + if(smram & 0x40) + memory_space->install_ram (0x000a0000, 0x000bffff, &ram[0x000a0000/4]); + + if(pam[1] & 0x01) + memory_space->install_rom (0x000c0000, 0x000c3fff, &ram[0x000c0000/4]); + if(pam[1] & 0x02) + memory_space->install_writeonly(0x000c0000, 0x000c3fff, &ram[0x000c0000/4]); + if(pam[1] & 0x10) + memory_space->install_rom (0x000c4000, 0x000c7fff, &ram[0x000c4000/4]); + if(pam[1] & 0x20) + memory_space->install_writeonly(0x000c4000, 0x000c7fff, &ram[0x000c4000/4]); + if(pam[2] & 0x01) + memory_space->install_rom (0x000c8000, 0x000cbfff, &ram[0x000c8000/4]); + if(pam[2] & 0x02) + memory_space->install_writeonly(0x000c8000, 0x000cbfff, &ram[0x000c8000/4]); + if(pam[2] & 0x10) + memory_space->install_rom (0x000cc000, 0x000cffff, &ram[0x000cc000/4]); + if(pam[2] & 0x20) + memory_space->install_writeonly(0x000cc000, 0x000cffff, &ram[0x000cc000/4]); + if(pam[3] & 0x01) + memory_space->install_rom (0x000d0000, 0x000d3fff, &ram[0x000d0000/4]); + if(pam[3] & 0x02) + memory_space->install_writeonly(0x000d0000, 0x000d3fff, &ram[0x000d0000/4]); + if(pam[3] & 0x10) + memory_space->install_rom (0x000d4000, 0x000d7fff, &ram[0x000d4000/4]); + if(pam[3] & 0x20) + memory_space->install_writeonly(0x000d4000, 0x000d7fff, &ram[0x000d4000/4]); + if(pam[4] & 0x01) + memory_space->install_rom (0x000d8000, 0x000dbfff, &ram[0x000d8000/4]); + if(pam[4] & 0x02) + memory_space->install_writeonly(0x000d8000, 0x000dbfff, &ram[0x000d8000/4]); + if(pam[4] & 0x10) + memory_space->install_rom (0x000dc000, 0x000dffff, &ram[0x000dc000/4]); + if(pam[4] & 0x20) + memory_space->install_writeonly(0x000dc000, 0x000dffff, &ram[0x000dc000/4]); + if(pam[5] & 0x01) + memory_space->install_rom (0x000e0000, 0x000e3fff, &ram[0x000e0000/4]); + if(pam[5] & 0x02) + memory_space->install_writeonly(0x000e0000, 0x000e3fff, &ram[0x000e0000/4]); + if(pam[5] & 0x10) + memory_space->install_rom (0x000e4000, 0x000e7fff, &ram[0x000e4000/4]); + if(pam[5] & 0x20) + memory_space->install_writeonly(0x000e4000, 0x000e7fff, &ram[0x000e4000/4]); + if(pam[6] & 0x01) + memory_space->install_rom (0x000e8000, 0x000ebfff, &ram[0x000e8000/4]); + if(pam[6] & 0x02) + memory_space->install_writeonly(0x000e8000, 0x000ebfff, &ram[0x000e8000/4]); + if(pam[6] & 0x10) + memory_space->install_rom (0x000ec000, 0x000effff, &ram[0x000ec000/4]); + if(pam[6] & 0x20) + memory_space->install_writeonly(0x000ec000, 0x000effff, &ram[0x000ec000/4]); + if(pam[0] & 0x10) + memory_space->install_rom (0x000f0000, 0x000fffff, &ram[0x000f0000/4]); + if(pam[0] & 0x20) + memory_space->install_writeonly(0x000f0000, 0x000fffff, &ram[0x000f0000/4]); + + memory_space->install_ram (0x00100000, 0x00efffff, &ram[0x00100000/4]); + if((dramc & 0xc0) != 0x80) + memory_space->install_ram (0x00f00000, 0x00ffffff, &ram[0x00f00000/4]); + + memory_space->install_ram (0x01000000, ram_size-1, &ram[0x01000000/4]); +} + + +READ8_MEMBER (i82439tx_host_device::pcon_r) +{ + return pcon; +} + +WRITE8_MEMBER(i82439tx_host_device::pcon_w) +{ + pcon = data; + logerror("pcon = %02x\n", pcon); +} + +READ8_MEMBER (i82439tx_host_device::cc_r) +{ + return cc; +} + +WRITE8_MEMBER(i82439tx_host_device::cc_w) +{ + cc = data; + logerror("cc = %02x\n", cc); +} + +READ8_MEMBER (i82439tx_host_device::dramec_r) +{ + return dramec; +} + +WRITE8_MEMBER(i82439tx_host_device::dramec_w) +{ + dramec = data; + logerror("dramec = %02x\n", dramec); +} + +READ8_MEMBER (i82439tx_host_device::dramc_r) +{ + return dramc; +} + +WRITE8_MEMBER(i82439tx_host_device::dramc_w) +{ + dramc = data; + logerror("dramc = %02x\n", dramc); + remap_cb(); +} + +READ8_MEMBER (i82439tx_host_device::dramt_r) +{ + return dramt; +} + +WRITE8_MEMBER(i82439tx_host_device::dramt_w) +{ + dramt = data; + logerror("dramt = %02x\n", dramt); +} + +READ8_MEMBER (i82439tx_host_device::pam0_r) +{ + return pam[offset]; +} + +WRITE8_MEMBER(i82439tx_host_device::pam0_w) +{ + pam[offset] = data; + logerror("pam[%d] = %02x\n", offset, pam[offset]); + remap_cb(); +} + +READ8_MEMBER (i82439tx_host_device::pam3_r) +{ + return pam[3+offset]; +} + +WRITE8_MEMBER(i82439tx_host_device::pam3_w) +{ + pam[3+offset] = data; + logerror("pam[%d] = %02x\n", 3+offset, pam[3+offset]); + remap_cb(); +} + +READ8_MEMBER (i82439tx_host_device::drb_r) +{ + return drb[offset]; +} + +WRITE8_MEMBER(i82439tx_host_device::drb_w) +{ + drb[offset] = data; + logerror("drb[%d] = %02x\n", offset, drb[offset]); +} + +READ8_MEMBER (i82439tx_host_device::drt_r) +{ + return drt; +} + +WRITE8_MEMBER(i82439tx_host_device::drt_w) +{ + drt = data; + logerror("drt = %02x\n", drt); +} + +READ8_MEMBER (i82439tx_host_device::drat_r) +{ + return drat; +} + +WRITE8_MEMBER(i82439tx_host_device::drat_w) +{ + drat = data; + logerror("drat = %02x\n", drat); +} + +READ8_MEMBER (i82439tx_host_device::smram_r) +{ + return smram; +} + +WRITE8_MEMBER(i82439tx_host_device::smram_w) +{ + smram = data; + logerror("smram = %02x\n", smram); + remap_cb(); +} + +READ8_MEMBER (i82439tx_host_device::errcmd_r) +{ + return errcmd; +} + +WRITE8_MEMBER(i82439tx_host_device::errcmd_w) +{ + errcmd = data; + logerror("errcmd = %02x\n", errcmd); +} + +READ8_MEMBER (i82439tx_host_device::errsts_r) +{ + return errsts; +} + +WRITE8_MEMBER(i82439tx_host_device::errsts_w) +{ + errsts = data; + logerror("errsts = %02x\n", errsts); +} + +READ8_MEMBER (i82439tx_host_device::errsyn_r) +{ + return errsyn; +} diff --git a/src/devices/machine/i82439tx.h b/src/devices/machine/i82439tx.h new file mode 100644 index 00000000000..8314df49da0 --- /dev/null +++ b/src/devices/machine/i82439tx.h @@ -0,0 +1,74 @@ +// license:BSD-3-Clause +// copyright-holders:Olivier Galibert +// Intel i82439hx northbridge (440hx) + +#ifndef I82439TX_H +#define I82439TX_H + +#include "pci.h" + +#define MCFG_I82439TX_ADD(_tag, _cpu_tag, _ram_size) \ + MCFG_PCI_HOST_ADD(_tag, I82439TX_NEW, 0x80867100, 0x03, 0x00000000) \ + downcast(device)->set_cpu_tag(_cpu_tag); \ + downcast(device)->set_ram_size(_ram_size); + +class i82439tx_host_device : public pci_host_device { +public: + i82439tx_host_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + + void set_cpu_tag(const char *tag); + void set_ram_size(int ram_size); + + DECLARE_READ8_MEMBER (pcon_r); + DECLARE_WRITE8_MEMBER(pcon_w); + DECLARE_READ8_MEMBER (cc_r); + DECLARE_WRITE8_MEMBER(cc_w); + DECLARE_READ8_MEMBER (dramec_r); + DECLARE_WRITE8_MEMBER(dramec_w); + DECLARE_READ8_MEMBER (dramc_r); + DECLARE_WRITE8_MEMBER(dramc_w); + DECLARE_READ8_MEMBER (dramt_r); + DECLARE_WRITE8_MEMBER(dramt_w); + DECLARE_READ8_MEMBER (pam0_r); + DECLARE_WRITE8_MEMBER(pam0_w); + DECLARE_READ8_MEMBER (pam3_r); + DECLARE_WRITE8_MEMBER(pam3_w); + DECLARE_READ8_MEMBER (drb_r); + DECLARE_WRITE8_MEMBER(drb_w); + DECLARE_READ8_MEMBER (drt_r); + DECLARE_WRITE8_MEMBER(drt_w); + DECLARE_READ8_MEMBER (drat_r); + DECLARE_WRITE8_MEMBER(drat_w); + DECLARE_READ8_MEMBER (smram_r); + DECLARE_WRITE8_MEMBER(smram_w); + DECLARE_READ8_MEMBER (errcmd_r); + DECLARE_WRITE8_MEMBER(errcmd_w); + DECLARE_READ8_MEMBER (errsts_r); + DECLARE_WRITE8_MEMBER(errsts_w); + DECLARE_READ8_MEMBER (errsyn_r); + + virtual void reset_all_mappings() override; + + virtual void map_extra(uint64_t memory_window_start, uint64_t memory_window_end, uint64_t memory_offset, address_space *memory_space, + uint64_t io_window_start, uint64_t io_window_end, uint64_t io_offset, address_space *io_space) override; + + virtual DECLARE_ADDRESS_MAP(config_map, 32) override; + +protected: + virtual void device_start() override; + virtual void device_reset() override; + +private: + const char *cpu_tag; + int ram_size; + cpu_device *cpu; + std::vector ram; + + uint8_t pcon, cc, dramec, dramc, dramt; + uint8_t pam[7], drb[8]; + uint8_t drt, drat, smram, errcmd, errsts, errsyn; +}; + +extern const device_type I82439TX_NEW; + +#endif diff --git a/src/mame/drivers/pcipc.cpp b/src/mame/drivers/pcipc.cpp index c635848af95..43bb71615c7 100644 --- a/src/mame/drivers/pcipc.cpp +++ b/src/mame/drivers/pcipc.cpp @@ -22,6 +22,7 @@ #include "machine/pci.h" #include "machine/pci-ide.h" #include "machine/i82439hx.h" +#include "machine/i82439tx.h" #include "machine/i82371sb.h" //#include "machine/fdc37c93x.h" #include "video/mga2064w.h" @@ -34,9 +35,11 @@ public: const char *const message; }; - static const boot_state_info boot_state_infos[]; + static const boot_state_info boot_state_infos_phoenix[]; + static const boot_state_info boot_state_infos_award[]; - DECLARE_WRITE8_MEMBER(boot_state_w); + DECLARE_WRITE8_MEMBER(boot_state_phoenix_w); + DECLARE_WRITE8_MEMBER(boot_state_award_w); pcipc_state(const machine_config &mconfig, device_type type, const char *tag); @@ -58,7 +61,7 @@ void pcipc_state::machine_reset() { } -const pcipc_state::boot_state_info pcipc_state::boot_state_infos[] = { +const pcipc_state::boot_state_info pcipc_state::boot_state_infos_phoenix[] = { { 0x02, "Verify Real Mode." }, { 0x04, "Get CPU type." }, { 0x06, "Initialize system hardware." }, @@ -181,12 +184,92 @@ const pcipc_state::boot_state_info pcipc_state::boot_state_infos[] = { { 0, nullptr } }; -WRITE8_MEMBER(pcipc_state::boot_state_w) +const pcipc_state::boot_state_info pcipc_state::boot_state_infos_award[] = { + {0x01, "Processor test; Processor status verification" }, + {0x02, "Processor test 2; Read/Write and verify all CPU registers" }, + {0x03, "Initialize chips; Disable NMI, PIE, AIE, UEI, SQWV. Disable video, parity checking, DMA. Reset math coprocessor. Clear all page registers and CMOS shutdown. Initialize DMA controller 0 and 1. Initialize interrupt controllers 0 and 1." }, + {0x04, "Test memory refresh toggle" }, + {0x05, "Blank video, initialize keyboard; Keyboard controller initialization" }, + {0x07, "Test CMOS interface and battery" }, + {0x08, "Set up low memory; Early chipset initialization, memory presence test, OEM chipset routines, clear low 64K memory, test first 64K memory" }, + {0x09, "Early cache initialization; Cyrix CPU specific, CPU and cache initialization" }, + {0x0A, "Set up interrupt vector table; Initialize first 120 interrupt vectors" }, + {0x0B, "Test CMOS RAM checksum" }, + {0x0C, "Initialize keyboard; Detect the type of keyboard controller" }, + {0x0D, "Initialize video interface; Detect CPU clock, read CMOS location 14h to find the type of video in use, detect and initialize video adapter" }, + {0x0E, "Test video memory; Write sign-on message to screen, setup shadow RAM" }, + {0x0F, "Test DMA controller 0; BIOS checksum test, keyboard detect and initialization" }, + {0x10, "Test DMA controller 1" }, + {0x11, "Test DMA page registers" }, + //{0x12-13, "Reserved" }, + {0x14, "Test timer counter 2" }, + {0x15, "Test 8259-1 mask bits" }, + {0x16, "Test 8259-2 mask bits" }, + {0x17, "Test stuck 8259 interrupt bits; Test stuck key" }, + {0x18, "Test 8259 interrupt functionality" }, + {0x19, "Test stuck NMI bits (parity I/O check)" }, + {0x1A, "Benchmark; Display CPU clock" }, + //{0x1B-1E, "Reserved" }, + {0x1F, "Set EISA mode; If the EISA memory checksum is good then EISA is initialized. If it's not good then ISA tests and clear EISA mode flag" }, + {0x20, "Enable slot 0; System board" }, + //{0x21-2F, "Enable slots 1-15" }, + {0x30, "Size base and extended memory; Size the base memory from 256K to 640K and the extended memory above 1MB" }, + {0x31, "Test base and extended memory; Test the base memory from 256K to 640K and the extended memory above 1MB using various bit patterns" }, + {0x32, "Test EISA extended memory" }, + //{0x33-3B, "Reserved" }, + {0x3C, "Setup enabled" }, + {0x3D, "Initialize and install mouse if present" }, + {0x3E, "Setup cache controller" }, + {0x40, "Display virus protect disable or enable" }, + {0x41, "Initialize floppy" }, + {0x42, "Initialize hard drive" }, + {0x43, "Detect & Init. serial & parallel ports" }, + {0x44, "Reserved" }, + {0x45, "Detect and Init. math coprocessor" }, + {0x46, "Reserved" }, + {0x47, "Reserved" }, + //{0x48-4D, "Reserved" }, + {0x4E, "Mfg. POST loop, or display messages" }, + {0x4F, "Security password" }, + {0x50, "Write CMOS; Write CMOS back to RAM and clear screen" }, + {0x51, "Pre-boot enable; Enable parity checking, enable NMI, enable cache before boot" }, + {0x52, "Initialize option ROM's; Initialize and ROM's present at locations C800h to EFFFFh" }, + {0x53, "Initialize time value" }, + {0x60, "Setup virus protect" }, + {0x61, "Set boot speed" }, + {0x62, "Setup numlock" }, + {0x63, "Boot attempt" }, + {0xB0, "Spurious" }, + {0xB1, "Unclaimed NMI" }, + {0xBE, "Chipset default initialization; Program chipset registers and power-on BIOS defaults." }, + {0xBF, "Chipset initialization; Reserved" }, + {0xC0, "Turn off chipset cache" }, + {0xC1, "Memory presence test; OEM specific, test the size of on-board memory" }, + {0xC5, "Early shadow; OEM specific, early shadow enable for fast boot" }, + {0xC6, "Cache presence test; External cache-size detection test" }, + //{0xE1-EF, "Setup pages" }, + {0xFF, "Boot loader" }, + { 0, nullptr } +}; + +WRITE8_MEMBER(pcipc_state::boot_state_phoenix_w) { const char *desc = ""; - for(int i=0; boot_state_infos[i].message; i++) - if(boot_state_infos[i].val == data) { - desc = boot_state_infos[i].message; + for(int i=0; boot_state_infos_phoenix[i].message; i++) + if(boot_state_infos_phoenix[i].val == data) { + desc = boot_state_infos_phoenix[i].message; + break; + } + logerror("Boot state %02x - %s\n", data, desc); + +} + +WRITE8_MEMBER(pcipc_state::boot_state_award_w) +{ + const char *desc = ""; + for(int i=0; boot_state_infos_award[i].message; i++) + if(boot_state_infos_award[i].val == data) { + desc = boot_state_infos_award[i].message; break; } logerror("Boot state %02x - %s\n", data, desc); @@ -199,22 +282,47 @@ static MACHINE_CONFIG_START(pcipc, pcipc_state) MCFG_PCI_ROOT_ADD( ":pci") MCFG_I82439HX_ADD( ":pci:00.0", ":maincpu", 256*1024*1024) MCFG_I82371SB_ISA_ADD(":pci:07.0") - MCFG_I82371SB_BOOT_STATE_HOOK(DEVWRITE8(":", pcipc_state, boot_state_w)) + MCFG_I82371SB_BOOT_STATE_HOOK(DEVWRITE8(":", pcipc_state, boot_state_phoenix_w)) +// MCFG_IDE_PCI_ADD( ":pci:07.1", 0x80867010, 0x03, 0x00000000) + MCFG_MGA2064W_ADD( ":pci:12.0") +MACHINE_CONFIG_END + +static MACHINE_CONFIG_START(pcipctx, pcipc_state) + MCFG_CPU_ADD("maincpu", PENTIUM, 60000000) + + MCFG_PCI_ROOT_ADD( ":pci") + MCFG_I82439TX_ADD( ":pci:00.0", ":maincpu", 256*1024*1024) + MCFG_I82371SB_ISA_ADD(":pci:07.0") + MCFG_I82371SB_BOOT_STATE_HOOK(DEVWRITE8(":", pcipc_state, boot_state_award_w)) // MCFG_IDE_PCI_ADD( ":pci:07.1", 0x80867010, 0x03, 0x00000000) MCFG_MGA2064W_ADD( ":pci:12.0") MACHINE_CONFIG_END ROM_START(pcipc) ROM_REGION32_LE(0x40000, ":pci:07.0", 0) /* PC bios */ - ROM_SYSTEM_BIOS(0, "n7ns04", "Version 21/01/98, without integrated sound") \ - ROMX_LOAD("m7ns04.rom", 0x00000, 0x40000, CRC(9c1f656b) SHA1(f4a0a522d8c47b6ddb6c01fe9a34ddf5b1977f8d), ROM_BIOS(1) ) \ - ROM_SYSTEM_BIOS(1, "n7s04", "Version 21/01/98, with integrated sound") \ - ROMX_LOAD("m7s04.rom", 0x00000, 0x40000, CRC(3689f5a9) SHA1(8daacdb0dc6783d2161680564ffe83ac2515f7ef), ROM_BIOS(2) ) \ - ROM_SYSTEM_BIOS(2, "crisis", "Version 07/01/98, for flash recovery") \ - ROMX_LOAD("crisis.rom", 0x00000, 0x40000, CRC(38a1458a) SHA1(8881ac336392cca79a772b4168f63efc31f953dd), ROM_BIOS(3) ) \ + ROM_SYSTEM_BIOS(0, "n7ns04", "Version 21/01/98, without integrated sound") + ROMX_LOAD("m7ns04.rom", 0x00000, 0x40000, CRC(9c1f656b) SHA1(f4a0a522d8c47b6ddb6c01fe9a34ddf5b1977f8d), ROM_BIOS(1) ) + ROM_SYSTEM_BIOS(1, "n7s04", "Version 21/01/98, with integrated sound") + ROMX_LOAD("m7s04.rom", 0x00000, 0x40000, CRC(3689f5a9) SHA1(8daacdb0dc6783d2161680564ffe83ac2515f7ef), ROM_BIOS(2) ) + ROM_SYSTEM_BIOS(2, "crisis", "Version 07/01/98, for flash recovery") + ROMX_LOAD("crisis.rom", 0x00000, 0x40000, CRC(38a1458a) SHA1(8881ac336392cca79a772b4168f63efc31f953dd), ROM_BIOS(3) ) + ROM_SYSTEM_BIOS(3, "5hx29", "5hx29") \ + ROMX_LOAD("5hx29.bin", 0x20000, 0x20000, CRC(07719a55) SHA1(b63993fd5186cdb4f28c117428a507cd069e1f68), ROM_BIOS(4) ) + ROM_REGION(0x8000,"ibm_vga", 0) + ROM_LOAD("ibm-vga.bin", 0x00000, 0x8000, BAD_DUMP CRC(74e3fadb) SHA1(dce6491424f1726203776dfae9a967a98a4ba7b5) ) +ROM_END + +ROM_START(pcipctx) + ROM_REGION32_LE(0x40000, ":pci:07.0", 0) /* PC bios */ + ROM_SYSTEM_BIOS(0, "ga586t2", "Gigabyte GA-586T2") // ITE 8679 I/O + ROMX_LOAD("gb_ga586t2.bin", 0x20000, 0x20000, CRC(3a50a6e1) SHA1(dea859b4f1492d0d08aacd260ed1e83e00ebac08), ROM_BIOS(1)) + + ROM_REGION(0x8000,"ibm_vga", 0) + ROM_LOAD("ibm-vga.bin", 0x00000, 0x8000, BAD_DUMP CRC(74e3fadb) SHA1(dce6491424f1726203776dfae9a967a98a4ba7b5) ) ROM_END static INPUT_PORTS_START(pcipc) INPUT_PORTS_END -COMP(1998, pcipc, 0, 0, pcipc, pcipc, driver_device, 0, "Hack Inc.", "Sandbox PCI PC", MACHINE_NO_SOUND) +COMP(1998, pcipc, 0, 0, pcipc, pcipc, driver_device, 0, "Hack Inc.", "Sandbox PCI PC (440HX)", MACHINE_NO_SOUND) +COMP(1998, pcipctx, 0, 0, pcipctx, pcipc, driver_device, 0, "Hack Inc.", "Sandbox PCI PC (440TX)", MACHINE_NO_SOUND) diff --git a/src/mame/mame.lst b/src/mame/mame.lst index 5c1b1909aa3..7e5035615be 100644 --- a/src/mame/mame.lst +++ b/src/mame/mame.lst @@ -29647,6 +29647,7 @@ pcfxga // PC-FX NEC 199? (PC-FX on a PC ISA Card) @source:pcipc.cpp pcipc // +pcipctx // @source:pcktgal.cpp pcktgal // (c) 1987 Data East Corporation (Japan)