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m68000: New implementation, generated from the micro/nanocode

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This commit is contained in:
Olivier Galibert 2022-12-14 22:03:56 +01:00
parent b733fd4b43
commit 74971c2f53
64 changed files with 1371528 additions and 555 deletions
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14
scripts/src/cpu.lua
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@ -1933,6 +1933,18 @@ if CPUS["M680X0"] then
MAME_DIR .. "src/devices/cpu/m68000/m68kcommon.cpp",
MAME_DIR .. "src/devices/cpu/m68000/m68000.h",
MAME_DIR .. "src/devices/cpu/m68000/m68000.cpp",
MAME_DIR .. "src/devices/cpu/m68000/m68000.lst",
MAME_DIR .. "src/devices/cpu/m68000/m68000gen.py",
MAME_DIR .. "src/devices/cpu/m68000/m68000-decode.cpp",
MAME_DIR .. "src/devices/cpu/m68000/m68000-head.h",
MAME_DIR .. "src/devices/cpu/m68000/m68000-sdf.cpp",
MAME_DIR .. "src/devices/cpu/m68000/m68000-sif.cpp",
MAME_DIR .. "src/devices/cpu/m68000/m68000-sdp.cpp",
MAME_DIR .. "src/devices/cpu/m68000/m68000-sip.cpp",
MAME_DIR .. "src/devices/cpu/m68000/m68000-sdfm.cpp",
MAME_DIR .. "src/devices/cpu/m68000/m68000-sifm.cpp",
MAME_DIR .. "src/devices/cpu/m68000/m68000-sdpm.cpp",
MAME_DIR .. "src/devices/cpu/m68000/m68000-sipm.cpp",
MAME_DIR .. "src/devices/cpu/m68000/m68008.h",
MAME_DIR .. "src/devices/cpu/m68000/m68008.cpp",
MAME_DIR .. "src/devices/cpu/m68000/m68010.h",
@ -1943,8 +1955,6 @@ if CPUS["M680X0"] then
MAME_DIR .. "src/devices/cpu/m68000/m68030.cpp",
MAME_DIR .. "src/devices/cpu/m68000/m68040.h",
MAME_DIR .. "src/devices/cpu/m68000/m68040.cpp",
MAME_DIR .. "src/devices/cpu/m68000/scc68070.h",
MAME_DIR .. "src/devices/cpu/m68000/scc68070.cpp",
MAME_DIR .. "src/devices/cpu/m68000/fscpu32.h",
MAME_DIR .. "src/devices/cpu/m68000/fscpu32.cpp",
MAME_DIR .. "src/devices/cpu/m68000/mcf5206e.h",

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src/devices/cpu/m68000/m68000-decode.cpp Normal file
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src/devices/cpu/m68000/m68000-sdf.cpp Normal file
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src/devices/cpu/m68000/m68000-sdfm.cpp Normal file
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src/devices/cpu/m68000/m68000.cpp
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@ -1,5 +1,5 @@
// license:BSD-3-Clause
// copyright-holders:Karl Stenerud
// copyright-holders:Olivier Galibert
#include "emu.h"
#include "m68000.h"
@ -12,24 +12,404 @@ std::unique_ptr<util::disasm_interface> m68000_device::create_disassembler()
return std::make_unique<m68k_disassembler>(m68k_disassembler::TYPE_68000);
}
m68000_device::m68000_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
: m68000_device(mconfig, M68000, tag, owner, clock)
m68000_device::m68000_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) : m68000_device(mconfig, M68000, tag, owner, clock)
{
}
m68000_device::m68000_device(const machine_config &mconfig, const device_type type, const char *tag, device_t *owner, u32 clock)
: m68000_musashi_device(mconfig, tag, owner, clock, type, 16,24)
m68000_device::m68000_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock)
: m68000_base_device(mconfig, type, tag, owner, clock),
m_cmpild_instr_callback(*this),
m_rte_instr_callback(*this),
m_tas_write_callback(*this),
m_program_config("program", ENDIANNESS_BIG, 16, 24),
m_opcodes_config("opcodes", ENDIANNESS_BIG, 16, 24),
m_uprogram_config("uprogram", ENDIANNESS_BIG, 16, 24),
m_uopcodes_config("uopcodes", ENDIANNESS_BIG, 16, 24),
m_cpu_space_config("cpu_space", ENDIANNESS_BIG, 16, 24, 0, address_map_constructor(FUNC(m68000_device::default_autovectors_map), this))
{
m_mmu = nullptr;
}
void m68000_device::abort_access(u32 reason)
{
m_post_run = reason;
m_post_run_cycles = m_icount;
m_icount = 0;
}
void m68000_device::do_post_run()
{
m_icount = m_post_run_cycles;
m_post_run_cycles = 0;
switch(m_post_run) {
case PR_BERR:
m_inst_state = S_BUS_ERROR;
m_inst_substate = 0;
m_icount -= 10;
break;
}
m_post_run = 0;
}
void m68000_device::trigger_bus_error()
{
abort_access(PR_BERR);
}
void m68000_device::berr_w(u16)
{
trigger_bus_error();
}
u16 m68000_device::berr_r()
{
if(!machine().side_effects_disabled())
trigger_bus_error();
return 0;
}
bool m68000_device::supervisor_mode() const noexcept
{
return m_sr & SR_S;
}
u16 m68000_device::get_fc() const noexcept
{
return (m_base_ssw | (m_sr & SR_S ? SSW_S : 0)) & 7;
}
void m68000_device::execute_run()
{
m_icount -= m_count_before_instruction_step;
if(m_icount < 0) {
m_count_before_instruction_step = -m_icount;
m_icount = 0;
} else
m_count_before_instruction_step = 0;
for(;;) {
if(m_icount > 0 && m_inst_substate)
(this->*(m_handlers_p[m_inst_state]))();
while(m_icount > 0) {
if(m_inst_state >= S_first_instruction) {
m_ipc = m_pc - 2;
m_irdi = m_ird;
if(machine().debug_flags & DEBUG_FLAG_ENABLED)
debugger_instruction_hook(m_ipc);
}
(this->*(m_handlers_f[m_inst_state]))();
}
if(m_post_run)
do_post_run();
else
break;
}
if(m_icount < 0) {
m_count_before_instruction_step = -m_icount;
m_icount = 0;
}
}
device_memory_interface::space_config_vector m68000_device::memory_space_config() const
{
device_memory_interface::space_config_vector scv;
scv.push_back(std::make_pair(AS_PROGRAM, &m_program_config));
if(has_configured_map(AS_OPCODES))
scv.push_back(std::make_pair(AS_OPCODES, &m_opcodes_config));
if(has_configured_map(AS_USER_PROGRAM))
scv.push_back(std::make_pair(AS_USER_PROGRAM, &m_uprogram_config));
if(has_configured_map(AS_USER_OPCODES))
scv.push_back(std::make_pair(AS_USER_OPCODES, &m_opcodes_config));
if(m_cpu_space_id == AS_CPU_SPACE)
scv.push_back(std::make_pair(AS_CPU_SPACE, &m_cpu_space_config));
return scv;
}
void m68000_device::default_autovectors_map(address_map &map)
{
if(m_cpu_space_id == AS_CPU_SPACE && !has_configured_map(AS_CPU_SPACE)) {
offs_t mask = make_bitmask<offs_t>(24);
map(mask - 0xf, mask).m(*this, FUNC(m68000_device::autovectors_map));
}
}
void m68000_device::device_start()
{
m68000_musashi_device::device_start();
init_cpu_m68000();
init_decode_table();
m_reset_cb.resolve_safe();
m_cmpild_instr_callback.resolve();
m_rte_instr_callback.resolve();
m_tas_write_callback.resolve();
m_s_program = &space(AS_PROGRAM);
m_s_opcodes = has_space(AS_OPCODES) ? &space(AS_OPCODES) : m_s_program;
m_s_uprogram = has_space(AS_USER_PROGRAM) ? &space(AS_USER_PROGRAM) : m_s_program;
m_s_uopcodes = has_space(AS_USER_OPCODES) ? &space(AS_USER_OPCODES) : has_space(AS_USER_PROGRAM) ? m_s_uprogram : m_s_opcodes;
m_s_cpu_space = &space(m_cpu_space_id);
m_s_program->specific(m_r_program);
m_s_opcodes->specific(m_r_opcodes);
m_s_uprogram->specific(m_r_uprogram);
m_s_uopcodes->specific(m_r_uopcodes);
m_s_cpu_space->specific(m_cpu_space);
if(m_mmu) {
m_handlers_f = s_handlers_if;
m_handlers_p = s_handlers_ip;
} else {
m_handlers_f = s_handlers_df;
m_handlers_p = s_handlers_dp;
}
save_item(NAME(m_da));
save_item(NAME(m_ipc));
save_item(NAME(m_pc));
save_item(NAME(m_au));
save_item(NAME(m_at));
save_item(NAME(m_aob));
save_item(NAME(m_sp));
save_item(NAME(m_dt));
save_item(NAME(m_int_vector));
save_item(NAME(m_isr));
save_item(NAME(m_sr));
save_item(NAME(m_dbin));
save_item(NAME(m_dbout));
save_item(NAME(m_edb));
save_item(NAME(m_irc));
save_item(NAME(m_ir));
save_item(NAME(m_ird));
save_item(NAME(m_irdi));
save_item(NAME(m_ftu));
save_item(NAME(m_aluo));
save_item(NAME(m_alue));
save_item(NAME(m_dcr));
save_item(NAME(m_movems));
save_item(NAME(m_movemr));
save_item(NAME(m_virq_state));
save_item(NAME(m_nmi_pending));
save_item(NAME(m_int_level));
save_item(NAME(m_int_next_state));
save_item(NAME(m_next_state));
save_item(NAME(m_inst_state));
save_item(NAME(m_inst_substate));
save_item(NAME(m_count_before_instruction_step));
save_item(NAME(m_bcount));
save_item(NAME(m_t));
save_item(NAME(m_post_run));
save_item(NAME(m_post_run_cycles));
memset(m_da, 0, sizeof(m_da));
m_ipc = 0;
m_pc = 0;
m_au = 0;
m_at = 0;
m_aob = 0;
m_sp = 0;
m_dt = 0;
m_isr = 0;
m_sr = 0;
m_dbin = 0;
m_dbout = 0;
m_edb = 0;
m_irc = 0;
m_ir = 0;
m_ird = 0;
m_irdi = 0;
m_ftu = 0;
m_aluo = 0;
m_alue = 0;
m_dcr = 0;
m_movemr = 0;
m_movems = 0;
m_virq_state = 0;
m_nmi_pending = 0;
m_int_level = 0;
m_int_next_state = 0;
m_next_state = 0;
m_inst_state = 0;
m_inst_substate = 0;
m_count_before_instruction_step = 0;
m_bcount = 0;
m_t = 0;
state_add(STATE_GENPCBASE, "PC", m_ipc).callimport();
state_add(STATE_GENPC, "rPC", m_pc);
state_add(STATE_GENFLAGS, "GENFLAGS", m_sr).noshow().callexport().formatstr("%16s");
state_add(M68K_SR, "SR", m_sr).callimport();
for(int r = 0; r != 8; r++)
state_add(M68K_D0 + r, string_format("D%d", r).c_str(), m_da[r]);
for(int r = 0; r != 7; r++)
state_add(M68K_A0 + r, string_format("A%d", r).c_str(), m_da[r+8]);
state_add(M68K_USP, "USP", m_da[15]);
state_add(M68K_SP, "SP", m_da[16]);
set_icountptr(m_icount);
}
m68000_device::m68000_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock,
const device_type type, u32 prg_data_width, u32 prg_address_bits, address_map_constructor internal_map)
: m68000_musashi_device(mconfig, tag, owner, clock, type, prg_data_width, prg_address_bits, internal_map)
void m68000_device::state_import(const device_state_entry &entry)
{
switch(entry.index()) {
case STATE_GENPCBASE: {
m_pc = m_ipc+2;
m_au = m_ipc+4;
auto dis = machine().disable_side_effects();
m_ir = m_ird = m_opcodes.read_word(m_ipc);
m_irc = m_dbin = m_opcodes.read_word(m_pc);
set_ftu_const();
m_inst_state = m_decode_table[m_ird];
m_inst_substate = 0;
break;
}
case M68K_SR:
m_sr &= (SR_SR|SR_CCR);
break;
}
}
void m68000_device::state_string_export(const device_state_entry &entry, std::string &str) const
{
switch(entry.index()) {
case STATE_GENFLAGS:
str = util::string_format("%c%c%d %c%c%c%c%c",
m_sr & SR_T ? 'T' : '.',
m_sr & SR_S ? 'S' : '.',
(m_sr & SR_I) >> 8,
m_sr & SR_X ? 'X' : '.',
m_sr & SR_N ? 'N' : '.',
m_sr & SR_Z ? 'Z' : '.',
m_sr & SR_V ? 'V' : '.',
m_sr & SR_C ? 'C' : '.');
break;
}
}
void m68000_device::device_reset()
{
m_inst_state = S_RESET;
m_inst_substate = 0;
m_count_before_instruction_step = 0;
m_post_run = 0;
m_post_run_cycles = 0;
update_user_super();
}
void m68000_device::update_user_super()
{
if(m_sr & 0x2000) {
m_sp = 16;
m_program = m_r_program;
m_opcodes = m_r_opcodes;
if(m_mmu)
m_mmu->set_super(true);
} else {
m_sp = 15;
m_program = m_r_uprogram;
m_opcodes = m_r_uopcodes;
if(m_mmu)
m_mmu->set_super(false);
}
}
void m68000_device::execute_set_input(int inputnum, int state)
{
if(inputnum == INPUT_LINE_NMI)
inputnum = 7;
if(inputnum > (m_interrupt_mixer ? 7 : 3))
return;
u32 old_level = m_int_level;
u32 vstate = m_virq_state;
u32 blevel;
if(state == ASSERT_LINE)
vstate |= 1 << inputnum;
else
vstate &= ~(1 << inputnum);
m_virq_state = vstate;
if(m_interrupt_mixer) {
for(blevel = 7; blevel > 0; blevel--)
if(vstate & (1 << blevel))
break;
} else
blevel = vstate;
m_int_level = blevel;
/* A transition from < 7 to 7 always interrupts (NMI) */
/* Note: Level 7 can also level trigger like a normal IRQ */
// FIXME: This may cause unintended level 7 interrupts if one or two IPL lines are asserted
// immediately before others are cleared. The actual 68000 imposes an input hold time.
if(old_level != 7 && m_int_level == 7)
m_nmi_pending = true;
update_interrupt();
}
void m68000_device::update_interrupt()
{
if(m_nmi_pending)
m_int_next_state = (7 << 24) | S_INTERRUPT;
else if(m_int_level > ((m_sr >> 8) & 7))
m_int_next_state = (m_int_level << 24) | S_INTERRUPT;
else
m_int_next_state = 0;
}
void m68000_device::init_decode_table()
{
m_decode_table.resize(0x10000, S_ILLEGAL);
for(int i=0; s_packed_decode_table[i].mask; i++) {
u16 value = s_packed_decode_table[i].value;
u16 mask = s_packed_decode_table[i].mask;
u16 state = s_packed_decode_table[i].state;
u16 cvalue = 0;
do {
// logerror("%04x/%04x %04x %4d\n", value, mask, cvalue, state);
if(m_decode_table[value | cvalue] == S_ILLEGAL)
m_decode_table[value | cvalue] = state;
else if(((value | cvalue) & 0xf0ff) != 0x6000)
logerror("Collision on %04x (%d / %d)\n", value | cvalue, state, m_decode_table[value | cvalue]);
cvalue = ((cvalue | mask) + 1) & ~mask;
} while(cvalue);
}
}
void m68000_device::set_ftu_const()
{
switch(m_ird >> 12) {
case 0x4: m_ftu = 0x80; break;
case 0x5: case 0xe: m_ftu = (m_ird >> 9) & 7; if(!m_ftu) m_ftu = 8; break;
case 0x6: case 0x7: m_ftu = s8(m_ird); break;
case 0x8: case 0xc: m_ftu = 0xf; break;
default: m_ftu = 0; break;
}
}
void m68000_device::start_interrupt_vector_lookup()
{
// flag for berr -> spurious
int level = m_next_state >> 24;
standard_irq_callback(level);
// Clear the nmi flag
if(level == 7) {
m_nmi_pending = false;
update_interrupt();
}
}
void m68000_device::end_interrupt_vector_lookup()
{
m_int_vector = (m_edb & 0xff) << 2;
m_int_next_state = 0;
}

910
src/devices/cpu/m68000/m68000.h
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@ -1,32 +1,922 @@
// license:BSD-3-Clause
// copyright-holders:Karl Stenerud
// copyright-holders:Olivier Galibert
#ifndef MAME_CPU_M68000_M68000_H
#define MAME_CPU_M68000_M68000_H
#pragma once
#include "m68kmusashi.h"
#include "m68kcommon.h"
class m68000_device : public m68000_musashi_device
class m68000_device : public m68000_base_device
{
public:
// construction/destruction
struct mmu {
virtual u16 read_program(offs_t addr, u16 mem_mask) = 0;
virtual void write_program(offs_t addr, u16 data, u16 mem_mask) = 0;
virtual u16 read_data(offs_t addr, u16 mem_mask) = 0;
virtual void write_data(offs_t addr, u16 data, u16 mem_mask) = 0;
virtual u16 read_cpu(offs_t addr, u16 mem_mask) = 0;
virtual void set_super(bool super) = 0;
};
m68000_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
// Device user interface
void trigger_bus_error();
void berr_w(u16);
u16 berr_r();
virtual bool supervisor_mode() const noexcept override;
virtual u16 get_fc() const noexcept override;
// Infrastructure interfaces
virtual std::unique_ptr<util::disasm_interface> create_disassembler() override;
virtual u32 execute_min_cycles() const noexcept override { return 4; }
virtual u32 execute_min_cycles() const noexcept override { return 1; }
virtual u32 execute_max_cycles() const noexcept override { return 158; }
// device-level overrides
virtual void execute_run() override;
virtual void execute_set_input(int inputnum, int state) override;
virtual void state_import(const device_state_entry &entry) override;
virtual void state_string_export(const device_state_entry &entry, std::string &str) const override;
virtual space_config_vector memory_space_config() const override;
virtual void device_start() override;
virtual void device_reset() override;
void set_current_mmu(mmu *m);
template <typename... T> void set_tas_write_callback(T &&... args) { m_tas_write_callback.set(std::forward<T>(args)...); }
template <typename... T> void set_cmpild_callback(T &&... args) { m_cmpild_instr_callback.set(std::forward<T>(args)...); }
template <typename... T> void set_rte_callback(T &&... args) { m_rte_instr_callback.set(std::forward<T>(args)...); }
protected:
m68000_device(const machine_config &mconfig, const device_type type, const char *tag, device_t *owner, u32 clock);
// Processor special states
// Must match the states array in m68000gen.py
enum {
S_RESET = 0,
S_BUS_ERROR,
S_ADDRESS_ERROR,
S_DOUBLE_FAULT,
S_INTERRUPT,
S_TRACE,
S_ILLEGAL,
S_PRIVILEDGE,
S_LINEA,
S_LINEF,
S_first_instruction = S_ILLEGAL
};
m68000_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock,
const device_type type, u32 prg_data_width, u32 prg_address_bits, address_map_constructor internal_map);
// SR flags
enum {
SR_C = 0x0001,
SR_V = 0x0002,
SR_Z = 0x0004,
SR_N = 0x0008,
SR_X = 0x0010,
SR_I = 0x0700,
SR_S = 0x2000,
SR_T = 0x8000,
SR_CCR = SR_C|SR_V|SR_Z|SR_N|SR_X,
SR_SR = SR_I|SR_S|SR_T,
};
// SSW contents
enum {
SSW_DATA = 0x01,
SSW_PROGRAM = 0x02,
SSW_CPU = 0x03,
SSW_S = 0x04,
SSW_N = 0x08,
SSW_R = 0x10,
SSW_CRITICAL = 0x20 // Not really part of SSW, go to double fault if that access fails
};
// Post-run actions
enum {
PR_NONE = 0,
PR_BERR = 1
};
// Decode table
struct decode_entry {
u16 value;
u16 mask;
u16 state;
};
static const decode_entry s_packed_decode_table[];
std::vector<u16> m_decode_table;
// Opcode handlers (d = direct, i = indirect, f = full, p = partial)
using handler = void (m68000_device::*)();
#include "m68000-head.h"
static const handler s_handlers_df[];
static const handler s_handlers_if[];
static const handler s_handlers_dp[];
static const handler s_handlers_ip[];
static const handler s_handlers_dfm[];
static const handler s_handlers_ifm[];
static const handler s_handlers_dpm[];
static const handler s_handlers_ipm[];
const handler *m_handlers_f;
const handler *m_handlers_p;
// Callbacks to host
write32sm_delegate m_cmpild_instr_callback; /* Called when a CMPI.L #v, Dn instruction is encountered */
write_line_delegate m_rte_instr_callback; /* Called when a RTE instruction is encountered */
write8sm_delegate m_tas_write_callback; /* Called instead of normal write by the TAS instruction,
allowing writeback to be disabled globally or selectively
or other side effects to be implemented */
// Address spaces and configurations for program/opcode super/user and cpu space
address_space_config m_program_config, m_opcodes_config, m_uprogram_config, m_uopcodes_config, m_cpu_space_config;
address_space *m_s_program, *m_s_opcodes, *m_s_uprogram, *m_s_uopcodes, *m_s_cpu_space;
// Fixed specifics
memory_access<24, 1, 0, ENDIANNESS_BIG>::specific m_r_program, m_r_opcodes, m_r_uprogram, m_r_uopcodes, m_cpu_space;
// Dynamic specifics, depending on supervisor state
memory_access<24, 1, 0, ENDIANNESS_BIG>::specific m_program, m_opcodes;
// MMU, if one present
mmu *m_mmu;
// Internal processor state, in inverse size order
u32 m_da[17]; // 8 data, 7 address, usp, ssp in that order
u32 m_ipc, m_pc, m_au, m_at, m_aob, m_dt, m_int_vector;
u32 m_sp; // 15 or 16, index of currently active sp
int m_icount, m_bcount, m_count_before_instruction_step, m_t;
u32 m_movems;
u16 m_isr, m_sr, m_dbin, m_dbout, m_edb;
u16 m_irc, m_ir, m_ird, m_ftu, m_aluo, m_alue, m_alub, m_movemr, m_irdi;
u16 m_base_ssw, m_ssw;
u8 m_dcr;
/* IRQ lines state */
u32 m_virq_state;
u32 m_nmi_pending;
u32 m_int_level;
u32 m_int_next_state;
// Current instruction state and substate
u16 m_inst_state;
u16 m_inst_substate;
u32 m_next_state;
u32 m_post_run;
int m_post_run_cycles;
// Typed constructor
m68000_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock);
// Create the decode table
void init_decode_table();
// Trigger an interruption
void abort_access(u32 reason);
// Wrap up an interruption
void do_post_run();
// cpu space map with autovectors
void default_autovectors_map(address_map &map);
// helper for interrupt vector access
void start_interrupt_vector_lookup();
void end_interrupt_vector_lookup();
// update needed stuff on priviledge level switch
void update_user_super();
// update needed stuff on interrupt level switch
void update_interrupt();
// dispatch instruction
inline void do_exec_full();
inline void do_exec_partial();
// movem step
inline int countr_zero(u16 v) {
// We will be c++20 someday
for(int i=0; i != 16; i++)
if(v & (1<<i))
return i;
return 16;
}
inline void step_movem() {
int r = countr_zero(m_movemr);
if(r > 15)
r = 0;
m_movems = map_sp(r);
m_movemr &= ~(1 << r);
}
void step_movem_predec() {
int r = countr_zero(m_movemr);
if(r > 15)
r = 0;
m_movems = map_sp(r ^ 0xf);
m_movemr &= ~(1 << r);
}
// helpers
static u32 merge_16_32(u16 h, u16 l) { return (h << 16) | l; }
static u16 high16(u32 v) { return v >> 16; }
static u32 ext32(u16 v) { return s32(s16(v)); }
static u16 ext32h(u16 v) { return v & 0x8000 ? 0xffff : 0x0000; }
static void set_16h(u32 &r, u16 v) { r = (r & 0x0000ffff) | (v << 16); }
static void set_16l(u32 &r, u16 v) { r = (r & 0xffff0000) | v; }
static void set_16l(u16 &r, u16 v) { r = v; }
static void set_8(u32 &r, u8 v) { r = (r & 0xffffff00) | v; }
static void set_8(u16 &r, u8 v) { r = (r & 0xff00) | v; }
static void set_8h(u16 &r, u8 v) { r = (r & 0x00ff) | (v << 8); }
static void set_8xl(u16 &r, u16 v) { r = (v & 0x00ff) | (v << 8); }
static void set_8xh(u16 &r, u16 v) { r = (v & 0xff00) | (v >> 8); }
inline int map_sp(int r) { return r == 15 ? m_sp : r; }
void set_ftu_const();
inline void alu_add(u16 a, u16 b) {
u32 r = b + a;
m_isr = 0;
if(!(r & 0xffff))
m_isr |= SR_Z;
if(r & 0x8000)
m_isr |= SR_N;
if(r & 0x10000)
m_isr |= SR_X|SR_C;
if(((b&a&~r) | ((~b)&(~a)&r)) & 0x8000)
m_isr |= SR_V;
m_aluo = r;
}
inline void alu_add8(u8 a, u8 b) {
u16 r = b + a;
m_isr = 0;
if(!(r & 0xff))
m_isr |= SR_Z;
if(r & 0x80)
m_isr |= SR_N;
if(r & 0x100)
m_isr |= SR_X|SR_C;
if(((b&a&~r) | ((~b)&(~a)&r)) & 0x80)
m_isr |= SR_V;
m_aluo = r;
}
inline void alu_addc(u16 a, u16 b) {
u32 r = b + a + ((m_isr & SR_C) ? 1 : 0);
m_isr = 0;
if(!(r & 0xffff))
m_isr |= SR_Z;
if(r & 0x8000)
m_isr |= SR_N;
if(r & 0x10000)
m_isr |= SR_X|SR_C;
if(((b&a&~r) | ((~b)&(~a)&r)) & 0x8000)
m_isr |= SR_V;
m_aluo = r;
}
inline void alu_addx(u16 a, u16 b) {
u32 r = b + a + ((m_sr & SR_X) ? 1 : 0);
m_isr = 0;
if(!(r & 0xffff))
m_isr |= SR_Z;
if(r & 0x8000)
m_isr |= SR_N;
if(r & 0x10000)
m_isr |= SR_X|SR_C;
if(((b&a&~r) | ((~b)&(~a)&r)) & 0x8000)
m_isr |= SR_V;
m_aluo = r;
}
inline void alu_addx8(u8 a, u8 b) {
u16 r = b + a + ((m_sr & SR_X) ? 1 : 0);
m_isr = 0;
if(!(r & 0xff))
m_isr |= SR_Z;
if(r & 0x80)
m_isr |= SR_N;
if(r & 0x100)
m_isr |= SR_X|SR_C;
if(((b&a&~r) | ((~b)&(~a)&r)) & 0x80)
m_isr |= SR_V;
m_aluo = r;
}
inline void alu_and(u16 a, u16 b) {
u16 r = b & a;
m_isr = m_sr & SR_X;
if(!r)
m_isr |= SR_Z;
if(r & 0x8000)
m_isr |= SR_N;
m_aluo = r;
}
inline void alu_andx(u16 a, u16 b) {
u16 r = b & a;
m_isr = m_sr & SR_X ? SR_X|SR_C : 0;
if(!r)
m_isr |= SR_Z;
if(r & 0x8000)
m_isr |= SR_N;
m_aluo = r;
}
inline void alu_and8(u16 a, u16 b) {
u16 r = b & a;
m_isr = m_sr & SR_X;
if(!(r & 0xff))
m_isr |= SR_Z;
if(r & 0x80)
m_isr |= SR_N;
m_aluo = r;
}
inline void alu_and8x(u8 a, u8 b) {
u8 r = b & a;
m_isr = m_sr & SR_X ? SR_X|SR_C : 0;
if(!r)
m_isr |= SR_Z;
if(r & 0x80)
m_isr |= SR_N;
m_aluo = r;
}
inline void alu_or(u16 a, u16 b) {
u16 r = b | a;
m_isr = m_sr & SR_X;
if(!r)
m_isr |= SR_Z;
if(r & 0x8000)
m_isr |= SR_N;
m_aluo = r;
}
inline void alu_or8(u8 a, u8 b) {
u8 r = b | a;
m_isr = m_sr & SR_X;
if(!r)
m_isr |= SR_Z;
if(r & 0x80)
m_isr |= SR_N;
m_aluo = r;
}
inline void alu_eor(u16 a, u16 b) {
u16 r = b ^ a;
m_isr = m_sr & SR_X;
if(!r)
m_isr |= SR_Z;
if(r & 0x8000)
m_isr |= SR_N;
m_aluo = r;
}
inline void alu_eor8(u8 a, u8 b) {
u8 r = b ^ a;
m_isr = m_sr & SR_X;
if(!r)
m_isr |= SR_Z;
if(r & 0x80)
m_isr |= SR_N;
m_aluo = r;
}
inline void alu_ext(u16 a) {
u16 r = s8(a);
m_isr = 0;
if(!r)
m_isr |= SR_Z;
if(r & 0x8000)
m_isr |= SR_N;
m_aluo = r;
}
inline void alu_not(u16 a) {
u16 r = ~a;
m_isr = 0;
if(!r)
m_isr |= SR_Z;
if(r & 0x8000)
m_isr |= SR_N;
m_aluo = r;
}
inline void alu_not8(u8 a) {
u8 r = ~a;
m_isr = 0;
if(!r)
m_isr |= SR_Z;
if(r & 0x80)
m_isr |= SR_N;
m_aluo = r;
}
inline void alu_sub(u16 a, u16 b) {
u32 r = b - a;
m_isr = 0;
if(!(r & 0xffff))
m_isr |= SR_Z;
if(r & 0x8000)
m_isr |= SR_N;
if(r & 0x10000)
m_isr |= SR_X|SR_C;
if(((b&(~a)&~r) | ((~b)&a&r)) & 0x8000)
m_isr |= SR_V;
m_aluo = r;
}
inline void alu_sub8(u8 a, u8 b) {
u16 r = b - a;
m_isr = 0;
if(!(r & 0xff))
m_isr |= SR_Z;
if(r & 0x80)
m_isr |= SR_N;
if(r & 0x100)
m_isr |= SR_X|SR_C;
if(((b&(~a)&~r) | ((~b)&a&r)) & 0x80)
m_isr |= SR_V;
m_aluo = r;
}
inline void alu_subc(u16 a, u16 b) {
u32 r = b - a - ((m_isr & SR_C) ? 1 : 0);
m_isr = 0;
if(!(r & 0xffff))
m_isr |= SR_Z;
if(r & 0x8000)
m_isr |= SR_N;
if(r & 0x10000)
m_isr |= SR_X|SR_C;
if(((b&(~a)&~r) | ((~b)&a&r)) & 0x8000)
m_isr |= SR_V;
m_aluo = r;
}
inline void alu_subx(u16 a, u16 b) {
u32 r = b - a - ((m_sr & SR_X) ? 1 : 0);
m_isr = 0;
if(!(r & 0xffff))
m_isr |= SR_Z;
if(r & 0x8000)
m_isr |= SR_N;
if(r & 0x10000)
m_isr |= SR_X|SR_C;
if(((b&(~a)&~r) | ((~b)&a&r)) & 0x8000)
m_isr |= SR_V;
m_aluo = r;
}
inline void alu_subx8(u8 a, u8 b) {
u16 r = b - a - ((m_sr & SR_X) ? 1 : 0);
m_isr = 0;
if(!(r & 0xff))
m_isr |= SR_Z;
if(r & 0x80)
m_isr |= SR_N;
if(r & 0x100)
m_isr |= SR_X|SR_C;
if(((b&(~a)&~r) | ((~b)&a&r)) & 0x80)
m_isr |= SR_V;
m_aluo = r;
}
inline void alu_abcd8(u8 a, u8 b) {
u8 hr = (b & 0xf) + (a & 0xf) + ((m_sr & SR_X) ? 1 : 0);
bool lcor = hr > 9;
u16 r1 = b + a + ((m_sr & SR_X) ? 1 : 0);
u16 r = r1 + (lcor ? 6 : 0);
if(r > 0x9f)
r += 0x60;
m_isr = 0;
if(!(r & 0xff))
m_isr |= SR_Z;
if(r & 0x80)
m_isr |= SR_N;
if(r & 0x300)
m_isr |= SR_X|SR_C;
if((r & 0x80) && !(r1 & 0x80))
m_isr |= SR_V;
m_aluo = r;
}
inline void alu_sbcd8(u8 a, u8 b) {
u8 hr = (b & 0xf) - (a & 0xf) - ((m_sr & SR_X) ? 1 : 0);
bool lcor = hr & 0x10;
u16 r1 = b - a - ((m_sr & SR_X) ? 1 : 0);
u16 r = r1 - (lcor ? 6 : 0);
if(r1 & 0x100)
r -= 0x60;
m_isr = 0;
if(!(r & 0xff))
m_isr |= SR_Z;
if(r & 0x80)
m_isr |= SR_N;
if(r & 0x300)
m_isr |= SR_X|SR_C;
if(!(r & 0x80) && (r1 & 0x80))
m_isr |= SR_V;
m_aluo = r;
}
inline void alu_sla0(u16 a) {
u32 r = (a << 17) | (m_alue << 1) | 0;
m_isr = m_sr & SR_X;
if(!r)
m_isr |= SR_Z;
if(r & 0x80000000)
m_isr |= SR_N;
if(a & 0x8000)
m_isr |= SR_C;
m_alue = r;
m_aluo = r >> 16;
}
inline void alu_sla1(u16 a) {
u32 r = (a << 17) | (m_alue << 1) | 1;
m_isr = m_sr & SR_X;
if(!r)
m_isr |= SR_Z;
if(r & 0x80000000)
m_isr |= SR_N;
if(a & 0x8000)
m_isr |= SR_C;
m_alue = r;
m_aluo = r >> 16;
}
inline void alu_over() {
m_isr = SR_V|SR_N;
}
inline void alu_asl(u16 a) {
u16 r = a << 1;
m_isr = m_sr & SR_V;
if(!r)
m_isr |= SR_Z;
if(r & 0x8000)
m_isr |= SR_N;
if(a & 0x8000)
m_isr |= SR_X|SR_C;
if((r^a) & 0x8000)
m_isr |= SR_V;
m_aluo = r;
}
inline void alu_asl8(u8 a) {
u8 r = a << 1;
m_isr = m_sr & SR_V;
if(!r)
m_isr |= SR_Z;
if(r & 0x80)
m_isr |= SR_N;
if(a & 0x80)
m_isr |= SR_X|SR_C;
if((r^a) & 0x80)
m_isr |= SR_V;
m_aluo = r;
}
inline void alu_asl32(u16 a) {
u32 r = (m_alue << 17) | (a << 1);
m_isr = m_sr & SR_V;
if(!r)
m_isr |= SR_Z;
if(r & 0x80000000)
m_isr |= SR_N;
if(m_alue & 0x8000)
m_isr |= SR_X|SR_C;
if(((r >> 16)^m_alue) & 0x8000)
m_isr |= SR_V;
m_aluo = r;
m_alue = r >> 16;
}
inline void alu_asr(u16 a) {
u16 r = a >> 1;
m_isr = 0;
if(!r)
m_isr |= SR_Z;
if(a & 0x8000) {
r |= 0x8000;
m_isr |= SR_N;
}
if(a & 0x0001)
m_isr |= SR_X|SR_C;
m_aluo = r;
}
inline void alu_asr8(u8 a) {
u8 r = a >> 1;
m_isr = 0;
if(!r)
m_isr |= SR_Z;
if(a & 0x80) {
r |= 0x80;
m_isr |= SR_N;
}
if(a & 0x01)
m_isr |= SR_X|SR_C;
m_aluo = r;
}
inline void alu_asr32(u16 a) {
u32 r = (m_alue << 15) | (a >> 1);
m_isr = 0;
if(!r)
m_isr |= SR_Z;
if(m_alue & 0x8000) {
r |= 0x80000000;
m_isr |= SR_N;
}
if(a & 0x0001)
m_isr |= SR_X|SR_C;
m_aluo = r;
m_alue = r >> 16;
}
inline void alu_lsl(u16 a) {
u16 r = a << 1;
m_isr = 0;
if(!r)
m_isr |= SR_Z;
if(r & 0x8000)
m_isr |= SR_N;
if(a & 0x8000)
m_isr |= SR_X|SR_C;
m_aluo = r;
}
inline void alu_lsl8(u8 a) {
u8 r = a << 1;
m_isr = 0;
if(!r)
m_isr |= SR_Z;
if(r & 0x80)
m_isr |= SR_N;
if(a & 0x80)
m_isr |= SR_X|SR_C;
m_aluo = r;
}
inline void alu_lsl32(u16 a) {
u32 r = (m_alue << 17) | (a << 1);
m_isr = 0;
if(!r)
m_isr |= SR_Z;
if(r & 0x80000000)
m_isr |= SR_N;
if(m_alue & 0x8000)
m_isr |= SR_X|SR_C;
m_aluo = r;
m_alue = r >> 16;
}
inline void alu_lsr(u16 a) {
u16 r = a >> 1;
m_isr = 0;
if(!r)
m_isr |= SR_Z;
if(a & 0x0001)
m_isr |= SR_X|SR_C;
m_aluo = r;
}
inline void alu_lsr8(u8 a) {
u8 r = a >> 1;
m_isr = 0;
if(!r)
m_isr |= SR_Z;
if(a & 0x01)
m_isr |= SR_X|SR_C;
m_aluo = r;
}
inline void alu_lsr32(u16 a) {
u32 r = (m_alue << 15) | (a >> 1);
m_isr = 0;
if(!r)
m_isr |= SR_Z;
if(a & 0x0001)
m_isr |= SR_X|SR_C;
m_aluo = r;
m_alue = r >> 16;
}
inline void alu_rol(u16 a) {
u16 r = a << 1;
m_isr = 0;
if(a & 0x8000) {
m_isr |= SR_X|SR_C;
r |= 0x0001;
}
if(r & 0x8000)
m_isr |= SR_N;
if(!r)
m_isr |= SR_Z;
m_aluo = r;
}
inline void alu_rol8(u8 a) {
u8 r = a << 1;
m_isr = 0;
if(a & 0x80) {
m_isr |= SR_X|SR_C;
r |= 0x01;
}
if(r & 0x80)
m_isr |= SR_N;
if(!r)
m_isr |= SR_Z;
m_aluo = r;
}
inline void alu_rol32(u16 a) {
u32 r = (m_alue << 17) | (a << 1);
m_isr = 0;
if(m_alue & 0x8000) {
m_isr |= SR_X|SR_C;
r |= 0x00000001;
}
if(r & 0x80000000)
m_isr |= SR_N;
if(!r)
m_isr |= SR_Z;
m_aluo = r;
m_alue = r >> 16;
}
inline void alu_ror(u16 a) {
u16 r = a >> 1;
m_isr = 0;
if(a & 0x0001) {
m_isr |= SR_X|SR_C|SR_N;
r |= 0x8000;
}
if(!r)
m_isr |= SR_Z;
m_aluo = r;
}
inline void alu_ror8(u8 a) {
u8 r = a >> 1;
m_isr = 0;
if(a & 0x01) {
m_isr |= SR_X|SR_C|SR_N;
r |= 0x80;
}
if(!r)
m_isr |= SR_Z;
m_aluo = r;
}
inline void alu_ror32(u16 a) {
u32 r = (m_alue << 15) | (a >> 1);
m_isr = 0;
if(a & 0x0001) {
m_isr |= SR_X|SR_C|SR_N;
r |= 0x80000000;
}
if(!r)
m_isr |= SR_Z;
m_aluo = r;
m_alue = r >> 16;
}
inline void alu_roxl(u16 a) {
u16 r = (a << 1) | ((m_sr & SR_X) ? 1 : 0);
m_isr = 0;
if(a & 0x8000)
m_isr |= SR_X|SR_C;
if(r & 0x8000)
m_isr |= SR_N;
if(!r)
m_isr |= SR_Z;
m_aluo = r;
}
inline void alu_roxl8(u8 a) {
u8 r = (a << 1) | ((m_sr & SR_X) ? 1 : 0);
m_isr = 0;
if(a & 0x80)
m_isr |= SR_X|SR_C;
if(r & 0x80)
m_isr |= SR_N;
if(!r)
m_isr |= SR_Z;
m_aluo = r;
}
inline void alu_roxl32(u16 a) {
u32 r = (m_alue << 17) | (a << 1) | ((m_sr & SR_X) ? 1 : 0);
m_isr = 0;
if(m_alue & 0x8000)
m_isr |= SR_X|SR_C;
if(r & 0x80000000)
m_isr |= SR_N;
if(!r)
m_isr |= SR_Z;
m_aluo = r;
m_alue = r >> 16;
}
inline void alu_roxr(u16 a) {
u16 r = (a >> 1) | ((m_sr & SR_X) ? 0x8000 : 0);
m_isr = 0;
if(a & 0x0001)
m_isr |= SR_X|SR_C;
if(r & 0x8000)
m_isr |= SR_N;
if(!r)
m_isr |= SR_Z;
m_aluo = r;
}
inline void alu_roxr8(u8 a) {
u8 r = (a >> 1) | ((m_sr & SR_X) ? 0x80 : 0);
m_isr = 0;
if(a & 0x01)
m_isr |= SR_X|SR_C;
if(r & 0x80)
m_isr |= SR_N;
if(!r)
m_isr |= SR_Z;
m_aluo = r;
}
inline void alu_roxr32(u32 a) {
u32 r = (m_alue << 15) | (a >> 1) | ((m_sr & SR_X) ? 0x80000000 : 0);
m_isr = 0;
if(a & 0x0001)
m_isr |= SR_X|SR_C;
if(r & 0x80000000)
m_isr |= SR_N;
if(!r)
m_isr |= SR_Z;
m_aluo = r;
m_alue = r >> 16;
}
inline void alu_roxr32ms(u16 a) {
u32 r = (a << 15) | (m_alue >> 1) | (((m_isr & (SR_N|SR_V)) == SR_N || (m_isr & (SR_N|SR_V)) == SR_V) ? 0x80000000 : 0);
m_isr = 0;
if(a & 0x0001)
m_isr |= SR_X;
if(r & 0x80000000)
m_isr |= SR_N;
if(!(r & 0xffff0000))
m_isr |= SR_Z;
m_aluo = r >> 16;
m_alue = r;
}
inline void alu_roxr32mu(u16 a) {
u32 r = (a << 15) | (m_alue >> 1) | ((m_isr & SR_C) ? 0x80000000 : 0);
m_isr = 0;
if(a & 0x0001)
m_isr |= SR_X;
if(r & 0x80000000)
m_isr |= SR_N;
if(!(r & 0xffff0000))
m_isr |= SR_Z;
m_aluo = r >> 16;
m_alue = r;
}
inline void sr_z() {
m_sr = (m_sr & ~SR_Z) | (m_isr & SR_Z);
}
inline void sr_nz_u() {
m_sr = (m_sr & ~SR_N & (m_isr | ~SR_Z)) | (m_isr & SR_N);
}
inline void sr_nzvc() {
m_sr = (m_sr & ~(SR_N|SR_Z|SR_V|SR_C)) | (m_isr & (SR_N|SR_Z|SR_V|SR_C));
}
inline void sr_nzvc_u() {
m_sr = (m_sr & ~(SR_N|SR_V|SR_C) & (m_isr | ~SR_Z)) | (m_isr & (SR_N|SR_V|SR_C));
}
inline void sr_xnzvc() {
m_sr = (m_sr & ~(SR_X|SR_N|SR_Z|SR_V|SR_C)) | (m_isr & (SR_X|SR_N|SR_Z|SR_V|SR_C));
}
inline void sr_xnzvc_u() {
m_sr = (m_sr & ~(SR_X|SR_N|SR_V|SR_C) & (m_isr | ~SR_Z)) | (m_isr & (SR_X|SR_N|SR_V|SR_C));
}
};
DECLARE_DEVICE_TYPE(M68000, m68000_device)

1528
src/devices/cpu/m68000/m68000.lst Normal file
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File diff suppressed because it is too large Load Diff

2416
src/devices/cpu/m68000/m68000gen.py Executable file
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File diff suppressed because it is too large Load Diff

20
src/devices/cpu/m68000/m68k_in.lst
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@ -2797,9 +2797,6 @@ b1c0 f1c0 cmpa l A+-DXWLdxI 01:6 7:7 234fc:4
u32 dst = DY();
u32 res = dst - src;
if (!m_cmpild_instr_callback.isnull())
(m_cmpild_instr_callback)(m_ir & 7, src);
m_n_flag = NFLAG_32(res);
m_not_z_flag = MASK_OUT_ABOVE_32(res);
m_v_flag = VFLAG_SUB_32(src, dst, res);
@ -6242,7 +6239,6 @@ f548 ffd8 ptest l . 4:8p
4e70 ffff reset . . 071234fc:0p
if(m_s_flag) {
m_reset_cb(1);
m68k_reset_peripherals();
m_icount -= m_cyc_reset;
m_reset_cb(0);
} else {
@ -6855,8 +6851,6 @@ e5c0 ffc0 roxl w A+-DXWL 01:8 7:14 234fc:5
u32 new_sr;
u32 new_pc;
if (!m_rte_instr_callback.isnull())
(m_rte_instr_callback)(1);
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
new_sr = m68ki_pull_16();
@ -6877,8 +6871,6 @@ e5c0 ffc0 roxl w A+-DXWL 01:8 7:14 234fc:5
u32 new_pc;
u32 format_word;
if (!m_rte_instr_callback.isnull())
(m_rte_instr_callback)(1);
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
format_word = m68ki_read_16(REG_A()[7]+6) >> 12;
@ -6932,8 +6924,6 @@ e5c0 ffc0 roxl w A+-DXWL 01:8 7:14 234fc:5
u32 new_pc;
u32 format_word;
if (!m_rte_instr_callback.isnull())
(m_rte_instr_callback)(1);
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
rte_loop:
@ -7804,15 +7794,7 @@ e5c0 ffc0 roxl w A+-DXWL 01:8 7:14 234fc:5
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
/* On the 68000 and 68010, the TAS instruction uses a unique bus cycle that may have
side effects (e.g. delaying DMA) or may fail to write back at all depending on the
bus implementation.
In particular, the Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS
to fail to write back in order to function properly. */
if (CPU_TYPE_IS_010_LESS() && !m_tas_write_callback.isnull())
(m_tas_write_callback)(ea, dst | 0x80);
else
m68ki_write_8(ea, dst | 0x80);
m68ki_write_8(ea, dst | 0x80);
4e40 fff0 trap . . 071234fc:4

12
src/devices/cpu/m68000/m68kcommon.h
View File

@ -42,7 +42,9 @@ class m68000_base_device : public cpu_device
{
public:
enum {
AS_CPU_SPACE = 4
AS_CPU_SPACE = 4,
AS_USER_PROGRAM = 5,
AS_USER_OPCODES = 6,
};
static constexpr u8 autovector(int level) { return 0x18 + level; }
@ -51,27 +53,23 @@ public:
void set_cpu_space(int space_id) { m_cpu_space_id = space_id; }
void disable_interrupt_mixer() { m_interrupt_mixer = false; }
auto reset_cb() { return m_reset_cb.bind(); }
template <typename... T> void set_tas_write_callback(T &&... args) { m_tas_write_callback.set(std::forward<T>(args)...); }
virtual u32 execute_input_lines() const noexcept override { return m_interrupt_mixer ? 8 : 3; } // number of input lines
virtual bool execute_input_edge_triggered(int inputnum) const noexcept override { return m_interrupt_mixer ? inputnum == M68K_IRQ_7 : false; }
virtual bool supervisor_mode() const noexcept = 0;
virtual u16 get_fc() const noexcept = 0;
protected:
bool m_interrupt_mixer = true; /* Indicates whether to put a virtual 8->3 priority mixer on the input lines */
int m_cpu_space_id = AS_CPU_SPACE; /* CPU space address space id */
devcb_write_line m_reset_cb;
write8sm_delegate m_tas_write_callback; /* Called instead of normal write8 by the TAS instruction,
allowing writeback to be disabled globally or selectively
or other side effects to be implemented */
m68000_base_device(const machine_config &mconfig, const device_type type, const char *tag, device_t *owner, u32 clock) :
cpu_device(mconfig, type, tag, owner, clock),
m_interrupt_mixer(true),
m_cpu_space_id(AS_CPU_SPACE),
m_reset_cb(*this),
m_tas_write_callback(*this)
m_reset_cb(*this)
{ }
};

13
src/devices/cpu/m68000/m68kcpu.cpp
View File

@ -1692,7 +1692,7 @@ void m68000_musashi_device::set_buserror_details(u32 fault_addr, u8 rw, u8 fc, b
m_mmu_tmp_buserror_sz = m_mmu_tmp_sz;
}
u16 m68000_musashi_device::get_fc()
u16 m68000_musashi_device::get_fc() const noexcept
{
return m_mmu_tmp_fc;
}
@ -2262,9 +2262,7 @@ m68000_musashi_device::m68000_musashi_device(const machine_config &mconfig, cons
: m68000_base_device(mconfig, type, tag, owner, clock),
m_program_config("program", ENDIANNESS_BIG, prg_data_width, prg_address_bits, 0, internal_map),
m_oprogram_config("decrypted_opcodes", ENDIANNESS_BIG, prg_data_width, prg_address_bits, 0, internal_map),
m_cpu_space_config("cpu_space", ENDIANNESS_BIG, prg_data_width, prg_address_bits, 0, address_map_constructor(FUNC(m68000_musashi_device::default_autovectors_map), this)),
m_cmpild_instr_callback(*this),
m_rte_instr_callback(*this)
m_cpu_space_config("cpu_space", ENDIANNESS_BIG, prg_data_width, prg_address_bits, 0, address_map_constructor(FUNC(m68000_musashi_device::default_autovectors_map), this))
{
clear_all();
}
@ -2275,9 +2273,7 @@ m68000_musashi_device::m68000_musashi_device(const machine_config &mconfig, cons
: m68000_base_device(mconfig, type, tag, owner, clock),
m_program_config("program", ENDIANNESS_BIG, prg_data_width, prg_address_bits),
m_oprogram_config("decrypted_opcodes", ENDIANNESS_BIG, prg_data_width, prg_address_bits),
m_cpu_space_config("cpu_space", ENDIANNESS_BIG, prg_data_width, prg_address_bits, 0, address_map_constructor(FUNC(m68000_musashi_device::default_autovectors_map), this)),
m_cmpild_instr_callback(*this),
m_rte_instr_callback(*this)
m_cpu_space_config("cpu_space", ENDIANNESS_BIG, prg_data_width, prg_address_bits, 0, address_map_constructor(FUNC(m68000_musashi_device::default_autovectors_map), this))
{
clear_all();
}
@ -2403,9 +2399,6 @@ void m68000_musashi_device::clear_all()
void m68000_musashi_device::device_start()
{
m_reset_cb.resolve_safe();
m_cmpild_instr_callback.resolve();
m_rte_instr_callback.resolve();
m_tas_write_callback.resolve();
}
void m68000_musashi_device::device_stop()

2
src/devices/cpu/m68000/m68kfpu.cpp
View File

@ -2,7 +2,7 @@
// copyright-holders:Karl Stenerud
#include "emu.h"
#include "m68000.h"
#include "m68kmusashi.h"
static constexpr int FPCC_N = 0x08000000;
static constexpr int FPCC_Z = 0x04000000;

2
src/devices/cpu/m68000/m68kmake.py
View File

@ -254,7 +254,7 @@ class Info:
f.write("// Generated source, edits will be lost. Run m68kmake.py instead\n")
f.write("\n")
f.write("#include \"emu.h\"\n")
f.write("#include \"m68000.h\"\n")
f.write("#include \"m68kmusashi.h\"\n")
f.write("\n")
for h in self.opcode_handlers:
f.write('void m68000_musashi_device::%s()\n{\n%s}\n' % (h.function_name, h.body))

10
src/devices/cpu/m68000/m68kmusashi.h
View File

@ -123,9 +123,7 @@ protected:
void define_state(void);
public:
template <typename... T> void set_cmpild_callback(T &&... args) { m_cmpild_instr_callback.set(std::forward<T>(args)...); }
template <typename... T> void set_rte_callback(T &&... args) { m_rte_instr_callback.set(std::forward<T>(args)...); }
u16 get_fc();
virtual u16 get_fc() const noexcept override;
void set_hmmu_enable(int enable);
void set_emmu_enable(int enable);
int get_pmmu_enable() const {return m_pmmu_enabled;}
@ -212,10 +210,6 @@ protected:
const u8* m_cyc_instruction;
const u8* m_cyc_exception;
/* Callbacks to host */
write32sm_delegate m_cmpild_instr_callback; /* Called when a CMPI.L #v, Dn instruction is encountered */
write_line_delegate m_rte_instr_callback; /* Called when a RTE instruction is encountered */
address_space *m_program, *m_oprogram, *m_cpu_space;
memory_access<24, 0, 0, ENDIANNESS_BIG>::cache m_oprogram8;
@ -333,8 +327,6 @@ protected:
#include "m68kops.h"
#include "m68kmmu.h"
virtual void m68k_reset_peripherals() { }
static double fx80_to_double(floatx80 fx)
{
u64 d;

102
src/devices/cpu/m68000/m68kops.cpp
View File

@ -1,7 +1,7 @@
// Generated source, edits will be lost. Run m68kmake.py instead
#include "emu.h"
#include "m68000.h"
#include "m68kmusashi.h"
void m68000_musashi_device::xa000_1010_071234fc()
{
@ -11401,9 +11401,6 @@ void m68000_musashi_device::x0c80_cmpi_l_071234fc()
u32 dst = DY();
u32 res = dst - src;
if (!m_cmpild_instr_callback.isnull())
(m_cmpild_instr_callback)(m_ir & 7, src);
m_n_flag = NFLAG_32(res);
m_not_z_flag = MASK_OUT_ABOVE_32(res);
m_v_flag = VFLAG_SUB_32(src, dst, res);
@ -25452,7 +25449,6 @@ void m68000_musashi_device::x4e70_reset_071234fc()
{
if(m_s_flag) {
m_reset_cb(1);
m68k_reset_peripherals();
m_icount -= m_cyc_reset;
m_reset_cb(0);
} else {
@ -26509,8 +26505,6 @@ void m68000_musashi_device::x4e73_rte_l_0()
u32 new_sr;
u32 new_pc;
if (!m_rte_instr_callback.isnull())
(m_rte_instr_callback)(1);
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
new_sr = m68ki_pull_16();
@ -26533,8 +26527,6 @@ void m68000_musashi_device::x4e73_rte_l_71()
u32 new_pc;
u32 format_word;
if (!m_rte_instr_callback.isnull())
(m_rte_instr_callback)(1);
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
format_word = m68ki_read_16(REG_A()[7]+6) >> 12;
@ -26590,8 +26582,6 @@ void m68000_musashi_device::x4e73_rte_l_234fc()
u32 new_pc;
u32 format_word;
if (!m_rte_instr_callback.isnull())
(m_rte_instr_callback)(1);
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
rte_loop:
@ -30166,15 +30156,7 @@ void m68000_musashi_device::x4ad0_tas_b_ai_071234fc()
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
/* On the 68000 and 68010, the TAS instruction uses a unique bus cycle that may have
side effects (e.g. delaying DMA) or may fail to write back at all depending on the
bus implementation.
In particular, the Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS
to fail to write back in order to function properly. */
if (CPU_TYPE_IS_010_LESS() && !m_tas_write_callback.isnull())
(m_tas_write_callback)(ea, dst | 0x80);
else
m68ki_write_8(ea, dst | 0x80);
m68ki_write_8(ea, dst | 0x80);
}
@ -30188,15 +30170,7 @@ void m68000_musashi_device::x4ad8_tas_b_pi_071234fc()
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
/* On the 68000 and 68010, the TAS instruction uses a unique bus cycle that may have
side effects (e.g. delaying DMA) or may fail to write back at all depending on the
bus implementation.
In particular, the Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS
to fail to write back in order to function properly. */
if (CPU_TYPE_IS_010_LESS() && !m_tas_write_callback.isnull())
(m_tas_write_callback)(ea, dst | 0x80);
else
m68ki_write_8(ea, dst | 0x80);
m68ki_write_8(ea, dst | 0x80);
}
@ -30210,15 +30184,7 @@ void m68000_musashi_device::x4adf_tas_b_pi7_071234fc()
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
/* On the 68000 and 68010, the TAS instruction uses a unique bus cycle that may have
side effects (e.g. delaying DMA) or may fail to write back at all depending on the
bus implementation.
In particular, the Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS
to fail to write back in order to function properly. */
if (CPU_TYPE_IS_010_LESS() && !m_tas_write_callback.isnull())
(m_tas_write_callback)(ea, dst | 0x80);
else
m68ki_write_8(ea, dst | 0x80);
m68ki_write_8(ea, dst | 0x80);
}
@ -30232,15 +30198,7 @@ void m68000_musashi_device::x4ae0_tas_b_pd_071234fc()
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
/* On the 68000 and 68010, the TAS instruction uses a unique bus cycle that may have
side effects (e.g. delaying DMA) or may fail to write back at all depending on the
bus implementation.
In particular, the Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS
to fail to write back in order to function properly. */
if (CPU_TYPE_IS_010_LESS() && !m_tas_write_callback.isnull())
(m_tas_write_callback)(ea, dst | 0x80);
else
m68ki_write_8(ea, dst | 0x80);
m68ki_write_8(ea, dst | 0x80);
}
@ -30254,15 +30212,7 @@ void m68000_musashi_device::x4ae7_tas_b_pd7_071234fc()
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
/* On the 68000 and 68010, the TAS instruction uses a unique bus cycle that may have
side effects (e.g. delaying DMA) or may fail to write back at all depending on the
bus implementation.
In particular, the Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS
to fail to write back in order to function properly. */
if (CPU_TYPE_IS_010_LESS() && !m_tas_write_callback.isnull())
(m_tas_write_callback)(ea, dst | 0x80);
else
m68ki_write_8(ea, dst | 0x80);
m68ki_write_8(ea, dst | 0x80);
}
@ -30276,15 +30226,7 @@ void m68000_musashi_device::x4ae8_tas_b_di_071234fc()
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
/* On the 68000 and 68010, the TAS instruction uses a unique bus cycle that may have
side effects (e.g. delaying DMA) or may fail to write back at all depending on the
bus implementation.
In particular, the Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS
to fail to write back in order to function properly. */
if (CPU_TYPE_IS_010_LESS() && !m_tas_write_callback.isnull())
(m_tas_write_callback)(ea, dst | 0x80);
else
m68ki_write_8(ea, dst | 0x80);
m68ki_write_8(ea, dst | 0x80);
}
@ -30298,15 +30240,7 @@ void m68000_musashi_device::x4af0_tas_b_ix_071234fc()
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
/* On the 68000 and 68010, the TAS instruction uses a unique bus cycle that may have
side effects (e.g. delaying DMA) or may fail to write back at all depending on the
bus implementation.
In particular, the Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS
to fail to write back in order to function properly. */
if (CPU_TYPE_IS_010_LESS() && !m_tas_write_callback.isnull())
(m_tas_write_callback)(ea, dst | 0x80);
else
m68ki_write_8(ea, dst | 0x80);
m68ki_write_8(ea, dst | 0x80);
}
@ -30320,15 +30254,7 @@ void m68000_musashi_device::x4af8_tas_b_aw_071234fc()
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
/* On the 68000 and 68010, the TAS instruction uses a unique bus cycle that may have
side effects (e.g. delaying DMA) or may fail to write back at all depending on the
bus implementation.
In particular, the Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS
to fail to write back in order to function properly. */
if (CPU_TYPE_IS_010_LESS() && !m_tas_write_callback.isnull())
(m_tas_write_callback)(ea, dst | 0x80);
else
m68ki_write_8(ea, dst | 0x80);
m68ki_write_8(ea, dst | 0x80);
}
@ -30342,15 +30268,7 @@ void m68000_musashi_device::x4af9_tas_b_al_071234fc()
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
/* On the 68000 and 68010, the TAS instruction uses a unique bus cycle that may have
side effects (e.g. delaying DMA) or may fail to write back at all depending on the
bus implementation.
In particular, the Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS
to fail to write back in order to function properly. */
if (CPU_TYPE_IS_010_LESS() && !m_tas_write_callback.isnull())
(m_tas_write_callback)(ea, dst | 0x80);
else
m68ki_write_8(ea, dst | 0x80);
m68ki_write_8(ea, dst | 0x80);
}

24
src/devices/cpu/m68000/scc68070.cpp
View File

@ -1,24 +0,0 @@
// license:BSD-3-Clause
// copyright-holders:Karl Stenerud
#include "emu.h"
#include "scc68070.h"
#include "m68kdasm.h"
std::unique_ptr<util::disasm_interface> scc68070_base_device::create_disassembler()
{
return std::make_unique<m68k_disassembler>(m68k_disassembler::TYPE_68000);
}
scc68070_base_device::scc68070_base_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock,
const device_type type, address_map_constructor internal_map)
: m68000_musashi_device(mconfig, tag, owner, clock, type, 16,32, internal_map)
{
}
void scc68070_base_device::device_start()
{
m68000_musashi_device::device_start();
init_cpu_scc68070();
}

26
src/devices/cpu/m68000/scc68070.h
View File

@ -1,26 +0,0 @@
// license:BSD-3-Clause
// copyright-holders:Karl Stenerud
#ifndef MAME_CPU_M68000_SCC68070_H
#define MAME_CPU_M68000_SCC68070_H
#pragma once
#include "m68kmusashi.h"
class scc68070_base_device : public m68000_musashi_device
{
protected:
virtual std::unique_ptr<util::disasm_interface> create_disassembler() override;
virtual u32 execute_min_cycles() const noexcept override { return 4; }
virtual u32 execute_max_cycles() const noexcept override { return 158; }
// device-level overrides
virtual void device_start() override;
scc68070_base_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock,
const device_type type, address_map_constructor internal_map);
};
#endif

55
src/devices/machine/68307.cpp
View File

@ -57,7 +57,7 @@ void m68307_cpu_device::device_add_mconfig(machine_config &config)
m68307_cpu_device::m68307_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
m68000_device(mconfig, tag, owner, clock, M68307, 16, 24, address_map_constructor(FUNC(m68307_cpu_device::internal_map), this)),
m68000_device(mconfig, M68307, tag, owner, clock),
m_write_irq(*this),
m_write_a_tx(*this),
m_write_b_tx(*this),
@ -79,6 +79,11 @@ m68307_cpu_device::m68307_cpu_device(const machine_config &mconfig, const char *
m_ipl = 0;
m_cpu_space_config.m_internal_map = address_map_constructor(FUNC(m68307_cpu_device::cpu_space_map), this);
auto imap = address_map_constructor(FUNC(m68307_cpu_device::internal_map), this);
m_program_config.m_internal_map = imap;
m_opcodes_config.m_internal_map = imap;
m_uprogram_config.m_internal_map = imap;
m_uopcodes_config.m_internal_map = imap;
}
@ -101,7 +106,7 @@ void m68307_cpu_device::device_reset()
set_ipl(0);
}
void m68307_cpu_device::m68k_reset_peripherals()
WRITE_LINE_MEMBER(m68307_cpu_device::reset_peripherals)
{
m_duart->reset();
@ -127,23 +132,6 @@ inline int m68307_cpu_device::calc_cs(offs_t address) const
return 0;
}
void m68307_cpu_device::init16_m68307(address_space &space)
{
m_space = &space;
space.cache(m_oprogram16);
space.specific(m_program16);
m_readimm16 = [this](offs_t address) -> u16 { /* m_m68307_currentcs = calc_cs(address); */ return m_oprogram16.read_word(address); };
m_read8 = [this](offs_t address) -> u8 { /* m_m68307_currentcs = calc_cs(address); */ return m_program16.read_byte(address); };
m_read16 = [this](offs_t address) -> u16 { /* m_m68307_currentcs = calc_cs(address); */ return m_program16.read_word(address); };
m_read32 = [this](offs_t address) -> u32 { /* m_m68307_currentcs = calc_cs(address); */ return m_program16.read_dword(address); };
m_write8 = [this](offs_t address, u8 data) { /* m_m68307_currentcs = calc_cs(address); */ m_program16.write_byte(address, data); };
m_write16 = [this](offs_t address, u16 data) { /* m_m68307_currentcs = calc_cs(address); */ m_program16.write_word(address, data); };
m_write32 = [this](offs_t address, u32 data) { /* m_m68307_currentcs = calc_cs(address); */ m_program16.write_dword(address, data); };
}
void m68307_cpu_device::set_port_callbacks(
porta_read_delegate &&porta_r,
porta_write_delegate &&porta_w,
@ -242,14 +230,14 @@ uint8_t m68307_cpu_device::int_ack(offs_t offset)
void m68307_cpu_device::device_start()
{
init_cpu_m68000();
reset_cb().append(FUNC(m68307_cpu_device::reset_peripherals));
m68000_device::device_start();
/* basic CS logic, timers, mbus, serial logic
set via remappable register
*/
init16_m68307(*m_program);
m_m68307SIM = new m68307_sim();
m_m68307MBUS = new m68307_mbus();
m_m68307TIMER = new m68307_timer();
@ -260,7 +248,6 @@ void m68307_cpu_device::device_start()
m_m68307MBUS->reset();
m_m68307TIMER->reset();
m_internal = &space(AS_PROGRAM);
m_m68307_base = 0xbfff;
m_m68307_scrhigh = 0x0007;
m_m68307_scrlow = 0xf010;
@ -281,7 +268,7 @@ void m68307_cpu_device::device_start()
uint16_t m68307_cpu_device::m68307_internal_base_r(offs_t offset, uint16_t mem_mask)
{
logerror("%08x m68307_internal_base_r %08x, (%04x)\n", m_ppc, offset*2,mem_mask);
logerror("%08x m68307_internal_base_r %08x, (%04x)\n", m_ipc, offset*2,mem_mask);
switch (offset<<1)
{
@ -297,7 +284,9 @@ uint16_t m68307_cpu_device::m68307_internal_base_r(offs_t offset, uint16_t mem_m
void m68307_cpu_device::m68307_internal_base_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
logerror("%08x m68307_internal_base_w %08x, %04x (%04x)\n", m_ppc, offset*2,data,mem_mask);
// emumem needs some kind of overlay capability... it's probably not the only one
logerror("%08x m68307_internal_base_w %08x, %04x (%04x)\n", m_ipc, offset*2,data,mem_mask);
int base;
//int mask = 0;
@ -308,10 +297,10 @@ void m68307_cpu_device::m68307_internal_base_w(offs_t offset, uint16_t data, uin
base = (m_m68307_base & 0x0fff) << 12;
//mask = (m_m68307_base & 0xe000) >> 13;
//if ( m_m68307_base & 0x1000 ) mask |= 7;
m_internal->unmap_readwrite(base+0x000, base+0x04f);
m_internal->unmap_readwrite(base+0x100, base+0x11f);
m_internal->unmap_readwrite(base+0x120, base+0x13f);
m_internal->unmap_readwrite(base+0x140, base+0x149);
m_s_program->unmap_readwrite(base+0x000, base+0x04f);
m_s_program->unmap_readwrite(base+0x100, base+0x11f);
m_s_program->unmap_readwrite(base+0x120, base+0x13f);
m_s_program->unmap_readwrite(base+0x140, base+0x149);
/* store new base address */
COMBINE_DATA(&m_m68307_base);
@ -320,10 +309,10 @@ void m68307_cpu_device::m68307_internal_base_w(offs_t offset, uint16_t data, uin
base = (m_m68307_base & 0x0fff) << 12;
//mask = (m_m68307_base & 0xe000) >> 13;
//if ( m_m68307_base & 0x1000 ) mask |= 7;
m_internal->install_readwrite_handler(base + 0x000, base + 0x04f, read16_delegate(*this, FUNC(m68307_cpu_device::m68307_internal_sim_r)), write16_delegate(*this, FUNC(m68307_cpu_device::m68307_internal_sim_w)));
m_internal->install_readwrite_handler(base + 0x100, base + 0x11f, read8sm_delegate(*this, FUNC(m68307_cpu_device::m68307_internal_serial_r)), write8sm_delegate(*this, FUNC(m68307_cpu_device::m68307_internal_serial_w)), 0xffff);
m_internal->install_readwrite_handler(base + 0x120, base + 0x13f, read16s_delegate(*this, FUNC(m68307_cpu_device::m68307_internal_timer_r)), write16s_delegate(*this, FUNC(m68307_cpu_device::m68307_internal_timer_w)));
m_internal->install_readwrite_handler(base + 0x140, base + 0x149, read8sm_delegate(*this, FUNC(m68307_cpu_device::m68307_internal_mbus_r)), write8sm_delegate(*this, FUNC(m68307_cpu_device::m68307_internal_mbus_w)), 0xffff);
m_s_program->install_readwrite_handler(base + 0x000, base + 0x04f, read16_delegate(*this, FUNC(m68307_cpu_device::m68307_internal_sim_r)), write16_delegate(*this, FUNC(m68307_cpu_device::m68307_internal_sim_w)));
m_s_program->install_readwrite_handler(base + 0x100, base + 0x11f, read8sm_delegate(*this, FUNC(m68307_cpu_device::m68307_internal_serial_r)), write8sm_delegate(*this, FUNC(m68307_cpu_device::m68307_internal_serial_w)), 0xffff);
m_s_program->install_readwrite_handler(base + 0x120, base + 0x13f, read16s_delegate(*this, FUNC(m68307_cpu_device::m68307_internal_timer_r)), write16s_delegate(*this, FUNC(m68307_cpu_device::m68307_internal_timer_w)));
m_s_program->install_readwrite_handler(base + 0x140, base + 0x149, read8sm_delegate(*this, FUNC(m68307_cpu_device::m68307_internal_mbus_r)), write8sm_delegate(*this, FUNC(m68307_cpu_device::m68307_internal_mbus_w)), 0xffff);
break;

6
src/devices/machine/68307.h
View File

@ -40,9 +40,9 @@ protected:
virtual void device_reset() override;
virtual void device_add_mconfig(machine_config &config) override;
virtual void m68k_reset_peripherals() override;
private:
DECLARE_WRITE_LINE_MEMBER(reset_peripherals);
void set_ipl(int level);
DECLARE_WRITE_LINE_MEMBER(timer0_interrupt);
DECLARE_WRITE_LINE_MEMBER(timer1_interrupt);
@ -56,8 +56,6 @@ private:
uint8_t m68307_duart_input_r() { return m_read_inport(); }
void m68307_duart_output_w(uint8_t data) { m_write_outport(data); }
void init16_m68307(address_space &space);
int calc_cs(offs_t address) const;
uint16_t m68307_internal_base_r(offs_t offset, uint16_t mem_mask = ~0);

24
src/devices/machine/68307bus.cpp
View File

@ -22,19 +22,19 @@ uint8_t m68307_cpu_device::m68307_internal_mbus_r(offs_t offset)
switch (offset)
{
case m68307BUS_MADR:
logerror("%08x m68307_internal_mbus_r %08x (MADR - M-Bus Address Register)\n", m_ppc, offset);
logerror("%08x m68307_internal_mbus_r %08x (MADR - M-Bus Address Register)\n", m_ipc, offset);
return machine().rand();
case m68307BUS_MFDR:
logerror("%08x m68307_internal_mbus_r %08x (MFDR - M-Bus Frequency Divider Register)\n", m_ppc, offset);
logerror("%08x m68307_internal_mbus_r %08x (MFDR - M-Bus Frequency Divider Register)\n", m_ipc, offset);
return machine().rand();
case m68307BUS_MBCR:
logerror("%08x m68307_internal_mbus_r %08x (MFCR - M-Bus Control Register)\n", m_ppc, offset);
logerror("%08x m68307_internal_mbus_r %08x (MFCR - M-Bus Control Register)\n", m_ipc, offset);
return mbus.m_MFCR;//machine().rand();
case m68307BUS_MBSR:
logerror("%08x m68307_internal_mbus_r %08x (MBSR - M-Bus Status Register)\n", m_ppc, offset);
logerror("%08x m68307_internal_mbus_r %08x (MBSR - M-Bus Status Register)\n", m_ipc, offset);
retval = 0;
if (mbus.m_busy) retval |= 0x20;
if (mbus.m_intpend) retval |= 0x02;
@ -42,13 +42,13 @@ uint8_t m68307_cpu_device::m68307_internal_mbus_r(offs_t offset)
return retval;
case m68307BUS_MBDR:
logerror("%08x m68307_internal_mbus_r %08x (MBDR - M-Bus Data I/O Register)\n", m_ppc, offset);
logerror("%08x m68307_internal_mbus_r %08x (MBDR - M-Bus Data I/O Register)\n", m_ipc, offset);
mbus.m_intpend = true;
mbus_interrupt(1);
return 0xff;//machine().rand();
default:
logerror("%08x m68307_internal_mbus_r %08x (UNKNOWN / ILLEGAL)\n", m_ppc, offset);
logerror("%08x m68307_internal_mbus_r %08x (UNKNOWN / ILLEGAL)\n", m_ipc, offset);
return 0x00;
}
@ -63,15 +63,15 @@ void m68307_cpu_device::m68307_internal_mbus_w(offs_t offset, uint8_t data)
switch (offset)
{
case m68307BUS_MADR:
logerror("%08x m68307_internal_mbus_w %08x, %02x (MADR - M-Bus Address Register)\n", m_ppc, offset,data);
logerror("%08x m68307_internal_mbus_w %08x, %02x (MADR - M-Bus Address Register)\n", m_ipc, offset,data);
break;
case m68307BUS_MFDR:
logerror("%08x m68307_internal_mbus_w %08x, %02x (MFDR - M-Bus Frequency Divider Register)\n", m_ppc, offset,data);
logerror("%08x m68307_internal_mbus_w %08x, %02x (MFDR - M-Bus Frequency Divider Register)\n", m_ipc, offset,data);
break;
case m68307BUS_MBCR:
logerror("%08x m68307_internal_mbus_w %08x, %02x (MFCR - M-Bus Control Register)\n", m_ppc, offset,data);
logerror("%08x m68307_internal_mbus_w %08x, %02x (MFCR - M-Bus Control Register)\n", m_ipc, offset,data);
mbus.m_MFCR = data;
if (data & 0x80)
@ -85,11 +85,11 @@ void m68307_cpu_device::m68307_internal_mbus_w(offs_t offset, uint8_t data)
break;
case m68307BUS_MBSR:
logerror("%08x m68307_internal_mbus_w %08x, %02x (MBSR - M-Bus Status Register)\n", m_ppc, offset,data);
logerror("%08x m68307_internal_mbus_w %08x, %02x (MBSR - M-Bus Status Register)\n", m_ipc, offset,data);
break;
case m68307BUS_MBDR:
logerror("%08x m68307_internal_mbus_w %08x, %02x (MBDR - M-Bus Data I/O Register)\n", m_ppc, offset,data);
logerror("%08x m68307_internal_mbus_w %08x, %02x (MBDR - M-Bus Data I/O Register)\n", m_ipc, offset,data);
mbus.m_intpend = true;
mbus_interrupt(1);
@ -97,7 +97,7 @@ void m68307_cpu_device::m68307_internal_mbus_w(offs_t offset, uint8_t data)
break;
default:
logerror("%08x m68307_internal_mbus_w %08x, %02x (UNKNOWN / ILLEGAL)\n", m_ppc, offset,data);
logerror("%08x m68307_internal_mbus_w %08x, %02x (UNKNOWN / ILLEGAL)\n", m_ipc, offset,data);
break;
}
}

20
src/devices/machine/68307sim.cpp
View File

@ -54,7 +54,7 @@ uint16_t m68307_cpu_device::m68307_internal_sim_r(address_space &space, offs_t o
case m68307SIM_OR3: return sim.m_or[3];
default:
logerror("%08x m68307_internal_sim_r %08x, (%04x)\n", m_ppc, offset*2, mem_mask);
logerror("%08x m68307_internal_sim_r %08x, (%04x)\n", m_ipc, offset*2, mem_mask);
return 0xff;
}
@ -70,12 +70,12 @@ void m68307_cpu_device::m68307_internal_sim_w(address_space &space, offs_t offse
switch (offset<<1)
{
case m68307SIM_PACNT:
logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port A (8-bit) Control Register - PACNT)\n", m_ppc, offset*2,data,mem_mask);
logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port A (8-bit) Control Register - PACNT)\n", m_ipc, offset*2,data,mem_mask);
sim.write_pacnt(data,mem_mask);
break;
case m68307SIM_PADDR:
logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port A (8-bit) Direction Register - PADDR)\n", m_ppc, offset*2,data,mem_mask);
logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port A (8-bit) Direction Register - PADDR)\n", m_ipc, offset*2,data,mem_mask);
sim.write_paddr(data,mem_mask);
break;
@ -84,12 +84,12 @@ void m68307_cpu_device::m68307_internal_sim_w(address_space &space, offs_t offse
break;
case m68307SIM_PBCNT:
logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port B (16-bit) Control Register - PBCNT)\n", m_ppc, offset*2,data,mem_mask);
logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port B (16-bit) Control Register - PBCNT)\n", m_ipc, offset*2,data,mem_mask);
sim.write_pbcnt(data,mem_mask);
break;
case m68307SIM_PBDDR:
logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port B (16-bit) Direction Register - PBDDR)\n", m_ppc, offset*2,data,mem_mask);
logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port B (16-bit) Direction Register - PBDDR)\n", m_ipc, offset*2,data,mem_mask);
sim.write_pbddr(data,mem_mask);
break;
@ -99,22 +99,22 @@ void m68307_cpu_device::m68307_internal_sim_w(address_space &space, offs_t offse
case m68307SIM_LICR1:
logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Latched Interrupt Control Register 1 - LICR1)\n", m_ppc, offset*2,data,mem_mask);
logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Latched Interrupt Control Register 1 - LICR1)\n", m_ipc, offset*2,data,mem_mask);
sim.write_licr1(this,data,mem_mask);
break;
case m68307SIM_LICR2:
logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Latched Interrupt Control Register 2 - LICR2)\n", m_ppc, offset*2,data,mem_mask);
logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Latched Interrupt Control Register 2 - LICR2)\n", m_ipc, offset*2,data,mem_mask);
sim.write_licr2(this,data,mem_mask);
break;
case m68307SIM_PICR:
logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Peripheral Interrupt Control Register - PICR)\n", m_ppc, offset*2,data,mem_mask);
logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Peripheral Interrupt Control Register - PICR)\n", m_ipc, offset*2,data,mem_mask);
sim.write_picr(this,data,mem_mask);
break;
case m68307SIM_PIVR:
logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Peripheral Interrupt Vector Register - PIVR)\n", m_ppc, offset*2,data,mem_mask);
logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Peripheral Interrupt Vector Register - PIVR)\n", m_ipc, offset*2,data,mem_mask);
sim.write_pivr(this,data,mem_mask);
break;
@ -146,7 +146,7 @@ void m68307_cpu_device::m68307_internal_sim_w(address_space &space, offs_t offse
default :
logerror("%08x m68307_internal_sim_w %08x, %04x (%04x)\n", m_ppc, offset*2,data,mem_mask);
logerror("%08x m68307_internal_sim_w %08x, %04x (%04x)\n", m_ipc, offset*2,data,mem_mask);
break;
}
}

24
src/devices/machine/68307tmu.cpp
View File

@ -25,11 +25,11 @@ uint16_t m68307_cpu_device::m68307_internal_timer_r(offs_t offset, uint16_t mem_
switch (offset&0x7)
{
case m68307TIMER_TCN: /* 0x3 (0x126 / 0x136) */
//if (m_ppc!=0x2182e) logerror("%08x m68307_internal_timer_r %08x (%04x) (TCN - Timer Counter for timer %d)\n", m_ppc, offset*2,mem_mask, which);
//if (m_ipc!=0x2182e) logerror("%08x m68307_internal_timer_r %08x (%04x) (TCN - Timer Counter for timer %d)\n", m_ipc, offset*2,mem_mask, which);
return timer.read_tcn(mem_mask, which);
default:
logerror("%08x m68307_internal_timer_r %08x, (%04x)\n", m_ppc, offset*2,mem_mask);
logerror("%08x m68307_internal_timer_r %08x, (%04x)\n", m_ipc, offset*2,mem_mask);
break;
}
@ -46,53 +46,53 @@ void m68307_cpu_device::m68307_internal_timer_w(offs_t offset, uint16_t data, ui
switch (offset&0x7)
{
case m68307TIMER_TMR: /* 0x0 (0x120 / 0x130) */
logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (TMR - Timer Mode Register for timer %d)\n", m_ppc, offset*2,data,mem_mask, which);
logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (TMR - Timer Mode Register for timer %d)\n", m_ipc, offset*2,data,mem_mask, which);
timer.write_tmr(data, mem_mask, which);
break;
case m68307TIMER_TRR: /* 0x1 (0x122 / 0x132) */
logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (TRR - Timer Reference Register for timer %d)\n", m_ppc, offset*2,data,mem_mask, which);
logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (TRR - Timer Reference Register for timer %d)\n", m_ipc, offset*2,data,mem_mask, which);
timer.write_trr(data, mem_mask, which);
break;
case m68307TIMER_TCR: /* 0x2 (0x124 / 0x134) */
logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (TCR - Timer Capture Register for timer %d) (illegal, read-only)\n", m_ppc, offset*2,data,mem_mask, which);
logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (TCR - Timer Capture Register for timer %d) (illegal, read-only)\n", m_ipc, offset*2,data,mem_mask, which);
break;
case m68307TIMER_TCN: /* 0x3 (0x126 / 0x136) */
logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (TCN - Timer Counter for timer %d)\n", m_ppc, offset*2,data,mem_mask, which);
logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (TCN - Timer Counter for timer %d)\n", m_ipc, offset*2,data,mem_mask, which);
break;
case m68307TIMER_TER: /* 0x4 (0x128 / 0x138) */
/* 8-bit only!! */
//logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (TER - Timer Event Register for timer %d)\n", m_ppc, offset*2,data,mem_mask, which);
//logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (TER - Timer Event Register for timer %d)\n", m_ipc, offset*2,data,mem_mask, which);
timer.write_ter(data, mem_mask, which);
break;
case m68307TIMER_WRR: /* 0x5 (0x12a / 0x13a) */
if (which==0)
{
logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (WRR - Watchdog Reference Register)\n", m_ppc, offset*2,data,mem_mask);
logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (WRR - Watchdog Reference Register)\n", m_ipc, offset*2,data,mem_mask);
}
else
{
logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (illegal)\n", m_ppc, offset*2,data,mem_mask);
logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (illegal)\n", m_ipc, offset*2,data,mem_mask);
}
break;
case m68307TIMER_WCR: /* 0x6 (0x12c / 0x13c) */
if (which==0)
{
logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (WRR - Watchdog Counter Register)\n", m_ppc, offset*2,data,mem_mask);
logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (WRR - Watchdog Counter Register)\n", m_ipc, offset*2,data,mem_mask);
}
else
{
logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (illegal)\n", m_ppc, offset*2,data,mem_mask);
logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (illegal)\n", m_ipc, offset*2,data,mem_mask);
}
break;
case m68307TIMER_XXX: /* 0x7 (0x12e / 0x13e) */
logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (illegal)\n", m_ppc, offset*2,data,mem_mask);
logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (illegal)\n", m_ipc, offset*2,data,mem_mask);
break;
}
}

4
src/devices/machine/68340.cpp
View File

@ -256,6 +256,8 @@ WRITE_LINE_MEMBER( m68340_cpu_device::set_modck )
void m68340_cpu_device::device_start()
{
reset_cb().append(FUNC(m68340_cpu_device::reset_peripherals));
fscpu32_device::device_start();
m_m68340SIM = new m68340_sim();
@ -271,7 +273,7 @@ void m68340_cpu_device::device_start()
m_internal = &space(AS_PROGRAM);
}
void m68340_cpu_device::m68k_reset_peripherals()
WRITE_LINE_MEMBER(m68340_cpu_device::reset_peripherals)
{
m_m68340SIM->module_reset();
m_m68340DMA->module_reset();

2
src/devices/machine/68340.h
View File

@ -49,7 +49,7 @@ protected:
virtual void device_reset() override;
virtual void device_add_mconfig(machine_config &config) override;
virtual void m68k_reset_peripherals() override;
DECLARE_WRITE_LINE_MEMBER(reset_peripherals);
private:
required_device<mc68340_serial_module_device> m_serial;

23
src/devices/machine/mc68328.cpp
View File

@ -47,8 +47,8 @@ DEFINE_DEVICE_TYPE(MC68EZ328, mc68ez328_device, "mc68ez328", "MC68EZ328 DragonBa
const u32 mc68328_base_device::VCO_DIVISORS[8] = { 2, 4, 8, 16, 1, 1, 1, 1 };
mc68328_base_device::mc68328_base_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, u32 addr_bits, address_map_constructor internal_map_ctor)
: m68000_device(mconfig, tag, owner, clock, type, 16, addr_bits, internal_map_ctor)
mc68328_base_device::mc68328_base_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock)
: m68000_device(mconfig, type, tag, owner, clock)
, m_pwm(nullptr)
, m_rtc(nullptr)
, m_spim(nullptr)
@ -78,7 +78,7 @@ mc68328_base_device::mc68328_base_device(const machine_config &mconfig, device_t
}
mc68328_device::mc68328_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
: mc68328_base_device(mconfig, MC68328, tag, owner, clock, 24, address_map_constructor(FUNC(mc68328_device::internal_map), this))
: mc68328_base_device(mconfig, MC68328, tag, owner, clock)
, m_out_port_j_cb(*this)
, m_out_port_k_cb(*this)
, m_out_port_m_cb(*this)
@ -87,12 +87,27 @@ mc68328_device::mc68328_device(const machine_config &mconfig, const char *tag, d
, m_in_port_m_cb(*this)
{
m_cpu_space_config.m_internal_map = address_map_constructor(FUNC(mc68328_device::cpu_space_map), this);
auto imap = address_map_constructor(FUNC(mc68328_device::internal_map), this);
m_program_config.m_internal_map = imap;
m_opcodes_config.m_internal_map = imap;
m_uprogram_config.m_internal_map = imap;
m_uopcodes_config.m_internal_map = imap;
}
mc68ez328_device::mc68ez328_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
: mc68328_base_device(mconfig, MC68EZ328, tag, owner, clock, 32, address_map_constructor(FUNC(mc68ez328_device::internal_map), this))
: mc68328_base_device(mconfig, MC68EZ328, tag, owner, clock)
{
m_cpu_space_config.m_internal_map = address_map_constructor(FUNC(mc68ez328_device::cpu_space_map), this);
m_cpu_space_config.m_addr_width = 32;
m_program_config.m_addr_width = 32;
m_opcodes_config.m_addr_width = 32;
m_uprogram_config.m_addr_width = 32;
m_uopcodes_config.m_addr_width = 32;
auto imap = address_map_constructor(FUNC(mc68ez328_device::internal_map), this);
m_program_config.m_internal_map = imap;
m_opcodes_config.m_internal_map = imap;
m_uprogram_config.m_internal_map = imap;
m_uopcodes_config.m_internal_map = imap;
}
void mc68328_base_device::base_internal_map(u32 addr_bits, address_map &map)

2
src/devices/machine/mc68328.h
View File

@ -131,7 +131,7 @@ public:
}
protected:
mc68328_base_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, u32 addr_bits, address_map_constructor internal_map_ctor);
mc68328_base_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock);
// device-level overrides
virtual void device_resolve_objects() override;

24
src/devices/machine/scc68070.cpp
View File

@ -239,7 +239,7 @@ void scc68070_device::cpu_space_map(address_map &map)
//-------------------------------------------------
scc68070_device::scc68070_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: scc68070_base_device(mconfig, tag, owner, clock, SCC68070, address_map_constructor(FUNC(scc68070_device::internal_map), this))
: m68000_device(mconfig, SCC68070, tag, owner, clock)
, m_iack2_callback(*this)
, m_iack4_callback(*this)
, m_iack5_callback(*this)
@ -258,6 +258,18 @@ scc68070_device::scc68070_device(const machine_config &mconfig, const char *tag,
, m_int2_line(CLEAR_LINE)
{
m_cpu_space_config.m_internal_map = address_map_constructor(FUNC(scc68070_device::cpu_space_map), this);
m_cpu_space_config.m_addr_width = 32;
m_program_config.m_addr_width = 32;
m_opcodes_config.m_addr_width = 32;
m_uprogram_config.m_addr_width = 32;
m_uopcodes_config.m_addr_width = 32;
auto imap = address_map_constructor(FUNC(scc68070_device::internal_map), this);
m_program_config.m_internal_map = imap;
m_opcodes_config.m_internal_map = imap;
m_uprogram_config.m_internal_map = imap;
m_uopcodes_config.m_internal_map = imap;
}
//-------------------------------------------------
@ -268,7 +280,7 @@ scc68070_device::scc68070_device(const machine_config &mconfig, const char *tag,
void scc68070_device::device_resolve_objects()
{
scc68070_base_device::device_resolve_objects();
m68000_device::device_resolve_objects();
m_iack2_callback.resolve_safe(autovector(2));
m_iack4_callback.resolve_safe(autovector(4));
@ -287,7 +299,9 @@ void scc68070_device::device_resolve_objects()
void scc68070_device::device_start()
{
scc68070_base_device::device_start();
reset_cb().append(FUNC(scc68070_device::reset_peripherals));
m68000_device::device_start();
save_item(NAME(m_ipl));
@ -378,7 +392,7 @@ void scc68070_device::device_start()
void scc68070_device::device_reset()
{
scc68070_base_device::device_reset();
m68000_device::device_reset();
m_lir = 0;
@ -448,7 +462,7 @@ void scc68070_device::device_reset()
set_timer_callback(0);
}
void scc68070_device::m68k_reset_peripherals()
WRITE_LINE_MEMBER(scc68070_device::reset_peripherals)
{
m_lir = 0;

7
src/devices/machine/scc68070.h
View File

@ -26,7 +26,7 @@ TODO:
#pragma once
#include "cpu/m68000/scc68070.h"
#include "cpu/m68000/m68000.h"
//**************************************************************************
// TYPE DEFINITIONS
@ -43,7 +43,7 @@ enum scc68070_ocr_bits
// ======================> scc68070_device
class scc68070_device : public scc68070_base_device
class scc68070_device : public m68000_device
{
public:
scc68070_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
@ -199,8 +199,7 @@ protected:
virtual u64 execute_clocks_to_cycles(u64 clocks) const noexcept override { return (clocks + 2 - 1) / 2; }
virtual u64 execute_cycles_to_clocks(u64 cycles) const noexcept override { return (cycles * 2); }
// m68000_base_device overrides
virtual void m68k_reset_peripherals() override;
DECLARE_WRITE_LINE_MEMBER(reset_peripherals);
private:
void internal_map(address_map &map);

2
src/devices/machine/tmp68301.cpp
View File

@ -166,7 +166,7 @@ void tmp68301_device::device_start()
m_in_parallel_cb.resolve_safe(0);
m_out_parallel_cb.resolve_safe();
m_program->install_device(0xfffc00, 0xffffff, *this, &tmp68301_device::tmp68301_regs);
m_s_program->install_device(0xfffc00, 0xffffff, *this, &tmp68301_device::tmp68301_regs);
save_item(NAME(m_regs));
save_item(NAME(m_icr));

2
src/mame/apple/mac.h
View File

@ -27,7 +27,7 @@
#include "macrtc.h"
#include "macscsi.h"
#include "sound/asc.h"
#include "cpu/m68000/m68000.h"
#include "cpu/m68000/m68kmusashi.h"
#include "emupal.h"
#include "screen.h"

2
src/mame/apple/mac128.cpp
View File

@ -611,7 +611,7 @@ WRITE_LINE_MEMBER(mac128_state::scsi_drq_w)
void mac128_state::scsi_berr_w(uint8_t data)
{
m_maincpu->pulse_input_line(M68K_LINE_BUSERROR, attotime::zero);
m_maincpu->trigger_bus_error();
}
uint16_t mac128_state::macplus_scsi_r(offs_t offset, uint16_t mem_mask)

2
src/mame/apple/macprtb.cpp
View File

@ -425,7 +425,7 @@ void macportable_state::scsi_w(offs_t offset, uint16_t data, uint16_t mem_mask)
void macportable_state::scsi_berr_w(uint8_t data)
{
m_maincpu->pulse_input_line(M68K_LINE_BUSERROR, attotime::zero);
m_maincpu->trigger_bus_error();
}
/***************************************************************************

27
src/mame/atari/atarist.cpp
View File

@ -189,8 +189,6 @@ protected:
void dma_base_w(offs_t offset, uint8_t data);
uint8_t mmu_r();
void mmu_w(uint8_t data);
uint16_t berr_r();
void berr_w(uint16_t data);
uint8_t ikbd_port1_r();
uint8_t ikbd_port2_r();
void ikbd_port2_w(uint8_t data);
@ -735,24 +733,6 @@ void st_state::mmu_w(uint8_t data)
m_mmu = data;
}
void st_state::berr_w(uint16_t data)
{
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
}
uint16_t st_state::berr_r()
{
if (!machine().side_effects_disabled())
{
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
}
return 0xffff;
}
//**************************************************************************
// IKBD
//**************************************************************************
@ -1524,12 +1504,12 @@ void st_state::cpu_space_map(address_map &map)
void st_state::st_map(address_map &map)
{
map.unmap_value_high();
map(0x000000, 0x000007).rom().region(M68000_TAG, 0).w(FUNC(st_state::berr_w));
map(0x000000, 0x000007).rom().region(M68000_TAG, 0).w(m_maincpu, FUNC(m68000_device::berr_w));
map(0x000008, 0x1fffff).ram();
map(0x200000, 0x3fffff).ram();
map(0x400000, 0xf9ffff).rw(FUNC(st_state::berr_r), FUNC(st_state::berr_w));
map(0x400000, 0xf9ffff).rw(m_maincpu, FUNC(m68000_device::berr_r), FUNC(m68000_device::berr_w));
//map(0xfa0000, 0xfbffff) // mapped by the cartslot
map(0xfc0000, 0xfeffff).rom().region(M68000_TAG, 0).w(FUNC(st_state::berr_w));
map(0xfc0000, 0xfeffff).rom().region(M68000_TAG, 0).w(m_maincpu, FUNC(m68000_device::berr_w));
map(0xff8001, 0xff8001).rw(FUNC(st_state::mmu_r), FUNC(st_state::mmu_w));
map(0xff8200, 0xff8203).rw(m_video, FUNC(st_video_device::shifter_base_r), FUNC(st_video_device::shifter_base_w)).umask16(0x00ff);
map(0xff8204, 0xff8209).r(m_video, FUNC(st_video_device::shifter_counter_r)).umask16(0x00ff);
@ -3098,6 +3078,7 @@ ROM_START( megaste )
ROMX_LOAD( "atari mega ste 205 019 tms27c010.bin", 0x00001, 0x20000, CRC(ea2a136d) SHA1(c3c259293de562d2a0fac4d41f95cf3d42ad6df4), ROM_BIOS(0) | ROM_SKIP(1) )
ROM_SYSTEM_BIOS( 1, "tos206", "TOS 2.06 (ST/STE TOS)" )
ROMX_LOAD( "tos206.bin", 0x00000, 0x40000, BAD_DUMP CRC(3f2f840f) SHA1(ee58768bdfc602c9b14942ce5481e97dd24e7c83), ROM_BIOS(1) )
ROMX_LOAD( "tos206.bin", 0x00000, 0x40000, CRC(3f2f840f) SHA1(ee58768bdfc602c9b14942ce5481e97dd24e7c83), ROM_BIOS(1) )
ROM_REGION( 0x1000, HD6301V1_TAG, 0 )
ROM_LOAD( "keyboard.u1", 0x0000, 0x1000, CRC(0296915d) SHA1(1102f20d38f333234041c13687d82528b7cde2e1) )

2
src/mame/atari/badlandsbl.cpp
View File

@ -61,7 +61,7 @@ uint32_t badlandsbl_state::screen_update_badlandsbl(screen_device &screen, bitma
if((m_spriteram[count+3] & 0xff) == 0xff)
return 0;
uint16 tile = m_spriteram[count];
uint16_t tile = m_spriteram[count];
int y = (511 - 14) - (m_spriteram[count+1] & 0x1ff);
int x = (m_spriteram[count+2] >> 7) - 7;
int color = (m_spriteram[count+3] >> 8) & 7;

2
src/mame/canon/cat.cpp
View File

@ -678,7 +678,7 @@ void cat_state::cat_opr_w(offs_t offset, uint16_t data)
*/
uint16_t cat_state::cat_wdt_r()
{
uint16 Retval = 0x0100; // set pfail to 1; should this be a dipswitch?
uint16_t Retval = 0x0100; // set pfail to 1; should this be a dipswitch?
return Retval | m_wdt_counter;
}

23
src/mame/ericsson/e9161.cpp
View File

@ -31,35 +31,18 @@ public:
void e9161(machine_config &config);
private:
u16 berr_r();
void berr_w(u16 data);
void mem_map(address_map &map);
required_device<cpu_device> m_maincpu;
required_device<m68000_device> m_maincpu;
required_device<hd63450_device> m_dmac;
};
u16 e9161_state::berr_r()
{
if (!machine().side_effects_disabled())
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
return 0xffff;
}
void e9161_state::berr_w(u16 data)
{
if (!machine().side_effects_disabled())
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
}
void e9161_state::mem_map(address_map &map)
{
map(0x000000, 0x000007).rom().region("program", 0);
map(0x000008, 0x01ffff).ram();
map(0x020000, 0x020001).w(FUNC(e9161_state::berr_w));
map(0xa00000, 0xa00001).mirror(0x1ffffe).r(FUNC(e9161_state::berr_r));
map(0x020000, 0x020001).w(m_maincpu, FUNC(m68000_device::berr_w));
map(0xa00000, 0xa00001).mirror(0x1ffffe).r(m_maincpu, FUNC(m68000_device::berr_r));
map(0xc00000, 0xc03fff).rom().region("program", 0);
map(0xe00000, 0xe03fff).ram();
map(0xffe000, 0xffe03f).rw(m_dmac, FUNC(hd63450_device::read), FUNC(hd63450_device::write));

28
src/mame/hp/hp9k.cpp
View File

@ -149,9 +149,6 @@ private:
uint8_t m_videoram[0x4000];
uint8_t m_screenram[0x800];
uint16_t buserror_r();
void buserror_w(uint16_t data);
uint16_t hp9k_videoram_r(offs_t offset, uint16_t mem_mask = ~0);
void hp9k_videoram_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
@ -295,35 +292,22 @@ void hp9k_state::hp9k_videoram_w(offs_t offset, uint16_t data, uint16_t mem_mask
}
}
uint16_t hp9k_state::buserror_r()
{
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
return 0;
}
void hp9k_state::buserror_w(uint16_t data)
{
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
}
void hp9k_state::hp9k_mem(address_map &map)
{
map.unmap_value_high();
map(0x000000, 0x000909).rom().region("bootrom", 0);
map(0x00090a, 0x00090d).rw(FUNC(hp9k_state::leds_r), FUNC(hp9k_state::leds_w));
map(0x00090e, 0x00ffff).rom().region("bootrom", 0x90e);
map(0x010000, 0x427fff).rw(FUNC(hp9k_state::buserror_r), FUNC(hp9k_state::buserror_w));
map(0x010000, 0x427fff).rw(m_maincpu, FUNC(m68000_device::berr_r), FUNC(m68000_device::berr_w));
map(0x428000, 0x428fff).rw(FUNC(hp9k_state::keyboard_r), FUNC(hp9k_state::keyboard_w));
map(0x429000, 0x50ffff).rw(FUNC(hp9k_state::buserror_r), FUNC(hp9k_state::buserror_w));
map(0x429000, 0x50ffff).rw(m_maincpu, FUNC(m68000_device::berr_r), FUNC(m68000_device::berr_w));
map(0x510000, 0x51ffff).rw(FUNC(hp9k_state::hp9k_videoram_r), FUNC(hp9k_state::hp9k_videoram_w));
map(0x520000, 0x52ffff).rw(FUNC(hp9k_state::buserror_r), FUNC(hp9k_state::buserror_w));
map(0x520000, 0x52ffff).rw(m_maincpu, FUNC(m68000_device::berr_r), FUNC(m68000_device::berr_w));
map(0x530000, 0x53ffff).ram(); // graphic memory
map(0x540000, 0x5effff).rw(FUNC(hp9k_state::buserror_r), FUNC(hp9k_state::buserror_w));
map(0x540000, 0x5effff).rw(m_maincpu, FUNC(m68000_device::berr_r), FUNC(m68000_device::berr_w));
map(0x5f0000, 0x5f3fff).rw(FUNC(hp9k_state::hp9k_prom_r), FUNC(hp9k_state::hp9k_prom_w));
//map(0x5f0000, 0x5f3fff).rw(FUNC(hp9k_state::buserror_r), FUNC(hp9k_state::buserror_w));
map(0x5f4000, 0xfbffff).rw(FUNC(hp9k_state::buserror_r), FUNC(hp9k_state::buserror_w));
//map(0x5f0000, 0x5f3fff).rw(m_maincpu, FUNC(m68000_device::berr_r), FUNC(m68000_device::berr_w));
map(0x5f4000, 0xfbffff).rw(m_maincpu, FUNC(m68000_device::berr_r), FUNC(m68000_device::berr_w));
map(0xFC0000, 0xffffff).ram(); // system ram
}

53
src/mame/hp/hp_ipc.cpp
View File

@ -414,8 +414,6 @@ protected:
virtual void machine_start() override;
virtual void machine_reset() override;
TIMER_CALLBACK_MEMBER(clear_bus_error);
private:
uint16_t mem_r(offs_t offset, uint16_t mem_mask);
void mem_w(offs_t offset, uint16_t data, uint16_t mem_mask);
@ -423,8 +421,6 @@ private:
void mmu_w(offs_t offset, uint16_t data);
uint16_t ram_r(offs_t offset, uint16_t mem_mask);
void ram_w(offs_t offset, uint16_t data, uint16_t mem_mask);
uint16_t trap_r(offs_t offset, uint16_t mem_mask);
void trap_w(offs_t offset, uint16_t data, uint16_t mem_mask);
void spkr_w(offs_t offset, uint16_t data);
uint8_t floppy_id_r();
@ -439,8 +435,6 @@ private:
[[maybe_unused]] DECLARE_WRITE_LINE_MEMBER(irq_6);
DECLARE_WRITE_LINE_MEMBER(irq_7);
emu_timer *m_bus_error_timer = nullptr;
void hp_ipc_mem_inner_base(address_map &map);
void hp_ipc_mem_inner_9807a(address_map &map);
void hp_ipc_mem_outer(address_map &map);
@ -473,33 +467,8 @@ private:
{
return (m_mmu[(m_maincpu->get_fc() >> 1) & 3] + offset) & 0x3FFFFF;
}
void set_bus_error(uint32_t address, bool write, uint16_t mem_mask);
bool m_bus_error = false;
};
TIMER_CALLBACK_MEMBER(hp_ipc_state::clear_bus_error)
{
m_bus_error = false;
}
void hp_ipc_state::set_bus_error(uint32_t address, bool rw, uint16_t mem_mask)
{
if (m_bus_error)
{
return;
}
if (!ACCESSING_BITS_8_15)
{
address++;
}
m_bus_error = true;
m_maincpu->set_buserror_details(address, rw, m_maincpu->get_fc());
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
m_bus_error_timer->adjust(m_maincpu->cycles_to_attotime(16)); // let rmw cycles complete
}
void hp_ipc_state::hp_ipc_mem_outer(address_map &map)
{
map(0x000000, 0xFFFFFF).rw(FUNC(hp_ipc_state::mem_r), FUNC(hp_ipc_state::mem_w));
@ -508,7 +477,7 @@ void hp_ipc_state::hp_ipc_mem_outer(address_map &map)
void hp_ipc_state::hp_ipc_mem_inner_base(address_map &map)
{
// bus error handler
map(0x0000000, 0x1FFFFFF).rw(FUNC(hp_ipc_state::trap_r), FUNC(hp_ipc_state::trap_w));
map(0x0000000, 0x1FFFFFF).rw(m_maincpu, FUNC(m68000_device::berr_r), FUNC(m68000_device::berr_w));
// user mode
map(0x1000000, 0x17FFFFF).rw(FUNC(hp_ipc_state::ram_r), FUNC(hp_ipc_state::ram_w));
@ -588,18 +557,6 @@ void hp_ipc_state::mem_w(offs_t offset, uint16_t data, uint16_t mem_mask)
m_bankdev->write16(offset, data, mem_mask);
}
uint16_t hp_ipc_state::trap_r(offs_t offset, uint16_t mem_mask)
{
if (!machine().side_effects_disabled()) set_bus_error((offset << 1) & 0xFFFFFF, true, mem_mask);
return 0xffff;
}
void hp_ipc_state::trap_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
if (!machine().side_effects_disabled()) set_bus_error((offset << 1) & 0xFFFFFF, false, mem_mask);
}
void hp_ipc_state::spkr_w(offs_t offset, uint16_t data)
{
m_spkr->cs_w(!BIT(data , 0));
@ -614,7 +571,8 @@ uint16_t hp_ipc_state::ram_r(offs_t offset, uint16_t mem_mask)
if (ram_address < m_lowest_ram_addr)
{
if (!machine().side_effects_disabled()) set_bus_error((offset << 1) + 0x800000, 0, mem_mask);
if (!machine().side_effects_disabled())
m_maincpu->trigger_bus_error();
}
else if (ram_address < 0x3c0000)
{
@ -631,7 +589,7 @@ void hp_ipc_state::ram_w(offs_t offset, uint16_t data, uint16_t mem_mask)
if (ram_address < m_lowest_ram_addr)
{
if (!machine().side_effects_disabled()) set_bus_error((offset << 1) + 0x800000, 1, mem_mask);
m_maincpu->trigger_bus_error();
}
else if (ram_address < 0x3c0000)
{
@ -736,9 +694,6 @@ WRITE_LINE_MEMBER(hp_ipc_state::irq_7)
void hp_ipc_state::machine_start()
{
m_bus_error_timer = timer_alloc(FUNC(hp_ipc_state::clear_bus_error), this);
m_bus_error = false;
m_bankdev->set_bank(1);
m_lowest_ram_addr = 0x3c0000 - (m_ram->size() >> 1);

2
src/mame/kurzweil/krz2000.cpp
View File

@ -277,7 +277,7 @@ void k2000_state::k2000_map(address_map &map)
map(0x680300, 0x6805FF).rw(FUNC(k2000_state::hobbes1_read), FUNC(k2000_state::hobbes1_write));
// SROM - Setup ROM?
uint32 srom_base = 0x280000;
uint32_t srom_base = 0x280000;
map(srom_base, srom_base + 0x40000 - 1).rom().region("maincpu", 0x100000);
// Calvin chip has a 20-bit address bus with A0 tied low and A12-15 tied high, giving it access to 0x?0??[0-E]

11
src/mame/luxor/abc1600.cpp
View File

@ -789,14 +789,6 @@ WRITE_LINE_MEMBER( abc1600_state::nmi_w )
}
}
void abc1600_state::buserr_w(offs_t offset, uint8_t data)
{
m_maincpu->set_buserror_details(offset, data, m_maincpu->get_fc());
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
}
//**************************************************************************
// MACHINE INITIALIZATION
@ -867,8 +859,7 @@ void abc1600_state::abc1600(machine_config &config)
// devices
ABC1600_MAC(config, m_mac, 0);
m_mac->set_addrmap(AS_PROGRAM, &abc1600_state::mac_mem);
m_mac->fc_cb().set(m_maincpu, FUNC(m68000_musashi_device::get_fc));
m_mac->buserr_cb().set(FUNC(abc1600_state::buserr_w));
m_mac->set_cpu(m_maincpu);
m_mac->in_tren0_cb().set(m_bus0i, FUNC(abcbus_slot_device::read_tren)); // TODO bus0x
m_mac->out_tren0_cb().set(m_bus0i, FUNC(abcbus_slot_device::write_tren)); // TODO bus0x
m_mac->in_tren1_cb().set(m_bus1, FUNC(abcbus_slot_device::read_tren));

1
src/mame/luxor/abc1600.h
View File

@ -132,7 +132,6 @@ private:
void cio_pc_w(uint8_t data);
void nmi_w(int state);
void buserr_w(offs_t offset, uint8_t data);
void cpu_space_map(address_map &map);

11
src/mame/luxor/abc1600mac.cpp
View File

@ -107,11 +107,10 @@ abc1600_mac_device::abc1600_mac_device(const machine_config &mconfig, const char
m_program_config("program", ENDIANNESS_BIG, 8, 21, 0, address_map_constructor(FUNC(abc1600_mac_device::program_map), this)),
m_mac_config("mac", ENDIANNESS_BIG, 8, 20, 0, address_map_constructor(FUNC(abc1600_mac_device::mac_map), this)),
m_rom(*this, "boot"),
m_cpu(*this, finder_base::DUMMY_TAG),
m_segment_ram(*this, "segment_ram", 0x400, ENDIANNESS_LITTLE),
m_page_ram(*this, "page_ram", 0x400*2, ENDIANNESS_LITTLE),
m_watchdog(*this, "watchdog"),
m_read_fc(*this),
m_write_buserr(*this),
m_read_tren(*this),
m_write_tren(*this),
m_boote(0),
@ -130,8 +129,6 @@ abc1600_mac_device::abc1600_mac_device(const machine_config &mconfig, const char
void abc1600_mac_device::device_start()
{
// resolve callbacks
m_read_fc.resolve_safe(0);
m_write_buserr.resolve_safe();
m_read_tren.resolve_all_safe(0xff);
m_write_tren.resolve_all_safe();
@ -198,7 +195,7 @@ inline offs_t abc1600_mac_device::get_physical_offset(offs_t offset, int task, b
m_cause = ((offset >> 13) & 0x1f) | DMAOK;
if (LOG && (offset != virtual_offset)) logerror("%s MAC %05x:%06x (SEGA %03x SEGD %02x PGA %03x PGD %04x NONX %u WP %u TASK %u FC %u MAGIC %u)\n",
machine().describe_context(), offset, virtual_offset, sega, segd, pga, page_data, nonx, wp, task, m_read_fc(), m_magic);
machine().describe_context(), offset, virtual_offset, sega, segd, pga, page_data, nonx, wp, task, m_cpu->get_fc(), m_magic);
return virtual_offset;
}
@ -215,7 +212,7 @@ uint8_t abc1600_mac_device::read(offs_t offset)
return m_rom->base()[offset & 0x3fff];
}
uint8_t fc = m_read_fc();
uint8_t fc = m_cpu->get_fc();
int task = m_task;
if (FC2)
@ -262,7 +259,7 @@ uint8_t abc1600_mac_device::read(offs_t offset)
void abc1600_mac_device::write(offs_t offset, uint8_t data)
{
uint8_t fc = m_read_fc();
uint8_t fc = m_cpu->get_fc();
int task = m_task;
if (FC2)

9
src/mame/luxor/abc1600mac.h
View File

@ -11,7 +11,7 @@
#pragma once
#include "cpu/m68000/m68000.h"
#include "cpu/m68000/m68008.h"
#include "machine/watchdog.h"
@ -35,8 +35,7 @@ class abc1600_mac_device : public device_t,
public:
abc1600_mac_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
auto fc_cb() { return m_read_fc.bind(); }
auto buserr_cb() { return m_write_buserr.bind(); }
template <typename T> void set_cpu(T &&tag) { m_cpu.set_tag(std::forward<T>(tag)); }
auto in_tren0_cb() { return m_read_tren[0].bind(); }
auto out_tren0_cb() { return m_write_tren[0].bind(); }
auto in_tren1_cb() { return m_read_tren[1].bind(); }
@ -112,14 +111,12 @@ private:
const address_space_config m_mac_config;
required_memory_region m_rom;
required_device<m68008_device> m_cpu;
memory_share_creator<u8> m_segment_ram;
memory_share_creator<u16> m_page_ram;
required_device<watchdog_timer_device> m_watchdog;
devcb_read8 m_read_fc;
devcb_write8 m_write_buserr;
devcb_read8::array<3> m_read_tren;
devcb_write8::array<3> m_write_tren;

2
src/mame/namco/namcond1.cpp
View File

@ -452,7 +452,7 @@ uint16_t namcond1_state::mcu_pa_read()
return 0xff;
}
void namcond1_state::mcu_pa_write(uint16 data)
void namcond1_state::mcu_pa_write(uint16_t data)
{
m_p8 = data;
}

2
src/mame/neogeo/neogeo.cpp
View File

@ -1906,7 +1906,7 @@ INPUT_CHANGED_MEMBER(aes_base_state::aes_jp1)
{
// Shorting JP1 causes a 68000 /BERR (Bus Error). On Dev Bios, this pops up the debug monitor.
if (newval)
m_maincpu->set_input_line(M68K_LINE_BUSERROR, HOLD_LINE);
m_maincpu->trigger_bus_error();
}

2
src/mame/neogeo/neogeo.h
View File

@ -118,7 +118,7 @@ protected:
virtual void device_post_load() override;
// devices
required_device<cpu_device> m_maincpu;
required_device<m68000_device> m_maincpu;
required_device<cpu_device> m_audiocpu;
// MVS-specific devices
optional_device<ym2610_device> m_ym;

28
src/mame/philips/cdi.cpp
View File

@ -84,7 +84,7 @@ TODO:
void cdi_state::cdimono1_mem(address_map &map)
{
map(0x000000, 0xffffff).rw(FUNC(cdi_state::bus_error_r), FUNC(cdi_state::bus_error_w));
map(0x000000, 0xffffff).rw(m_maincpu, FUNC(scc68070_device::berr_r), FUNC(scc68070_device::berr_w));
map(0x000000, 0x07ffff).rw(FUNC(cdi_state::plane_r<0>), FUNC(cdi_state::plane_w<0>)).share("plane0");
map(0x200000, 0x27ffff).rw(FUNC(cdi_state::plane_r<1>), FUNC(cdi_state::plane_w<1>)).share("plane1");
map(0x300000, 0x303bff).rw(m_cdic, FUNC(cdicdic_device::ram_r), FUNC(cdicdic_device::ram_w));
@ -238,32 +238,6 @@ uint16_t cdi_state::main_rom_r(offs_t offset)
}
/**********************
* BERR Handling *
**********************/
uint16_t cdi_state::bus_error_r(offs_t offset)
{
if(!machine().side_effects_disabled())
{
m_maincpu->set_buserror_details(offset*2, true, m_maincpu->get_fc());
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
}
return 0xff;
}
void cdi_state::bus_error_w(offs_t offset, uint16_t data)
{
if(!machine().side_effects_disabled())
{
m_maincpu->set_buserror_details(offset*2, false, m_maincpu->get_fc());
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
}
}
/**********************
* Quizard Protection *
**********************/

3
src/mame/philips/cdi.h
View File

@ -69,9 +69,6 @@ private:
uint16_t dvc_r(offs_t offset, uint16_t mem_mask = ~0);
void dvc_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
uint16_t bus_error_r(offs_t offset);
void bus_error_w(offs_t offset, uint16_t data);
required_shared_ptr_array<uint16_t, 2> m_plane_ram;
optional_device<m68hc05c8_device> m_servo;
optional_device<m68hc05c8_device> m_slave;

34
src/mame/quantel/dpb7000.cpp
View File

@ -160,9 +160,6 @@ private:
void tablet_program_map(address_map &map);
void tablet_data_map(address_map &map);
uint16_t bus_error_r(offs_t offset);
void bus_error_w(offs_t offset, uint16_t data);
void csr_w(uint8_t data);
uint8_t csr_r();
@ -212,7 +209,7 @@ private:
void process_byte_from_disc(uint8_t data_byte);
uint8_t process_byte_to_disc();
required_device<m68000_base_device> m_maincpu;
required_device<m68000_device> m_maincpu;
required_device_array<acia6850_device, 3> m_acia;
required_device<input_merger_device> m_p_int;
required_device<com8116_device> m_brg;
@ -486,11 +483,11 @@ void dpb7000_state::main_map(address_map &map)
{
map(0x000000, 0x09ffff).rom().region("monitor", 0);
map(0x0006aa, 0x0006ab).nopw();
map(0xb00000, 0xb7ffff).rw(FUNC(dpb7000_state::bus_error_r), FUNC(dpb7000_state::bus_error_w));
map(0xb00000, 0xb7ffff).rw(m_maincpu, FUNC(m68000_device::berr_r), FUNC(m68000_device::berr_w));
map(0xb80000, 0xbfffff).ram();
//map(0xb00000, 0xbfffff).rw(FUNC(dpb7000_state::bus_error_r), FUNC(dpb7000_state::bus_error_w));
//map(0xb00000, 0xbfffff).rw(m_maincpu, FUNC(m68000_device::berr_r), FUNC(m68000_device::berr_w));
//map(0xfc0000, 0xffd3ff).ram();
map(0xffd000, 0xffd3ff).rw(FUNC(dpb7000_state::bus_error_r), FUNC(dpb7000_state::bus_error_w));
map(0xffd000, 0xffd3ff).rw(m_maincpu, FUNC(m68000_device::berr_r), FUNC(m68000_device::berr_w));
map(0xffe000, 0xffefff).ram().share("vduram").umask16(0x00ff);
map(0xfff801, 0xfff801).rw(m_crtc, FUNC(sy6545_1_device::status_r), FUNC(sy6545_1_device::address_w)).cswidth(16);
map(0xfff803, 0xfff803).rw(m_crtc, FUNC(sy6545_1_device::register_r), FUNC(sy6545_1_device::register_w)).cswidth(16);
@ -1160,29 +1157,6 @@ MC6845_ON_UPDATE_ADDR_CHANGED(dpb7000_state::crtc_addr_changed)
{
}
uint16_t dpb7000_state::bus_error_r(offs_t offset)
{
if(!machine().side_effects_disabled())
{
m68000_musashi_device *cpuptr = downcast<m68000_musashi_device *>(m_maincpu.target());
cpuptr->set_buserror_details(0xb00000 + offset*2, true, cpuptr->get_fc());
cpuptr->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
cpuptr->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
}
return 0xff;
}
void dpb7000_state::bus_error_w(offs_t offset, uint16_t data)
{
if(!machine().side_effects_disabled())
{
m68000_musashi_device *cpuptr = downcast<m68000_musashi_device *>(m_maincpu.target());
cpuptr->set_buserror_details(0xb00000 + offset*2, false, cpuptr->get_fc());
cpuptr->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
cpuptr->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
}
}
void dpb7000_state::csr_w(uint8_t data)
{
LOGMASKED(LOG_CSR, "%s: Card Select write: %02x (%04x)\n", machine().describe_context(), data & 0x0f, data);

3
src/mame/sega/fd1094.cpp
View File

@ -614,9 +614,6 @@ void fd1094_device::change_state(int newstate)
// notify of the state change
m_state_change(state());
// force a flush of the prefetch cache on any state change
set_state_int(M68K_PREF_ADDR, 0x0010);
}

2
src/mame/sega/megadriv.h
View File

@ -46,7 +46,7 @@ protected:
uint32_t screen_update_megadriv(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
DECLARE_WRITE_LINE_MEMBER(screen_vblank_megadriv);
required_device<m68000_base_device> m_maincpu;
required_device<m68000_device> m_maincpu;
required_device<timer_device> m_scan_timer;
required_device<sega315_5313_device> m_vdp;
optional_device<screen_device> m_screen;

2
src/mame/sega/model2.cpp
View File

@ -7308,7 +7308,7 @@ void model2_state::init_powsledm ()
u32 model2_state::doa_prot_r(offs_t offset, u32 mem_mask)
{
// doa only reads 16-bits at a time, while STV reads 32-bits
uint32 ret = 0;
uint32_t ret = 0;
if (mem_mask&0xffff0000) ret |= (m_0229crypt->data_r()<<16);
if (mem_mask&0x0000ffff) ret |= m_0229crypt->data_r();

6
src/mame/sega/model2.h
View File

@ -274,7 +274,7 @@ private:
bool m_render_unk = false;
bool m_render_mode = false;
bool m_render_test_mode = false;
int16 m_crtc_xoffset = 0, m_crtc_yoffset = 0;
int16_t m_crtc_xoffset = 0, m_crtc_yoffset = 0;
u32 *geo_process_command( geo_state *geo, u32 opcode, u32 *input, bool *end_code );
// geo commands
@ -660,8 +660,8 @@ public:
bitmap_rgb32& destmap() { return m_destmap; }
void model2_3d_render(triangle *tri, const rectangle &cliprect);
void set_xoffset(int16 xoffs) { m_xoffs = xoffs; }
void set_yoffset(int16 yoffs) { m_yoffs = yoffs; }
void set_xoffset(int16_t xoffs) { m_xoffs = xoffs; }
void set_yoffset(int16_t yoffs) { m_yoffs = yoffs; }
/* checker = 0, textured = 0, transparent = 0 */
#define MODEL2_FUNC 0

2
src/mame/sega/segahang.cpp
View File

@ -252,7 +252,7 @@ uint8_t segahang_state::sound_data_r()
uint8_t segahang_state::i8751_r(offs_t offset)
{
offs_t addr = (m_i8751_addr << 16) | (offset ^ 1);
uint8 data = m_maincpu->space(AS_PROGRAM).read_byte(addr);
uint8_t data = m_maincpu->space(AS_PROGRAM).read_byte(addr);
LOGMASKED(LOG_MCU, "i8751_r: %06x = %02x\n", addr, data);

4
src/mame/sega/stv.cpp
View File

@ -437,7 +437,7 @@ void stv_state::init_stv()
TODO: game doesn't work if not in debugger?
*/
uint32 stv_state::magzun_hef_hack_r()
uint32_t stv_state::magzun_hef_hack_r()
{
if(m_maincpu->pc()==0x604bf20) return 0x00000001; //HWEF
@ -929,7 +929,7 @@ uint32_t stv_state::decathlt_prot_r(offs_t offset, uint32_t mem_mask)
m_5838crypt->debug_helper(m_protbankval);
}
uint32 ret = 0;
uint32_t ret = 0;
if (mem_mask & 0xffff0000) ret |= (m_5838crypt->data_r()<<16);
if (mem_mask & 0x0000ffff) ret |= m_5838crypt->data_r();
return ret;

15
src/mame/skeleton/symbolics.cpp
View File

@ -101,8 +101,7 @@ public:
void init_symbolics();
private:
required_device<m68000_base_device> m_maincpu;
[[maybe_unused]] uint16_t buserror_r();
required_device<m68000_device> m_maincpu;
[[maybe_unused]] uint16_t fep_paddle_id_prom_r();
//uint16_t ram_parity_hack_r(offs_t offset);
//void ram_parity_hack_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
@ -118,16 +117,6 @@ private:
//TIMER_CALLBACK_MEMBER(outfifo_read_cb);
};
uint16_t symbolics_state::buserror_r()
{
if(!machine().side_effects_disabled())
{
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
}
return 0;
}
uint16_t symbolics_state::fep_paddle_id_prom_r() // bits 8 and 9 do something special if both are set.
{
return 0x0300;
@ -265,7 +254,7 @@ void symbolics_state::m68k_mem(address_map &map)
//map(0x020002, 0x03ffff).ram().region("fepdram", 0); /* Local FEP ram seems to be here? there are 18 mcm4164s on the pcb which probably map here, plus 2 parity bits? */
// 2x AM9128-10PC 2048x8 SRAMs @F7 and @G7 map somewhere
// 6x AM2148-50 1024x4bit SRAMs @F22-F27 map somewhere
//map(0x040000, 0xffffff).r(FUNC(symbolics_state::buserror_r));
//map(0x040000, 0xffffff).r(m_maincpu, FUNC(m68000_device::berr_r));
//map(0x800000, 0xffffff).ram(); /* paged access to lispm ram? */
//FF00B0 is readable, may be to read the MC/SQ/DP/AU continuity lines?
map(0xff00a0, 0xff00bf).rom().region("fep_paddle_prom",0);

27
src/mame/skeleton/wicat.cpp
View File

@ -86,8 +86,6 @@ private:
void send_key(uint8_t val);
uint16_t invalid_r(offs_t offset);
void invalid_w(offs_t offset, uint16_t data);
uint16_t memmap_r();
void memmap_w(uint16_t data);
DECLARE_WRITE_LINE_MEMBER(adir_w);
@ -148,7 +146,7 @@ void wicat_state::main_mem(address_map &map)
map(0x000000, 0x001fff).rom().region("c2", 0x0000);
map(0x020000, 0x1fffff).ram();
map(0x200000, 0x2fffff).ram();
map(0x300000, 0xdfffff).rw(FUNC(wicat_state::invalid_r), FUNC(wicat_state::invalid_w));
map(0x300000, 0xdfffff).rw(m_maincpu, FUNC(m68000_device::berr_r), FUNC(m68000_device::berr_w));
map(0xeff800, 0xeffbff).ram(); // memory mapping SRAM, used during boot sequence for storing various data (TODO)
map(0xeffc00, 0xeffc01).rw(FUNC(wicat_state::memmap_r), FUNC(wicat_state::memmap_w));
map(0xf00000, 0xf00007).rw(m_uart[0], FUNC(scn2661c_device::read), FUNC(scn2661c_device::write)).umask16(0xff00); // UARTs
@ -164,7 +162,7 @@ void wicat_state::main_mem(address_map &map)
map(0xf000d0, 0xf000d0).w("ledlatch", FUNC(ls259_device::write_nibble_d3));
map(0xf00180, 0xf0018f).rw(FUNC(wicat_state::hdc_r), FUNC(wicat_state::hdc_w)); // WD1000
map(0xf00190, 0xf0019f).rw(FUNC(wicat_state::fdc_r), FUNC(wicat_state::fdc_w)); // FD1795
map(0xf00f00, 0xf00fff).rw(FUNC(wicat_state::invalid_r), FUNC(wicat_state::invalid_w));
map(0xf00f00, 0xf00fff).rw(m_maincpu, FUNC(m68000_device::berr_r), FUNC(m68000_device::berr_w));
}
void wicat_state::video_mem(address_map &map)
@ -374,27 +372,6 @@ void wicat_state::via_b_w(uint8_t data)
logerror("VIA: write %02x to port B\n",data);
}
uint16_t wicat_state::invalid_r(offs_t offset)
{
if(!machine().side_effects_disabled())
{
m_maincpu->set_buserror_details(0x300000+offset*2-2,true,m_maincpu->get_fc());
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
}
return 0xff;
}
void wicat_state::invalid_w(offs_t offset, uint16_t data)
{
if(!machine().side_effects_disabled())
{
m_maincpu->set_buserror_details(0x300000+offset*2-2,false,m_maincpu->get_fc());
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
}
}
// TODO
uint16_t wicat_state::memmap_r()
{