mirror of
https://github.com/holub/mame
synced 2025-05-24 06:30:04 +03:00
Added function calls to replace the MIPS3 DRC's various CPU_SET_INFO
bits. Fixed DCS2 speedup handler so it doesn't get lost during a memory remap.
This commit is contained in:
Aaron Giles
parent
2f9ee68652
commit
75f0ff10d1
@ -225,6 +225,11 @@ struct _mips3_config
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PUBLIC FUNCTIONS
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***************************************************************************/
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void mips3drc_set_options(const device_config *device, UINT32 options);
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void mips3drc_add_fastram(const device_config *device, offs_t start, offs_t end, UINT8 readonly, void *base);
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void mips3drc_add_hotspot(const device_config *device, offs_t pc, UINT32 opcode, UINT32 cycles);
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#if (HAS_R4600)
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CPU_GET_INFO( r4600be );
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#define CPU_R4600BE CPU_GET_INFO_NAME( r4600be )
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@ -565,27 +565,9 @@ static CPU_DISASSEMBLE( mips3 )
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static CPU_SET_INFO( mips3 )
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{
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mips3_state *mips3 = *(mips3_state **)device->token;
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switch (state)
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{
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/* --- the following bits of info are set as 64-bit signed integers --- */
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case CPUINFO_INT_MIPS3_DRC_OPTIONS: mips3->impstate->drcoptions = info->i; break;
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case CPUINFO_INT_MIPS3_FASTRAM_SELECT: if (info->i >= 0 && info->i < MIPS3_MAX_FASTRAM) mips3->impstate->fastram_select = info->i; mips3->impstate->cache_dirty = TRUE; break;
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case CPUINFO_INT_MIPS3_FASTRAM_START: mips3->impstate->fastram[mips3->impstate->fastram_select].start = info->i; mips3->impstate->cache_dirty = TRUE; break;
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case CPUINFO_INT_MIPS3_FASTRAM_END: mips3->impstate->fastram[mips3->impstate->fastram_select].end = info->i; mips3->impstate->cache_dirty = TRUE; break;
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case CPUINFO_INT_MIPS3_FASTRAM_READONLY: mips3->impstate->fastram[mips3->impstate->fastram_select].readonly = info->i; mips3->impstate->cache_dirty = TRUE; break;
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case CPUINFO_INT_MIPS3_HOTSPOT_SELECT: if (info->i >= 0 && info->i < MIPS3_MAX_HOTSPOTS) mips3->impstate->hotspot_select = info->i; mips3->impstate->cache_dirty = TRUE; break;
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case CPUINFO_INT_MIPS3_HOTSPOT_PC: mips3->impstate->hotspot[mips3->impstate->hotspot_select].pc = info->i; mips3->impstate->cache_dirty = TRUE; break;
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case CPUINFO_INT_MIPS3_HOTSPOT_OPCODE: mips3->impstate->hotspot[mips3->impstate->hotspot_select].opcode = info->i; mips3->impstate->cache_dirty = TRUE; break;
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case CPUINFO_INT_MIPS3_HOTSPOT_CYCLES: mips3->impstate->hotspot[mips3->impstate->hotspot_select].cycles = info->i; mips3->impstate->cache_dirty = TRUE; break;
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/* --- the following bits of info are set as pointers to data or functions --- */
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case CPUINFO_PTR_MIPS3_FASTRAM_BASE: mips3->impstate->fastram[mips3->impstate->fastram_select].base = info->p; break;
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/* --- everything else is handled generically --- */
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default: mips3com_set_info(mips3, state, info); break;
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}
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/* --- everything is handled generically --- */
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mips3com_set_info(mips3, state, info);
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}
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@ -621,6 +603,53 @@ static CPU_GET_INFO( mips3 )
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}
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/*-------------------------------------------------
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mips3drc_set_options - configure DRC options
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-------------------------------------------------*/
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void mips3drc_set_options(const device_config *device, UINT32 options)
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{
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mips3_state *mips3 = *(mips3_state **)device->token;
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mips3->impstate->drcoptions = options;
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}
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/*-------------------------------------------------
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mips3drc_add_fastram - add a new fastram
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region
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-------------------------------------------------*/
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void mips3drc_add_fastram(const device_config *device, offs_t start, offs_t end, UINT8 readonly, void *base)
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{
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mips3_state *mips3 = *(mips3_state **)device->token;
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if (mips3->impstate->fastram_select < ARRAY_LENGTH(mips3->impstate->fastram))
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{
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mips3->impstate->fastram[mips3->impstate->fastram_select].start = start;
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mips3->impstate->fastram[mips3->impstate->fastram_select].end = end;
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mips3->impstate->fastram[mips3->impstate->fastram_select].readonly = readonly;
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mips3->impstate->fastram[mips3->impstate->fastram_select].base = base;
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mips3->impstate->fastram_select++;
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}
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}
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/*-------------------------------------------------
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mips3drc_add_hotspot - add a new hotspot
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-------------------------------------------------*/
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void mips3drc_add_hotspot(const device_config *device, offs_t pc, UINT32 opcode, UINT32 cycles)
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{
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mips3_state *mips3 = *(mips3_state **)device->token;
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if (mips3->impstate->hotspot_select < ARRAY_LENGTH(mips3->impstate->hotspot))
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{
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mips3->impstate->hotspot[mips3->impstate->hotspot_select].pc = pc;
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mips3->impstate->hotspot[mips3->impstate->hotspot_select].opcode = opcode;
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mips3->impstate->hotspot[mips3->impstate->hotspot_select].cycles = cycles;
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mips3->impstate->hotspot_select++;
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}
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}
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/***************************************************************************
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CACHE MANAGEMENT
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@ -288,6 +288,8 @@ struct _dcs_state
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const address_space *program;
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const address_space *data;
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UINT8 rev;
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offs_t polling_offset;
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UINT32 polling_count;
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/* sound output */
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UINT8 channels;
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@ -415,6 +417,7 @@ static void recompute_sample_rate(running_machine *machine);
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static void sound_tx_callback(const device_config *device, int port, INT32 data);
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static READ16_HANDLER( dcs_polling_r );
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static WRITE16_HANDLER( dcs_polling_w );
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static TIMER_CALLBACK( transfer_watchdog_callback );
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static int preprocess_write(running_machine *machine, UINT16 data);
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@ -1018,8 +1021,9 @@ void dcs2_init(running_machine *machine, int dram_in_mb, offs_t polling_offset)
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dcs.auto_ack = FALSE;
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/* install the speedup handler */
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dcs.polling_offset = polling_offset;
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if (polling_offset)
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dcs_polling_base = memory_install_read16_handler(cpu_get_address_space(dcs.cpu, ADDRESS_SPACE_DATA), polling_offset, polling_offset, 0, 0, dcs_polling_r);
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dcs_polling_base = memory_install_readwrite16_handler(cpu_get_address_space(dcs.cpu, ADDRESS_SPACE_DATA), polling_offset, polling_offset, 0, 0, dcs_polling_r, dcs_polling_w);
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/* allocate a watchdog timer for HLE transfers */
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transfer.hle_enabled = (ENABLE_HLE_TRANSFERS && dram_in_mb != 0);
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@ -1161,6 +1165,10 @@ static void sdrc_remap_memory(running_machine *machine)
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/* update the bank pointers */
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sdrc_update_bank_pointers(machine);
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/* reinstall the polling hotspot */
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if (dcs.polling_offset)
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dcs_polling_base = memory_install_readwrite16_handler(cpu_get_address_space(dcs.cpu, ADDRESS_SPACE_DATA), dcs.polling_offset, dcs.polling_offset, 0, 0, dcs_polling_r, dcs_polling_w);
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}
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@ -2058,11 +2066,19 @@ static void sound_tx_callback(const device_config *device, int port, INT32 data)
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static READ16_HANDLER( dcs_polling_r )
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{
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cpu_eat_cycles(space->cpu, 1000);
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if (dcs.polling_count++ > 5)
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cpu_eat_cycles(space->cpu, 10000);
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return *dcs_polling_base;
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}
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static WRITE16_HANDLER( dcs_polling_w )
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{
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dcs.polling_count = 0;
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COMBINE_DATA(dcs_polling_base);
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}
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/***************************************************************************
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DATA TRANSFER HLE MECHANISM
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@ -421,11 +421,6 @@ static INTERRUPT_GEN( n64_vblank )
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signal_rcp_interrupt(device->machine, VI_INTERRUPT);
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}
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static MACHINE_RESET( aleck64 )
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{
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n64_machine_reset(machine);
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}
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static MACHINE_DRIVER_START( aleck64 )
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/* basic machine hardware */
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MDRV_CPU_ADD("maincpu", R4600BE, 93750000)
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@ -437,7 +432,8 @@ static MACHINE_DRIVER_START( aleck64 )
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MDRV_CPU_CONFIG(n64_rsp_config)
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MDRV_CPU_PROGRAM_MAP(rsp_map, 0)
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MDRV_MACHINE_RESET( aleck64 )
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MDRV_MACHINE_START( n64 )
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MDRV_MACHINE_RESET( n64 )
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MDRV_SCREEN_ADD("screen", RASTER)
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MDRV_SCREEN_REFRESH_RATE(60)
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@ -1451,6 +1451,16 @@ static INTERRUPT_GEN( irq_start )
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}
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static MACHINE_START(hyperneo)
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{
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/* set the fastest DRC options */
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mips3drc_set_options(machine->cpu[0], MIPS3DRC_FASTEST_OPTIONS + MIPS3DRC_STRICT_VERIFY);
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/* configure fast RAM regions for DRC */
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mips3drc_add_fastram(machine->cpu[0], 0x00000000, 0x00ffffff, FALSE, hng_mainram);
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mips3drc_add_fastram(machine->cpu[0], 0x04000000, 0x05ffffff, TRUE, hng_cart);
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mips3drc_add_fastram(machine->cpu[0], 0x1fc00000, 0x1fc7ffff, TRUE, rombase);
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}
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static MACHINE_RESET(hyperneo)
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@ -1487,28 +1497,6 @@ static MACHINE_RESET(hyperneo)
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// "Display List" init - ugly
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activeBuffer = 0 ;
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/* set the fastest DRC options */
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device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_DRC_OPTIONS, MIPS3DRC_FASTEST_OPTIONS + MIPS3DRC_STRICT_VERIFY);
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/* configure fast RAM regions for DRC */
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device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_SELECT, 0);
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device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_START, 0x00000000);
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device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_END, 0x00ffffff);
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device_set_info_ptr(machine->cpu[0], CPUINFO_PTR_MIPS3_FASTRAM_BASE, hng_mainram);
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device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_READONLY, 0);
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device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_SELECT, 1);
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device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_START, 0x04000000);
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device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_END, 0x05ffffff);
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device_set_info_ptr(machine->cpu[0], CPUINFO_PTR_MIPS3_FASTRAM_BASE, hng_cart);
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device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_READONLY, 1);
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device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_SELECT, 2);
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device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_START, 0x1fc00000);
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device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_END, 0x1fc7ffff);
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device_set_info_ptr(machine->cpu[0], CPUINFO_PTR_MIPS3_FASTRAM_BASE, rombase);
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device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_READONLY, 1);
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}
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@ -1527,6 +1515,7 @@ static MACHINE_DRIVER_START( hng64 )
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MDRV_CPU_IO_MAP(hng_comm_io_map, 0)
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MDRV_GFXDECODE(hng64)
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MDRV_MACHINE_START(hyperneo)
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MDRV_MACHINE_RESET(hyperneo)
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MDRV_SCREEN_ADD("screen", RASTER)
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@ -190,26 +190,12 @@ static MACHINE_START( kinst )
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}
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/* set the fastest DRC options */
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device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_DRC_OPTIONS, MIPS3DRC_FASTEST_OPTIONS);
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mips3drc_set_options(machine->cpu[0], MIPS3DRC_FASTEST_OPTIONS);
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/* configure fast RAM regions for DRC */
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device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_SELECT, 0);
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device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_START, 0x08000000);
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device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_END, 0x087fffff);
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device_set_info_ptr(machine->cpu[0], CPUINFO_PTR_MIPS3_FASTRAM_BASE, rambase2);
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device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_READONLY, 0);
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device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_SELECT, 1);
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device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_START, 0x00000000);
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device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_END, 0x0007ffff);
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device_set_info_ptr(machine->cpu[0], CPUINFO_PTR_MIPS3_FASTRAM_BASE, rambase);
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device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_READONLY, 0);
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device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_SELECT, 2);
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device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_START, 0x1fc00000);
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device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_END, 0x1fc7ffff);
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device_set_info_ptr(machine->cpu[0], CPUINFO_PTR_MIPS3_FASTRAM_BASE, rombase);
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device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_READONLY, 1);
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mips3drc_add_fastram(machine->cpu[0], 0x08000000, 0x087fffff, FALSE, rambase2);
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mips3drc_add_fastram(machine->cpu[0], 0x00000000, 0x0007ffff, FALSE, rambase);
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mips3drc_add_fastram(machine->cpu[0], 0x1fc00000, 0x1fc7ffff, TRUE, rombase);
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}
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@ -456,8 +456,6 @@ static UINT32 *asic_reset;
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static UINT8 pending_analog_read;
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static UINT8 status_leds;
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static int speedup_index;
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static UINT32 cmos_write_enabled;
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@ -511,20 +509,11 @@ static MACHINE_START( seattle )
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galileo.timer[3].timer = timer_alloc(machine, galileo_timer_callback, NULL);
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/* set the fastest DRC options, but strict verification */
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device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_DRC_OPTIONS, MIPS3DRC_FASTEST_OPTIONS + MIPS3DRC_STRICT_VERIFY);
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mips3drc_set_options(machine->cpu[0], MIPS3DRC_FASTEST_OPTIONS + MIPS3DRC_STRICT_VERIFY);
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/* configure fast RAM regions for DRC */
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device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_SELECT, 0);
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device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_START, 0x00000000);
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device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_END, 0x007fffff);
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device_set_info_ptr(machine->cpu[0], CPUINFO_PTR_MIPS3_FASTRAM_BASE, rambase);
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device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_READONLY, 0);
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device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_SELECT, 1);
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device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_START, 0x1fc00000);
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device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_END, 0x1fc7ffff);
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device_set_info_ptr(machine->cpu[0], CPUINFO_PTR_MIPS3_FASTRAM_BASE, rombase);
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device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_READONLY, 1);
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mips3drc_add_fastram(machine->cpu[0], 0x00000000, 0x007fffff, FALSE, rambase);
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mips3drc_add_fastram(machine->cpu[0], 0x1fc00000, 0x1fc7ffff, TRUE, rombase);
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/* register for save states */
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state_save_register_global_array(machine, galileo.reg);
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@ -2806,17 +2795,6 @@ static void init_common(running_machine *machine, int ioasic, int serialnum, int
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memory_install_readwrite32_device_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), device, 0x16c00000, 0x16c0003f, 0, 0, ethernet_r, ethernet_w);
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break;
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}
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/* reset speedups */
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speedup_index = 0;
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}
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static void add_speedup(running_machine *machine, offs_t pc, UINT32 op)
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{
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device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_HOTSPOT_SELECT, speedup_index++);
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device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_HOTSPOT_PC, pc);
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device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_HOTSPOT_OPCODE, op);
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device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_HOTSPOT_CYCLES, 250);
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}
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@ -2826,9 +2804,9 @@ static DRIVER_INIT( wg3dh )
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init_common(machine, MIDWAY_IOASIC_STANDARD, 310/* others? */, 80, PHOENIX_CONFIG);
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/* speedups */
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add_speedup(machine, 0x8004413C, 0x0C0054B4); /* confirmed */
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add_speedup(machine, 0x80094930, 0x00A2102B); /* confirmed */
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add_speedup(machine, 0x80092984, 0x3C028011); /* confirmed */
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mips3drc_add_hotspot(machine->cpu[0], 0x8004413C, 0x0C0054B4, 250); /* confirmed */
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mips3drc_add_hotspot(machine->cpu[0], 0x80094930, 0x00A2102B, 250); /* confirmed */
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mips3drc_add_hotspot(machine->cpu[0], 0x80092984, 0x3C028011, 250); /* confirmed */
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}
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@ -2838,7 +2816,7 @@ static DRIVER_INIT( mace )
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init_common(machine, MIDWAY_IOASIC_MACE, 319/* others? */, 80, SEATTLE_CONFIG);
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/* speedups */
|
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add_speedup(machine, 0x800108F8, 0x8C420000); /* confirmed */
|
||||
mips3drc_add_hotspot(machine->cpu[0], 0x800108F8, 0x8C420000, 250); /* confirmed */
|
||||
}
|
||||
|
||||
|
||||
@ -2848,9 +2826,9 @@ static DRIVER_INIT( sfrush )
|
||||
init_common(machine, MIDWAY_IOASIC_STANDARD, 315/* no alternates */, 100, FLAGSTAFF_CONFIG);
|
||||
|
||||
/* speedups */
|
||||
add_speedup(machine, 0x80059F34, 0x3C028012); /* confirmed */
|
||||
add_speedup(machine, 0x800A5AF4, 0x8E300010); /* confirmed */
|
||||
add_speedup(machine, 0x8004C260, 0x3C028012); /* confirmed */
|
||||
mips3drc_add_hotspot(machine->cpu[0], 0x80059F34, 0x3C028012, 250); /* confirmed */
|
||||
mips3drc_add_hotspot(machine->cpu[0], 0x800A5AF4, 0x8E300010, 250); /* confirmed */
|
||||
mips3drc_add_hotspot(machine->cpu[0], 0x8004C260, 0x3C028012, 250); /* confirmed */
|
||||
}
|
||||
|
||||
|
||||
@ -2860,10 +2838,10 @@ static DRIVER_INIT( sfrushrk )
|
||||
init_common(machine, MIDWAY_IOASIC_SFRUSHRK, 331/* unknown */, 100, FLAGSTAFF_CONFIG);
|
||||
|
||||
/* speedups */
|
||||
add_speedup(machine, 0x800343E8, 0x3C028012); /* confirmed */
|
||||
add_speedup(machine, 0x8008F4F0, 0x3C028012); /* confirmed */
|
||||
add_speedup(machine, 0x800A365C, 0x8E300014); /* confirmed */
|
||||
add_speedup(machine, 0x80051DAC, 0x3C028012); /* confirmed */
|
||||
mips3drc_add_hotspot(machine->cpu[0], 0x800343E8, 0x3C028012, 250); /* confirmed */
|
||||
mips3drc_add_hotspot(machine->cpu[0], 0x8008F4F0, 0x3C028012, 250); /* confirmed */
|
||||
mips3drc_add_hotspot(machine->cpu[0], 0x800A365C, 0x8E300014, 250); /* confirmed */
|
||||
mips3drc_add_hotspot(machine->cpu[0], 0x80051DAC, 0x3C028012, 250); /* confirmed */
|
||||
}
|
||||
|
||||
|
||||
@ -2874,8 +2852,8 @@ static DRIVER_INIT( calspeed )
|
||||
midway_ioasic_set_auto_ack(1);
|
||||
|
||||
/* speedups */
|
||||
add_speedup(machine, 0x80032534, 0x02221024); /* confirmed */
|
||||
add_speedup(machine, 0x800B1BE4, 0x8E110014); /* confirmed */
|
||||
mips3drc_add_hotspot(machine->cpu[0], 0x80032534, 0x02221024, 250); /* confirmed */
|
||||
mips3drc_add_hotspot(machine->cpu[0], 0x800B1BE4, 0x8E110014, 250); /* confirmed */
|
||||
}
|
||||
|
||||
|
||||
@ -2885,9 +2863,9 @@ static DRIVER_INIT( vaportrx )
|
||||
init_common(machine, MIDWAY_IOASIC_VAPORTRX, 324/* 334? unknown */, 100, SEATTLE_WIDGET_CONFIG);
|
||||
|
||||
/* speedups */
|
||||
add_speedup(machine, 0x80049F14, 0x3C028020); /* confirmed */
|
||||
add_speedup(machine, 0x8004859C, 0x3C028020); /* confirmed */
|
||||
add_speedup(machine, 0x8005922C, 0x8E020014); /* confirmed */
|
||||
mips3drc_add_hotspot(machine->cpu[0], 0x80049F14, 0x3C028020, 250); /* confirmed */
|
||||
mips3drc_add_hotspot(machine->cpu[0], 0x8004859C, 0x3C028020, 250); /* confirmed */
|
||||
mips3drc_add_hotspot(machine->cpu[0], 0x8005922C, 0x8E020014, 250); /* confirmed */
|
||||
}
|
||||
|
||||
|
||||
@ -2909,8 +2887,8 @@ static DRIVER_INIT( blitz )
|
||||
rombase[0x934/4] += 4;
|
||||
|
||||
/* main CPU speedups */
|
||||
add_speedup(machine, 0x80135510, 0x3C028024); /* confirmed */
|
||||
add_speedup(machine, 0x800087DC, 0x8E820010); /* confirmed */
|
||||
mips3drc_add_hotspot(machine->cpu[0], 0x80135510, 0x3C028024, 250); /* confirmed */
|
||||
mips3drc_add_hotspot(machine->cpu[0], 0x800087DC, 0x8E820010, 250); /* confirmed */
|
||||
}
|
||||
|
||||
|
||||
@ -2920,8 +2898,8 @@ static DRIVER_INIT( blitz99 )
|
||||
init_common(machine, MIDWAY_IOASIC_BLITZ99, 481/* or 484 or 520 */, 80, SEATTLE_CONFIG);
|
||||
|
||||
/* speedups */
|
||||
add_speedup(machine, 0x8014E41C, 0x3C038025); /* confirmed */
|
||||
add_speedup(machine, 0x80011F10, 0x8E020018); /* confirmed */
|
||||
mips3drc_add_hotspot(machine->cpu[0], 0x8014E41C, 0x3C038025, 250); /* confirmed */
|
||||
mips3drc_add_hotspot(machine->cpu[0], 0x80011F10, 0x8E020018, 250); /* confirmed */
|
||||
}
|
||||
|
||||
|
||||
@ -2931,8 +2909,8 @@ static DRIVER_INIT( blitz2k )
|
||||
init_common(machine, MIDWAY_IOASIC_BLITZ99, 494/* or 498 */, 80, SEATTLE_CONFIG);
|
||||
|
||||
/* speedups */
|
||||
add_speedup(machine, 0x8015773C, 0x3C038025); /* confirmed */
|
||||
add_speedup(machine, 0x80012CA8, 0x8E020018); /* confirmed */
|
||||
mips3drc_add_hotspot(machine->cpu[0], 0x8015773C, 0x3C038025, 250); /* confirmed */
|
||||
mips3drc_add_hotspot(machine->cpu[0], 0x80012CA8, 0x8E020018, 250); /* confirmed */
|
||||
}
|
||||
|
||||
|
||||
@ -2945,8 +2923,8 @@ static DRIVER_INIT( carnevil )
|
||||
memory_install_readwrite32_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x16800000, 0x1680001f, 0, 0, carnevil_gun_r, carnevil_gun_w);
|
||||
|
||||
/* speedups */
|
||||
add_speedup(machine, 0x8015176C, 0x3C03801A); /* confirmed */
|
||||
add_speedup(machine, 0x80011FBC, 0x8E020018); /* confirmed */
|
||||
mips3drc_add_hotspot(machine->cpu[0], 0x8015176C, 0x3C03801A, 250); /* confirmed */
|
||||
mips3drc_add_hotspot(machine->cpu[0], 0x80011FBC, 0x8E020018, 250); /* confirmed */
|
||||
}
|
||||
|
||||
|
||||
@ -2956,9 +2934,9 @@ static DRIVER_INIT( hyprdriv )
|
||||
init_common(machine, MIDWAY_IOASIC_HYPRDRIV, 469/* unknown */, 80, SEATTLE_WIDGET_CONFIG);
|
||||
|
||||
/* speedups */
|
||||
add_speedup(machine, 0x801643BC, 0x3C03801B); /* confirmed */
|
||||
add_speedup(machine, 0x80011FB8, 0x8E020018); /* confirmed */
|
||||
//add_speedup(machine, 0x80136A80, 0x3C02801D); /* potential */
|
||||
mips3drc_add_hotspot(machine->cpu[0], 0x801643BC, 0x3C03801B, 250); /* confirmed */
|
||||
mips3drc_add_hotspot(machine->cpu[0], 0x80011FB8, 0x8E020018, 250); /* confirmed */
|
||||
//mips3drc_add_hotspot(machine->cpu[0], 0x80136A80, 0x3C02801D, 250); /* potential */
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -448,8 +448,6 @@
|
||||
static UINT32 *rambase, *rombase;
|
||||
static size_t ramsize;
|
||||
|
||||
static int speedup_index;
|
||||
|
||||
static UINT32 *nile_regs;
|
||||
static UINT16 nile_irq_state;
|
||||
static UINT16 ide_irq_state;
|
||||
@ -545,20 +543,11 @@ static MACHINE_START( vegas )
|
||||
dcs_idma_cs = 0;
|
||||
|
||||
/* set the fastest DRC options, but strict verification */
|
||||
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_DRC_OPTIONS, MIPS3DRC_FASTEST_OPTIONS + MIPS3DRC_STRICT_VERIFY + MIPS3DRC_FLUSH_PC);
|
||||
mips3drc_set_options(machine->cpu[0], MIPS3DRC_FASTEST_OPTIONS + MIPS3DRC_STRICT_VERIFY + MIPS3DRC_FLUSH_PC);
|
||||
|
||||
/* configure fast RAM regions for DRC */
|
||||
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_SELECT, 0);
|
||||
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_START, 0x00000000);
|
||||
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_END, ramsize - 1);
|
||||
device_set_info_ptr(machine->cpu[0], CPUINFO_PTR_MIPS3_FASTRAM_BASE, rambase);
|
||||
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_READONLY, 0);
|
||||
|
||||
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_SELECT, 1);
|
||||
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_START, 0x1fc00000);
|
||||
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_END, 0x1fc7ffff);
|
||||
device_set_info_ptr(machine->cpu[0], CPUINFO_PTR_MIPS3_FASTRAM_BASE, rombase);
|
||||
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_READONLY, 1);
|
||||
mips3drc_add_fastram(machine->cpu[0], 0x00000000, ramsize - 1, FALSE, rambase);
|
||||
mips3drc_add_fastram(machine->cpu[0], 0x1fc00000, 0x1fc7ffff, TRUE, rombase);
|
||||
|
||||
/* register for save states */
|
||||
state_save_register_global(machine, nile_irq_state);
|
||||
@ -2481,17 +2470,6 @@ static void init_common(running_machine *machine, int ioasic, int serialnum)
|
||||
/* allocate RAM for the timekeeper */
|
||||
timekeeper_nvram_size = 0x8000;
|
||||
timekeeper_nvram = auto_malloc(timekeeper_nvram_size);
|
||||
|
||||
/* reset speedups */
|
||||
speedup_index = 0;
|
||||
}
|
||||
|
||||
static void add_speedup(running_machine *machine, offs_t pc, UINT32 op)
|
||||
{
|
||||
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_HOTSPOT_SELECT, speedup_index++);
|
||||
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_HOTSPOT_PC, pc);
|
||||
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_HOTSPOT_OPCODE, op);
|
||||
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_HOTSPOT_CYCLES, 250);
|
||||
}
|
||||
|
||||
|
||||
@ -2501,10 +2479,10 @@ static DRIVER_INIT( gauntleg )
|
||||
init_common(machine, MIDWAY_IOASIC_CALSPEED, 340/* 340=39", 322=27", others? */);
|
||||
|
||||
/* speedups */
|
||||
add_speedup(machine, 0x80015430, 0x8CC38060); /* confirmed */
|
||||
add_speedup(machine, 0x80015464, 0x3C09801E); /* confirmed */
|
||||
add_speedup(machine, 0x800C8918, 0x8FA2004C); /* confirmed */
|
||||
add_speedup(machine, 0x800C8890, 0x8FA20024); /* confirmed */
|
||||
mips3drc_add_hotspot(machine->cpu[0], 0x80015430, 0x8CC38060, 250); /* confirmed */
|
||||
mips3drc_add_hotspot(machine->cpu[0], 0x80015464, 0x3C09801E, 250); /* confirmed */
|
||||
mips3drc_add_hotspot(machine->cpu[0], 0x800C8918, 0x8FA2004C, 250); /* confirmed */
|
||||
mips3drc_add_hotspot(machine->cpu[0], 0x800C8890, 0x8FA20024, 250); /* confirmed */
|
||||
}
|
||||
|
||||
|
||||
@ -2514,10 +2492,10 @@ static DRIVER_INIT( gauntdl )
|
||||
init_common(machine, MIDWAY_IOASIC_GAUNTDL, 346/* 347, others? */);
|
||||
|
||||
/* speedups */
|
||||
add_speedup(machine, 0x800158B8, 0x8CC3CC40); /* confirmed */
|
||||
add_speedup(machine, 0x800158EC, 0x3C0C8022); /* confirmed */
|
||||
add_speedup(machine, 0x800D40C0, 0x8FA2004C); /* confirmed */
|
||||
add_speedup(machine, 0x800D4038, 0x8FA20024); /* confirmed */
|
||||
mips3drc_add_hotspot(machine->cpu[0], 0x800158B8, 0x8CC3CC40, 250); /* confirmed */
|
||||
mips3drc_add_hotspot(machine->cpu[0], 0x800158EC, 0x3C0C8022, 250); /* confirmed */
|
||||
mips3drc_add_hotspot(machine->cpu[0], 0x800D40C0, 0x8FA2004C, 250); /* confirmed */
|
||||
mips3drc_add_hotspot(machine->cpu[0], 0x800D4038, 0x8FA20024, 250); /* confirmed */
|
||||
}
|
||||
|
||||
|
||||
@ -2527,7 +2505,7 @@ static DRIVER_INIT( warfa )
|
||||
init_common(machine, MIDWAY_IOASIC_MACE, 337/* others? */);
|
||||
|
||||
/* speedups */
|
||||
add_speedup(machine, 0x8009436C, 0x0C031663); /* confirmed */
|
||||
mips3drc_add_hotspot(machine->cpu[0], 0x8009436C, 0x0C031663, 250); /* confirmed */
|
||||
}
|
||||
|
||||
|
||||
@ -2537,10 +2515,10 @@ static DRIVER_INIT( tenthdeg )
|
||||
init_common(machine, MIDWAY_IOASIC_GAUNTDL, 330/* others? */);
|
||||
|
||||
/* speedups */
|
||||
add_speedup(machine, 0x80051CD8, 0x0C023C15); /* confirmed */
|
||||
add_speedup(machine, 0x8005E674, 0x3C028017); /* confirmed */
|
||||
add_speedup(machine, 0x8002DBCC, 0x8FA2002C); /* confirmed */
|
||||
add_speedup(machine, 0x80015930, 0x8FC20244); /* confirmed */
|
||||
mips3drc_add_hotspot(machine->cpu[0], 0x80051CD8, 0x0C023C15, 250); /* confirmed */
|
||||
mips3drc_add_hotspot(machine->cpu[0], 0x8005E674, 0x3C028017, 250); /* confirmed */
|
||||
mips3drc_add_hotspot(machine->cpu[0], 0x8002DBCC, 0x8FA2002C, 250); /* confirmed */
|
||||
mips3drc_add_hotspot(machine->cpu[0], 0x80015930, 0x8FC20244, 250); /* confirmed */
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -84,6 +84,7 @@ extern WRITE32_HANDLER( n64_si_reg_w );
|
||||
extern READ32_HANDLER( n64_pif_ram_r );
|
||||
extern WRITE32_HANDLER( n64_pif_ram_w );
|
||||
|
||||
void n64_machine_reset(running_machine *machine);
|
||||
MACHINE_START( n64 );
|
||||
MACHINE_RESET( n64 );
|
||||
|
||||
#endif
|
||||
|
||||
@ -1567,7 +1567,15 @@ WRITE32_HANDLER( n64_pif_ram_w )
|
||||
|
||||
//static UINT16 crc_seed = 0x3f;
|
||||
|
||||
void n64_machine_reset(running_machine *machine)
|
||||
MACHINE_START( n64 )
|
||||
{
|
||||
mips3drc_set_options(machine->cpu[0], MIPS3DRC_FASTEST_OPTIONS + MIPS3DRC_STRICT_VERIFY);
|
||||
|
||||
/* configure fast RAM regions for DRC */
|
||||
mips3drc_add_fastram(machine->cpu[0], 0x00000000, 0x007fffff, FALSE, rdram);
|
||||
}
|
||||
|
||||
MACHINE_RESET( n64 )
|
||||
{
|
||||
int i;
|
||||
//UINT32 *pif_rom = (UINT32*)memory_region(machine, "user1");
|
||||
@ -1623,15 +1631,6 @@ void n64_machine_reset(running_machine *machine)
|
||||
|
||||
cic_status = 0;
|
||||
|
||||
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_DRC_OPTIONS, MIPS3DRC_FASTEST_OPTIONS + MIPS3DRC_STRICT_VERIFY);
|
||||
|
||||
/* configure fast RAM regions for DRC */
|
||||
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_SELECT, 0);
|
||||
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_START, 0x00000000);
|
||||
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_END, 0x007fffff);
|
||||
device_set_info_ptr(machine->cpu[0], CPUINFO_PTR_MIPS3_FASTRAM_BASE, rdram);
|
||||
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_READONLY, 0);
|
||||
|
||||
audio_timer = timer_alloc(machine, audio_timer_callback, NULL);
|
||||
timer_adjust_oneshot(audio_timer, attotime_never, 0);
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user