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https://github.com/holub/mame
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MCS51 additions
* Implemented cmos features: powerdown & idle * Added comments about special function registers on Philips 80C52 * cleaned up reset routines
This commit is contained in:
Couriersud
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c911e7c3a8
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@ -70,7 +70,6 @@
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*
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* - Implement 80C52 extended serial capabilities
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* - Full Timer support (all modes)
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* - Implement cmos features
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* - Fix serial communication - This is a big hack (but working) right now.
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* - Implement 83C751 in sslam.c
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* - Fix cardline.c
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@ -81,6 +80,7 @@
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* a 0 written to it's latch. At least cardline expects a 1 here.
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*
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* Done:
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* - Implemented cmos features
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* - Implemented 80C52 interrupt handling
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* - Fix segas18.c (segaic16.c) memory handling.
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* - Fix sslam.c
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@ -116,9 +116,8 @@ enum
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{
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FEATURE_NONE = 0x00,
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FEATURE_I8052 = 0x01,
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FEATURE_CMOS_IDLE = 0x02,
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FEATURE_CMOS_POWERDOWN = 0x04,
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FEATURE_I80C52 = 0x08,
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FEATURE_CMOS = 0x02,
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FEATURE_I80C52 = 0x04,
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};
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/* Internal address in SFR of registers */
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@ -158,6 +157,11 @@ enum
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ADDR_IPH = 0xb7,
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ADDR_SADDR = 0xa9,
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ADDR_SADEN = 0xb9,
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/* Philips 80C52 */
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AUXR = 0x8e,
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AUXR1 = 0xa2,
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};
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/* PC vectors */
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@ -329,6 +333,22 @@ struct _mcs51_regs
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#define SADDR SFR_A(ADDR_SADDR)
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#define SADEN SFR_A(ADDR_SADEN)
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/* Philips 80C52 */
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/* ============= */
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/* Reduced EMI Mode
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* The AO bit (AUXR.0) in the AUXR register when set disables the
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* ALE output.
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*/
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#define AUXR SFR_A(ADDR_AUXR)
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/* The dual DPTR structure (see Figure 12) is a way by which the
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* 80C52/54/58 will specify the address of an external data memory
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* location. There are two 16-bit DPTR registers that address the
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* external memory, and a single bit called DPS = AUXR1/bit0 that
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* allows the program code to switch between them.
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*/
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#define AUXR1 SFR_A(ADDR_AUXR1)
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/* WRITE accessors */
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/* Shortcuts */
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@ -420,6 +440,11 @@ struct _mcs51_regs
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#define SET_CT2(n) SET_BIT(T2CON, 1, n) //Sets Timer 2 Counter/Timer Mode
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#define SET_CP(n) SET_BIT(T2CON, 0, n) //Sets Timer 2 Capture/Reload Mode
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#define SET_GF1(n) SET_BIT(PCON, 3, n)
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#define SET_GF0(n) SET_BIT(PCON, 2, n)
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#define SET_PD(n) SET_BIT(PCON, 1, n)
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#define SET_IDL(n) SET_BIT(PCON, 0, n)
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/* Macros for accessing flags */
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#define GET_CY GET_BIT(PSW, 7)
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@ -477,10 +502,10 @@ struct _mcs51_regs
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/* Only in 80C51BH & other cmos */
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#define GET_GF1 GET_BIT(TMOD, 3)
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#define GET_GF0 GET_BIT(TMOD, 2)
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#define GET_PD GET_BIT(TMOD, 1)
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#define GET_IDL GET_BIT(TMOD, 0)
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#define GET_GF1 GET_BIT(PCON, 3)
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#define GET_GF0 GET_BIT(PCON, 2)
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#define GET_PD GET_BIT(PCON, 1)
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#define GET_IDL (GET_BIT(PCON, 0) & ~(GET_PD)) /* PD takes precedence! */
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/* 8052 Only flags */
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#define GET_TF2 GET_BIT(T2CON, 7)
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@ -1478,6 +1503,16 @@ static void check_irqs(void)
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if (!ints) return;
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/* CLear IDL - got enabled interrupt */
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if (mcs51.features & FEATURE_CMOS)
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{
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/* any interrupt terminates idle mode */
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SET_IDL(0);
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/* external interrupt wakes up */
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if (ints & (GET_IE0 | GET_IE1))
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SET_PD(0);
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}
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for (i=0; i<mcs51.num_interrupts; i++)
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{
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if (ints & (1<<i))
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@ -1493,6 +1528,7 @@ static void check_irqs(void)
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/* Skip the interrupt request if currently processing interrupt
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* and the new request does not have a higher priority
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*/
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if(mcs51.irq_active && (priority_request <= mcs51.cur_irq_prio))
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{
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LOG(("higher or equal priority irq in progress already, skipping ...\n"));
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@ -1683,9 +1719,28 @@ static int mcs51_execute(int cycles)
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/* external interrupts may have been set since we last checked */
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mcs51.inst_cycles = 0;
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check_irqs();
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/* if in powerdown, just return */
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if ((mcs51.features & FEATURE_CMOS) && GET_PD)
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{
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mcs51_icount = 0;
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return cycles;
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}
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mcs51_icount -= mcs51.inst_cycles;
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burn_cycles(mcs51.inst_cycles);
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if ((mcs51.features & FEATURE_CMOS) && GET_IDL)
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{
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do
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{
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/* burn the cycles */
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mcs51_icount--;
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burn_cycles(1);
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} while( mcs51_icount > 0 );
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return cycles - mcs51_icount;
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}
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do
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{
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/* Read next opcode */
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@ -1820,7 +1875,7 @@ static void i80c51_init(int index, int clock, const void *config, int (*irqcallb
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{
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mcs51_init(index, clock, config, irqcallback);
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mcs51.features |= (FEATURE_CMOS_IDLE | FEATURE_CMOS_POWERDOWN);
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mcs51.features |= FEATURE_CMOS;
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}
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/* Reset registers to the initial values */
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@ -1856,6 +1911,7 @@ static void mcs51_reset(void)
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SCON = 0;
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TCON = 0;
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TMOD = 0;
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PCON = 0;
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TH1 = 0;
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TH0 = 0;
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TL1 = 0;
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@ -1866,6 +1922,26 @@ static void mcs51_reset(void)
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SET_P1(0xff);
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SET_P0(0xff);
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/* 8052 Only registers */
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if (mcs51.features & FEATURE_I8052)
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{
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T2CON = 0;
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RCAP2L = 0;
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RCAP2H = 0;
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TL2 = 0;
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TH2 = 0;
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}
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/* 80C52 Only registers */
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if (mcs51.features & FEATURE_I80C52)
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{
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IPH = 0;
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update_irq_prio(IP, IPH);
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SADDR = 0;
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SADEN = 0;
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}
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}
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/* Shut down CPU core */
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@ -1924,18 +2000,6 @@ static void i8052_init (int index, int clock, const void *config, int (*irqcallb
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mcs51.sfr_write = i8052_sfr_write;
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}
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static void i8052_reset(void)
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{
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mcs51_reset();
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//8052 Only registers
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T2CON = 0;
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RCAP2L = 0;
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RCAP2H = 0;
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TL2 = 0;
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TH2 = 0;
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}
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/****************************************************************************
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* 80C52 Section
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****************************************************************************/
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@ -1980,7 +2044,7 @@ static void i80c52_init(int index, int clock, const void *config, int (*irqcallb
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{
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i8052_init(index, clock, config, irqcallback);
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mcs51.features |= (FEATURE_I80C52 | FEATURE_CMOS_IDLE | FEATURE_CMOS_POWERDOWN);
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mcs51.features |= (FEATURE_I80C52 | FEATURE_CMOS);
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mcs51.sfr_read = i80c52_sfr_read;
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mcs51.sfr_write = i80c52_sfr_write;
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}
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@ -1992,14 +2056,6 @@ static void i80c31_init(int index, int clock, const void *config, int (*irqcallb
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mcs51.ram_mask = 0x7F; /* 128 bytes of ram */
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}
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static void i80c52_reset(void)
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{
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i8052_reset();
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IRAM_W(ADDR_IPH, 0);
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SADDR = 0;
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SADEN = 0;
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}
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/***************************************************************************
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ADDRESS MAPS
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@ -2226,7 +2282,6 @@ void i8032_get_info(UINT32 state, cpuinfo *info)
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switch (state)
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{
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case CPUINFO_PTR_INIT: info->init = i8052_init; break;
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case CPUINFO_PTR_RESET: info->reset = i8052_reset; break;
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case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_DATA: info->internal_map8 = address_map_data_8bit; break;
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@ -2241,7 +2296,6 @@ void i8052_get_info(UINT32 state, cpuinfo *info)
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switch (state)
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{
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case CPUINFO_PTR_INIT: info->init = i8052_init; break;
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case CPUINFO_PTR_RESET: info->reset = i8052_reset; break;
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case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_PROGRAM: info->internal_map8 = address_map_program_13bit; break;
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case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_DATA: info->internal_map8 = address_map_data_8bit; break;
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@ -2270,7 +2324,6 @@ void i8752_get_info(UINT32 state, cpuinfo *info)
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switch (state)
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{
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case CPUINFO_PTR_INIT: info->init = i8052_init; break;
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case CPUINFO_PTR_RESET: info->reset = i8052_reset; break;
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case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_PROGRAM: info->internal_map8 = address_map_program_13bit; break;
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case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_DATA: info->internal_map8 = address_map_data_8bit; break;
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@ -2292,7 +2345,6 @@ void i80c31_get_info(UINT32 state, cpuinfo *info)
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switch (state)
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{
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case CPUINFO_PTR_INIT: info->init = i80c31_init; break;
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case CPUINFO_PTR_RESET: info->reset = i80c52_reset; break;
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case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_PROGRAM: info->internal_map8 = NULL; break;
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case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_DATA: info->internal_map8 = address_map_data_7bit; break;
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@ -2317,7 +2369,6 @@ void i80c32_get_info(UINT32 state, cpuinfo *info)
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switch (state)
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{
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case CPUINFO_PTR_INIT: info->init = i80c52_init; break;
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case CPUINFO_PTR_RESET: info->reset = i80c52_reset; break;
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case CPUINFO_STR_NAME: strcpy(info->s, "I80C32"); break;
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default: i8032_get_info(state, info); break;
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}
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@ -2328,7 +2379,6 @@ void i80c52_get_info(UINT32 state, cpuinfo *info)
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switch (state)
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{
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case CPUINFO_PTR_INIT: info->init = i80c52_init; break;
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case CPUINFO_PTR_RESET: info->reset = i80c52_reset; break;
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case CPUINFO_STR_NAME: strcpy(info->s, "I80C52"); break;
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default: i8052_get_info(state, info); break;
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}
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@ -2349,7 +2399,6 @@ void i87c52_get_info(UINT32 state, cpuinfo *info)
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switch (state)
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{
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case CPUINFO_PTR_INIT: info->init = i80c52_init; break;
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case CPUINFO_PTR_RESET: info->reset = i80c52_reset; break;
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case CPUINFO_STR_NAME: strcpy(info->s, "I87C52"); break;
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default: i8752_get_info(state, info); break;
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}
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@ -89,10 +89,11 @@ void i8752_get_info(UINT32 state, cpuinfo *info);
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/* cmos variants */
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void i80c31_get_info(UINT32 state, cpuinfo *info);
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void i80c32_get_info(UINT32 state, cpuinfo *info);
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void i80c51_get_info(UINT32 state, cpuinfo *info);
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void i80c52_get_info(UINT32 state, cpuinfo *info);
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void i87c51_get_info(UINT32 state, cpuinfo *info);
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void i80c32_get_info(UINT32 state, cpuinfo *info);
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void i80c52_get_info(UINT32 state, cpuinfo *info);
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void i87c52_get_info(UINT32 state, cpuinfo *info);
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/* 4k internal perom and 128 internal ram and 2 analog comparators */
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