mirror of
https://github.com/holub/mame
synced 2025-10-04 16:34:53 +03:00
Spacing cleanups.
This commit is contained in:
Aaron Giles
parent
2d19847752
commit
76278ddf02
@ -72,7 +72,7 @@ static const double bb_engine_gains[16] =
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/*
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8253 Programmable Interval Timer
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8253 Programmable Interval Timer
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*/
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static struct
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{
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@ -90,35 +90,35 @@ static struct
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} pit8253;
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/*
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Port A Port B
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====== ======
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Port A Port B
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====== ======
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0: Engine 1 gain (FR) #0 0: Coin Counter 1
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1: Engine 1 gain (FR) #1 1: Coin Counter 2
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2: Engine 1 gain (FR) #2 2: Coin Counter 3 (Unused)
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3: Engine 1 gain (FR) #3 3: Engine 0 gain
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4: Engine 1 gain (FL) #0 4: Noise EN1
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5: Engine 1 gain (FL) #1 5: Noise EN2
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6: Engine 1 gain (FL) #2 6: Enable YM IC24 output on RR
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7: Engine 1 gain (FL) #3 7: Enable YM IC19 output on RL
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0: Engine 1 gain (FR) #0 0: Coin Counter 1
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1: Engine 1 gain (FR) #1 1: Coin Counter 2
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2: Engine 1 gain (FR) #2 2: Coin Counter 3 (Unused)
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3: Engine 1 gain (FR) #3 3: Engine 0 gain
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4: Engine 1 gain (FL) #0 4: Noise EN1
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5: Engine 1 gain (FL) #1 5: Noise EN2
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6: Engine 1 gain (FL) #2 6: Enable YM IC24 output on RR
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7: Engine 1 gain (FL) #3 7: Enable YM IC19 output on RL
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The engine sounds are generated by an 8253. There are two channels.
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The engine sounds are generated by an 8253. There are two channels.
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#0 is the player's buggy
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#1 is the opponents' buggies
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#0 is the player's buggy
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#1 is the opponents' buggies
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+------------> GAIN[1] +--> FL
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| +--> FR
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+------------> GAIN[1] +--> FL
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| +--> FR
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8255 #0 --+--> BL
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+--> BR
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+--> BR
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8255 #1 --+--> GAIN[2] ---> FL
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+--> GAIN[3] ---> FR
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8255 #1 --+--> GAIN[2] ---> FL
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+--> GAIN[3] ---> FR
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[1] is used to amplify sound during tunnel.
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[2] and [3] are stereo fades
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[2] and [3] are stereo fades
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*/
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@ -201,7 +201,7 @@ static void tx1_stream_update(void *param, stream_sample_t **inputs, stream_samp
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}
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/*
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This is admittedly a bit of a hack job...
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This is admittedly a bit of a hack job...
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*/
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static void buggyboy_stream_update(void *param, stream_sample_t **inputs, stream_sample_t **buffer, int length)
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{
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@ -100,7 +100,7 @@ static READ32_HANDLER( cmos_r )
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static WRITE32_HANDLER( zpram_w )
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{
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/* ZPRAM seems to use the same protection control as CMOS */
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// if (!cmos_protected)
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// if (!cmos_protected)
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COMBINE_DATA(zpram + offset);
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cmos_protected = TRUE;
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}
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@ -279,12 +279,12 @@ static READ32_HANDLER( unknown_8d0000_r )
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}
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static WRITE32_HANDLER( unknown_8d0000_w )
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{
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// logerror("%06X:write to %06X = %08X\n", activecpu_get_pc(), 0x8d0000 + offset, data);
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// logerror("%06X:write to %06X = %08X\n", activecpu_get_pc(), 0x8d0000 + offset, data);
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COMBINE_DATA(&unknown_8d0000[offset]);
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}
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static WRITE32_HANDLER( unknown_9d0000_w )
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{
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// logerror("%06X:write to %06X = %08X\n", activecpu_get_pc(), 0x9d0000 + offset, data);
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// logerror("%06X:write to %06X = %08X\n", activecpu_get_pc(), 0x9d0000 + offset, data);
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COMBINE_DATA(&unknown_8d0000[offset]);
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}
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@ -480,7 +480,7 @@ static ADDRESS_MAP_START( tharrier_writemem, ADDRESS_SPACE_PROGRAM, 16 )
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// AM_RANGE(0x080018, 0x080019) AM_WRITE(nmk_tilebank_w)
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AM_RANGE(0x08001e, 0x08001f) AM_WRITE(soundlatch_word_w)
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AM_RANGE(0x088000, 0x0883ff) AM_WRITE(paletteram16_RRRRGGGGBBBBRGBx_word_w) AM_BASE(&paletteram16)
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// AM_RANGE(0x08c000, 0x08c007) AM_WRITE(nmk_scroll_w)
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// AM_RANGE(0x08c000, 0x08c007) AM_WRITE(nmk_scroll_w)
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AM_RANGE(0x090000, 0x093fff) AM_WRITE(nmk_bgvideoram_w) AM_BASE(&nmk_bgvideoram)
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AM_RANGE(0x09c000, 0x09c7ff) AM_WRITE(MWA16_NOP) /* Unused txvideoram area? */
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AM_RANGE(0x09d000, 0x09d7ff) AM_WRITE(nmk_txvideoram_w) AM_BASE(&nmk_txvideoram)
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@ -635,7 +635,7 @@ anything to compare,infact
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/*
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static READ16_HANDLER( mcu_shared_r )
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{
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return nmk16_mcu_shared_ram[offset];
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return nmk16_mcu_shared_ram[offset];
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}
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*/
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@ -840,11 +840,11 @@ static WRITE16_HANDLER( tdragon_mainram_w )
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static ADDRESS_MAP_START( tdragon_readmem, ADDRESS_SPACE_PROGRAM, 16 )
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AM_RANGE(0x000000, 0x03ffff) AM_READ(MRA16_ROM)
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AM_RANGE(0x044022, 0x044023) AM_READ(MRA16_NOP) /* No Idea */
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// AM_RANGE(0x0b0000, 0x0b7fff) AM_READ(MRA16_RAM) /* Work RAM */
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// AM_RANGE(0x0b8000, 0x0b8fff) AM_READ(MRA16_RAM) /* Sprite RAM */
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// AM_RANGE(0x0b9000, 0x0bdfff) AM_READ(MRA16_RAM) /* Work RAM */
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// AM_RANGE(0x0be000, 0x0befff) AM_READ(MRA16_RAM) /* Work RAM */
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// AM_RANGE(0x0bf000, 0x0bffff) AM_READ(MRA16_RAM) /* Work RAM */
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// AM_RANGE(0x0b0000, 0x0b7fff) AM_READ(MRA16_RAM) /* Work RAM */
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// AM_RANGE(0x0b8000, 0x0b8fff) AM_READ(MRA16_RAM) /* Sprite RAM */
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// AM_RANGE(0x0b9000, 0x0bdfff) AM_READ(MRA16_RAM) /* Work RAM */
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// AM_RANGE(0x0be000, 0x0befff) AM_READ(MRA16_RAM) /* Work RAM */
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// AM_RANGE(0x0bf000, 0x0bffff) AM_READ(MRA16_RAM) /* Work RAM */
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AM_RANGE(0x0b0000, 0x0bffff) AM_RAM AM_WRITE( tdragon_mainram_w ) AM_BASE(&nmk16_mainram)
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@ -860,11 +860,11 @@ ADDRESS_MAP_END
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static ADDRESS_MAP_START( tdragon_writemem, ADDRESS_SPACE_PROGRAM, 16 )
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AM_RANGE(0x000000, 0x03ffff) AM_WRITE(MWA16_ROM)
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// AM_RANGE(0x0b0000, 0x0b7fff) AM_WRITE(MWA16_RAM) /* Work RAM */
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// AM_RANGE(0x0b8000, 0x0b8fff) AM_WRITE(MWA16_RAM) AM_BASE(&spriteram16) AM_SIZE(&spriteram_size) /* Sprite RAM */
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// AM_RANGE(0x0b9000, 0x0bdfff) AM_WRITE(MWA16_RAM) AM_BASE(&nmk16_mcu_work_ram) /* Work RAM */
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// AM_RANGE(0x0be000, 0x0befff) AM_RAM AM_READWRITE(mcu_shared_r,tdragon_mcu_shared_w) AM_BASE(&nmk16_mcu_shared_ram) /* Work RAM */
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// AM_RANGE(0x0bf000, 0x0bffff) AM_WRITE(MWA16_RAM) /* Work RAM */
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// AM_RANGE(0x0b0000, 0x0b7fff) AM_WRITE(MWA16_RAM) /* Work RAM */
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// AM_RANGE(0x0b8000, 0x0b8fff) AM_WRITE(MWA16_RAM) AM_BASE(&spriteram16) AM_SIZE(&spriteram_size) /* Sprite RAM */
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// AM_RANGE(0x0b9000, 0x0bdfff) AM_WRITE(MWA16_RAM) AM_BASE(&nmk16_mcu_work_ram) /* Work RAM */
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// AM_RANGE(0x0be000, 0x0befff) AM_RAM AM_READWRITE(mcu_shared_r,tdragon_mcu_shared_w) AM_BASE(&nmk16_mcu_shared_ram) /* Work RAM */
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// AM_RANGE(0x0bf000, 0x0bffff) AM_WRITE(MWA16_RAM) /* Work RAM */
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AM_RANGE(0x0c0014, 0x0c0015) AM_WRITE(nmk_flipscreen_w) /* Maybe */
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AM_RANGE(0x0c0018, 0x0c0019) AM_WRITE(nmk_tilebank_w) /* Tile Bank ? */
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AM_RANGE(0x0c001e, 0x0c001f) AM_WRITE(NMK004_w)
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@ -7,27 +7,27 @@
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Games supported:
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* TX-1 (1983) [2 sets]
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* Buggy Boy (1985)
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* Buggy Boy Junior (1986)
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* Buggy Boy Junior (1986)
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Notes:
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* 'buggyboy' and 'tx1' are preliminary
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* 'buggyboy' set is using ROMs from 'buggybjr' for testing purposes
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until the original set can be dumped.
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Notes:
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* 'buggyboy' and 'tx1' are preliminary
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* 'buggyboy' set is using ROMs from 'buggybjr' for testing purposes
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until the original set can be dumped.
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****************************************************************************
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Buggy Boy Error Codes TX-1 Error Codes
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===================== ================
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Buggy Boy Error Codes TX-1 Error Codes
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===================== ================
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1 Main CPU RAM 1 Main microprocessor RAM
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2 Video (character) RAM 2 Video RAM
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3 Road/common RAM 3 Common RAM
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4 Sound RAM 4 Sound RAM
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5 Main CPU ROM 5 Main microprocessor ROM
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6 Sound ROM 6 Sound ROM
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8 Auxillary ROM 10 Interface ROM (time-out error)
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12 Arithmetic unit 11 Common RAM (access for arithmetic CPU)
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22 Main 8086-Z80 timeout 12 Common RAM (access for arithmetic CPU)
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1 Main CPU RAM 1 Main microprocessor RAM
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2 Video (character) RAM 2 Video RAM
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3 Road/common RAM 3 Common RAM
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4 Sound RAM 4 Sound RAM
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5 Main CPU ROM 5 Main microprocessor ROM
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6 Sound ROM 6 Sound ROM
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8 Auxillary ROM 10 Interface ROM (time-out error)
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12 Arithmetic unit 11 Common RAM (access for arithmetic CPU)
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22 Main 8086-Z80 timeout 12 Common RAM (access for arithmetic CPU)
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13 Arithmetic RAM
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14 Common RAM (access for arithmetic CPU)
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15 Object RAM
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@ -353,18 +353,18 @@ static READ16_HANDLER( dipswitches_r )
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}
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/*
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(TODO) TS: Connected in place of dipswitch A bit 0
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Accessed on startup as some sort of acknowledgement
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(TODO) TS: Connected in place of dipswitch A bit 0
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Accessed on startup as some sort of acknowledgement
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*/
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static WRITE8_HANDLER( ts_w )
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{
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// TS = 1;
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// TS = 1;
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z80_ram[offset] = data;
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}
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static READ8_HANDLER( ts_r )
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{
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// TS = 1;
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// TS = 1;
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return z80_ram[offset];
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}
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@ -659,7 +659,7 @@ static struct CustomSound_interface bb_custom_interface =
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static MACHINE_DRIVER_START( tx1 )
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MDRV_CPU_ADD(I8086, 5000000)
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MDRV_CPU_PROGRAM_MAP(tx1_main, 0)
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// MDRV_WATCHDOG_TIME_INIT(5)
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// MDRV_WATCHDOG_TIME_INIT(5)
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MDRV_CPU_ADD(I8086,5000000)
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MDRV_CPU_PROGRAM_MAP(tx1_math, 0)
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@ -699,7 +699,7 @@ static MACHINE_DRIVER_START( tx1 )
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MDRV_VIDEO_UPDATE(tx1)
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MDRV_SPEAKER_STANDARD_STEREO("Front Left", "Front Right")
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// MDRV_SPEAKER_STANDARD_STEREO("Rear Left", "Rear Right")
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// MDRV_SPEAKER_STANDARD_STEREO("Rear Left", "Rear Right")
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MDRV_SOUND_ADD(AY8910, TX1_PIXEL_CLOCK / 8)
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MDRV_SOUND_CONFIG(tx1_ay8910_interface)
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@ -716,7 +716,7 @@ MACHINE_DRIVER_END
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static MACHINE_DRIVER_START( buggyboy )
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MDRV_CPU_ADD(BUGGYBOY_CPU_TYPE, 5000000)
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MDRV_CPU_PROGRAM_MAP(buggyboy_main, 0)
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// MDRV_WATCHDOG_TIME_INIT(5)
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// MDRV_WATCHDOG_TIME_INIT(5)
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MDRV_CPU_ADD(BUGGYBOY_CPU_TYPE, 5000000)
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MDRV_CPU_PROGRAM_MAP(buggyboy_math, 0)
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@ -753,7 +753,7 @@ static MACHINE_DRIVER_START( buggyboy )
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MDRV_VIDEO_UPDATE(buggyboy)
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MDRV_SPEAKER_STANDARD_STEREO("Front Left", "Front Right")
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// MDRV_SPEAKER_STANDARD_STEREO("Rear Left", "Rear Right")
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// MDRV_SPEAKER_STANDARD_STEREO("Rear Left", "Rear Right")
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MDRV_SOUND_ADD(YM2149, BUGGYBOY_ZCLK / 4)
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MDRV_SOUND_CONFIG(buggyboy_ym2149_interface_1)
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@ -773,7 +773,7 @@ MACHINE_DRIVER_END
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static MACHINE_DRIVER_START( buggybjr )
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MDRV_CPU_ADD(BUGGYBOY_CPU_TYPE, 5000000)
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MDRV_CPU_PROGRAM_MAP(buggybjr_main, 0)
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// MDRV_WATCHDOG_TIME_INIT(5)
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// MDRV_WATCHDOG_TIME_INIT(5)
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MDRV_CPU_ADD(BUGGYBOY_CPU_TYPE, 5000000)
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MDRV_CPU_PROGRAM_MAP(buggyboy_math, 0)
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@ -807,7 +807,7 @@ static MACHINE_DRIVER_START( buggybjr )
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MDRV_VIDEO_EOF(buggyboy)
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MDRV_SPEAKER_STANDARD_STEREO("Front Left", "Front Right")
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// MDRV_SPEAKER_STANDARD_STEREO("Rear Left", "Rear Right")
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// MDRV_SPEAKER_STANDARD_STEREO("Rear Left", "Rear Right")
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MDRV_SOUND_ADD(YM2149, BUGGYBOY_ZCLK / 4)
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MDRV_SOUND_CONFIG(buggyboy_ym2149_interface_1)
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@ -9,17 +9,17 @@
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#include "tx1.h"
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/*
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6845 cursor output is connected to the main CPU interrupt pin.
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The CRTC is programmed to provide a rudimentary VBLANK interrupt.
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6845 cursor output is connected to the main CPU interrupt pin.
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The CRTC is programmed to provide a rudimentary VBLANK interrupt.
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TODO: Calc TX-1 values...
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TODO: Calc TX-1 values...
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*/
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#define CURSOR_YPOS 239
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#define CURSOR_XPOS 168
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/*
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Globals
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Globals
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*/
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static UINT16 *prom;
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@ -41,7 +41,7 @@ static struct
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} math;
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/*
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Helper functions
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Helper functions
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*/
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#define INC_PROM_ADDR ( math.promaddr = (math.promaddr + 1) & 0x1ff )
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#define ROR16(val, shift) ( ((UINT16)val >> shift) | ((UINT16)val << (16 - shift)) )
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@ -59,7 +59,7 @@ INLINE UINT8 reverse_nibble(UINT8 nibble)
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/*
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TODO: Check interrupt timing from CRT config. Probably different between games.
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TODO: Check interrupt timing from CRT config. Probably different between games.
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*/
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static TIMER_CALLBACK( interrupt_callback )
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{
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@ -68,7 +68,7 @@ static TIMER_CALLBACK( interrupt_callback )
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}
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/*
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SN74S516 16x16 Multiplier/Divider
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SN74S516 16x16 Multiplier/Divider
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*/
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static struct
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{
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@ -91,11 +91,11 @@ static struct
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} SN74S516;
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/*
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State transition table
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State transition table
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A little different to the real thing in that
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there are no states between final input and
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multiplication/division.
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A little different to the real thing in that
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there are no states between final input and
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multiplication/division.
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*/
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static const UINT8 state_table[16][8] =
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{
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@ -259,8 +259,8 @@ static void kick_sn74s516(UINT16 *data, const int ins)
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#define CLEAR_SEQUENCE (SN74S516.code = 0)
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/*
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Remember to change the Z/W flag.
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*/
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Remember to change the Z/W flag.
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*/
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switch (SN74S516.state)
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{
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case 0:
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@ -477,11 +477,11 @@ static void tx1_update_state(void)
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go = 1;
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}
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/*
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Example:
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120 /GO /LHIEN
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121 /GO /LLOEN
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Both 120 and 121 are used.
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*/
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Example:
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120 /GO /LHIEN
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121 /GO /LLOEN
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Both 120 and 121 are used.
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*/
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else if ( (GO_EN(math.inslatch) && GO_EN(prom[math.promaddr])) && (LHIEN(math.inslatch) && LLOEN(prom[math.promaddr])) )
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{
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go = 1;
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@ -512,8 +512,8 @@ static void tx1_update_state(void)
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UINT16 data;
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int dsel = (math.inslatch >> 8) & TX1_DSEL;
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// int tfad = (math.inslatch & 0x1c00);
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// int ps = math.ppshift & 0x78;
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// int tfad = (math.inslatch & 0x1c00);
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// int ps = math.ppshift & 0x78;
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if ( (dsel & 1) == 0 )
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@ -539,9 +539,9 @@ static void tx1_update_state(void)
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kick_sn74s516(&data, ins);
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}
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/*
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TODO: Changed ppshift to muxlatch for TX-1
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Changed masks.
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*/
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TODO: Changed ppshift to muxlatch for TX-1
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Changed masks.
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*/
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else if ( LHIEN(math.inslatch) || LLOEN(math.inslatch) )
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{
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UINT16 data;
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@ -635,29 +635,29 @@ READ16_HANDLER( tx1_math_r )
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{
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||||
|
||||
/* TODO
|
||||
SEL0 = 1 (DSEL = 0 or ???????)
|
||||
DSEL1 = 0
|
||||
*/
|
||||
SEL0 = 1 (DSEL = 0 or ???????)
|
||||
DSEL1 = 0
|
||||
*/
|
||||
int dsel = (math.inslatch >> 8) & TX1_DSEL;
|
||||
// int tfad = (math.inslatch & 0x1c00);
|
||||
// int ps = math.ppshift & 0x78;
|
||||
// int tfad = (math.inslatch & 0x1c00);
|
||||
// int ps = math.ppshift & 0x78;
|
||||
|
||||
/*
|
||||
Actual MUX selects
|
||||
00 Straight from DLATCH
|
||||
01 Straight from ROM
|
||||
10 << 4
|
||||
11 Halves swapped, << 3
|
||||
Actual MUX selects
|
||||
00 Straight from DLATCH
|
||||
01 Straight from ROM
|
||||
10 << 4
|
||||
11 Halves swapped, << 3
|
||||
|
||||
If DSEL = x0, MUX = x1
|
||||
If DSEL = x0, MUX = x1
|
||||
|
||||
00 -> 01
|
||||
00 -> 01
|
||||
|
||||
10 -> 11
|
||||
10 -> 11
|
||||
|
||||
10 = 11
|
||||
00 = 01
|
||||
*/
|
||||
10 = 11
|
||||
00 = 01
|
||||
*/
|
||||
|
||||
// TEST!
|
||||
if ( (dsel & 1) == 0 )
|
||||
@ -672,9 +672,9 @@ READ16_HANDLER( tx1_math_r )
|
||||
else if ( dsel == 1 )
|
||||
{
|
||||
/*
|
||||
TODO make this constant somewhere
|
||||
e.g. math.retval = math.romptr[ get_tx1_datarom_addr() ];
|
||||
*/
|
||||
TODO make this constant somewhere
|
||||
e.g. math.retval = math.romptr[ get_tx1_datarom_addr() ];
|
||||
*/
|
||||
UINT16 *romdata = (UINT16*)memory_region(REGION_USER1);
|
||||
UINT16 addr = get_tx1_datarom_addr();
|
||||
math.retval = romdata[addr];
|
||||
@ -736,7 +736,7 @@ WRITE16_HANDLER( tx1_math_w )
|
||||
math.cpulatch = data;
|
||||
offset <<= 1;
|
||||
|
||||
// printf("W %x: %x\n", 0x3000 + offset, data);
|
||||
// printf("W %x: %x\n", 0x3000 + offset, data);
|
||||
|
||||
/* /MLPCS */
|
||||
if ( offset < 0x400 )
|
||||
@ -1124,7 +1124,7 @@ READ16_HANDLER( buggyboy_math_r )
|
||||
|
||||
/* TODO */
|
||||
//if (math.mux == BB_MUX_PPSEN)
|
||||
// math.ppshift = math.retval;
|
||||
// math.ppshift = math.retval;
|
||||
}
|
||||
/* /PPSEN */
|
||||
else if ( offset < 0x800 )
|
||||
@ -1261,7 +1261,7 @@ WRITE16_HANDLER( buggyboy_math_w )
|
||||
}
|
||||
|
||||
/*
|
||||
This is for ROM range 0x5000-0x7fff
|
||||
This is for ROM range 0x5000-0x7fff
|
||||
*/
|
||||
READ16_HANDLER( buggyboy_spcs_rom_r )
|
||||
{
|
||||
|
||||
@ -1047,7 +1047,7 @@ if (
|
||||
|
||||
|
||||
/* do a simple backface cull; not sure if the hardware does it, but I see no other
|
||||
reason for a polygon normal here */
|
||||
reason for a polygon normal here */
|
||||
|
||||
/* extract the polygon normal */
|
||||
normal[0] = (INT8)(databuffer[0] >> 0);
|
||||
@ -1062,8 +1062,8 @@ if (
|
||||
{
|
||||
if (logit)
|
||||
logerror("quad (culled %08X)\n", rotnormal[2]);
|
||||
// if (input_code_pressed(KEYCODE_COMMA))
|
||||
// return;
|
||||
// if (input_code_pressed(KEYCODE_COMMA))
|
||||
// return;
|
||||
}
|
||||
|
||||
if (logit)
|
||||
@ -1342,8 +1342,8 @@ static void render_poly_solid(void *dest, INT32 scanline, const poly_extent *ext
|
||||
if (depth > 0x7fff) depth = 0x7fff;
|
||||
if (depth >= 0)
|
||||
{
|
||||
// UINT32 finalcolor = (((color & 0x7c00) * curv) & 0x7c000000) | (((color & 0x03e0) * curv) & 0x03e00000) | (((color & 0x001f) * curv) & 0x001f0000);
|
||||
// waveram_plot_check_depth(scanline, x, finalcolor >> 16, depth);
|
||||
// UINT32 finalcolor = (((color & 0x7c00) * curv) & 0x7c000000) | (((color & 0x03e0) * curv) & 0x03e00000) | (((color & 0x001f) * curv) & 0x001f0000);
|
||||
// waveram_plot_check_depth(scanline, x, finalcolor >> 16, depth);
|
||||
waveram_plot_check_depth(scanline, x, color, depth);
|
||||
}
|
||||
curz += dzdx;
|
||||
|
||||
@ -388,8 +388,8 @@ static void zeus_register32_w(offs_t offset, UINT32 data, int logit)
|
||||
UINT32 oldval = zeusbase[offset];
|
||||
|
||||
/* writes to register $CC need to force a partial update */
|
||||
// if ((offset & ~1) == 0xcc)
|
||||
// video_screen_update_partial(0, video_screen_get_vpos(0));
|
||||
// if ((offset & ~1) == 0xcc)
|
||||
// video_screen_update_partial(0, video_screen_get_vpos(0));
|
||||
|
||||
/* always write to low word? */
|
||||
zeusbase[offset] = data;
|
||||
@ -424,11 +424,11 @@ static void zeus_register_update(offs_t offset, UINT32 oldval, int logit)
|
||||
case 0x20:
|
||||
/* toggles between two values based on the page:
|
||||
|
||||
Page # zeusbase[0x20] zeusbase[0x38]
|
||||
------ -------------- --------------
|
||||
0 $04000190 $00000000
|
||||
1 $04000000 $01900000
|
||||
*/
|
||||
Page # zeusbase[0x20] zeusbase[0x38]
|
||||
------ -------------- --------------
|
||||
0 $04000190 $00000000
|
||||
1 $04000000 $01900000
|
||||
*/
|
||||
break;
|
||||
|
||||
case 0x33:
|
||||
@ -489,12 +489,12 @@ static void zeus_register_update(offs_t offset, UINT32 oldval, int logit)
|
||||
if (zeusbase[0x40] == 0x00890000)
|
||||
{
|
||||
/*
|
||||
zeusbase[0x4e]:
|
||||
bit 0-1: which register triggers write through
|
||||
bit 3: enable write through via these registers
|
||||
bit 4: seems to be set during reads, when 0x41 is used for latching
|
||||
bit 6: enable autoincrement on write through
|
||||
*/
|
||||
zeusbase[0x4e]:
|
||||
bit 0-1: which register triggers write through
|
||||
bit 3: enable write through via these registers
|
||||
bit 4: seems to be set during reads, when 0x41 is used for latching
|
||||
bit 6: enable autoincrement on write through
|
||||
*/
|
||||
if ((zeusbase[0x4e] & 0x08) && (offset & 3) == (zeusbase[0x4e] & 3))
|
||||
{
|
||||
void *dest = waveram_ptr_from_expanded_addr(0, zeusbase[0x41]);
|
||||
@ -566,13 +566,13 @@ static void zeus_register_update(offs_t offset, UINT32 oldval, int logit)
|
||||
if (zeusbase[0x50] == 0x00890000)
|
||||
{
|
||||
/*
|
||||
zeusbase[0x5e]:
|
||||
bit 0-1: which register triggers write through
|
||||
bit 3: enable write through via these registers
|
||||
bit 4: seems to be set during reads, when 0x51 is used for latching
|
||||
bit 5: unknown, currently used to specify ordering, but this is suspect
|
||||
bit 6: enable autoincrement on write through
|
||||
*/
|
||||
zeusbase[0x5e]:
|
||||
bit 0-1: which register triggers write through
|
||||
bit 3: enable write through via these registers
|
||||
bit 4: seems to be set during reads, when 0x51 is used for latching
|
||||
bit 5: unknown, currently used to specify ordering, but this is suspect
|
||||
bit 6: enable autoincrement on write through
|
||||
*/
|
||||
if ((zeusbase[0x5e] & 0x08) && (offset & 3) == (zeusbase[0x5e] & 3))
|
||||
{
|
||||
void *dest = waveram_ptr_from_expanded_addr(1, zeusbase[0x51]);
|
||||
|
||||
@ -846,12 +846,12 @@ VIDEO_UPDATE( bjtwin )
|
||||
VIDEO_EOF( nmk )
|
||||
{
|
||||
/* sprites are DMA'd from Main RAM to a private buffer automatically
|
||||
(or at least this is how I interpret the datasheet) */
|
||||
(or at least this is how I interpret the datasheet) */
|
||||
|
||||
/* -- I actually see little evidence to support this, sprite lag
|
||||
in some games should be checked on real boards */
|
||||
in some games should be checked on real boards */
|
||||
|
||||
// memcpy(spriteram_old2,spriteram_old,0x1000);
|
||||
// memcpy(spriteram_old2,spriteram_old,0x1000);
|
||||
memcpy(spriteram_old2,nmk16_mainram+0x8000/2,0x1000);
|
||||
}
|
||||
|
||||
|
||||
@ -12,7 +12,7 @@
|
||||
#define PRINT_CRTC_DATA 1
|
||||
|
||||
/*
|
||||
HD46505S-2 CRT Controller
|
||||
HD46505S-2 CRT Controller
|
||||
*/
|
||||
READ16_HANDLER( tx1_crtc_r )
|
||||
{
|
||||
@ -519,9 +519,9 @@ VIDEO_UPDATE( tx1 )
|
||||
{
|
||||
rectangle rect = { 0, 768 - 1, 0, 240 - 1 };
|
||||
|
||||
// tilemap_set_scrollx(tx1_tilemap, 0, scroll);
|
||||
// tilemap_set_scrollx(tx1_tilemap, 0, scroll);
|
||||
tilemap_draw(tx1_bitmap, &rect, tx1_tilemap, 0, 0);
|
||||
// tx1_draw_road(tx1_bitmap, &rect);
|
||||
// tx1_draw_road(tx1_bitmap, &rect);
|
||||
tx1_draw_objects(tx1_bitmap, &rect);
|
||||
}
|
||||
|
||||
@ -961,9 +961,9 @@ static void buggybjr_draw_road(UINT8 *bitmap)
|
||||
else
|
||||
{
|
||||
/*
|
||||
TODO: When ROM is not enabled, data = 0xff
|
||||
But does anybody care?
|
||||
*/
|
||||
TODO: When ROM is not enabled, data = 0xff
|
||||
But does anybody care?
|
||||
*/
|
||||
rc0 = rc1 = rc2 = rc3 = 0;
|
||||
}
|
||||
|
||||
@ -1008,8 +1008,8 @@ static void buggybjr_draw_road(UINT8 *bitmap)
|
||||
px3 = BIT(rc3, pix);
|
||||
|
||||
/*
|
||||
Uh oh...
|
||||
*/
|
||||
Uh oh...
|
||||
*/
|
||||
if (vp2)
|
||||
ic4_o18 = (hps00 && hps01 && hp3_en && !hps30) ||
|
||||
(!hp0_en && hps01 && hp3_en && !hps30) ||
|
||||
@ -1210,24 +1210,24 @@ static void buggybjr_draw_road(UINT8 *bitmap)
|
||||
|
||||
/***************************************************************************
|
||||
|
||||
Buggy Boy Object Drawing
|
||||
Buggy Boy Object Drawing
|
||||
|
||||
X-scaling isn't quite right but you wouldn't notice...
|
||||
X-scaling isn't quite right but you wouldn't notice...
|
||||
|
||||
-------- xxxxxxxx Object number
|
||||
xxxxxxxx -------- Y position
|
||||
-------- xxxxxxxx Object number
|
||||
xxxxxxxx -------- Y position
|
||||
|
||||
xxxxxxxx xxxxxxxx Y scale value
|
||||
xxxxxxxx xxxxxxxx Y scale value
|
||||
|
||||
-------- xxxxxxxx X scale
|
||||
00 = Invisible?
|
||||
80 = 1:1
|
||||
FF = Double size
|
||||
xxxxxxxx -------- Attributes
|
||||
-------- xxxxxxxx X scale
|
||||
00 = Invisible?
|
||||
80 = 1:1
|
||||
FF = Double size
|
||||
xxxxxxxx -------- Attributes
|
||||
|
||||
xxxxxxxx xxxxxxxx Y scale delta
|
||||
xxxxxxxx xxxxxxxx Y scale delta
|
||||
|
||||
------xx xxxxxxxx X position
|
||||
------xx xxxxxxxx X position
|
||||
|
||||
**************************************************************************/
|
||||
static void buggyboy_draw_objs(UINT8 *bitmap)
|
||||
@ -1361,11 +1361,11 @@ static void buggyboy_draw_objs(UINT8 *bitmap)
|
||||
UINT32 low_addr = ((x_acc >> (FRAC + 3)) & MASK);
|
||||
|
||||
/*
|
||||
Objects are grouped by width (either 16, 8 or 4 tiles) in
|
||||
the LUT ROMs. The ROM address lines therefore indicate
|
||||
width and are used to determine the correct scan order
|
||||
when x-flip is set.
|
||||
*/
|
||||
Objects are grouped by width (either 16, 8 or 4 tiles) in
|
||||
the LUT ROMs. The ROM address lines therefore indicate
|
||||
width and are used to determine the correct scan order
|
||||
when x-flip is set.
|
||||
*/
|
||||
if (gxflip)
|
||||
{
|
||||
UINT32 xor_mask;
|
||||
@ -1477,16 +1477,16 @@ static void buggyboy_draw_objs(UINT8 *bitmap)
|
||||
|
||||
|
||||
/*
|
||||
2400-24FF is road control (R/W)
|
||||
2400-24FF is road control (R/W)
|
||||
|
||||
/GAS = 24XX:
|
||||
/BASET0 = 2400-F, 2410-F
|
||||
/BASET1 = 2420-F, 2430-F
|
||||
/BSET = 2440-F, 2450-F
|
||||
/HASET = 2460-F, 2470-F
|
||||
/HSET = 2480-F, 2490-F
|
||||
/WASET = 24A0-F, 24B0-F
|
||||
/FLAGS = 24E0-F, 24F0-F
|
||||
/GAS = 24XX:
|
||||
/BASET0 = 2400-F, 2410-F
|
||||
/BASET1 = 2420-F, 2430-F
|
||||
/BSET = 2440-F, 2450-F
|
||||
/HASET = 2460-F, 2470-F
|
||||
/HSET = 2480-F, 2490-F
|
||||
/WASET = 24A0-F, 24B0-F
|
||||
/FLAGS = 24E0-F, 24F0-F
|
||||
*/
|
||||
WRITE16_HANDLER( buggyboy_gas_w )
|
||||
{
|
||||
@ -1621,7 +1621,7 @@ VIDEO_START( buggybjr )
|
||||
}
|
||||
|
||||
/*
|
||||
Draw the tilemap with scrolling
|
||||
Draw the tilemap with scrolling
|
||||
*/
|
||||
static void buggyboy_draw_char(UINT8 *bitmap)
|
||||
{
|
||||
|
||||
@ -9,4 +9,4 @@
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
const char build_version[] = "0.122 ("__DATE__")";
|
||||
const char build_version[] = "0.122u1 ("__DATE__")";
|
||||
|
||||
Loading…
Reference in New Issue
Block a user