mirror of
https://github.com/holub/mame
synced 2025-06-30 16:00:01 +03:00
-cdi.cpp: Switched SERVO and SLAVE MCUs to use the correct device type with internal maps. [Ryan Holtz]
This commit is contained in:
MooglyGuy
parent
9672337a76
commit
7673e5260f
@ -48,8 +48,9 @@ TODO:
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#define LOG_SERVO (1 << 0)
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#define LOG_SLAVE (1 << 1)
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#define LOG_ALL (LOG_SERVO | LOG_SLAVE)
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#define VERBOSE (0)
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#define VERBOSE (LOG_ALL)
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#include "logmacro.h"
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#define ENABLE_UART_PRINTING (0)
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@ -117,21 +118,6 @@ void cdi_state::cdi910_mem(address_map &map)
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}
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void cdi_state::cdimono2_servo_mem(address_map &map)
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{
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map(0x0000, 0x001f).rw(FUNC(cdi_state::servo_io_r), FUNC(cdi_state::servo_io_w));
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map(0x0050, 0x00ff).ram();
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map(0x0100, 0x1fff).rom().region("servo", 0x100);
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}
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void cdi_state::cdimono2_slave_mem(address_map &map)
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{
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map(0x0000, 0x001f).rw(FUNC(cdi_state::slave_io_r), FUNC(cdi_state::slave_io_w));
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map(0x0050, 0x00ff).ram();
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map(0x0100, 0x1fff).rom().region("slave", 0x100);
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}
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/*************************
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* Input ports *
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*************************/
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@ -273,8 +259,6 @@ MACHINE_RESET_MEMBER( cdi_state, cdimono1 )
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uint16_t *src = (uint16_t*)memregion("maincpu")->base();
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uint16_t *dst = m_planea;
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memcpy(dst, src, 0x8);
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memset(m_servo_io_regs, 0, 0x20);
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memset(m_slave_io_regs, 0, 0x20);
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// Quizard Protection HLE data
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memset(m_seeds, 0, 10 * sizeof(uint16_t));
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@ -497,407 +481,6 @@ void cdi_state::quizard_handle_byte_tx(uint8_t data)
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}
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/**************************
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* 68HC05 Handlers *
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**************************/
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READ8_MEMBER( cdi_state::servo_io_r )
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{
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if (machine().side_effects_disabled())
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{
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return 0;
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}
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uint8_t ret = m_servo_io_regs[offset];
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switch(offset)
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{
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case m68hc05eg_io_reg_t::PORT_A_DATA:
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LOGMASKED(LOG_SERVO, "SERVO Port A Data read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::PORT_B_DATA:
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ret = 0x08;
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LOGMASKED(LOG_SERVO, "SERVO Port B Data read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::PORT_C_DATA:
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ret |= INV_CADDYSWITCH_IN;
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LOGMASKED(LOG_SERVO, "SERVO Port C Data read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::PORT_D_INPUT:
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LOGMASKED(LOG_SERVO, "SERVO Port D Input read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::PORT_A_DDR:
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LOGMASKED(LOG_SERVO, "SERVO Port A DDR read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::PORT_B_DDR:
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LOGMASKED(LOG_SERVO, "SERVO Port B DDR read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::PORT_C_DDR:
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LOGMASKED(LOG_SERVO, "SERVO Port C DDR read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::SPI_CTRL:
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LOGMASKED(LOG_SERVO, "SERVO SPI Control read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::SPI_STATUS:
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LOGMASKED(LOG_SERVO, "SERVO SPI Status read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::SPI_DATA:
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LOGMASKED(LOG_SERVO, "SERVO SPI Data read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::SCC_BAUD:
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LOGMASKED(LOG_SERVO, "SERVO SCC Baud Rate read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::SCC_CTRL1:
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LOGMASKED(LOG_SERVO, "SERVO SCC Control 1 read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::SCC_CTRL2:
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LOGMASKED(LOG_SERVO, "SERVO SCC Control 2 read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::SCC_STATUS:
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LOGMASKED(LOG_SERVO, "SERVO SCC Status read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::SCC_DATA:
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LOGMASKED(LOG_SERVO, "SERVO SCC Data read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::TIMER_CTRL:
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LOGMASKED(LOG_SERVO, "SERVO Timer Control read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::TIMER_STATUS:
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LOGMASKED(LOG_SERVO, "SERVO Timer Status read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::ICAP_HI:
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LOGMASKED(LOG_SERVO, "SERVO Input Capture Hi read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::ICAP_LO:
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LOGMASKED(LOG_SERVO, "SERVO Input Capture Lo read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::OCMP_HI:
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LOGMASKED(LOG_SERVO, "SERVO Output Compare Hi read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::OCMP_LO:
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LOGMASKED(LOG_SERVO, "SERVO Output Compare Lo read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::COUNT_HI:
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{
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const uint16_t count = (m_servo->total_cycles() / 4) & 0x0000ffff;
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ret = count >> 8;
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LOGMASKED(LOG_SERVO, "SERVO Count Hi read (%02x)\n", ret);
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break;
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}
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case m68hc05eg_io_reg_t::COUNT_LO:
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{
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const uint16_t count = (m_servo->total_cycles() / 4) & 0x0000ffff;
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ret = count & 0x00ff;
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LOGMASKED(LOG_SERVO, "SERVO Count Lo read (%02x)\n", ret);
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break;
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}
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case m68hc05eg_io_reg_t::ACOUNT_HI:
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{
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const uint16_t count = (m_servo->total_cycles() / 4) & 0x0000ffff;
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ret = count >> 8;
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LOGMASKED(LOG_SERVO, "SERVO Alternate Count Hi read (%02x)\n", ret);
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break;
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}
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case m68hc05eg_io_reg_t::ACOUNT_LO:
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{
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const uint16_t count = (m_servo->total_cycles() / 4) & 0x0000ffff;
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ret = count & 0x00ff;
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LOGMASKED(LOG_SERVO, "SERVO Alternate Count Lo read (%02x)\n", ret);
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break;
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}
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default:
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logerror("Unknown SERVO I/O read (%02x)\n", offset);
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break;
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}
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return ret;
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}
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WRITE8_MEMBER( cdi_state::servo_io_w )
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{
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switch(offset)
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{
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case m68hc05eg_io_reg_t::PORT_A_DATA:
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LOGMASKED(LOG_SERVO, "SERVO Port A Data write (%02x)\n", data);
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return;
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case m68hc05eg_io_reg_t::PORT_B_DATA:
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LOGMASKED(LOG_SERVO, "SERVO Port B Data write (%02x)\n", data);
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return;
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case m68hc05eg_io_reg_t::PORT_C_DATA:
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LOGMASKED(LOG_SERVO, "SERVO Port C Data write (%02x)\n", data);
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return;
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case m68hc05eg_io_reg_t::PORT_D_INPUT:
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LOGMASKED(LOG_SERVO, "SERVO Port D Input write (%02x)\n", data);
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return;
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case m68hc05eg_io_reg_t::PORT_A_DDR:
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LOGMASKED(LOG_SERVO, "SERVO Port A DDR write (%02x)\n", data);
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break;
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case m68hc05eg_io_reg_t::PORT_B_DDR:
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LOGMASKED(LOG_SERVO, "SERVO Port B DDR write (%02x)\n", data);
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break;
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case m68hc05eg_io_reg_t::PORT_C_DDR:
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LOGMASKED(LOG_SERVO, "SERVO Port C DDR write (%02x)\n", data);
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break;
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case m68hc05eg_io_reg_t::SPI_CTRL:
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LOGMASKED(LOG_SERVO, "SERVO SPI Control write (%02x)\n", data);
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break;
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case m68hc05eg_io_reg_t::SPI_STATUS:
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LOGMASKED(LOG_SERVO, "SERVO SPI Status write (%02x)\n", data);
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break;
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case m68hc05eg_io_reg_t::SPI_DATA:
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LOGMASKED(LOG_SERVO, "SERVO SPI Data write (%02x)\n", data);
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break;
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case m68hc05eg_io_reg_t::SCC_BAUD:
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LOGMASKED(LOG_SERVO, "SERVO SCC Baud Rate write (%02x)\n", data);
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break;
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case m68hc05eg_io_reg_t::SCC_CTRL1:
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LOGMASKED(LOG_SERVO, "SERVO SCC Control 1 write (%02x)\n", data);
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break;
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case m68hc05eg_io_reg_t::SCC_CTRL2:
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LOGMASKED(LOG_SERVO, "SERVO SCC Control 2 write (%02x)\n", data);
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break;
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case m68hc05eg_io_reg_t::SCC_STATUS:
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LOGMASKED(LOG_SERVO, "SERVO SCC Status write (%02x)\n", data);
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break;
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case m68hc05eg_io_reg_t::SCC_DATA:
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LOGMASKED(LOG_SERVO, "SERVO SCC Data write (%02x)\n", data);
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break;
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case m68hc05eg_io_reg_t::TIMER_CTRL:
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LOGMASKED(LOG_SERVO, "SERVO Timer Control write (%02x)\n", data);
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break;
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case m68hc05eg_io_reg_t::TIMER_STATUS:
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LOGMASKED(LOG_SERVO, "SERVO Timer Status write (%02x)\n", data);
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break;
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case m68hc05eg_io_reg_t::ICAP_HI:
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LOGMASKED(LOG_SERVO, "SERVO Input Capture Hi write (%02x)\n", data);
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break;
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case m68hc05eg_io_reg_t::ICAP_LO:
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LOGMASKED(LOG_SERVO, "SERVO Input Capture Lo write (%02x)\n", data);
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break;
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case m68hc05eg_io_reg_t::OCMP_HI:
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LOGMASKED(LOG_SERVO, "SERVO Output Compare Hi write (%02x)\n", data);
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break;
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case m68hc05eg_io_reg_t::OCMP_LO:
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LOGMASKED(LOG_SERVO, "SERVO Output Compare Lo write (%02x)\n", data);
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break;
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case m68hc05eg_io_reg_t::COUNT_HI:
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LOGMASKED(LOG_SERVO, "SERVO Count Hi write (%02x)\n", data);
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break;
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case m68hc05eg_io_reg_t::COUNT_LO:
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LOGMASKED(LOG_SERVO, "SERVO Count Lo write (%02x)\n", data);
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break;
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case m68hc05eg_io_reg_t::ACOUNT_HI:
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LOGMASKED(LOG_SERVO, "SERVO Alternate Count Hi write (%02x)\n", data);
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break;
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case m68hc05eg_io_reg_t::ACOUNT_LO:
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LOGMASKED(LOG_SERVO, "SERVO Alternate Count Lo write (%02x)\n", data);
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break;
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default:
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logerror("Unknown SERVO I/O write (%02x = %02x)\n", offset, data);
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break;
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}
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m_servo_io_regs[offset] = data;
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}
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READ8_MEMBER( cdi_state::slave_io_r )
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{
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if (machine().side_effects_disabled())
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{
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return 0;
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}
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uint8_t ret = m_slave_io_regs[offset];
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switch(offset)
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{
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case m68hc05eg_io_reg_t::PORT_A_DATA:
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LOGMASKED(LOG_SLAVE, "SLAVE Port A Data read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::PORT_B_DATA:
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LOGMASKED(LOG_SLAVE, "SLAVE Port B Data read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::PORT_C_DATA:
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LOGMASKED(LOG_SLAVE, "SLAVE Port C Data read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::PORT_D_INPUT:
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LOGMASKED(LOG_SLAVE, "SLAVE Port D Input read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::PORT_A_DDR:
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LOGMASKED(LOG_SLAVE, "SLAVE Port A DDR read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::PORT_B_DDR:
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LOGMASKED(LOG_SLAVE, "SLAVE Port B DDR read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::PORT_C_DDR:
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LOGMASKED(LOG_SLAVE, "SLAVE Port C DDR read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::SPI_CTRL:
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LOGMASKED(LOG_SLAVE, "SLAVE SPI Control read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::SPI_STATUS:
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LOGMASKED(LOG_SLAVE, "SLAVE SPI Status read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::SPI_DATA:
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LOGMASKED(LOG_SLAVE, "SLAVE SPI Data read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::SCC_BAUD:
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LOGMASKED(LOG_SLAVE, "SLAVE SCC Baud Rate read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::SCC_CTRL1:
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LOGMASKED(LOG_SLAVE, "SLAVE SCC Control 1 read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::SCC_CTRL2:
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LOGMASKED(LOG_SLAVE, "SLAVE SCC Control 2 read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::SCC_STATUS:
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LOGMASKED(LOG_SLAVE, "SLAVE SCC Status read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::SCC_DATA:
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LOGMASKED(LOG_SLAVE, "SLAVE SCC Data read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::TIMER_CTRL:
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LOGMASKED(LOG_SLAVE, "SLAVE Timer Control read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::TIMER_STATUS:
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LOGMASKED(LOG_SLAVE, "SLAVE Timer Status read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::ICAP_HI:
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LOGMASKED(LOG_SLAVE, "SLAVE Input Capture Hi read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::ICAP_LO:
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LOGMASKED(LOG_SLAVE, "SLAVE Input Capture Lo read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::OCMP_HI:
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LOGMASKED(LOG_SLAVE, "SLAVE Output Compare Hi read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::OCMP_LO:
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LOGMASKED(LOG_SLAVE, "SLAVE Output Compare Lo read (%02x)\n", ret);
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break;
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case m68hc05eg_io_reg_t::COUNT_HI:
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{
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const uint16_t count = (m_slave->total_cycles() / 4) & 0x0000ffff;
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ret = count >> 8;
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LOGMASKED(LOG_SLAVE, "SLAVE Count Hi read (%02x)\n", ret);
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break;
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}
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case m68hc05eg_io_reg_t::COUNT_LO:
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{
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const uint16_t count = (m_slave->total_cycles() / 4) & 0x0000ffff;
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ret = count & 0x00ff;
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LOGMASKED(LOG_SLAVE, "SLAVE Count Lo read (%02x)\n", ret);
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break;
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}
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case m68hc05eg_io_reg_t::ACOUNT_HI:
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{
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const uint16_t count = (m_slave->total_cycles() / 4) & 0x0000ffff;
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ret = count >> 8;
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LOGMASKED(LOG_SLAVE, "SLAVE Alternate Count Hi read (%02x)\n", ret);
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break;
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}
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case m68hc05eg_io_reg_t::ACOUNT_LO:
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{
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const uint16_t count = (m_slave->total_cycles() / 4) & 0x0000ffff;
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ret = count & 0x00ff;
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LOGMASKED(LOG_SLAVE, "SLAVE Alternate Count Lo read (%02x)\n", ret);
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break;
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}
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default:
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logerror("Unknown SLAVE I/O read (%02x)\n", offset);
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break;
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}
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return ret;
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}
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WRITE8_MEMBER( cdi_state::slave_io_w )
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{
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switch(offset)
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{
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case m68hc05eg_io_reg_t::PORT_A_DATA:
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LOGMASKED(LOG_SLAVE, "SLAVE Port A Data write (%02x)\n", data);
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return;
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case m68hc05eg_io_reg_t::PORT_B_DATA:
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LOGMASKED(LOG_SLAVE, "SLAVE Port B Data write (%02x)\n", data);
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return;
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case m68hc05eg_io_reg_t::PORT_C_DATA:
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LOGMASKED(LOG_SLAVE, "SLAVE Port C Data write (%02x)\n", data);
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return;
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case m68hc05eg_io_reg_t::PORT_D_INPUT:
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LOGMASKED(LOG_SLAVE, "SLAVE Port D Input write (%02x)\n", data);
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return;
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case m68hc05eg_io_reg_t::PORT_A_DDR:
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LOGMASKED(LOG_SLAVE, "SLAVE Port A DDR write (%02x)\n", data);
|
||||
break;
|
||||
case m68hc05eg_io_reg_t::PORT_B_DDR:
|
||||
LOGMASKED(LOG_SLAVE, "SLAVE Port B DDR write (%02x)\n", data);
|
||||
break;
|
||||
case m68hc05eg_io_reg_t::PORT_C_DDR:
|
||||
LOGMASKED(LOG_SLAVE, "SLAVE Port C DDR write (%02x)\n", data);
|
||||
break;
|
||||
case m68hc05eg_io_reg_t::SPI_CTRL:
|
||||
LOGMASKED(LOG_SLAVE, "SLAVE SPI Control write (%02x)\n", data);
|
||||
break;
|
||||
case m68hc05eg_io_reg_t::SPI_STATUS:
|
||||
LOGMASKED(LOG_SLAVE, "SLAVE SPI Status write (%02x)\n", data);
|
||||
break;
|
||||
case m68hc05eg_io_reg_t::SPI_DATA:
|
||||
LOGMASKED(LOG_SLAVE, "SLAVE SPI Data write (%02x)\n", data);
|
||||
break;
|
||||
case m68hc05eg_io_reg_t::SCC_BAUD:
|
||||
LOGMASKED(LOG_SLAVE, "SLAVE SCC Baud Rate write (%02x)\n", data);
|
||||
break;
|
||||
case m68hc05eg_io_reg_t::SCC_CTRL1:
|
||||
LOGMASKED(LOG_SLAVE, "SLAVE SCC Control 1 write (%02x)\n", data);
|
||||
break;
|
||||
case m68hc05eg_io_reg_t::SCC_CTRL2:
|
||||
LOGMASKED(LOG_SLAVE, "SLAVE SCC Control 2 write (%02x)\n", data);
|
||||
break;
|
||||
case m68hc05eg_io_reg_t::SCC_STATUS:
|
||||
LOGMASKED(LOG_SLAVE, "SLAVE SCC Status write (%02x)\n", data);
|
||||
break;
|
||||
case m68hc05eg_io_reg_t::SCC_DATA:
|
||||
LOGMASKED(LOG_SLAVE, "SLAVE SCC Data write (%02x)\n", data);
|
||||
break;
|
||||
case m68hc05eg_io_reg_t::TIMER_CTRL:
|
||||
LOGMASKED(LOG_SLAVE, "SLAVE Timer Control write (%02x)\n", data);
|
||||
break;
|
||||
case m68hc05eg_io_reg_t::TIMER_STATUS:
|
||||
LOGMASKED(LOG_SLAVE, "SLAVE Timer Status write (%02x)\n", data);
|
||||
break;
|
||||
case m68hc05eg_io_reg_t::ICAP_HI:
|
||||
LOGMASKED(LOG_SLAVE, "SLAVE Input Capture Hi write (%02x)\n", data);
|
||||
break;
|
||||
case m68hc05eg_io_reg_t::ICAP_LO:
|
||||
LOGMASKED(LOG_SLAVE, "SLAVE Input Capture Lo write (%02x)\n", data);
|
||||
break;
|
||||
case m68hc05eg_io_reg_t::OCMP_HI:
|
||||
LOGMASKED(LOG_SLAVE, "SLAVE Output Compare Hi write (%02x)\n", data);
|
||||
break;
|
||||
case m68hc05eg_io_reg_t::OCMP_LO:
|
||||
LOGMASKED(LOG_SLAVE, "SLAVE Output Compare Lo write (%02x)\n", data);
|
||||
break;
|
||||
case m68hc05eg_io_reg_t::COUNT_HI:
|
||||
LOGMASKED(LOG_SLAVE, "SLAVE Count Hi write (%02x)\n", data);
|
||||
break;
|
||||
case m68hc05eg_io_reg_t::COUNT_LO:
|
||||
LOGMASKED(LOG_SLAVE, "SLAVE Count Lo write (%02x)\n", data);
|
||||
break;
|
||||
case m68hc05eg_io_reg_t::ACOUNT_HI:
|
||||
LOGMASKED(LOG_SLAVE, "SLAVE Alternate Count Hi write (%02x)\n", data);
|
||||
break;
|
||||
case m68hc05eg_io_reg_t::ACOUNT_LO:
|
||||
LOGMASKED(LOG_SLAVE, "SLAVE Alternate Count Lo write (%02x)\n", data);
|
||||
break;
|
||||
default:
|
||||
logerror("Unknown SLAVE I/O write (%02x = %02x)\n", offset, data);
|
||||
break;
|
||||
}
|
||||
|
||||
m_slave_io_regs[offset] = data;
|
||||
}
|
||||
|
||||
/*************************
|
||||
* LCD screen *
|
||||
*************************/
|
||||
@ -1056,10 +639,8 @@ void cdi_state::cdimono2(machine_config &config)
|
||||
|
||||
MCFG_MACHINE_RESET_OVERRIDE( cdi_state, cdimono2 )
|
||||
|
||||
M68HC05EG(config, m_servo, 4_MHz_XTAL); // FIXME: actually MC68HC05C8
|
||||
m_servo->set_addrmap(AS_PROGRAM, &cdi_state::cdimono2_servo_mem);
|
||||
M68HC05EG(config, m_slave, 4_MHz_XTAL); // FIXME: actually MC68HC05C8
|
||||
m_slave->set_addrmap(AS_PROGRAM, &cdi_state::cdimono2_slave_mem);
|
||||
M68HC05C8(config, m_servo, 4_MHz_XTAL);
|
||||
M68HC05C8(config, m_slave, 4_MHz_XTAL);
|
||||
|
||||
CDROM(config, "cdrom").set_interface("cdi_cdrom");
|
||||
SOFTWARE_LIST(config, "cd_list").set_original("cdi").set_filter("!DVC");
|
||||
@ -1111,10 +692,8 @@ void cdi_state::cdi910(machine_config &config)
|
||||
|
||||
MCFG_MACHINE_RESET_OVERRIDE( cdi_state, cdimono2 )
|
||||
|
||||
M68HC05EG(config, m_servo, 4_MHz_XTAL); // FIXME: actually MC68HSC05C8
|
||||
m_servo->set_addrmap(AS_PROGRAM, &cdi_state::cdimono2_servo_mem);
|
||||
M68HC05EG(config, m_slave, 4_MHz_XTAL); // FIXME: actually MC68HSC05C8
|
||||
m_slave->set_addrmap(AS_PROGRAM, &cdi_state::cdimono2_slave_mem);
|
||||
M68HC05C8(config, m_servo, 4_MHz_XTAL);
|
||||
M68HC05C8(config, m_slave, 4_MHz_XTAL);
|
||||
|
||||
CDROM(config, "cdrom").set_interface("cdi_cdrom");
|
||||
SOFTWARE_LIST(config, "cd_list").set_original("cdi").set_filter("!DVC");
|
||||
|
||||
@ -10,6 +10,7 @@
|
||||
#include "sound/dmadac.h"
|
||||
#include "video/mcd212.h"
|
||||
#include "cpu/mcs51/mcs51.h"
|
||||
#include "cpu/m6805/m68hc05.h"
|
||||
#include "screen.h"
|
||||
|
||||
/*----------- driver state -----------*/
|
||||
@ -33,35 +34,6 @@ public:
|
||||
, m_dmadac(*this, "dac%u", 1U)
|
||||
{ }
|
||||
|
||||
enum m68hc05eg_io_reg_t
|
||||
{
|
||||
PORT_A_DATA = 0x00,
|
||||
PORT_B_DATA = 0x01,
|
||||
PORT_C_DATA = 0x02,
|
||||
PORT_D_INPUT = 0x03,
|
||||
PORT_A_DDR = 0x04,
|
||||
PORT_B_DDR = 0x05,
|
||||
PORT_C_DDR = 0x06,
|
||||
SPI_CTRL = 0x0a,
|
||||
SPI_STATUS = 0x0b,
|
||||
SPI_DATA = 0x0c,
|
||||
SCC_BAUD = 0x0d,
|
||||
SCC_CTRL1 = 0x0e,
|
||||
SCC_CTRL2 = 0x0f,
|
||||
SCC_STATUS = 0x10,
|
||||
SCC_DATA = 0x11,
|
||||
TIMER_CTRL = 0x12,
|
||||
TIMER_STATUS = 0x13,
|
||||
ICAP_HI = 0x14,
|
||||
ICAP_LO = 0x15,
|
||||
OCMP_HI = 0x16,
|
||||
OCMP_LO = 0x17,
|
||||
COUNT_HI = 0x18,
|
||||
COUNT_LO = 0x19,
|
||||
ACOUNT_HI = 0x1a,
|
||||
ACOUNT_LO = 0x1b
|
||||
};
|
||||
|
||||
enum servo_portc_bit_t
|
||||
{
|
||||
INV_JUC_OUT = (1 << 2),
|
||||
@ -74,8 +46,8 @@ public:
|
||||
optional_ioport m_input1;
|
||||
optional_ioport m_input2;
|
||||
optional_device<cdislave_device> m_slave_hle;
|
||||
optional_device<cpu_device> m_servo;
|
||||
optional_device<cpu_device> m_slave;
|
||||
optional_device<m68hc05c8_device> m_servo;
|
||||
optional_device<m68hc05c8_device> m_slave;
|
||||
optional_device<cdicdic_device> m_cdic;
|
||||
required_device<cdda_device> m_cdda;
|
||||
required_device<mcd212_device> m_mcd212;
|
||||
@ -85,9 +57,6 @@ public:
|
||||
|
||||
INTERRUPT_GEN_MEMBER( mcu_frame );
|
||||
|
||||
uint8_t m_servo_io_regs[0x20];
|
||||
uint8_t m_slave_io_regs[0x20];
|
||||
|
||||
uint8_t m_timer_set;
|
||||
emu_timer *m_test_timer;
|
||||
|
||||
@ -104,10 +73,6 @@ public:
|
||||
DECLARE_MACHINE_RESET(quizard2);
|
||||
DECLARE_MACHINE_RESET(quizard3);
|
||||
DECLARE_MACHINE_RESET(quizard4);
|
||||
DECLARE_READ8_MEMBER(servo_io_r);
|
||||
DECLARE_WRITE8_MEMBER(servo_io_w);
|
||||
DECLARE_READ8_MEMBER(slave_io_r);
|
||||
DECLARE_WRITE8_MEMBER(slave_io_w);
|
||||
|
||||
DECLARE_READ8_MEMBER(quizard_mcu_p1_r);
|
||||
|
||||
@ -127,8 +92,6 @@ public:
|
||||
void cdi910_mem(address_map &map);
|
||||
void cdimono1_mem(address_map &map);
|
||||
void cdimono2_mem(address_map &map);
|
||||
void cdimono2_servo_mem(address_map &map);
|
||||
void cdimono2_slave_mem(address_map &map);
|
||||
void cdi070_cpuspace(address_map &map);
|
||||
|
||||
// Quizard Protection HLE
|
||||
|
||||
Loading…
Reference in New Issue
Block a user