video/atirage.cpp: add base x86 interface for atirageiidvd_device

src/devices/video/atirage.cpp

@@ -143,7 +143,7 @@ void atirage_device::device_start()
 {
 	pci_device::device_start();
 
-	add_map(0x1000000, M_MEM, FUNC(atirage_device::mem_map));   // 16 MB memory map
+	add_map(0x1000000, M_MEM | M_PREF, FUNC(atirage_device::mem_map));   // 16 MB memory map
 	add_map(0x100, M_IO, FUNC(atirage_device::io_map));     // 256 byte I/O map
 	add_map(0x01000, M_MEM, FUNC(atirage_device::reg_map)); // 4K register map
 
@@ -211,6 +211,7 @@ void atirageiic_device::device_start()
 	m_regs0[CONFIG_CHIP_ID+3] = 0x3a;
 }
 
+// TODO: this core is currently hardwired to legacy x86 interface, as a testbed for p5txla
 void atirageiidvd_device::device_start()
 {
 	// Mach64 GT-B [3D Rage II+ DVD]
@@ -221,6 +222,7 @@ void atirageiidvd_device::device_start()
 	m_regs0[CONFIG_CHIP_ID] = 0x55;
 	m_regs0[CONFIG_CHIP_ID+1] = 0x47;
 	m_regs0[CONFIG_CHIP_ID+3] = 0x3a;
+//	m_regs0[CRTC_GEN_CNTL+3] = 0;
 
 	// TODO: opt-in Mach64 legacy x86 memory & i/o VGA bridge control
 	command = 0;
@@ -229,6 +231,21 @@ void atirageiidvd_device::device_start()
 	expansion_rom_base = 0xc0000;
 }
 
+void atirageiidvd_device::device_reset()
+{
+	atirage_device::device_reset();
+	// TODO: verify actual x86 BAR defaults
+	// p5txla starts up with (unmapped) writes at I/O $6100, eventually relocating BAR1 to $6300.
+	// 2mbsgr VGA BIOS (at least, PC=c1c2d) does an inefficient CONFIG_CHIP_ID scan of the I/O
+	// space thru all of $xxe0, instead of just using BLK_IO_BASE readback alias at VGA $3c3.
+	// On top, we need to remap BARs 0 & 2 on x86 because otherwise it will clash with real memory
+	// area, perhaps they are supposed to be disabled on startup?
+	set_map_address(0, 0xf0000000);
+	set_map_address(1, 0x6100);
+	set_map_address(2, 0xe0000000);
+	remap_cb();
+}
+
 ROM_START( atirageiidvd )
 	ROM_REGION32_LE( 0x10000, "vga_rom", ROMREGION_ERASEFF )
 	// Header, P/N then date
@@ -245,6 +262,36 @@ const tiny_rom_entry *atirageiidvd_device::device_rom_region() const
 	return ROM_NAME(atirageiidvd);
 }
 
+uint8_t atirageiidvd_device::vram_r(offs_t offset)
+{
+	return downcast<mach64_device *>(m_mach64.target())->mem_r(offset);
+}
+
+void atirageiidvd_device::vram_w(offs_t offset, uint8_t data)
+{
+	downcast<mach64_device *>(m_mach64.target())->mem_w(offset, data);
+}
+
+void atirageiidvd_device::legacy_io_map(address_map &map)
+{
+	map(0x0000, 0x02f).m(m_mach64, FUNC(mach64_device::io_map));
+}
+
+void atirageiidvd_device::map_extra(uint64_t memory_window_start, uint64_t memory_window_end, uint64_t memory_offset, address_space *memory_space,
+							uint64_t io_window_start, uint64_t io_window_end, uint64_t io_offset, address_space *io_space)
+{
+	if (BIT(command, 1))
+	{
+		memory_space->install_readwrite_handler(0xa0000, 0xbffff, read8sm_delegate(*this, FUNC(atirageiidvd_device::vram_r)), write8sm_delegate(*this, FUNC(atirageiidvd_device::vram_w)));
+	}
+
+	if (BIT(command, 0))
+	{
+		io_space->install_device(0x03b0, 0x03df, *this, &atirageiidvd_device::legacy_io_map);
+		io_space->install_readwrite_handler(0x01ce, 0x01cf, read8sm_delegate(*m_mach64, FUNC(mach64_device::ati_port_ext_r)), write8sm_delegate(*m_mach64, FUNC(mach64_device::ati_port_ext_w)));
+	}
+}
+
 void atiragepro_device::device_start()
 {
 	// Rage Pro PCI

src/devices/video/atirage.h

@@ -86,8 +86,15 @@ public:
 
 protected:
 	virtual void device_start() override;
+	virtual void device_reset() override;
 
 	virtual const tiny_rom_entry *device_rom_region() const override;
+	virtual void map_extra(uint64_t memory_window_start, uint64_t memory_window_end, uint64_t memory_offset, address_space *memory_space,
+	uint64_t io_window_start, uint64_t io_window_end, uint64_t io_offset, address_space *io_space) override;
+
+	u8 vram_r(offs_t offset);
+	void vram_w(offs_t offset, uint8_t data);
+	void legacy_io_map(address_map &map);
 
 private:
 	required_memory_region m_vga_rom;

src/devices/video/pc_vga.cpp

@@ -960,7 +960,8 @@ void vga_device::crtc_map(address_map &map)
 		// 1--- ---- data
 	map(0x24, 0x24).lr8(
 		NAME([this](offs_t offset) {
-			LOG("CR24 read undocumented Attribute reg\n");
+			if (!machine().side_effects_disabled())
+				LOG("CR24 read undocumented Attribute reg\n");
 			return vga.attribute.state << 7;
 		})
 	);
@@ -1574,7 +1575,6 @@ void vga_device::recompute_params_clock(int divisor, int xtal)
 
 	refresh  = HZ_TO_ATTOSECONDS(pixel_clock) * (hblank_period) * vblank_period;
 	screen().configure((hblank_period), (vblank_period), visarea, refresh );
-	//popmessage("%d %d\n",vga.crtc.horz_total * 8,vga.crtc.vert_total);
 	m_vblank_timer->adjust( screen().time_until_pos(vga.crtc.vert_blank_start + vga.crtc.vert_blank_end) );
 }
 

src/mame/taito/taitowlf.cpp

@@ -8,8 +8,8 @@ rewritten by Angelo Salese to use the new PCI model
 Three board system consisting of a P5TX-LA PC motherboard, a Taito main board and a rom board.
 
 TODO:
-- The Retro Web MB pic has a Winbond w83877tf Super I/O but neither BIOSes accesses it,
-  is it specific to the (unavailable) ECS P5TX-LA BIOS?
+- The Retro Web MB pic lists a Winbond w83877tf Super I/O but neither BIOSes properly init that,
+  eventually failing with p5txla later on with PnP sequence. Missing power on default?
 - p5txla: Rage VGA chip sets up screen with 8x1, making MAME unresponsive.
           Needs x86 VGA legacy map bridge to fix.
 - pf2012: verify ISA irq 7 source (particularly ACK, PORT_IMPULSE(1) won't work),