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pci/vision: add Vision964, start implementing new MMIO for Vision 968

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This commit is contained in:
angelosa 2024-02-25 13:55:23 +01:00
parent 1e3ebf9ae2
commit 76f499059f
5 changed files with 147 additions and 16 deletions
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3
src/devices/bus/pci/pci_slot.cpp
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@ -107,7 +107,7 @@ void pci_cards(device_slot_interface &device)
// 0x00 - backward compatible pre-class code
// device.option_add("voodoo1", VOODOO_1_PCI);
device.option_add("vision864", VISION864_PCI);
device.option_add("vision968", VISION968_PCI);
device.option_add("vision964", VISION964_PCI);
// 0x01 - mass storage controllers
device.option_add("aha2940au", AHA2940AU);
@ -117,6 +117,7 @@ void pci_cards(device_slot_interface &device)
device.option_add("rtl8139", RTL8139_PCI);
// 0x03 - display controllers
device.option_add("vision968", VISION968_PCI);
device.option_add("virge", VIRGE_PCI);
device.option_add("virgedx", VIRGEDX_PCI);
device.option_add("riva128", RIVA128);

125
src/devices/bus/pci/vision.cpp
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@ -23,7 +23,7 @@ TODO:
DEFINE_DEVICE_TYPE(VISION864_PCI, vision864_device, "vision864", "S3 86C864 Vision864")
// Vision868
// Vision964
DEFINE_DEVICE_TYPE(VISION964_PCI, vision964_device, "vision964", "S3 86C964 Vision964")
DEFINE_DEVICE_TYPE(VISION968_PCI, vision968_device, "vision968", "S3 86C968 Vision968")
@ -44,7 +44,7 @@ vision864_device::vision864_device(const machine_config &mconfig, const char *ta
// 88c2 = 86c864-P DRAM v2
// 88c3 = 86c864-P DRAM v3
// NOTE: class code = 0 (backward compatible VGA device)
set_ids(0x533388c1, 0x00, 0x000100, 0x533388c1);
set_ids(0x533388c1, 0x00, 0x000100, 0x00000000);
}
ROM_START( vision864 )
@ -69,20 +69,19 @@ void vision864_device::device_add_mconfig(machine_config &config)
m_vga->set_screen("screen");
// 1MB, option for 2MB
m_vga->set_vram_size(2*1024*1024);
// m_vga->linear_config_changed().set(FUNC(s3_vga_device::linear_config_changed_w));
}
void vision864_device::device_start()
{
pci_card_device::device_start();
// add_map(64 * 1024 * 1024, M_MEM | M_DISABLED, FUNC(vision864_device::lfb_map));
// set_map_address(0, 0x70000000);
// add_map(64 * 1024 * 1024, M_MEM | M_DISABLED, FUNC(vision864_device::lfb_map));
// set_map_address(0, 0x70000000);
add_rom((u8 *)m_bios->base(), 0x8000);
expansion_rom_base = 0xc0000;
// Shouldn't have an intr pin
// TODO: can't read the intr pin reg but still has an INTA#
}
void vision864_device::device_reset()
@ -126,6 +125,53 @@ void vision864_device::map_extra(uint64_t memory_window_start, uint64_t memory_w
}
}
/******************
*
* Vision964
*
*****************/
vision964_device::vision964_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
: vision864_device(mconfig, type, tag, owner, clock)
{
}
vision964_device::vision964_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: vision964_device(mconfig, VISION964_PCI, tag, owner, clock)
{
// device IDs:
// 88d0-88d1 = 86c964 VRAM v0-1
// 88d2-88d3 = 86c964-P VRAM v2-3
// NOTE: class code = 0 (backward compatible VGA device)
set_ids(0x533388d0, 0x00, 0x000100, 0x00000000);
}
ROM_START( vision964 )
ROM_REGION32_LE( 0x8000, "bios", ROMREGION_ERASEFF )
ROM_DEFAULT_BIOS("mirocrys")
ROM_SYSTEM_BIOS( 0, "mirocrys", "miroCRYSTAL Rev.2.13" )
ROMX_LOAD( "mirocrystal.vbi", 0x0000, 0x8000, CRC(d0b0aa1c) SHA1(004e2432c4783f1539a7989e7d9ee422df09e695), ROM_BIOS(0) )
ROM_END
const tiny_rom_entry *vision964_device::device_rom_region() const
{
return ROM_NAME(vision964);
}
void vision964_device::device_add_mconfig(machine_config &config)
{
screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER));
screen.set_raw(XTAL(25'174'800), 900, 0, 640, 526, 0, 480);
screen.set_screen_update("vga", FUNC(s3_vga_device::screen_update));
S3_VGA(config, m_vga, 0);
m_vga->set_screen("screen");
// 2MB/4MB/8MB
m_vga->set_vram_size(4*1024*1024);
}
/******************
*
* Vision968
@ -133,12 +179,12 @@ void vision864_device::map_extra(uint64_t memory_window_start, uint64_t memory_w
*****************/
vision968_device::vision968_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: vision864_device(mconfig, VISION968_PCI, tag, owner, clock)
: vision964_device(mconfig, VISION968_PCI, tag, owner, clock)
{
// device IDs:
// 88f0-88f3 = 86c968 RAM v0-3
// NOTE: class code = 0 (backward compatible VGA device)
set_ids(0x533388f0, 0x00, 0x000100, 0x533388f0);
// first device to actually have a real class code
set_ids(0x533388f0, 0x00, 0x030000, 0x00000000);
}
ROM_START( vision968 )
@ -154,7 +200,7 @@ ROM_START( vision968 )
ROM_IGNORE( 0x8000 )
ROM_SYSTEM_BIOS( 2, "speamp64", "SPEA/Videoseven V7-Mercury P-64 v1.01-08" )
ROMX_LOAD( "spea.bin", 0x0000, 0x8000, CRC(2caeadaf) SHA1(236829f1e6065a2f0ebee91f71891d8402f0ab5a), ROM_BIOS(2) )
ROMX_LOAD( "spea.bin", 0x0000, 0x8000, CRC(2caeadaf) SHA1(236829f1e6065a2f0ebee91f71891d8402f0ab5a), ROM_BIOS(2) )
ROM_IGNORE( 0x8000 )
ROM_END
@ -173,5 +219,62 @@ void vision968_device::device_add_mconfig(machine_config &config)
m_vga->set_screen("screen");
// 2MB/4MB/8MB
m_vga->set_vram_size(4*1024*1024);
// m_vga->linear_config_changed().set(FUNC(s3_vga_device::linear_config_changed_w));
// m_vga->linear_config_changed().set(FUNC(s3_vga_device::linear_config_changed_w));
}
void vision968_device::device_start()
{
pci_card_device::device_start();
// add_map(64 * 1024 * 1024, M_MEM | M_DISABLED, FUNC(vision968_device::lfb_map));
add_map(64 * 1024 * 1024, M_MEM, FUNC(vision968_device::lfb_map));
set_map_address(0, 0x70000000);
add_rom((u8 *)m_bios->base(), 0x8000);
expansion_rom_base = 0xc0000;
// INTA#
intr_pin = 1;
}
void vision968_device::device_reset()
{
pci_card_device::device_reset();
command = 0x0020;
command_mask = 0x23;
// Adds fast back-to-back
status = 0x0280;
remap_cb();
}
// TODO: 0x0200'0000 "mirror" (really an endian relocation?)
void vision968_device::lfb_map(address_map &map)
{
map(0x0000'0000, 0x00ff'ffff).rw(m_vga, FUNC(s3_vga_device::mem_linear_r), FUNC(s3_vga_device::mem_linear_w));
// map(0x0100'0000, 0x0100'7fff) image transfer data
map(0x0100'8000, 0x0100'803f).m(FUNC(vision968_device::config_map));
// map(0x0100'8100, 0x0100'816f) packed copro regs
// map(0x0100'82e8, 0x0100'82e8) current ypos
// map(0x0100'82ea, 0x0100'82ea) current ypos-2
map(0x0100'83b0, 0x0100'83df).m(m_vga, FUNC(s3_vga_device::io_map));
// map(0x0100'8502, 0x0100'8502) (VGA $0102 alias)
// map(0x0100'8504, 0x0100'8504) (VGA $42e8 alias)
// map(0x0100'8508, 0x0100'8508) (VGA $46e8 alias)
// map(0x0100'850c, 0x0100'850c) (VGA $4ae8 alias)
// map(0x0100'86e8, 0x0100'8eea) PnP copro region
// map(0x0101'0000, 0x0101'3fff) Pixel formatter data transfer
// map(0x0101'4000, 0x0101'7fff) Pixel formatter Mask data
// map(0x0101'8080, 0x0101'809f) Pixel formatter regs
}
void vision968_device::map_extra(uint64_t memory_window_start, uint64_t memory_window_end, uint64_t memory_offset, address_space *memory_space,
uint64_t io_window_start, uint64_t io_window_end, uint64_t io_offset, address_space *io_space)
{
vision964_device::map_extra(
memory_window_start, memory_window_end, memory_offset, memory_space,
io_window_start, io_window_end, io_offset, io_space
);
// TODO: new MMIO goes here
}

23
src/devices/bus/pci/vision.h
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@ -38,7 +38,20 @@ private:
void vram_w(offs_t offset, uint8_t data);
};
class vision968_device : public vision864_device
class vision964_device : public vision864_device
{
public:
vision964_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:
vision964_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
virtual void device_add_mconfig(machine_config &config) override;
virtual const tiny_rom_entry *device_rom_region() const override;
};
class vision968_device : public vision964_device
{
public:
vision968_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
@ -47,9 +60,17 @@ protected:
virtual void device_add_mconfig(machine_config &config) override;
virtual const tiny_rom_entry *device_rom_region() const override;
virtual void device_start() override;
virtual void device_reset() override;
virtual void map_extra(uint64_t memory_window_start, uint64_t memory_window_end, uint64_t memory_offset, address_space *memory_space,
uint64_t io_window_start, uint64_t io_window_end, uint64_t io_offset, address_space *io_space) override;
void lfb_map(address_map &map);
};
DECLARE_DEVICE_TYPE(VISION864_PCI, vision864_device)
DECLARE_DEVICE_TYPE(VISION964_PCI, vision964_device)
DECLARE_DEVICE_TYPE(VISION968_PCI, vision968_device)
#endif // MAME_BUS_PCI_S3VISION_PCI_H

7
src/devices/video/pc_vga_s3.cpp
View File

@ -78,6 +78,7 @@ void s3_vga_device::device_reset()
vga_device::device_reset();
// Power-on strapping bits. Sampled at reset, but can be modified later.
// These are just assumed defaults.
// TODO: expose as configuration option (PD pins)
s3.strapping = 0x000f0b1e;
s3.sr10 = 0x42;
s3.sr11 = 0x41;
@ -116,7 +117,7 @@ void s3_vga_device::s3_define_video_mode()
svga.rgb15_en = 0;
svga.rgb16_en = 0;
svga.rgb32_en = 0;
// FIXME: vision has only first 7 modes
// FIXME: vision864 has only first 7 modes
switch((s3.ext_misc_ctrl_2) >> 4)
{
// 0001 Mode 8: 2x 8-bit 1 VCLK/2 pixels
@ -196,6 +197,7 @@ void s3_vga_device::crtc_map(address_map &map)
s3_define_video_mode();
})
);
// TODO: CR32, CR33 & CR34 (backward compatibility)
map(0x35, 0x35).lrw8(
NAME([this] (offs_t offset) {
return s3.crt_reg_lock;
@ -229,6 +231,7 @@ void s3_vga_device::crtc_map(address_map &map)
return (s3.strapping & 0x0000ff00) >> 8; // enable chipset, 64k BIOS size, internal DCLK/MCLK
}),
NAME([this] (offs_t offset, u8 data) {
// TODO: monitor ID at 7-5 (PD15-13)
if(s3.reg_lock2 == 0xa5)
{
s3.strapping = (s3.strapping & 0xffff00ff) | (data << 8);
@ -532,6 +535,7 @@ bit 0-1 DAC Register Select Bits. Passed to the RS2 and RS3 pins on the
s3.extended_dac_ctrl = data;
})
);
// TODO: bits 7-4 (w/o?) for GPIO
map(0x5c, 0x5c).lr8(
NAME([this] (offs_t offset) {
u8 res = 0;
@ -664,6 +668,7 @@ bit 0 Vertical Total bit 10. Bit 10 of the Vertical Total register (3d4h
void s3_vga_device::sequencer_map(address_map &map)
{
svga_device::sequencer_map(map);
// TODO: SR8 (unlocks SRD)
// Memory CLK PLL
map(0x10, 0x10).lrw8(
NAME([this] (offs_t offset) { return s3.sr10; }),

5
src/mame/misc/odyssey.cpp
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@ -10,8 +10,9 @@
TODO:
- bp f7ae6,1,{eip+=0xf;g} fails ISA state $0f;
- Accesses S3 video in Old MMIO mode, draws 32-bit color mode GFXs;
- Hangs after playing with LPT1;
- Accesses S3 video in New MMIO mode, core fumbles on video mode setup
(prepares linear for 32bpp, core sets SVGA 8bpp instead)
- Hangs after playing with LPT1 & IDE checks;
*******************************************************************************