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ide: deambiguate cs access between 16 and 32 bits [O. Galibert]

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This commit is contained in:
Olivier Galibert 2017-12-15 12:45:49 +01:00
parent 00c799de12
commit 77829f8671
58 changed files with 284 additions and 284 deletions
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8
src/devices/bus/a1bus/a1cffa.cpp
View File

@ -100,7 +100,7 @@ READ8_MEMBER(a1bus_cffa_device::cffa_r)
break;
case 0x8:
m_lastdata = m_ata->read_cs0(space, (offset & 0xf) - 8, 0xff);
m_lastdata = m_ata->read16_cs0(space, (offset & 0xf) - 8, 0xff);
return m_lastdata & 0x00ff;
case 0x9:
@ -110,7 +110,7 @@ READ8_MEMBER(a1bus_cffa_device::cffa_r)
case 0xd:
case 0xe:
case 0xf:
return m_ata->read_cs0(space, (offset & 0xf) - 8, 0xff);
return m_ata->read16_cs0(space, (offset & 0xf) - 8, 0xff);
}
return 0xff;
@ -135,7 +135,7 @@ WRITE8_MEMBER(a1bus_cffa_device::cffa_w)
case 0x8:
m_ata->write_cs0(space, (offset & 0xf) - 8, data, 0xff);
m_ata->write16_cs0(space, (offset & 0xf) - 8, data, 0xff);
break;
case 0x9:
@ -145,7 +145,7 @@ WRITE8_MEMBER(a1bus_cffa_device::cffa_w)
case 0xd:
case 0xe:
case 0xf:
m_ata->write_cs0(space, (offset & 0xf) - 8, data, 0xff);
m_ata->write16_cs0(space, (offset & 0xf) - 8, data, 0xff);
break;
}

8
src/devices/bus/a2bus/a2cffa.cpp
View File

@ -148,7 +148,7 @@ uint8_t a2bus_cffa2000_device::read_c0nx(address_space &space, uint8_t offset)
// Apple /// driver uses sta $c080,x when writing, which causes spurious reads of c088
if (!m_inwritecycle)
{
m_lastreaddata = m_ata->read_cs0(space, offset - 8, 0xffff);
m_lastreaddata = m_ata->read16_cs0(space, offset - 8, 0xffff);
}
return m_lastreaddata & 0xff;
@ -159,7 +159,7 @@ uint8_t a2bus_cffa2000_device::read_c0nx(address_space &space, uint8_t offset)
case 0xd:
case 0xe:
case 0xf:
return m_ata->read_cs0(space, offset-8, 0xff);
return m_ata->read16_cs0(space, offset-8, 0xff);
}
return 0xff;
@ -195,7 +195,7 @@ void a2bus_cffa2000_device::write_c0nx(address_space &space, uint8_t offset, uin
m_lastdata &= 0xff00;
m_lastdata |= data;
// printf("%02x to 8, m_lastdata = %x\n", data, m_lastdata);
m_ata->write_cs0(space, offset-8, m_lastdata, 0xffff);
m_ata->write16_cs0(space, offset-8, m_lastdata, 0xffff);
break;
case 9:
@ -205,7 +205,7 @@ void a2bus_cffa2000_device::write_c0nx(address_space &space, uint8_t offset, uin
case 0xd:
case 0xe:
case 0xf:
m_ata->write_cs0(space, offset-8, data, 0xff);
m_ata->write16_cs0(space, offset-8, data, 0xff);
break;
}
}

12
src/devices/bus/a2bus/a2vulcan.cpp
View File

@ -168,7 +168,7 @@ uint8_t a2bus_vulcanbase_device::read_c0nx(address_space &space, uint8_t offset)
switch (offset)
{
case 0:
m_lastdata = m_ata->read_cs0(space, offset, 0xffff);
m_lastdata = m_ata->read16_cs0(space, offset, 0xffff);
// printf("IDE: read %04x\n", m_lastdata);
m_last_read_was_0 = true;
return m_lastdata&0xff;
@ -181,7 +181,7 @@ uint8_t a2bus_vulcanbase_device::read_c0nx(address_space &space, uint8_t offset)
}
else
{
return m_ata->read_cs0(space, offset, 0xff);
return m_ata->read16_cs0(space, offset, 0xff);
}
case 2:
@ -190,7 +190,7 @@ uint8_t a2bus_vulcanbase_device::read_c0nx(address_space &space, uint8_t offset)
case 5:
case 6:
case 7:
return m_ata->read_cs0(space, offset, 0xff);
return m_ata->read16_cs0(space, offset, 0xff);
default:
logerror("a2vulcan: unknown read @ C0n%x\n", offset);
@ -222,11 +222,11 @@ void a2bus_vulcanbase_device::write_c0nx(address_space &space, uint8_t offset, u
m_lastdata &= 0x00ff;
m_lastdata |= (data << 8);
// printf("IDE: write %04x\n", m_lastdata);
m_ata->write_cs0(space, 0, m_lastdata, 0xffff);
m_ata->write16_cs0(space, 0, m_lastdata, 0xffff);
}
else
{
m_ata->write_cs0(space, offset, data, 0xff);
m_ata->write16_cs0(space, offset, data, 0xff);
}
break;
@ -237,7 +237,7 @@ void a2bus_vulcanbase_device::write_c0nx(address_space &space, uint8_t offset, u
case 6:
case 7:
// printf("%02x to IDE controller @ %x\n", data, offset);
m_ata->write_cs0(space, offset, data, 0xff);
m_ata->write16_cs0(space, offset, data, 0xff);
break;
case 9: // ROM bank

8
src/devices/bus/a2bus/a2zipdrive.cpp
View File

@ -111,10 +111,10 @@ uint8_t a2bus_zipdrivebase_device::read_c0nx(address_space &space, uint8_t offse
case 5:
case 6:
case 7:
return m_ata->read_cs0(space, offset, 0xff);
return m_ata->read16_cs0(space, offset, 0xff);
case 8: // data port
m_lastdata = m_ata->read_cs0(space, offset, 0xffff);
m_lastdata = m_ata->read16_cs0(space, offset, 0xffff);
// printf("%04x @ IDE data\n", m_lastdata);
return m_lastdata&0xff;
@ -147,7 +147,7 @@ void a2bus_zipdrivebase_device::write_c0nx(address_space &space, uint8_t offset,
case 6:
case 7:
// printf("%02x to IDE controller @ %x\n", data, offset);
m_ata->write_cs0(space, offset, data, 0xff);
m_ata->write16_cs0(space, offset, data, 0xff);
break;
case 8:
@ -159,7 +159,7 @@ void a2bus_zipdrivebase_device::write_c0nx(address_space &space, uint8_t offset,
// printf("%02x to IDE data hi\n", data);
m_lastdata &= 0x00ff;
m_lastdata |= (data << 8);
m_ata->write_cs0(space, 0, m_lastdata, 0xffff);
m_ata->write16_cs0(space, 0, m_lastdata, 0xffff);
break;
default:

10
src/devices/bus/adam/ide.cpp
View File

@ -114,7 +114,7 @@ uint8_t powermate_ide_device::adam_bd_r(address_space &space, offs_t offset, uin
case 0x05:
case 0x06:
case 0x07:
data = m_ata->read_cs0(space, offset & 0x07, 0xff);
data = m_ata->read16_cs0(space, offset & 0x07, 0xff);
break;
case 0x40: // Printer status
@ -135,7 +135,7 @@ uint8_t powermate_ide_device::adam_bd_r(address_space &space, offs_t offset, uin
break;
case 0x58:
m_ata_data = m_ata->read_cs0(space, 0, 0xffff);
m_ata_data = m_ata->read16_cs0(space, 0, 0xffff);
data = m_ata_data & 0xff;
break;
@ -145,7 +145,7 @@ uint8_t powermate_ide_device::adam_bd_r(address_space &space, offs_t offset, uin
break;
case 0x5a:
data = m_ata->read_cs1(space, 6, 0xff);
data = m_ata->read16_cs1(space, 6, 0xff);
break;
case 0x5b: // Digital Input Register
@ -174,7 +174,7 @@ void powermate_ide_device::adam_bd_w(address_space &space, offs_t offset, uint8_
case 0x05:
case 0x06:
case 0x07:
m_ata->write_cs0(space, offset & 0x07, data, 0xff);
m_ata->write16_cs0(space, offset & 0x07, data, 0xff);
break;
case 0x40:
@ -186,7 +186,7 @@ void powermate_ide_device::adam_bd_w(address_space &space, offs_t offset, uint8_
case 0x58:
m_ata_data |= data;
m_ata->write_cs0(space, 0, m_ata_data, 0xffff);
m_ata->write16_cs0(space, 0, m_ata_data, 0xffff);
break;
case 0x59:

16
src/devices/bus/amiga/zorro/buddha.cpp
View File

@ -257,7 +257,7 @@ WRITE16_MEMBER( buddha_device::ide_interrupt_enable_w )
READ16_MEMBER( buddha_device::ide_0_cs0_r )
{
uint16_t data = m_ata_0->read_cs0(space, (offset >> 1) & 0x07, (mem_mask << 8) | (mem_mask >> 8));
uint16_t data = m_ata_0->read16_cs0(space, (offset >> 1) & 0x07, (mem_mask << 8) | (mem_mask >> 8));
data = (data << 8) | (data >> 8);
if (VERBOSE)
@ -274,12 +274,12 @@ WRITE16_MEMBER( buddha_device::ide_0_cs0_w )
mem_mask = (mem_mask << 8) | (mem_mask >> 8);
data = (data << 8) | (data >> 8);
m_ata_0->write_cs0(space, (offset >> 1) & 0x07, data, mem_mask);
m_ata_0->write16_cs0(space, (offset >> 1) & 0x07, data, mem_mask);
}
READ16_MEMBER( buddha_device::ide_0_cs1_r )
{
uint16_t data = m_ata_0->read_cs1(space, (offset >> 1) & 0x07, (mem_mask << 8) | (mem_mask >> 8));
uint16_t data = m_ata_0->read16_cs1(space, (offset >> 1) & 0x07, (mem_mask << 8) | (mem_mask >> 8));
data = (data << 8) | (data >> 8);
if (VERBOSE)
@ -296,12 +296,12 @@ WRITE16_MEMBER( buddha_device::ide_0_cs1_w )
mem_mask = (mem_mask << 8) | (mem_mask >> 8);
data = (data << 8) | (data >> 8);
m_ata_0->write_cs1(space, (offset >> 1) & 0x07, data, mem_mask);
m_ata_0->write16_cs1(space, (offset >> 1) & 0x07, data, mem_mask);
}
READ16_MEMBER( buddha_device::ide_1_cs0_r )
{
uint16_t data = m_ata_1->read_cs0(space, (offset >> 1) & 0x07, (mem_mask << 8) | (mem_mask >> 8));
uint16_t data = m_ata_1->read16_cs0(space, (offset >> 1) & 0x07, (mem_mask << 8) | (mem_mask >> 8));
data = (data << 8) | (data >> 8);
if (VERBOSE)
@ -318,12 +318,12 @@ WRITE16_MEMBER( buddha_device::ide_1_cs0_w )
mem_mask = (mem_mask << 8) | (mem_mask >> 8);
data = (data << 8) | (data >> 8);
m_ata_1->write_cs0(space, (offset >> 1) & 0x07, data, mem_mask);
m_ata_1->write16_cs0(space, (offset >> 1) & 0x07, data, mem_mask);
}
READ16_MEMBER( buddha_device::ide_1_cs1_r )
{
uint16_t data = m_ata_1->read_cs1(space, (offset >> 1) & 0x07, (mem_mask << 8) | (mem_mask >> 8));
uint16_t data = m_ata_1->read16_cs1(space, (offset >> 1) & 0x07, (mem_mask << 8) | (mem_mask >> 8));
data = (data << 8) | (data >> 8);
if (VERBOSE)
@ -340,5 +340,5 @@ WRITE16_MEMBER( buddha_device::ide_1_cs1_w )
mem_mask = (mem_mask << 8) | (mem_mask >> 8);
data = (data << 8) | (data >> 8);
m_ata_1->write_cs1(space, (offset >> 1) & 0x07, data, mem_mask);
m_ata_1->write16_cs1(space, (offset >> 1) & 0x07, data, mem_mask);
}

8
src/devices/bus/c64/ide64.cpp
View File

@ -172,13 +172,13 @@ uint8_t c64_ide64_cartridge_device::c64_cd_r(address_space &space, offs_t offset
if (io1_offset >= 0x20 && io1_offset < 0x28)
{
m_ata_data = m_ata->read_cs0(space, offset & 0x07, 0xffff);
m_ata_data = m_ata->read16_cs0(space, offset & 0x07, 0xffff);
data = m_ata_data & 0xff;
}
else if (io1_offset >= 0x28 && io1_offset < 0x30)
{
m_ata_data = m_ata->read_cs1(space, offset & 0x07, 0xffff);
m_ata_data = m_ata->read16_cs1(space, offset & 0x07, 0xffff);
data = m_ata_data & 0xff;
}
@ -275,13 +275,13 @@ void c64_ide64_cartridge_device::c64_cd_w(address_space &space, offs_t offset, u
{
m_ata_data = (m_ata_data & 0xff00) | data;
m_ata->write_cs0(space, offset & 0x07, m_ata_data, 0xffff);
m_ata->write16_cs0(space, offset & 0x07, m_ata_data, 0xffff);
}
else if (io1_offset >= 0x28 && io1_offset < 0x30)
{
m_ata_data = (m_ata_data & 0xff00) | data;
m_ata->write_cs1(space, offset & 0x07, m_ata_data, 0xffff);
m_ata->write16_cs1(space, offset & 0x07, m_ata_data, 0xffff);
}
else if (io1_offset == 0x31)
{

10
src/devices/bus/cpc/symbfac2.cpp
View File

@ -135,27 +135,27 @@ READ8_MEMBER(cpc_symbiface2_device::ide_cs0_r)
else
{
m_iohigh = true;
m_ide_data = m_ide->read_cs0(space,offset);
m_ide_data = m_ide->read16_cs0(space,offset);
return m_ide_data & 0xff;
}
}
else
return m_ide->read_cs0(space,offset);
return m_ide->read16_cs0(space,offset);
}
WRITE8_MEMBER(cpc_symbiface2_device::ide_cs0_w)
{
m_ide->write_cs0(space,offset,data);
m_ide->write16_cs0(space,offset,data);
}
READ8_MEMBER(cpc_symbiface2_device::ide_cs1_r)
{
return m_ide->read_cs1(space,offset);
return m_ide->read16_cs1(space,offset);
}
WRITE8_MEMBER(cpc_symbiface2_device::ide_cs1_w)
{
m_ide->write_cs1(space,offset,data);
m_ide->write16_cs1(space,offset,data);
}
// RTC (Dallas DS1287A)

6
src/devices/bus/isa/ide.cpp
View File

@ -16,16 +16,16 @@
READ8_MEMBER(isa16_ide_device::ide16_alt_r )
{
return m_ide->read_cs1(space, 6/2, 0xff);
return m_ide->read16_cs1(space, 6/2, 0xff);
}
WRITE8_MEMBER(isa16_ide_device::ide16_alt_w )
{
m_ide->write_cs1(space, 6/2, data, 0xff);
m_ide->write16_cs1(space, 6/2, data, 0xff);
}
DEVICE_ADDRESS_MAP_START(map, 16, isa16_ide_device)
AM_RANGE(0x0, 0x7) AM_DEVREADWRITE("ide", ide_controller_device, read_cs0, write_cs0)
AM_RANGE(0x0, 0x7) AM_DEVREADWRITE("ide", ide_controller_device, read16_cs0, write16_cs0)
ADDRESS_MAP_END
DEVICE_ADDRESS_MAP_START(alt_map, 8, isa16_ide_device)

12
src/devices/bus/isa/side116.cpp
View File

@ -134,13 +134,13 @@ READ8_MEMBER( side116_device::read )
if (offset == 0)
{
uint16_t ide_data = m_ata->read_cs0(space, 0, 0xffff);
uint16_t ide_data = m_ata->read16_cs0(space, 0, 0xffff);
data = ide_data & 0xff;
m_latch = ide_data >> 8;
}
else if (offset < 8)
{
data = m_ata->read_cs0(space, offset & 7, 0xff);
data = m_ata->read16_cs0(space, offset & 7, 0xff);
}
else if (offset == 8)
{
@ -148,7 +148,7 @@ READ8_MEMBER( side116_device::read )
}
else
{
data = m_ata->read_cs1(space, offset & 7, 0xff);
data = m_ata->read16_cs1(space, offset & 7, 0xff);
}
return data;
@ -159,11 +159,11 @@ WRITE8_MEMBER( side116_device::write )
if (offset == 0)
{
uint16_t ide_data = (m_latch << 8) | data;
m_ata->write_cs0(space, 0, ide_data, 0xffff);
m_ata->write16_cs0(space, 0, ide_data, 0xffff);
}
else if (offset < 8)
{
m_ata->write_cs0(space, offset & 7, data, 0xff);
m_ata->write16_cs0(space, offset & 7, data, 0xff);
}
else if (offset == 8)
{
@ -171,7 +171,7 @@ WRITE8_MEMBER( side116_device::write )
}
else
{
m_ata->write_cs1(space, offset & 7, data, 0xff);
m_ata->write16_cs1(space, offset & 7, data, 0xff);
}
}

12
src/devices/bus/isa/xtide.cpp
View File

@ -63,13 +63,13 @@ READ8_MEMBER( xtide_device::read )
if (offset == 0)
{
uint16_t data16 = m_ata->read_cs0(space, offset & 7, 0xffff);
uint16_t data16 = m_ata->read16_cs0(space, offset & 7, 0xffff);
result = data16 & 0xff;
m_d8_d15_latch = data16 >> 8;
}
else if (offset < 8)
{
result = m_ata->read_cs0(space, offset & 7, 0xff);
result = m_ata->read16_cs0(space, offset & 7, 0xff);
}
else if (offset == 8)
{
@ -77,7 +77,7 @@ READ8_MEMBER( xtide_device::read )
}
else
{
result = m_ata->read_cs1(space, offset & 7, 0xff);
result = m_ata->read16_cs1(space, offset & 7, 0xff);
}
// logerror("%s xtide_device::read: offset=%d, result=%2X\n",device->machine().describe_context(),offset,result);
@ -93,11 +93,11 @@ WRITE8_MEMBER( xtide_device::write )
{
// Data register transfer low byte and latched high
uint16_t data16 = (m_d8_d15_latch << 8) | data;
m_ata->write_cs0(space, offset & 7, data16, 0xffff);
m_ata->write16_cs0(space, offset & 7, data16, 0xffff);
}
else if (offset < 8)
{
m_ata->write_cs0(space, offset & 7, data, 0xff);
m_ata->write16_cs0(space, offset & 7, data, 0xff);
}
else if (offset == 8)
{
@ -105,7 +105,7 @@ WRITE8_MEMBER( xtide_device::write )
}
else
{
m_ata->write_cs1(space, offset & 7, data, 0xff);
m_ata->write16_cs1(space, offset & 7, data, 0xff);
}
}

8
src/devices/bus/kc/d004.cpp
View File

@ -433,11 +433,11 @@ READ8_MEMBER(kc_d004_gide_device::gide_r)
{
if (ide_cs == 0 )
{
m_ata_data = m_ata->read_cs0(space, io_addr & 0x07, 0xffff);
m_ata_data = m_ata->read16_cs0(space, io_addr & 0x07, 0xffff);
}
else
{
m_ata_data = m_ata->read_cs1(space, io_addr & 0x07, 0xffff);
m_ata_data = m_ata->read16_cs1(space, io_addr & 0x07, 0xffff);
}
}
@ -482,11 +482,11 @@ WRITE8_MEMBER(kc_d004_gide_device::gide_w)
{
if (ide_cs == 0)
{
m_ata->write_cs0(space, io_addr & 0x07, m_ata_data, 0xffff);
m_ata->write16_cs0(space, io_addr & 0x07, m_ata_data, 0xffff);
}
else
{
m_ata->write_cs1(space, io_addr & 0x07, m_ata_data, 0xffff);
m_ata->write16_cs1(space, io_addr & 0x07, m_ata_data, 0xffff);
}
}
}

16
src/devices/bus/lpci/southbridge.cpp
View File

@ -136,22 +136,22 @@ southbridge_device::southbridge_device(const machine_config &mconfig, device_typ
/// HACK: the memory system cannot cope with mixing the 8 bit device map from the fdc with a 32 bit handler
READ8_MEMBER(southbridge_device::ide_read_cs1_r)
{
return m_ide->read_cs1(space, 1, (uint32_t) 0xff0000) >> 16;
return m_ide->read32_cs1(space, 1, (uint32_t) 0xff0000) >> 16;
}
WRITE8_MEMBER(southbridge_device::ide_write_cs1_w)
{
m_ide->write_cs1(space, 1, (uint32_t) data << 16, (uint32_t) 0xff0000);
m_ide->write32_cs1(space, 1, (uint32_t) data << 16, (uint32_t) 0xff0000);
}
READ8_MEMBER(southbridge_device::ide2_read_cs1_r)
{
return m_ide2->read_cs1(space, 1, (uint32_t) 0xff0000) >> 16;
return m_ide2->read32_cs1(space, 1, (uint32_t) 0xff0000) >> 16;
}
WRITE8_MEMBER(southbridge_device::ide2_write_cs1_w)
{
m_ide2->write_cs1(space, 1, (uint32_t) data << 16, (uint32_t) 0xff0000);
m_ide2->write32_cs1(space, 1, (uint32_t) data << 16, (uint32_t) 0xff0000);
}
//-------------------------------------------------
@ -169,11 +169,11 @@ void southbridge_device::device_start()
spaceio.install_readwrite_handler(0x0080, 0x009f, read8_delegate(FUNC(southbridge_device::at_page8_r),this), write8_delegate(FUNC(southbridge_device::at_page8_w),this), 0xffffffff);
spaceio.install_readwrite_handler(0x00a0, 0x00bf, read8_delegate(FUNC(pic8259_device::read),&(*m_pic8259_slave)), write8_delegate(FUNC(pic8259_device::write),&(*m_pic8259_slave)), 0xffffffff);
spaceio.install_readwrite_handler(0x00c0, 0x00df, read8_delegate(FUNC(southbridge_device::at_dma8237_2_r),this), write8_delegate(FUNC(southbridge_device::at_dma8237_2_w),this), 0xffffffff);
spaceio.install_readwrite_handler(0x0170, 0x0177, read32_delegate(FUNC(bus_master_ide_controller_device::read_cs0),&(*m_ide2)), write32_delegate(FUNC(bus_master_ide_controller_device::write_cs0), &(*m_ide2)),0xffffffff);
spaceio.install_readwrite_handler(0x01f0, 0x01f7, read32_delegate(FUNC(bus_master_ide_controller_device::read_cs0),&(*m_ide)), write32_delegate(FUNC(bus_master_ide_controller_device::write_cs0), &(*m_ide)),0xffffffff);
spaceio.install_readwrite_handler(0x0170, 0x0177, read32_delegate(FUNC(bus_master_ide_controller_device::read32_cs0),&(*m_ide2)), write32_delegate(FUNC(bus_master_ide_controller_device::write32_cs0), &(*m_ide2)),0xffffffff);
spaceio.install_readwrite_handler(0x01f0, 0x01f7, read32_delegate(FUNC(bus_master_ide_controller_device::read32_cs0),&(*m_ide)), write32_delegate(FUNC(bus_master_ide_controller_device::write32_cs0), &(*m_ide)),0xffffffff);
// HACK: this works if you take out the (non working) fdc
// spaceio.install_readwrite_handler(0x0370, 0x0377, read32_delegate(FUNC(bus_master_ide_controller_device::read_cs1),&(*m_ide2)), write32_delegate(FUNC(bus_master_ide_controller_device::write_cs1), &(*m_ide2)),0xffffffff);
// spaceio.install_readwrite_handler(0x03f0, 0x03f7, read32_delegate(FUNC(bus_master_ide_controller_device::read_cs1),&(*m_ide)), write32_delegate(FUNC(bus_master_ide_controller_device::write_cs1), &(*m_ide)),0xffffffff);
// spaceio.install_readwrite_handler(0x0370, 0x0377, read32_delegate(FUNC(bus_master_ide_controller_device::read32_cs1),&(*m_ide2)), write32_delegate(FUNC(bus_master_ide_controller_device::write32_cs1), &(*m_ide2)),0xffffffff);
// spaceio.install_readwrite_handler(0x03f0, 0x03f7, read32_delegate(FUNC(bus_master_ide_controller_device::read32_cs1),&(*m_ide)), write32_delegate(FUNC(bus_master_ide_controller_device::write32_cs1), &(*m_ide)),0xffffffff);
spaceio.install_readwrite_handler(0x0374, 0x0377, read8_delegate(FUNC(southbridge_device::ide2_read_cs1_r),this), write8_delegate(FUNC(southbridge_device::ide2_write_cs1_w), this),0xff0000);
spaceio.install_readwrite_handler(0x03f4, 0x03f7, read8_delegate(FUNC(southbridge_device::ide_read_cs1_r),this), write8_delegate(FUNC(southbridge_device::ide_write_cs1_w), this),0xff0000);
spaceio.nop_readwrite(0x00e0, 0x00ef);

14
src/devices/bus/ql/qubide.cpp
View File

@ -210,15 +210,15 @@ uint8_t qubide_device::read(address_space &space, offs_t offset, uint8_t data)
switch (offset & 0x0f)
{
case 0:
data = m_ata->read_cs1(space, 0x07, 0xff);
data = m_ata->read16_cs1(space, 0x07, 0xff);
break;
default:
data = m_ata->read_cs0(space, offset & 0x07, 0xff);
data = m_ata->read16_cs0(space, offset & 0x07, 0xff);
break;
case 0x08: case 0x0a: case 0x0c:
m_ata_data = m_ata->read_cs0(space, 0x00, 0xffff);
m_ata_data = m_ata->read16_cs0(space, 0x00, 0xffff);
data = m_ata_data >> 8;
break;
@ -228,7 +228,7 @@ uint8_t qubide_device::read(address_space &space, offs_t offset, uint8_t data)
break;
case 0x0e: case 0x0f:
data = m_ata->read_cs1(space, 0x05, 0xff);
data = m_ata->read16_cs1(space, 0x05, 0xff);
break;
}
}
@ -255,7 +255,7 @@ void qubide_device::write(address_space &space, offs_t offset, uint8_t data)
switch (offset & 0x0f)
{
case 0: case 0x0e: case 0x0f:
m_ata->write_cs1(space, 0x05, data, 0xff);
m_ata->write16_cs1(space, 0x05, data, 0xff);
break;
case 0x08: case 0x0a: case 0x0c:
@ -265,11 +265,11 @@ void qubide_device::write(address_space &space, offs_t offset, uint8_t data)
case 0x09: case 0x0b: case 0x0d:
m_ata_data = (m_ata_data & 0xff00) | data;
m_ata->write_cs0(space, 0x00, m_ata_data, 0xffff);
m_ata->write16_cs0(space, 0x00, m_ata_data, 0xffff);
break;
default:
m_ata->write_cs0(space, offset & 0x07, data, 0xff);
m_ata->write16_cs0(space, offset & 0x07, data, 0xff);
break;
}
}

8
src/devices/bus/ti99/peb/tn_ide.cpp
View File

@ -160,7 +160,7 @@ READ8Z_MEMBER(nouspikel_ide_interface_device::readz)
case 2: /* IDE registers set 1 (CS1Fx) */
if (m_tms9995_mode ? (!(addr & 1)) : (addr & 1))
{ /* first read triggers 16-bit read cycle */
m_input_latch = (! (addr & 0x10)) ? m_ata->read_cs0(space, (addr >> 1) & 0x7, 0xffff) : 0;
m_input_latch = (! (addr & 0x10)) ? m_ata->read16_cs0(space, (addr >> 1) & 0x7, 0xffff) : 0;
}
/* return latched input */
@ -171,7 +171,7 @@ READ8Z_MEMBER(nouspikel_ide_interface_device::readz)
case 3: /* IDE registers set 2 (CS3Fx) */
if (m_tms9995_mode ? (!(addr & 1)) : (addr & 1))
{ /* first read triggers 16-bit read cycle */
m_input_latch = (! (addr & 0x10)) ? m_ata->read_cs1(space, (addr >> 1) & 0x7, 0xffff) : 0;
m_input_latch = (! (addr & 0x10)) ? m_ata->read16_cs1(space, (addr >> 1) & 0x7, 0xffff) : 0;
}
/* return latched input */
@ -243,7 +243,7 @@ WRITE8_MEMBER(nouspikel_ide_interface_device::write)
if (m_tms9995_mode ? (addr & 1) : (!(addr & 1)))
{ /* second write triggers 16-bit write cycle */
m_ata->write_cs0(space, (addr >> 1) & 0x7, m_output_latch, 0xffff);
m_ata->write16_cs0(space, (addr >> 1) & 0x7, m_output_latch, 0xffff);
}
break;
case 3: /* IDE registers set 2 (CS3Fx) */
@ -261,7 +261,7 @@ WRITE8_MEMBER(nouspikel_ide_interface_device::write)
if (m_tms9995_mode ? (addr & 1) : (!(addr & 1)))
{ /* second write triggers 16-bit write cycle */
m_ata->write_cs1(space, (addr >> 1) & 0x7, m_output_latch, 0xffff);
m_ata->write16_cs1(space, (addr >> 1) & 0x7, m_output_latch, 0xffff);
}
break;
}

8
src/devices/machine/atadev.h
View File

@ -25,12 +25,12 @@ public:
device_ata_interface(const machine_config &mconfig, device_t &device);
virtual uint16_t read_dma() = 0;
virtual DECLARE_READ16_MEMBER(read_cs0) = 0;
virtual DECLARE_READ16_MEMBER(read_cs1) = 0;
virtual DECLARE_READ16_MEMBER(read16_cs0) = 0;
virtual DECLARE_READ16_MEMBER(read16_cs1) = 0;
virtual void write_dma(uint16_t data) = 0;
virtual DECLARE_WRITE16_MEMBER(write_cs0) = 0;
virtual DECLARE_WRITE16_MEMBER(write_cs1) = 0;
virtual DECLARE_WRITE16_MEMBER(write16_cs0) = 0;
virtual DECLARE_WRITE16_MEMBER(write16_cs1) = 0;
virtual DECLARE_WRITE_LINE_MEMBER(write_dmack) = 0;
virtual DECLARE_WRITE_LINE_MEMBER(write_csel) = 0;
virtual DECLARE_WRITE_LINE_MEMBER(write_dasp) = 0;

8
src/devices/machine/ataflash.cpp
View File

@ -37,11 +37,11 @@ READ16_MEMBER( ata_flash_pccard_device::read_memory )
if(offset <= 7)
{
m_8bit_data_transfers = !ACCESSING_BITS_8_15; // HACK
return read_cs0(space, offset, mem_mask);
return read16_cs0(space, offset, mem_mask);
}
else if(offset <= 15)
{
return read_cs1(space, offset & 7, mem_mask);
return read16_cs1(space, offset & 7, mem_mask);
}
else
{
@ -54,11 +54,11 @@ WRITE16_MEMBER( ata_flash_pccard_device::write_memory )
if(offset <= 7)
{
m_8bit_data_transfers = !ACCESSING_BITS_8_15; // HACK
write_cs0(space, offset, data, mem_mask);
write16_cs0(space, offset, data, mem_mask);
}
else if( offset <= 15)
{
write_cs1(space, offset & 7, data, mem_mask);
write16_cs1(space, offset & 7, data, mem_mask);
}
}

8
src/devices/machine/atahle.cpp
View File

@ -584,7 +584,7 @@ uint16_t ata_hle_device::read_dma()
return result;
}
READ16_MEMBER( ata_hle_device::read_cs0 )
READ16_MEMBER( ata_hle_device::read16_cs0 )
{
/* logit */
// if (offset != IDE_CS0_DATA_RW && offset != IDE_CS0_STATUS_R)
@ -702,7 +702,7 @@ READ16_MEMBER( ata_hle_device::read_cs0 )
return result;
}
READ16_MEMBER( ata_hle_device::read_cs1 )
READ16_MEMBER( ata_hle_device::read16_cs1 )
{
/* logit */
// if (offset != IDE_CS1_ALTERNATE_STATUS_R)
@ -806,7 +806,7 @@ void ata_hle_device::write_dma( uint16_t data )
}
}
WRITE16_MEMBER( ata_hle_device::write_cs0 )
WRITE16_MEMBER( ata_hle_device::write16_cs0 )
{
/* logit */
if (offset != IDE_CS0_DATA_RW)
@ -915,7 +915,7 @@ WRITE16_MEMBER( ata_hle_device::write_cs0 )
}
}
WRITE16_MEMBER( ata_hle_device::write_cs1 )
WRITE16_MEMBER( ata_hle_device::write16_cs1 )
{
/* logit */
LOG(("%s:IDE cs1 write to %X = %08X, mem_mask=%d\n", machine().describe_context(), offset, data, mem_mask));

8
src/devices/machine/atahle.h
View File

@ -19,12 +19,12 @@ class ata_hle_device : public device_t, public device_ata_interface
{
public:
virtual uint16_t read_dma() override;
virtual DECLARE_READ16_MEMBER(read_cs0) override;
virtual DECLARE_READ16_MEMBER(read_cs1) override;
virtual DECLARE_READ16_MEMBER(read16_cs0) override;
virtual DECLARE_READ16_MEMBER(read16_cs1) override;
virtual void write_dma(uint16_t data) override;
virtual DECLARE_WRITE16_MEMBER(write_cs0) override;
virtual DECLARE_WRITE16_MEMBER(write_cs1) override;
virtual DECLARE_WRITE16_MEMBER(write16_cs0) override;
virtual DECLARE_WRITE16_MEMBER(write16_cs1) override;
virtual DECLARE_WRITE_LINE_MEMBER(write_csel) override;
virtual DECLARE_WRITE_LINE_MEMBER(write_dasp) override;
virtual DECLARE_WRITE_LINE_MEMBER(write_dmack) override;

16
src/devices/machine/ataintf.cpp
View File

@ -136,12 +136,12 @@ uint16_t ata_interface_device::read_dma()
return result;
}
READ16_MEMBER( ata_interface_device::read_cs0 )
READ16_MEMBER( ata_interface_device::read16_cs0 )
{
uint16_t result = mem_mask;
for (auto & elem : m_slot)
if (elem->dev() != nullptr)
result &= elem->dev()->read_cs0(space, offset, mem_mask);
result &= elem->dev()->read16_cs0(space, offset, mem_mask);
// { static int last_status = -1; if (offset == 7 ) { if( result == last_status ) return last_status; last_status = result; } else last_status = -1; }
@ -150,12 +150,12 @@ READ16_MEMBER( ata_interface_device::read_cs0 )
return result;
}
READ16_MEMBER( ata_interface_device::read_cs1 )
READ16_MEMBER( ata_interface_device::read16_cs1 )
{
uint16_t result = mem_mask;
for (auto & elem : m_slot)
if (elem->dev() != nullptr)
result &= elem->dev()->read_cs1(space, offset, mem_mask);
result &= elem->dev()->read16_cs1(space, offset, mem_mask);
// logerror( "%s: read cs1 %04x %04x %04x\n", machine().describe_context(), offset, result, mem_mask );
@ -178,22 +178,22 @@ void ata_interface_device::write_dma( uint16_t data )
elem->dev()->write_dma(data);
}
WRITE16_MEMBER( ata_interface_device::write_cs0 )
WRITE16_MEMBER( ata_interface_device::write16_cs0 )
{
// logerror( "%s: write cs0 %04x %04x %04x\n", machine().describe_context(), offset, data, mem_mask );
for (auto & elem : m_slot)
if (elem->dev() != nullptr)
elem->dev()->write_cs0(space, offset, data, mem_mask);
elem->dev()->write16_cs0(space, offset, data, mem_mask);
}
WRITE16_MEMBER( ata_interface_device::write_cs1 )
WRITE16_MEMBER( ata_interface_device::write16_cs1 )
{
// logerror( "%s: write cs1 %04x %04x %04x\n", machine().describe_context(), offset, data, mem_mask );
for (auto & elem : m_slot)
if (elem->dev() != nullptr)
elem->dev()->write_cs1(space, offset, data, mem_mask);
elem->dev()->write16_cs1(space, offset, data, mem_mask);
}
WRITE_LINE_MEMBER( ata_interface_device::write_dmack )

8
src/devices/machine/ataintf.h
View File

@ -86,12 +86,12 @@ public:
template <class Object> static devcb_base &set_dasp_handler(device_t &device, Object &&cb) { return downcast<ata_interface_device &>(device).m_dasp_handler.set_callback(std::forward<Object>(cb)); }
uint16_t read_dma();
virtual DECLARE_READ16_MEMBER(read_cs0);
virtual DECLARE_READ16_MEMBER(read_cs1);
virtual DECLARE_READ16_MEMBER(read16_cs0);
virtual DECLARE_READ16_MEMBER(read16_cs1);
void write_dma(uint16_t data);
virtual DECLARE_WRITE16_MEMBER(write_cs0);
virtual DECLARE_WRITE16_MEMBER(write_cs1);
virtual DECLARE_WRITE16_MEMBER(write16_cs0);
virtual DECLARE_WRITE16_MEMBER(write16_cs1);
DECLARE_WRITE_LINE_MEMBER(write_dmack);
protected:

52
src/devices/machine/idectrl.cpp
View File

@ -36,7 +36,7 @@ ide_controller_device::ide_controller_device(const machine_config &mconfig, devi
{
}
READ16_MEMBER( ide_controller_device::read_cs0 )
READ16_MEMBER( ide_controller_device::read16_cs0 )
{
if (mem_mask == 0xffff && offset == 1)
{
@ -45,48 +45,48 @@ READ16_MEMBER( ide_controller_device::read_cs0 )
}
if (mem_mask == 0xff00)
{
return ata_interface_device::read_cs0(space, (offset * 2) + 1, 0xff) << 8;
return ata_interface_device::read16_cs0(space, (offset * 2) + 1, 0xff) << 8;
}
else
{
return ata_interface_device::read_cs0(space, offset * 2, mem_mask);
return ata_interface_device::read16_cs0(space, offset * 2, mem_mask);
}
}
READ16_MEMBER( ide_controller_device::read_cs1 )
READ16_MEMBER( ide_controller_device::read16_cs1 )
{
if (mem_mask == 0xff00)
{
return ata_interface_device::read_cs1(space, (offset * 2) + 1, 0xff) << 8;
return ata_interface_device::read16_cs1(space, (offset * 2) + 1, 0xff) << 8;
}
else
{
return ata_interface_device::read_cs1(space, offset * 2, mem_mask);
return ata_interface_device::read16_cs1(space, offset * 2, mem_mask);
}
}
WRITE16_MEMBER( ide_controller_device::write_cs0 )
WRITE16_MEMBER( ide_controller_device::write16_cs0 )
{
if (mem_mask == 0xffff && offset == 1 ){ offset = 0; popmessage( "requires ide_controller_32_device" ); }
if (mem_mask == 0xff00)
{
return ata_interface_device::write_cs0(space, (offset * 2) + 1, data >> 8, 0xff);
return ata_interface_device::write16_cs0(space, (offset * 2) + 1, data >> 8, 0xff);
}
else
{
return ata_interface_device::write_cs0(space, offset * 2, data, mem_mask);
return ata_interface_device::write16_cs0(space, offset * 2, data, mem_mask);
}
}
WRITE16_MEMBER( ide_controller_device::write_cs1 )
WRITE16_MEMBER( ide_controller_device::write16_cs1 )
{
if (mem_mask == 0xff00)
{
return ata_interface_device::write_cs1(space, (offset * 2) + 1, data >> 8, 0xff);
return ata_interface_device::write16_cs1(space, (offset * 2) + 1, data >> 8, 0xff);
}
else
{
return ata_interface_device::write_cs1(space, offset * 2, data, mem_mask);
return ata_interface_device::write16_cs1(space, offset * 2, data, mem_mask);
}
}
@ -103,65 +103,65 @@ ide_controller_32_device::ide_controller_32_device(const machine_config &mconfig
{
}
READ32_MEMBER(ide_controller_32_device::read_cs0)
READ32_MEMBER(ide_controller_32_device::read32_cs0)
{
uint32_t data = 0;
if (ACCESSING_BITS_0_15)
{
data = ide_controller_device::read_cs0(space, (offset * 2), mem_mask);
data = ide_controller_device::read16_cs0(space, (offset * 2), mem_mask);
if (offset == 0 && ACCESSING_BITS_16_31)
data |= ide_controller_device::read_cs0(space, (offset * 2), mem_mask >> 16) << 16;
data |= ide_controller_device::read16_cs0(space, (offset * 2), mem_mask >> 16) << 16;
}
else if (ACCESSING_BITS_16_31)
{
data = ide_controller_device::read_cs0(space, (offset * 2) + 1, mem_mask >> 16) << 16;
data = ide_controller_device::read16_cs0(space, (offset * 2) + 1, mem_mask >> 16) << 16;
}
return data;
}
READ32_MEMBER(ide_controller_32_device::read_cs1)
READ32_MEMBER(ide_controller_32_device::read32_cs1)
{
uint32_t data = 0;
if (ACCESSING_BITS_0_15)
{
data = ide_controller_device::read_cs1(space, (offset * 2), mem_mask);
data = ide_controller_device::read16_cs1(space, (offset * 2), mem_mask);
}
else if (ACCESSING_BITS_16_23)
{
data = ide_controller_device::read_cs1(space, (offset * 2) + 1, mem_mask >> 16) << 16;
data = ide_controller_device::read16_cs1(space, (offset * 2) + 1, mem_mask >> 16) << 16;
}
return data;
}
WRITE32_MEMBER(ide_controller_32_device::write_cs0)
WRITE32_MEMBER(ide_controller_32_device::write32_cs0)
{
if (ACCESSING_BITS_0_15)
{
ide_controller_device::write_cs0(space, (offset * 2), data, mem_mask);
ide_controller_device::write16_cs0(space, (offset * 2), data, mem_mask);
if (offset == 0 && ACCESSING_BITS_16_31)
ata_interface_device::write_cs0(space, (offset * 2), data >> 16, mem_mask >> 16);
ata_interface_device::write16_cs0(space, (offset * 2), data >> 16, mem_mask >> 16);
}
else if (ACCESSING_BITS_16_31)
{
ide_controller_device::write_cs0(space, (offset * 2) + 1, data >> 16, mem_mask >> 16);
ide_controller_device::write16_cs0(space, (offset * 2) + 1, data >> 16, mem_mask >> 16);
}
}
WRITE32_MEMBER(ide_controller_32_device::write_cs1)
WRITE32_MEMBER(ide_controller_32_device::write32_cs1)
{
if (ACCESSING_BITS_0_15)
{
ide_controller_device::write_cs1(space, (offset * 2), data, mem_mask);
ide_controller_device::write16_cs1(space, (offset * 2), data, mem_mask);
}
else if (ACCESSING_BITS_16_31)
{
ide_controller_device::write_cs1(space, (offset * 2) + 1, data >> 16, mem_mask >> 16);
ide_controller_device::write16_cs1(space, (offset * 2) + 1, data >> 16, mem_mask >> 16);
}
}

24
src/devices/machine/idectrl.h
View File

@ -32,10 +32,10 @@ class ide_controller_device : public ata_interface_device
public:
ide_controller_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
virtual DECLARE_READ16_MEMBER(read_cs0) override;
virtual DECLARE_READ16_MEMBER(read_cs1) override;
virtual DECLARE_WRITE16_MEMBER(write_cs0) override;
virtual DECLARE_WRITE16_MEMBER(write_cs1) override;
virtual DECLARE_READ16_MEMBER(read16_cs0) override;
virtual DECLARE_READ16_MEMBER(read16_cs1) override;
virtual DECLARE_WRITE16_MEMBER(write16_cs0) override;
virtual DECLARE_WRITE16_MEMBER(write16_cs1) override;
protected:
ide_controller_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
@ -57,19 +57,19 @@ class ide_controller_32_device : public ide_controller_device
public:
ide_controller_32_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
virtual DECLARE_READ32_MEMBER(read_cs0);
virtual DECLARE_READ32_MEMBER(read_cs1);
virtual DECLARE_WRITE32_MEMBER(write_cs0);
virtual DECLARE_WRITE32_MEMBER(write_cs1);
virtual DECLARE_READ32_MEMBER(read32_cs0);
virtual DECLARE_READ32_MEMBER(read32_cs1);
virtual DECLARE_WRITE32_MEMBER(write32_cs0);
virtual DECLARE_WRITE32_MEMBER(write32_cs1);
protected:
ide_controller_32_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
private:
using ide_controller_device::read_cs0;
using ide_controller_device::read_cs1;
using ide_controller_device::write_cs0;
using ide_controller_device::write_cs1;
using ide_controller_device::read16_cs0;
using ide_controller_device::read16_cs1;
using ide_controller_device::write16_cs0;
using ide_controller_device::write16_cs1;
};
DECLARE_DEVICE_TYPE(IDE_CONTROLLER_32, ide_controller_32_device)

12
src/devices/machine/pci-ide.cpp
View File

@ -27,7 +27,7 @@ DEVICE_ADDRESS_MAP_START(config_map, 32, ide_pci_device)
ADDRESS_MAP_END
DEVICE_ADDRESS_MAP_START(chan1_data_command_map, 32, ide_pci_device)
AM_RANGE(0x0, 0x7) AM_DEVREADWRITE("ide", bus_master_ide_controller_device, read_cs0, write_cs0)
AM_RANGE(0x0, 0x7) AM_DEVREADWRITE("ide", bus_master_ide_controller_device, read32_cs0, write32_cs0)
ADDRESS_MAP_END
DEVICE_ADDRESS_MAP_START(chan1_control_map, 32, ide_pci_device)
@ -35,7 +35,7 @@ DEVICE_ADDRESS_MAP_START(chan1_control_map, 32, ide_pci_device)
ADDRESS_MAP_END
DEVICE_ADDRESS_MAP_START(chan2_data_command_map, 32, ide_pci_device)
AM_RANGE(0x0, 0x7) AM_DEVREADWRITE("ide2", bus_master_ide_controller_device, read_cs0, write_cs0)
AM_RANGE(0x0, 0x7) AM_DEVREADWRITE("ide2", bus_master_ide_controller_device, read32_cs0, write32_cs0)
ADDRESS_MAP_END
DEVICE_ADDRESS_MAP_START(chan2_control_map, 32, ide_pci_device)
@ -117,7 +117,7 @@ READ32_MEMBER(ide_pci_device::ide_read_cs1)
{
// PCI offset starts at 0x3f4, idectrl expects 0x3f0
uint32_t data;
data = m_ide->read_cs1(space, 1, mem_mask);
data = m_ide->read32_cs1(space, 1, mem_mask);
if (0)
logerror("%s:ide_read_cs1 offset=%08X data=%08X mask=%08X\n", machine().describe_context(), offset, data, mem_mask);
return data;
@ -126,21 +126,21 @@ READ32_MEMBER(ide_pci_device::ide_read_cs1)
WRITE32_MEMBER(ide_pci_device::ide_write_cs1)
{
// PCI offset starts at 0x3f4, idectrl expects 0x3f0
m_ide->write_cs1(space, 1, data, mem_mask);
m_ide->write32_cs1(space, 1, data, mem_mask);
}
READ32_MEMBER(ide_pci_device::ide2_read_cs1)
{
// PCI offset starts at 0x374, idectrl expects 0x370
uint32_t data;
data = m_ide2->read_cs1(space, 1, mem_mask);
data = m_ide2->read32_cs1(space, 1, mem_mask);
return data;
}
WRITE32_MEMBER(ide_pci_device::ide2_write_cs1)
{
// PCI offset starts at 0x374, idectrl expects 0x370
m_ide2->write_cs1(space, 1, data, mem_mask);
m_ide2->write32_cs1(space, 1, data, mem_mask);
}
WRITE_LINE_MEMBER(ide_pci_device::ide_interrupt)

24
src/mame/drivers/amiga.cpp
View File

@ -755,9 +755,9 @@ READ16_MEMBER( a4000_state::ide_r )
// this very likely doesn't respond to all the addresses, figure out which ones
if (BIT(offset, 12))
data = m_ata->read_cs1(space, (offset >> 1) & 0x07, mem_mask);
data = m_ata->read16_cs1(space, (offset >> 1) & 0x07, mem_mask);
else
data = m_ata->read_cs0(space, (offset >> 1) & 0x07, mem_mask);
data = m_ata->read16_cs0(space, (offset >> 1) & 0x07, mem_mask);
// swap
data = (data << 8) | (data >> 8);
@ -777,9 +777,9 @@ WRITE16_MEMBER( a4000_state::ide_w )
// this very likely doesn't respond to all the addresses, figure out which ones
if (BIT(offset, 12))
m_ata->write_cs1(space, (offset >> 1) & 0x07, data, mem_mask);
m_ata->write16_cs1(space, (offset >> 1) & 0x07, data, mem_mask);
else
m_ata->write_cs0(space, (offset >> 1) & 0x07, data, mem_mask);
m_ata->write16_cs0(space, (offset >> 1) & 0x07, data, mem_mask);
}
WRITE_LINE_MEMBER( a4000_state::ide_interrupt_w )
@ -1658,10 +1658,10 @@ static MACHINE_CONFIG_DERIVED( a600, amiga_base )
MCFG_GAYLE_ADD("gayle", amiga_state::CLK_28M_PAL / 2, a600_state::GAYLE_ID)
MCFG_GAYLE_INT2_HANDLER(WRITELINE(a600_state, gayle_int2_w))
MCFG_GAYLE_CS0_READ_HANDLER(DEVREAD16("ata", ata_interface_device, read_cs0))
MCFG_GAYLE_CS0_WRITE_HANDLER(DEVWRITE16("ata", ata_interface_device, write_cs0))
MCFG_GAYLE_CS1_READ_HANDLER(DEVREAD16("ata", ata_interface_device, read_cs1))
MCFG_GAYLE_CS1_WRITE_HANDLER(DEVWRITE16("ata", ata_interface_device, write_cs1))
MCFG_GAYLE_CS0_READ_HANDLER(DEVREAD16("ata", ata_interface_device, read16_cs0))
MCFG_GAYLE_CS0_WRITE_HANDLER(DEVWRITE16("ata", ata_interface_device, write16_cs0))
MCFG_GAYLE_CS1_READ_HANDLER(DEVREAD16("ata", ata_interface_device, read16_cs1))
MCFG_GAYLE_CS1_WRITE_HANDLER(DEVWRITE16("ata", ata_interface_device, write16_cs1))
MCFG_ATA_INTERFACE_ADD("ata", ata_devices, "hdd", nullptr, false)
MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("gayle", gayle_device, ide_interrupt_w))
@ -1711,10 +1711,10 @@ static MACHINE_CONFIG_DERIVED( a1200, amiga_base )
MCFG_GAYLE_ADD("gayle", amiga_state::CLK_28M_PAL / 2, a1200_state::GAYLE_ID)
MCFG_GAYLE_INT2_HANDLER(WRITELINE(a1200_state, gayle_int2_w))
MCFG_GAYLE_CS0_READ_HANDLER(DEVREAD16("ata", ata_interface_device, read_cs0))
MCFG_GAYLE_CS0_WRITE_HANDLER(DEVWRITE16("ata", ata_interface_device, write_cs0))
MCFG_GAYLE_CS1_READ_HANDLER(DEVREAD16("ata", ata_interface_device, read_cs1))
MCFG_GAYLE_CS1_WRITE_HANDLER(DEVWRITE16("ata", ata_interface_device, write_cs1))
MCFG_GAYLE_CS0_READ_HANDLER(DEVREAD16("ata", ata_interface_device, read16_cs0))
MCFG_GAYLE_CS0_WRITE_HANDLER(DEVWRITE16("ata", ata_interface_device, write16_cs0))
MCFG_GAYLE_CS1_READ_HANDLER(DEVREAD16("ata", ata_interface_device, read16_cs1))
MCFG_GAYLE_CS1_WRITE_HANDLER(DEVWRITE16("ata", ata_interface_device, write16_cs1))
MCFG_ATA_INTERFACE_ADD("ata", ata_devices, "hdd", nullptr, false)
MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("gayle", gayle_device, ide_interrupt_w))

8
src/mame/drivers/at.cpp
View File

@ -216,10 +216,10 @@ static ADDRESS_MAP_START( ficpio_io, AS_IO, 32, at_state )
ADDRESS_MAP_UNMAP_HIGH
AM_RANGE(0x00a8, 0x00af) AM_DEVREADWRITE8("chipset", vt82c496_device, read, write, 0xffffffff)
AM_RANGE(0x0000, 0x00ff) AM_DEVICE16("mb", at_mb_device, map, 0xffffffff)
AM_RANGE(0x0170, 0x0177) AM_DEVREADWRITE("ide2", ide_controller_32_device, read_cs0, write_cs0)
AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE("ide", ide_controller_32_device, read_cs0, write_cs0)
AM_RANGE(0x0370, 0x0377) AM_DEVREADWRITE("ide2", ide_controller_32_device, read_cs1, write_cs1)
AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE("ide", ide_controller_32_device, read_cs1, write_cs1)
AM_RANGE(0x0170, 0x0177) AM_DEVREADWRITE("ide2", ide_controller_32_device, read32_cs0, write32_cs0)
AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE("ide", ide_controller_32_device, read32_cs0, write32_cs0)
AM_RANGE(0x0370, 0x0377) AM_DEVREADWRITE("ide2", ide_controller_32_device, read32_cs1, write32_cs1)
AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE("ide", ide_controller_32_device, read32_cs1, write32_cs1)
AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_device, read, write)
ADDRESS_MAP_END

4
src/mame/drivers/bebox.cpp
View File

@ -47,14 +47,14 @@ static ADDRESS_MAP_START( bebox_mem, AS_PROGRAM, 64, bebox_state )
AM_RANGE(0x80000080, 0x8000009F) AM_READWRITE8(bebox_page_r, bebox_page_w, 0xffffffffffffffffU )
AM_RANGE(0x800000A0, 0x800000BF) AM_DEVREADWRITE8("pic8259_2", pic8259_device, read, write, 0xffffffffffffffffU )
AM_RANGE(0x800000C0, 0x800000DF) AM_READWRITE8(at_dma8237_1_r, at_dma8237_1_w, 0xffffffffffffffffU)
AM_RANGE(0x800001F0, 0x800001F7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffffffffffffU )
AM_RANGE(0x800001F0, 0x800001F7) AM_DEVREADWRITE16("ide", ide_controller_device, read16_cs0, write16_cs0, 0xffffffffffffffffU )
AM_RANGE(0x800002F8, 0x800002FF) AM_DEVREADWRITE8( "ns16550_1", ns16550_device, ins8250_r, ins8250_w, 0xffffffffffffffffU )
AM_RANGE(0x80000380, 0x80000387) AM_DEVREADWRITE8( "ns16550_2", ns16550_device, ins8250_r, ins8250_w, 0xffffffffffffffffU )
AM_RANGE(0x80000388, 0x8000038F) AM_DEVREADWRITE8( "ns16550_3", ns16550_device, ins8250_r, ins8250_w, 0xffffffffffffffffU )
AM_RANGE(0x800003b0, 0x800003bf) AM_DEVREADWRITE8("vga", cirrus_gd5428_device, port_03b0_r, port_03b0_w, 0xffffffffffffffffU)
AM_RANGE(0x800003c0, 0x800003cf) AM_DEVREADWRITE8("vga", cirrus_gd5428_device, port_03c0_r, port_03c0_w, 0xffffffffffffffffU)
AM_RANGE(0x800003d0, 0x800003df) AM_DEVREADWRITE8("vga", cirrus_gd5428_device, port_03d0_r, port_03d0_w, 0xffffffffffffffffU)
AM_RANGE(0x800003F0, 0x800003F7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffffffffffffU )
AM_RANGE(0x800003F0, 0x800003F7) AM_DEVREADWRITE16("ide", ide_controller_device, read16_cs1, write16_cs1, 0xffffffffffffffffU )
AM_RANGE(0x800003F0, 0x800003F7) AM_DEVICE8( "smc37c78", smc37c78_device, map, 0xffffffffffffffffU )
AM_RANGE(0x800003F8, 0x800003FF) AM_DEVREADWRITE8( "ns16550_0",ns16550_device, ins8250_r, ins8250_w, 0xffffffffffffffffU )
AM_RANGE(0x80000480, 0x8000048F) AM_READWRITE8(bebox_80000480_r, bebox_80000480_w, 0xffffffffffffffffU )

4
src/mame/drivers/calchase.cpp
View File

@ -415,7 +415,7 @@ static ADDRESS_MAP_START( calchase_io, AS_IO, 32, calchase_state )
//AM_RANGE(0x00e8, 0x00eb) AM_NOP
AM_RANGE(0x00e8, 0x00ef) AM_NOP //AMI BIOS write to this ports as delays between I/O ports operations sending al value -> NEWIODELAY
AM_RANGE(0x0170, 0x0177) AM_NOP //To debug
AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE("ide", ide_controller_32_device, read_cs0, write_cs0)
AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE("ide", ide_controller_32_device, read32_cs0, write32_cs0)
AM_RANGE(0x0200, 0x021f) AM_NOP //To debug
AM_RANGE(0x0260, 0x026f) AM_NOP //To debug
AM_RANGE(0x0278, 0x027b) AM_WRITENOP//AM_WRITE(pnp_config_w)
@ -434,7 +434,7 @@ static ADDRESS_MAP_START( calchase_io, AS_IO, 32, calchase_state )
AM_RANGE(0x0378, 0x037f) AM_NOP //To debug
// AM_RANGE(0x0300, 0x03af) AM_NOP
// AM_RANGE(0x03b0, 0x03df) AM_NOP
AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE("ide", ide_controller_32_device, read_cs1, write_cs1)
AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE("ide", ide_controller_32_device, read32_cs1, write32_cs1)
AM_RANGE(0x03f8, 0x03ff) AM_NOP // To debug Serial Port COM1:
AM_RANGE(0x0a78, 0x0a7b) AM_WRITENOP//AM_WRITE(pnp_data_w)
AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)

8
src/mame/drivers/cobra.cpp
View File

@ -1947,7 +1947,7 @@ READ16_MEMBER(cobra_state::sub_ata0_r)
{
mem_mask = ( mem_mask << 8 ) | ( mem_mask >> 8 );
uint32_t data = m_ata->read_cs0(space, offset, mem_mask);
uint32_t data = m_ata->read16_cs0(space, offset, mem_mask);
data = ( data << 8 ) | ( data >> 8 );
return data;
@ -1958,14 +1958,14 @@ WRITE16_MEMBER(cobra_state::sub_ata0_w)
mem_mask = ( mem_mask << 8 ) | ( mem_mask >> 8 );
data = ( data << 8 ) | ( data >> 8 );
m_ata->write_cs0(space, offset, data, mem_mask);
m_ata->write16_cs0(space, offset, data, mem_mask);
}
READ16_MEMBER(cobra_state::sub_ata1_r)
{
mem_mask = ( mem_mask << 8 ) | ( mem_mask >> 8 );
uint32_t data = m_ata->read_cs1(space, offset, mem_mask);
uint32_t data = m_ata->read16_cs1(space, offset, mem_mask);
return ( data << 8 ) | ( data >> 8 );
}
@ -1975,7 +1975,7 @@ WRITE16_MEMBER(cobra_state::sub_ata1_w)
mem_mask = ( mem_mask << 8 ) | ( mem_mask >> 8 );
data = ( data << 8 ) | ( data >> 8 );
m_ata->write_cs1(space, offset, data, mem_mask);
m_ata->write16_cs1(space, offset, data, mem_mask);
}
READ32_MEMBER(cobra_state::sub_comram_r)

4
src/mame/drivers/csplayh5.cpp
View File

@ -152,10 +152,10 @@ static ADDRESS_MAP_START( csplayh5_sub_map, AS_PROGRAM, 16, csplayh5_state )
AM_RANGE(0x000000, 0x01ffff) AM_ROM
AM_RANGE(0x02000a, 0x02000b) AM_READ(test_r)
// AM_RANGE(0x020008, 0x02000f) AM_DEVREADWRITE("ide", ide_controller_device, read_cs0, write_cs0)
// AM_RANGE(0x020008, 0x02000f) AM_DEVREADWRITE("ide", ide_controller_device, read16_cs0, write16_cs0)
AM_RANGE(0x040018, 0x040019) AM_READ(test_r)
AM_RANGE(0x040028, 0x04002f) AM_DEVREADWRITE("ide", ide_controller_device, read_cs0, write_cs0) // correct?
AM_RANGE(0x040028, 0x04002f) AM_DEVREADWRITE("ide", ide_controller_device, read16_cs0, write16_cs0) // correct?
AM_RANGE(0x040036, 0x040037) AM_READ(test_r)
AM_RANGE(0x078000, 0x07ffff) AM_MIRROR(0xf80000) AM_RAM //AM_SHARE("nvram")

4
src/mame/drivers/dccons.cpp
View File

@ -367,8 +367,8 @@ static ADDRESS_MAP_START( dc_map, AS_PROGRAM, 64, dc_cons_state )
AM_RANGE(0x00200000, 0x0021ffff) AM_ROM AM_REGION("dcflash",0)//AM_READWRITE8(dc_flash_r,dc_flash_w, 0xffffffffffffffffU)
AM_RANGE(0x005f6800, 0x005f69ff) AM_READWRITE(dc_sysctrl_r, dc_sysctrl_w )
AM_RANGE(0x005f6c00, 0x005f6cff) AM_DEVICE32( "maple_dc", maple_dc_device, amap, 0xffffffffffffffffU )
AM_RANGE(0x005f7000, 0x005f701f) AM_DEVREADWRITE16("ata", ata_interface_device, read_cs1, write_cs1, 0x0000ffff0000ffffU )
AM_RANGE(0x005f7080, 0x005f709f) AM_DEVREADWRITE16("ata", ata_interface_device, read_cs0, write_cs0, 0x0000ffff0000ffffU )
AM_RANGE(0x005f7000, 0x005f701f) AM_DEVREADWRITE16("ata", ata_interface_device, read16_cs1, write16_cs1, 0x0000ffff0000ffffU )
AM_RANGE(0x005f7080, 0x005f709f) AM_DEVREADWRITE16("ata", ata_interface_device, read16_cs0, write16_cs0, 0x0000ffff0000ffffU )
AM_RANGE(0x005f7400, 0x005f74ff) AM_READWRITE32(dc_mess_g1_ctrl_r, dc_mess_g1_ctrl_w, 0xffffffffffffffffU )
AM_RANGE(0x005f7800, 0x005f78ff) AM_READWRITE(dc_g2_ctrl_r, dc_g2_ctrl_w )
AM_RANGE(0x005f7c00, 0x005f7cff) AM_DEVICE32("powervr2", powervr2_device, pd_dma_map, 0xffffffffffffffffU)

12
src/mame/drivers/djmain.cpp
View File

@ -406,23 +406,23 @@ static ADDRESS_MAP_START(maincpu_djmainj, AS_PROGRAM, 32, djmain_state)
AM_RANGE(0xc00000, 0xc01fff) AM_DEVREADWRITE("k056832", k056832_device, ram_long_r, ram_long_w) // VIDEO RAM (tilemap) (beatmania)
AM_RANGE(0xc02000, 0xc02047) AM_WRITE(unknownc02000_w) // ??
AM_RANGE(0xf00000, 0xf0000f) AM_DEVREADWRITE16("ata", ata_interface_device, read_cs0, write_cs0, 0xffffffff) // IDE control regs (beatmania)
AM_RANGE(0xf40000, 0xf4000f) AM_DEVREADWRITE16("ata", ata_interface_device, read_cs1, write_cs1, 0xffffffff) // IDE status control reg (beatmania)
AM_RANGE(0xf00000, 0xf0000f) AM_DEVREADWRITE16("ata", ata_interface_device, read16_cs0, write16_cs0, 0xffffffff) // IDE control regs (beatmania)
AM_RANGE(0xf40000, 0xf4000f) AM_DEVREADWRITE16("ata", ata_interface_device, read16_cs1, write16_cs1, 0xffffffff) // IDE status control reg (beatmania)
ADDRESS_MAP_END
static ADDRESS_MAP_START(maincpu_djmainu, AS_PROGRAM, 32, djmain_state)
AM_IMPORT_FROM(maincpu_djmain)
AM_RANGE(0xd00000, 0xd0000f) AM_DEVREADWRITE16("ata", ata_interface_device, read_cs0, write_cs0, 0xffffffff) // IDE control regs (hiphopmania)
AM_RANGE(0xd40000, 0xd4000f) AM_DEVREADWRITE16("ata", ata_interface_device, read_cs1, write_cs1, 0xffffffff) // IDE status control reg (hiphopmania)
AM_RANGE(0xd00000, 0xd0000f) AM_DEVREADWRITE16("ata", ata_interface_device, read16_cs0, write16_cs0, 0xffffffff) // IDE control regs (hiphopmania)
AM_RANGE(0xd40000, 0xd4000f) AM_DEVREADWRITE16("ata", ata_interface_device, read16_cs1, write16_cs1, 0xffffffff) // IDE status control reg (hiphopmania)
AM_RANGE(0xe00000, 0xe01fff) AM_DEVREADWRITE("k056832", k056832_device, ram_long_r, ram_long_w) // VIDEO RAM (tilemap) (hiphopmania)
ADDRESS_MAP_END
static ADDRESS_MAP_START(maincpu_djmaina, AS_PROGRAM, 32, djmain_state)
AM_IMPORT_FROM(maincpu_djmain)
AM_RANGE(0xc00000, 0xc0000f) AM_DEVREADWRITE16("ata", ata_interface_device, read_cs0, write_cs0, 0xffffffff) // IDE control regs
AM_RANGE(0xc40000, 0xc4000f) AM_DEVREADWRITE16("ata", ata_interface_device, read_cs1, write_cs1, 0xffffffff) // IDE status control reg
AM_RANGE(0xc00000, 0xc0000f) AM_DEVREADWRITE16("ata", ata_interface_device, read16_cs0, write16_cs0, 0xffffffff) // IDE control regs
AM_RANGE(0xc40000, 0xc4000f) AM_DEVREADWRITE16("ata", ata_interface_device, read16_cs1, write16_cs1, 0xffffffff) // IDE status control reg
AM_RANGE(0xf00000, 0xf01fff) AM_DEVREADWRITE("k056832", k056832_device, ram_long_r, ram_long_w) // VIDEO RAM (tilemap)
ADDRESS_MAP_END

20
src/mame/drivers/firebeat.cpp
View File

@ -448,12 +448,12 @@ READ32_MEMBER(firebeat_state::ata_command_r )
// printf("ata_command_r: %08X, %08X\n", offset, mem_mask);
if (ACCESSING_BITS_16_31)
{
r = m_ata->read_cs0(space, offset*2, BYTESWAP16((mem_mask >> 16) & 0xffff));
r = m_ata->read16_cs0(space, offset*2, BYTESWAP16((mem_mask >> 16) & 0xffff));
return BYTESWAP16(r) << 16;
}
else
{
r = m_ata->read_cs0(space, (offset*2) + 1, BYTESWAP16((mem_mask >> 0) & 0xffff));
r = m_ata->read16_cs0(space, (offset*2) + 1, BYTESWAP16((mem_mask >> 0) & 0xffff));
return BYTESWAP16(r) << 0;
}
}
@ -464,11 +464,11 @@ WRITE32_MEMBER(firebeat_state::ata_command_w )
if (ACCESSING_BITS_16_31)
{
m_ata->write_cs0(space, offset*2, BYTESWAP16((data >> 16) & 0xffff), BYTESWAP16((mem_mask >> 16) & 0xffff));
m_ata->write16_cs0(space, offset*2, BYTESWAP16((data >> 16) & 0xffff), BYTESWAP16((mem_mask >> 16) & 0xffff));
}
else
{
m_ata->write_cs0(space, (offset*2) + 1, BYTESWAP16((data >> 0) & 0xffff), BYTESWAP16((mem_mask >> 0) & 0xffff));
m_ata->write16_cs0(space, (offset*2) + 1, BYTESWAP16((data >> 0) & 0xffff), BYTESWAP16((mem_mask >> 0) & 0xffff));
}
}
@ -480,12 +480,12 @@ READ32_MEMBER(firebeat_state::ata_control_r )
if (ACCESSING_BITS_16_31)
{
r = m_ata->read_cs1(space, offset*2, BYTESWAP16((mem_mask >> 16) & 0xffff));
r = m_ata->read16_cs1(space, offset*2, BYTESWAP16((mem_mask >> 16) & 0xffff));
return BYTESWAP16(r) << 16;
}
else
{
r = m_ata->read_cs1(space, (offset*2) + 1, BYTESWAP16((mem_mask >> 0) & 0xffff));
r = m_ata->read16_cs1(space, (offset*2) + 1, BYTESWAP16((mem_mask >> 0) & 0xffff));
return BYTESWAP16(r) << 0;
}
}
@ -494,11 +494,11 @@ WRITE32_MEMBER(firebeat_state::ata_control_w )
{
if (ACCESSING_BITS_16_31)
{
m_ata->write_cs1(space, offset*2, BYTESWAP16(data >> 16) & 0xffff, BYTESWAP16((mem_mask >> 16) & 0xffff));
m_ata->write16_cs1(space, offset*2, BYTESWAP16(data >> 16) & 0xffff, BYTESWAP16((mem_mask >> 16) & 0xffff));
}
else
{
m_ata->write_cs1(space, (offset*2) + 1, BYTESWAP16(data >> 0) & 0xffff, BYTESWAP16((mem_mask >> 0) & 0xffff));
m_ata->write16_cs1(space, (offset*2) + 1, BYTESWAP16(data >> 0) & 0xffff, BYTESWAP16((mem_mask >> 0) & 0xffff));
}
}
@ -1079,8 +1079,8 @@ static ADDRESS_MAP_START( spu_map, AS_PROGRAM, 16, firebeat_state )
AM_RANGE(0x230000, 0x230001) AM_WRITE(spu_irq_ack_w)
AM_RANGE(0x260000, 0x260001) AM_WRITE(spu_sdram_bank_w)
AM_RANGE(0x280000, 0x2807ff) AM_READWRITE(m68k_spu_share_r, m68k_spu_share_w)
AM_RANGE(0x300000, 0x30000f) AM_DEVREADWRITE("spu_ata", ata_interface_device, read_cs0, write_cs0)
AM_RANGE(0x340000, 0x34000f) AM_DEVREADWRITE("spu_ata", ata_interface_device, read_cs1, write_cs1)
AM_RANGE(0x300000, 0x30000f) AM_DEVREADWRITE("spu_ata", ata_interface_device, read16_cs0, write16_cs0)
AM_RANGE(0x340000, 0x34000f) AM_DEVREADWRITE("spu_ata", ata_interface_device, read16_cs1, write16_cs1)
AM_RANGE(0x400000, 0x400fff) AM_DEVREADWRITE("rf5c400", rf5c400_device, rf5c400_r, rf5c400_w)
AM_RANGE(0x800000, 0x83ffff) AM_RAM // SDRAM
AM_RANGE(0xfc0000, 0xffffff) AM_RAM // SDRAM

4
src/mame/drivers/fruitpc.cpp
View File

@ -73,12 +73,12 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( fruitpc_io, AS_IO, 32, fruitpc_state )
AM_IMPORT_FROM(pcat32_io_common)
AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff)
AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read16_cs0, write16_cs0, 0xffffffff)
AM_RANGE(0x0310, 0x0313) AM_READ8(fruit_inp_r, 0xffffffff)
AM_RANGE(0x03b0, 0x03bf) AM_DEVREADWRITE8("vga", vga_device, port_03b0_r, port_03b0_w, 0xffffffff)
AM_RANGE(0x03c0, 0x03cf) AM_DEVREADWRITE8("vga", vga_device, port_03c0_r, port_03c0_w, 0xffffffff)
AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff)
AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff)
AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read16_cs1, write16_cs1, 0xffffffff)
ADDRESS_MAP_END
static INPUT_PORTS_START( fruitpc )

4
src/mame/drivers/funkball.cpp
View File

@ -359,8 +359,8 @@ static ADDRESS_MAP_START(funkball_io, AS_IO, 32, funkball_state)
AM_IMPORT_FROM(pcat32_io_common)
AM_RANGE(0x00e8, 0x00ef) AM_NOP
AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff)
AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff)
AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read16_cs0, write16_cs0, 0xffffffff)
AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read16_cs1, write16_cs1, 0xffffffff)
AM_RANGE(0x03f8, 0x03ff) AM_READWRITE8(serial_r,serial_w,0xffffffff)
AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)

4
src/mame/drivers/gamecstl.cpp
View File

@ -352,11 +352,11 @@ static ADDRESS_MAP_START(gamecstl_io, AS_IO, 32, gamecstl_state )
AM_IMPORT_FROM(pcat32_io_common)
AM_RANGE(0x00e8, 0x00eb) AM_NOP
AM_RANGE(0x00ec, 0x00ef) AM_NOP
AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff)
AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read16_cs0, write16_cs0, 0xffffffff)
AM_RANGE(0x0300, 0x03af) AM_NOP
AM_RANGE(0x03b0, 0x03df) AM_NOP
AM_RANGE(0x0278, 0x027b) AM_WRITE(pnp_config_w)
AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff)
AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read16_cs1, write16_cs1, 0xffffffff)
AM_RANGE(0x0a78, 0x0a7b) AM_WRITE(pnp_data_w)
AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)
ADDRESS_MAP_END

16
src/mame/drivers/jaguar.cpp
View File

@ -382,7 +382,7 @@ public:
{
}
virtual DECLARE_WRITE16_MEMBER(write_cs0) override
virtual DECLARE_WRITE16_MEMBER(write16_cs0) override
{
// the first write is to the device head register
if( offset == 6 && (m_status & IDE_STATUS_DRQ))
@ -390,7 +390,7 @@ public:
m_status &= ~IDE_STATUS_DRQ;
}
ide_hdd_device::write_cs0(space, offset, data, mem_mask);
ide_hdd_device::write16_cs0(space, offset, data, mem_mask);
}
};
@ -1325,8 +1325,8 @@ static ADDRESS_MAP_START( r3000_map, AS_PROGRAM, 32, jaguar_state )
AM_RANGE(0x04800000, 0x04bfffff) AM_ROMBANK("maingfxbank")
AM_RANGE(0x04c00000, 0x04dfffff) AM_ROMBANK("mainsndbank")
AM_RANGE(0x04e00030, 0x04e0003f) AM_DEVREADWRITE("ide", vt83c461_device, read_config, write_config)
AM_RANGE(0x04e001f0, 0x04e001f7) AM_DEVREADWRITE("ide", vt83c461_device, read_cs0, write_cs0)
AM_RANGE(0x04e003f0, 0x04e003f7) AM_DEVREADWRITE("ide", vt83c461_device, read_cs1, write_cs1)
AM_RANGE(0x04e001f0, 0x04e001f7) AM_DEVREADWRITE("ide", vt83c461_device, read32_cs0, write32_cs0)
AM_RANGE(0x04e003f0, 0x04e003f7) AM_DEVREADWRITE("ide", vt83c461_device, read32_cs1, write32_cs1)
AM_RANGE(0x04f00000, 0x04f003ff) AM_READWRITE16(tom_regs_r, tom_regs_w, 0xffffffff)
AM_RANGE(0x04f00400, 0x04f007ff) AM_RAM AM_SHARE("gpuclut")
AM_RANGE(0x04f02100, 0x04f021ff) AM_READWRITE(gpuctrl_r, gpuctrl_w)
@ -1361,8 +1361,8 @@ static ADDRESS_MAP_START( m68020_map, AS_PROGRAM, 32, jaguar_state )
AM_RANGE(0xb70000, 0xb70003) AM_READWRITE(misc_control_r, misc_control_w)
AM_RANGE(0xc00000, 0xdfffff) AM_ROMBANK("mainsndbank")
AM_RANGE(0xe00030, 0xe0003f) AM_DEVREADWRITE("ide", vt83c461_device, read_config, write_config)
AM_RANGE(0xe001f0, 0xe001f7) AM_DEVREADWRITE("ide", vt83c461_device, read_cs0, write_cs0)
AM_RANGE(0xe003f0, 0xe003f7) AM_DEVREADWRITE("ide", vt83c461_device, read_cs1, write_cs1)
AM_RANGE(0xe001f0, 0xe001f7) AM_DEVREADWRITE("ide", vt83c461_device, read32_cs0, write32_cs0)
AM_RANGE(0xe003f0, 0xe003f7) AM_DEVREADWRITE("ide", vt83c461_device, read32_cs1, write32_cs1)
AM_RANGE(0xf00000, 0xf003ff) AM_READWRITE16(tom_regs_r, tom_regs_w, 0xffffffff)
AM_RANGE(0xf00400, 0xf007ff) AM_RAM AM_SHARE("gpuclut")
AM_RANGE(0xf02100, 0xf021ff) AM_READWRITE(gpuctrl_r, gpuctrl_w)
@ -1391,8 +1391,8 @@ static ADDRESS_MAP_START( gpu_map, AS_PROGRAM, 32, jaguar_state )
AM_RANGE(0x800000, 0xbfffff) AM_ROMBANK("gpugfxbank")
AM_RANGE(0xc00000, 0xdfffff) AM_ROMBANK("dspsndbank")
AM_RANGE(0xe00030, 0xe0003f) AM_DEVREADWRITE("ide", vt83c461_device, read_config, write_config)
AM_RANGE(0xe001f0, 0xe001f7) AM_DEVREADWRITE("ide", vt83c461_device, read_cs0, write_cs0)
AM_RANGE(0xe003f0, 0xe003f7) AM_DEVREADWRITE("ide", vt83c461_device, read_cs1, write_cs1)
AM_RANGE(0xe001f0, 0xe001f7) AM_DEVREADWRITE("ide", vt83c461_device, read32_cs0, write32_cs0)
AM_RANGE(0xe003f0, 0xe003f7) AM_DEVREADWRITE("ide", vt83c461_device, read32_cs1, write32_cs1)
AM_RANGE(0xf00000, 0xf003ff) AM_READWRITE16(tom_regs_r, tom_regs_w, 0xffffffff)
AM_RANGE(0xf00400, 0xf007ff) AM_RAM AM_SHARE("gpuclut")
AM_RANGE(0xf02100, 0xf021ff) AM_READWRITE(gpuctrl_r, gpuctrl_w)

8
src/mame/drivers/kinst.cpp
View File

@ -342,25 +342,25 @@ INTERRUPT_GEN_MEMBER(kinst_state::irq0_start)
READ32_MEMBER(kinst_state::ide_r)
{
return m_ata->read_cs0(space, offset / 2, mem_mask);
return m_ata->read16_cs0(space, offset / 2, mem_mask);
}
WRITE32_MEMBER(kinst_state::ide_w)
{
m_ata->write_cs0(space, offset / 2, data, mem_mask);
m_ata->write16_cs0(space, offset / 2, data, mem_mask);
}
READ32_MEMBER(kinst_state::ide_extra_r)
{
return m_ata->read_cs1(space, 6, 0xff);
return m_ata->read16_cs1(space, 6, 0xff);
}
WRITE32_MEMBER(kinst_state::ide_extra_w)
{
m_ata->write_cs1(space, 6, data, 0xff);
m_ata->write16_cs1(space, 6, data, 0xff);
}

8
src/mame/drivers/ksys573.cpp
View File

@ -558,7 +558,7 @@ static ADDRESS_MAP_START( konami573_map, AS_PROGRAM, 32, ksys573_state )
AM_RANGE( 0x1f400004, 0x1f400007 ) AM_READ_PORT( "IN1" )
AM_RANGE( 0x1f400008, 0x1f40000b ) AM_READ_PORT( "IN2" )
AM_RANGE( 0x1f40000c, 0x1f40000f ) AM_READ_PORT( "IN3" )
AM_RANGE( 0x1f480000, 0x1f48000f ) AM_DEVREADWRITE16( "ata", ata_interface_device, read_cs0, write_cs0, 0xffffffff )
AM_RANGE( 0x1f480000, 0x1f48000f ) AM_DEVREADWRITE16( "ata", ata_interface_device, read16_cs0, write16_cs0, 0xffffffff )
AM_RANGE( 0x1f500000, 0x1f500003 ) AM_READWRITE16( control_r, control_w, 0x0000ffff ) // Konami can't make a game without a "control" register.
AM_RANGE( 0x1f560000, 0x1f560003 ) AM_WRITE16( atapi_reset_w, 0x0000ffff )
AM_RANGE( 0x1f5c0000, 0x1f5c0003 ) AM_WRITENOP // watchdog?
@ -629,15 +629,15 @@ TIMER_CALLBACK_MEMBER( ksys573_state::atapi_xfer_end )
for( int i = 0; i < m_atapi_xfersize; i++ )
{
uint32_t d = m_ata->read_cs0( space, (uint32_t) 0, (uint32_t) 0xffff ) << 0;
d |= m_ata->read_cs0( space, (uint32_t) 0, (uint32_t) 0xffff ) << 16;
uint32_t d = m_ata->read16_cs0( space, (uint32_t) 0, (uint32_t) 0xffff ) << 0;
d |= m_ata->read16_cs0( space, (uint32_t) 0, (uint32_t) 0xffff ) << 16;
m_p_n_psxram[ m_atapi_xferbase / 4 ] = d;
m_atapi_xferbase += 4;
}
/// HACK: konami80s only works if you dma more data than requested
if( ( m_ata->read_cs1( space, (uint32_t) 6, (uint32_t) 0xffff ) & 8 ) != 0 )
if( ( m_ata->read16_cs1( space, (uint32_t) 6, (uint32_t) 0xffff ) & 8 ) != 0 )
{
m_atapi_timer->adjust( m_maincpu->cycles_to_attotime( ( ATAPI_CYCLES_PER_SECTOR * ( m_atapi_xfersize / 64 ) ) ) );
}

4
src/mame/drivers/mediagx.cpp
View File

@ -760,9 +760,9 @@ static ADDRESS_MAP_START(mediagx_io, AS_IO, 32, mediagx_state )
AM_RANGE(0x0020, 0x0023) AM_READWRITE8(io20_r, io20_w, 0xffff0000)
AM_IMPORT_FROM(pcat32_io_common)
AM_RANGE(0x00e8, 0x00eb) AM_NOP // I/O delay port
AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE("ide", ide_controller_32_device, read_cs0, write_cs0)
AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE("ide", ide_controller_32_device, read32_cs0, write32_cs0)
AM_RANGE(0x0378, 0x037b) AM_READWRITE(parallel_port_r, parallel_port_w)
AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE("ide", ide_controller_32_device, read_cs1, write_cs1)
AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE("ide", ide_controller_32_device, read32_cs1, write32_cs1)
AM_RANGE(0x0400, 0x04ff) AM_READWRITE(ad1847_r, ad1847_w)
AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)
ADDRESS_MAP_END

4
src/mame/drivers/midqslvr.cpp
View File

@ -374,11 +374,11 @@ static ADDRESS_MAP_START(midqslvr_io, AS_IO, 32, midqslvr_state)
AM_IMPORT_FROM(pcat32_io_common)
AM_RANGE(0x00e8, 0x00ef) AM_NOP
AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff)
AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read16_cs0, write16_cs0, 0xffffffff)
AM_RANGE(0x03b0, 0x03bf) AM_DEVREADWRITE8("vga", vga_device, port_03b0_r, port_03b0_w, 0xffffffff)
AM_RANGE(0x03c0, 0x03cf) AM_DEVREADWRITE8("vga", vga_device, port_03c0_r, port_03c0_w, 0xffffffff)
AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff)
AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff)
AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read16_cs1, write16_cs1, 0xffffffff)
AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)
ADDRESS_MAP_END

2
src/mame/drivers/midvunit.cpp
View File

@ -624,7 +624,7 @@ static ADDRESS_MAP_START( midvplus_map, AS_PROGRAM, 32, midvunit_state )
AM_RANGE(0x990000, 0x99000f) AM_DEVREADWRITE("ioasic", midway_ioasic_device, read, write)
AM_RANGE(0x994000, 0x994000) AM_WRITE(midvunit_control_w)
AM_RANGE(0x995020, 0x995020) AM_WRITE(midvunit_cmos_protect_w)
AM_RANGE(0x9a0000, 0x9a0007) AM_DEVREADWRITE16("ata", ata_interface_device, read_cs0, write_cs0, 0x0000ffff)
AM_RANGE(0x9a0000, 0x9a0007) AM_DEVREADWRITE16("ata", ata_interface_device, read16_cs0, write16_cs0, 0x0000ffff)
AM_RANGE(0x9c0000, 0x9c7fff) AM_RAM_WRITE(midvunit_paletteram_w) AM_SHARE("paletteram")
AM_RANGE(0x9d0000, 0x9d000f) AM_READWRITE(midvplus_misc_r, midvplus_misc_w) AM_SHARE("midvplus_misc")
AM_RANGE(0xa00000, 0xbfffff) AM_READWRITE(midvunit_textureram_r, midvunit_textureram_w) AM_SHARE("textureram")

8
src/mame/drivers/pc9801.cpp
View File

@ -511,22 +511,22 @@ WRITE8_MEMBER(pc9801_state::ide_ctrl_w)
READ16_MEMBER(pc9801_state::ide_cs0_r)
{
return (m_ide_sel ? m_ide2 : m_ide1)->read_cs0(space, offset, mem_mask);
return (m_ide_sel ? m_ide2 : m_ide1)->read16_cs0(space, offset, mem_mask);
}
WRITE16_MEMBER(pc9801_state::ide_cs0_w)
{
(m_ide_sel ? m_ide2 : m_ide1)->write_cs0(space, offset, data, mem_mask);
(m_ide_sel ? m_ide2 : m_ide1)->write16_cs0(space, offset, data, mem_mask);
}
READ16_MEMBER(pc9801_state::ide_cs1_r)
{
return (m_ide_sel ? m_ide2 : m_ide1)->read_cs1(space, offset, mem_mask);
return (m_ide_sel ? m_ide2 : m_ide1)->read16_cs1(space, offset, mem_mask);
}
WRITE16_MEMBER(pc9801_state::ide_cs1_w)
{
(m_ide_sel ? m_ide2 : m_ide1)->write_cs1(space, offset, data, mem_mask);
(m_ide_sel ? m_ide2 : m_ide1)->write16_cs1(space, offset, data, mem_mask);
}
WRITE_LINE_MEMBER(pc9801_state::ide1_irq_w)

4
src/mame/drivers/photoply.cpp
View File

@ -50,14 +50,14 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( photoply_io, AS_IO, 32, photoply_state )
AM_IMPORT_FROM(pcat32_io_common)
AM_RANGE(0x00e8, 0x00eb) AM_NOP
AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff)
AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read16_cs0, write16_cs0, 0xffffffff)
AM_RANGE(0x0278, 0x027f) AM_RAM //parallel port 2
AM_RANGE(0x0378, 0x037f) AM_RAM //parallel port
//AM_RANGE(0x03bc, 0x03bf) AM_RAM //parallel port 3
AM_RANGE(0x03b0, 0x03bf) AM_DEVREADWRITE8("vga", vga_device, port_03b0_r, port_03b0_w, 0xffffffff)
AM_RANGE(0x03c0, 0x03cf) AM_DEVREADWRITE8("vga", vga_device, port_03c0_r, port_03c0_w, 0xffffffff)
AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff)
AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff)
AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read16_cs1, write16_cs1, 0xffffffff)
ADDRESS_MAP_END
#define AT_KEYB_HELPER(bit, text, key1) \

12
src/mame/drivers/qdrmfgp.cpp
View File

@ -224,7 +224,7 @@ READ16_MEMBER(qdrmfgp_state::gp2_ide_std_r)
break;
}
}
return m_ata->read_cs0(space, offset, mem_mask);
return m_ata->read16_cs0(space, offset, mem_mask);
}
@ -318,8 +318,8 @@ static ADDRESS_MAP_START( qdrmfgp_map, AS_PROGRAM, 16, qdrmfgp_state )
AM_RANGE(0x880000, 0x881fff) AM_DEVREADWRITE("k056832", k056832_device, ram_word_r, ram_word_w) /* vram */
AM_RANGE(0x882000, 0x883fff) AM_DEVREADWRITE("k056832", k056832_device, ram_word_r, ram_word_w) /* vram (mirror) */
AM_RANGE(0x900000, 0x901fff) AM_READ(v_rom_r) /* gfxrom through */
AM_RANGE(0xa00000, 0xa0000f) AM_DEVREADWRITE("ata", ata_interface_device, read_cs0, write_cs0) /* IDE control regs */
AM_RANGE(0xa40000, 0xa4000f) AM_DEVREADWRITE("ata", ata_interface_device, read_cs1, write_cs1) /* IDE status control reg */
AM_RANGE(0xa00000, 0xa0000f) AM_DEVREADWRITE("ata", ata_interface_device, read16_cs0, write16_cs0) /* IDE control regs */
AM_RANGE(0xa40000, 0xa4000f) AM_DEVREADWRITE("ata", ata_interface_device, read16_cs1, write16_cs1) /* IDE status control reg */
AM_RANGE(0xc00000, 0xcbffff) AM_READWRITE(sndram_r, sndram_w) /* sound ram */
ADDRESS_MAP_END
@ -342,11 +342,11 @@ static ADDRESS_MAP_START( qdrmfgp2_map, AS_PROGRAM, 16, qdrmfgp_state )
AM_RANGE(0x89f000, 0x8a0fff) AM_READWRITE(gp2_vram_mirror_r, gp2_vram_mirror_w) /* vram (mirror) */
AM_RANGE(0x900000, 0x901fff) AM_READ(v_rom_r) /* gfxrom through */
#if IDE_HACK
AM_RANGE(0xa00000, 0xa0000f) AM_READ(gp2_ide_std_r) AM_DEVWRITE("ata", ata_interface_device, write_cs0) /* IDE control regs */
AM_RANGE(0xa00000, 0xa0000f) AM_READ(gp2_ide_std_r) AM_DEVWRITE("ata", ata_interface_device, write16_cs0) /* IDE control regs */
#else
AM_RANGE(0xa00000, 0xa0000f) AM_DEVREADWRITE("ata", ata_interface_device, read_cs0, write_cs0) /* IDE control regs */
AM_RANGE(0xa00000, 0xa0000f) AM_DEVREADWRITE("ata", ata_interface_device, read16_cs0, write16_cs0) /* IDE control regs */
#endif
AM_RANGE(0xa40000, 0xa4000f) AM_DEVREADWRITE("ata", ata_interface_device, read_cs1, write_cs1) /* IDE status control reg */
AM_RANGE(0xa40000, 0xa4000f) AM_DEVREADWRITE("ata", ata_interface_device, read16_cs1, write16_cs1) /* IDE status control reg */
AM_RANGE(0xc00000, 0xcbffff) AM_READWRITE(sndram_r,sndram_w) /* sound ram */
ADDRESS_MAP_END

4
src/mame/drivers/quakeat.cpp
View File

@ -95,11 +95,11 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( quake_io, AS_IO, 32, quakeat_state )
AM_IMPORT_FROM(pcat32_io_common)
AM_RANGE(0x00e8, 0x00eb) AM_NOP
// AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff)
// AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read16_cs0, write16_cs0, 0xffffffff)
AM_RANGE(0x0300, 0x03af) AM_NOP
AM_RANGE(0x03b0, 0x03df) AM_NOP
// AM_RANGE(0x0278, 0x027b) AM_WRITE(pnp_config_w)
// AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff)
// AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read16_cs1, write16_cs1, 0xffffffff)
// AM_RANGE(0x0a78, 0x0a7b) AM_WRITE(pnp_data_w)
// AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_device, read, write)
ADDRESS_MAP_END

8
src/mame/drivers/queen.cpp
View File

@ -243,13 +243,13 @@ static ADDRESS_MAP_START( queen_io, AS_IO, 32, queen_state )
AM_IMPORT_FROM(pcat32_io_common)
AM_RANGE(0x00e8, 0x00ef) AM_NOP
AM_RANGE(0x0170, 0x0177) AM_DEVREADWRITE("ide2", ide_controller_32_device, read_cs0, write_cs0)
AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff)
AM_RANGE(0x0370, 0x0377) AM_DEVREADWRITE("ide2", ide_controller_32_device, read_cs1, write_cs1)
AM_RANGE(0x0170, 0x0177) AM_DEVREADWRITE("ide2", ide_controller_32_device, read32_cs0, write32_cs0)
AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read16_cs0, write16_cs0, 0xffffffff)
AM_RANGE(0x0370, 0x0377) AM_DEVREADWRITE("ide2", ide_controller_32_device, read32_cs1, write32_cs1)
AM_RANGE(0x03b0, 0x03bf) AM_DEVREADWRITE8("vga", vga_device, port_03b0_r, port_03b0_w, 0xffffffff)
AM_RANGE(0x03c0, 0x03cf) AM_DEVREADWRITE8("vga", vga_device, port_03c0_r, port_03c0_w, 0xffffffff)
AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff)
AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff)
AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read16_cs1, write16_cs1, 0xffffffff)
AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)
ADDRESS_MAP_END

8
src/mame/drivers/savquest.cpp
View File

@ -750,14 +750,14 @@ static ADDRESS_MAP_START(savquest_io, AS_IO, 32, savquest_state)
AM_RANGE(0x00e8, 0x00ef) AM_NOP
AM_RANGE(0x0170, 0x0177) AM_DEVREADWRITE("ide2", ide_controller_32_device, read_cs0, write_cs0)
AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE("ide", ide_controller_32_device, read_cs0, write_cs0)
AM_RANGE(0x0170, 0x0177) AM_DEVREADWRITE("ide2", ide_controller_32_device, read32_cs0, write32_cs0)
AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE("ide", ide_controller_32_device, read32_cs0, write32_cs0)
AM_RANGE(0x0378, 0x037b) AM_READWRITE8(parallel_port_r, parallel_port_w, 0xffffffff)
AM_RANGE(0x03b0, 0x03bf) AM_DEVREADWRITE8("vga", vga_device, port_03b0_r, port_03b0_w, 0xffffffff)
AM_RANGE(0x03c0, 0x03cf) AM_DEVREADWRITE8("vga", vga_device, port_03c0_r, port_03c0_w, 0xffffffff)
AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff)
AM_RANGE(0x0370, 0x0377) AM_DEVREADWRITE("ide2", ide_controller_32_device, read_cs1, write_cs1)
AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE("ide", ide_controller_32_device, read_cs1, write_cs1)
AM_RANGE(0x0370, 0x0377) AM_DEVREADWRITE("ide2", ide_controller_32_device, read32_cs1, write32_cs1)
AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE("ide", ide_controller_32_device, read32_cs1, write32_cs1)
AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)

12
src/mame/drivers/taitotz.cpp
View File

@ -2176,7 +2176,7 @@ WRITE8_MEMBER(taitotz_state::tlcs_rtc_w)
READ16_MEMBER(taitotz_state::tlcs_ide0_r)
{
uint16_t d = m_ata->read_cs0(space, offset, mem_mask);
uint16_t d = m_ata->read16_cs0(space, offset, mem_mask);
if (offset == 7)
d &= ~0x2; // Type Zero doesn't like the index bit. It's defined as vendor-specific, so it probably shouldn't be up...
// The status check explicitly checks for 0x50 (drive ready, seek complete).
@ -2185,7 +2185,7 @@ READ16_MEMBER(taitotz_state::tlcs_ide0_r)
READ16_MEMBER(taitotz_state::tlcs_ide1_r)
{
uint16_t d = m_ata->read_cs1(space, offset, mem_mask);
uint16_t d = m_ata->read16_cs1(space, offset, mem_mask);
if (offset == 6)
d &= ~0x2; // Type Zero doesn't like the index bit. It's defined as vendor-specific, so it probably shouldn't be up...
// The status check explicitly checks for 0x50 (drive ready, seek complete).
@ -2223,8 +2223,8 @@ static ADDRESS_MAP_START( tlcs900h_mem, AS_PROGRAM, 16, taitotz_state)
AM_RANGE(0x044000, 0x04400f) AM_READWRITE8(tlcs_rtc_r, tlcs_rtc_w, 0xffff)
AM_RANGE(0x060000, 0x061fff) AM_READWRITE8(tlcs_common_r, tlcs_common_w, 0xffff)
AM_RANGE(0x064000, 0x064fff) AM_RAM AM_SHARE("mbox_ram") // MBox
AM_RANGE(0x068000, 0x06800f) AM_DEVWRITE("ata", ata_interface_device, write_cs0) AM_READ(tlcs_ide0_r)
AM_RANGE(0x06c000, 0x06c00f) AM_DEVWRITE("ata", ata_interface_device, write_cs1) AM_READ(tlcs_ide1_r)
AM_RANGE(0x068000, 0x06800f) AM_DEVWRITE("ata", ata_interface_device, write16_cs0) AM_READ(tlcs_ide0_r)
AM_RANGE(0x06c000, 0x06c00f) AM_DEVWRITE("ata", ata_interface_device, write16_cs1) AM_READ(tlcs_ide1_r)
AM_RANGE(0xfc0000, 0xffffff) AM_ROM AM_REGION("io_cpu", 0)
ADDRESS_MAP_END
@ -2234,8 +2234,8 @@ static ADDRESS_MAP_START( landhigh_tlcs900h_mem, AS_PROGRAM, 16, taitotz_state)
AM_RANGE(0x404000, 0x40400f) AM_READWRITE8(tlcs_rtc_r, tlcs_rtc_w, 0xffff)
AM_RANGE(0x900000, 0x901fff) AM_READWRITE8(tlcs_common_r, tlcs_common_w, 0xffff)
AM_RANGE(0x910000, 0x910fff) AM_RAM AM_SHARE("mbox_ram") // MBox
AM_RANGE(0x908000, 0x90800f) AM_DEVWRITE("ata", ata_interface_device, write_cs0) AM_READ(tlcs_ide0_r)
AM_RANGE(0x918000, 0x91800f) AM_DEVWRITE("ata", ata_interface_device, write_cs1) AM_READ(tlcs_ide1_r)
AM_RANGE(0x908000, 0x90800f) AM_DEVWRITE("ata", ata_interface_device, write16_cs0) AM_READ(tlcs_ide0_r)
AM_RANGE(0x918000, 0x91800f) AM_DEVWRITE("ata", ata_interface_device, write16_cs1) AM_READ(tlcs_ide1_r)
AM_RANGE(0xfc0000, 0xffffff) AM_ROM AM_REGION("io_cpu", 0)
ADDRESS_MAP_END

2
src/mame/drivers/turrett.cpp
View File

@ -96,7 +96,7 @@ static ADDRESS_MAP_START( cpu_map, AS_PROGRAM, 32, turrett_state )
AM_RANGE(0x04000100, 0x04000103) AM_READWRITE(int_r, int_w)
AM_RANGE(0x04000200, 0x040003ff) AM_DEVREADWRITE("ttsound", turrett_device, read, write)
AM_RANGE(0x08000000, 0x0800000f) AM_READWRITE(video_r, video_w)
AM_RANGE(0x08000200, 0x080003ff) AM_DEVREADWRITE16("ata", ata_interface_device, read_cs0, write_cs0, 0xffffffff)
AM_RANGE(0x08000200, 0x080003ff) AM_DEVREADWRITE16("ata", ata_interface_device, read16_cs0, write16_cs0, 0xffffffff)
AM_RANGE(0x1fc00000, 0x1fdfffff) AM_ROM AM_REGION("maincpu", 0)
ADDRESS_MAP_END

2
src/mame/drivers/twinkle.cpp
View File

@ -916,7 +916,7 @@ static ADDRESS_MAP_START( sound_map, AS_PROGRAM, 16, twinkle_state )
AM_RANGE(0x250000, 0x250003) AM_WRITE(spu_ata_dma_high_w) AM_READNOP
AM_RANGE(0x260000, 0x260001) AM_WRITE(spu_wavebank_w) AM_READNOP
AM_RANGE(0x280000, 0x280fff) AM_READWRITE(shared_68k_r, shared_68k_w)
AM_RANGE(0x300000, 0x30000f) AM_DEVREADWRITE("ata", ata_interface_device, read_cs0, write_cs0)
AM_RANGE(0x300000, 0x30000f) AM_DEVREADWRITE("ata", ata_interface_device, read16_cs0, write16_cs0)
// 34000E = ???
AM_RANGE(0x34000e, 0x34000f) AM_WRITENOP
AM_RANGE(0x400000, 0x400fff) AM_DEVREADWRITE("rfsnd", rf5c400_device, rf5c400_r, rf5c400_w)

24
src/mame/drivers/viper.cpp
View File

@ -1370,7 +1370,7 @@ READ64_MEMBER(viper_state::cf_card_data_r)
{
case 0x8: // Duplicate Even RD Data
{
r |= m_ata->read_cs0(space, 0, mem_mask >> 16) << 16;
r |= m_ata->read16_cs0(space, 0, mem_mask >> 16) << 16;
break;
}
@ -1391,7 +1391,7 @@ WRITE64_MEMBER(viper_state::cf_card_data_w)
{
case 0x8: // Duplicate Even RD Data
{
m_ata->write_cs0(space, 0, data >> 16, mem_mask >> 16);
m_ata->write16_cs0(space, 0, data >> 16, mem_mask >> 16);
break;
}
@ -1422,7 +1422,7 @@ READ64_MEMBER(viper_state::cf_card_r)
case 0x6: // Select Card/Head
case 0x7: // Status
{
r |= m_ata->read_cs0(space, offset & 7, mem_mask >> 16) << 16;
r |= m_ata->read16_cs0(space, offset & 7, mem_mask >> 16) << 16;
break;
}
@ -1431,13 +1431,13 @@ READ64_MEMBER(viper_state::cf_card_r)
case 0xd: // Duplicate Error
{
r |= m_ata->read_cs0(space, 1, mem_mask >> 16) << 16;
r |= m_ata->read16_cs0(space, 1, mem_mask >> 16) << 16;
break;
}
case 0xe: // Alt Status
case 0xf: // Drive Address
{
r |= m_ata->read_cs1(space, offset & 7, mem_mask >> 16) << 16;
r |= m_ata->read16_cs1(space, offset & 7, mem_mask >> 16) << 16;
break;
}
@ -1487,7 +1487,7 @@ WRITE64_MEMBER(viper_state::cf_card_w)
case 0x6: // Select Card/Head
case 0x7: // Command
{
m_ata->write_cs0(space, offset & 7, data >> 16, mem_mask >> 16);
m_ata->write16_cs0(space, offset & 7, data >> 16, mem_mask >> 16);
break;
}
@ -1496,13 +1496,13 @@ WRITE64_MEMBER(viper_state::cf_card_w)
case 0xd: // Duplicate Features
{
m_ata->write_cs0(space, 1, data >> 16, mem_mask >> 16);
m_ata->write16_cs0(space, 1, data >> 16, mem_mask >> 16);
break;
}
case 0xe: // Device Ctl
case 0xf: // Reserved
{
m_ata->write_cs1(space, offset & 7, data >> 16, mem_mask >> 16);
m_ata->write16_cs1(space, offset & 7, data >> 16, mem_mask >> 16);
break;
}
@ -1557,10 +1557,10 @@ READ64_MEMBER(viper_state::ata_r)
switch(offset & 0x80)
{
case 0x00:
r |= m_ata->read_cs0(space, reg, mem_mask >> 16) << 16;
r |= m_ata->read16_cs0(space, reg, mem_mask >> 16) << 16;
break;
case 0x80:
r |= m_ata->read_cs1(space, reg, mem_mask >> 16) << 16;
r |= m_ata->read16_cs1(space, reg, mem_mask >> 16) << 16;
break;
}
}
@ -1577,10 +1577,10 @@ WRITE64_MEMBER(viper_state::ata_w)
switch(offset & 0x80)
{
case 0x00:
m_ata->write_cs0(space, reg, data >> 16, mem_mask >> 16);
m_ata->write16_cs0(space, reg, data >> 16, mem_mask >> 16);
break;
case 0x80:
m_ata->write_cs1(space, reg, data >> 16, mem_mask >> 16);
m_ata->write16_cs1(space, reg, data >> 16, mem_mask >> 16);
break;
}
}

4
src/mame/drivers/voyager.cpp
View File

@ -266,7 +266,7 @@ static ADDRESS_MAP_START( voyager_io, AS_IO, 32, voyager_state )
//AM_RANGE(0x00e8, 0x00eb) AM_NOP
AM_RANGE(0x00e8, 0x00ef) AM_NOP //AMI BIOS write to this ports as delays between I/O ports operations sending al value -> NEWIODELAY
AM_RANGE(0x0170, 0x0177) AM_NOP //To debug
AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff)
AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read16_cs0, write16_cs0, 0xffffffff)
AM_RANGE(0x0200, 0x021f) AM_NOP //To debug
AM_RANGE(0x0260, 0x026f) AM_NOP //To debug
AM_RANGE(0x0278, 0x027b) AM_WRITENOP//AM_WRITE(pnp_config_w)
@ -285,7 +285,7 @@ static ADDRESS_MAP_START( voyager_io, AS_IO, 32, voyager_state )
AM_RANGE(0x0378, 0x037f) AM_NOP //To debug
// AM_RANGE(0x0300, 0x03af) AM_NOP
// AM_RANGE(0x03b0, 0x03df) AM_NOP
AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff)
AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read16_cs1, write16_cs1, 0xffffffff)
AM_RANGE(0x03f8, 0x03ff) AM_NOP // To debug Serial Port COM1:
AM_RANGE(0x0a78, 0x0a7b) AM_WRITENOP//AM_WRITE(pnp_data_w)
AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)

8
src/mame/drivers/vp101.cpp
View File

@ -318,8 +318,8 @@ static ADDRESS_MAP_START( main_map, AS_PROGRAM, 32, vp10x_state )
AM_RANGE(0x1ca00010, 0x1ca00013) AM_READ(test_r) // bits here cause various test mode stuff
AM_RANGE(0x1cf00000, 0x1cf00003) AM_NOP AM_READNOP
AM_RANGE(0x1d000030, 0x1d000033) AM_WRITE(dmaaddr_w) // ATA DMA destination address
AM_RANGE(0x1d000040, 0x1d00005f) AM_DEVREADWRITE16("ata", ata_interface_device, read_cs0, write_cs0, 0x0000ffff)
AM_RANGE(0x1d000060, 0x1d00007f) AM_DEVREADWRITE16("ata", ata_interface_device, read_cs1, write_cs1, 0x0000ffff)
AM_RANGE(0x1d000040, 0x1d00005f) AM_DEVREADWRITE16("ata", ata_interface_device, read16_cs0, write16_cs0, 0x0000ffff)
AM_RANGE(0x1d000060, 0x1d00007f) AM_DEVREADWRITE16("ata", ata_interface_device, read16_cs1, write16_cs1, 0x0000ffff)
AM_RANGE(0x1f200000, 0x1f200003) AM_READWRITE(pic_r, pic_w)
AM_RANGE(0x1f807000, 0x1f807fff) AM_RAM AM_SHARE("nvram")
AM_RANGE(0x1fc00000, 0x1fffffff) AM_ROM AM_REGION("maincpu", 0)
@ -327,8 +327,8 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( vp50_map, AS_PROGRAM, 32, vp10x_state )
AM_RANGE(0x00000000, 0x03ffffff) AM_RAM AM_SHARE("mainram")
AM_RANGE(0x1f000010, 0x1f00001f) AM_DEVREADWRITE16("ata", ata_interface_device, read_cs1, write_cs1, 0xffffffff)
AM_RANGE(0x1f000020, 0x1f00002f) AM_DEVREADWRITE16("ata", ata_interface_device, read_cs0, write_cs0, 0xffffffff)
AM_RANGE(0x1f000010, 0x1f00001f) AM_DEVREADWRITE16("ata", ata_interface_device, read16_cs1, write16_cs1, 0xffffffff)
AM_RANGE(0x1f000020, 0x1f00002f) AM_DEVREADWRITE16("ata", ata_interface_device, read16_cs0, write16_cs0, 0xffffffff)
AM_RANGE(0x1f400000, 0x1f400003) AM_NOP // FPGA bitstream download?
AM_RANGE(0x1f400800, 0x1f400bff) AM_RAM AM_SHARE("nvram")
AM_RANGE(0x1fc00000, 0x1fffffff) AM_ROM AM_REGION("maincpu", 0)

16
src/mame/drivers/zn.cpp
View File

@ -1278,7 +1278,7 @@ void zn_state::atpsx_dma_read( uint32_t *p_n_psxram, uint32_t n_address, int32_t
n_size <<= 1;
while( n_size > 0 )
{
psxwriteword( p_n_psxram, n_address, m_vt83c461->read_cs0(space, (uint32_t) 0, (uint32_t) 0xffff) );
psxwriteword( p_n_psxram, n_address, m_vt83c461->read32_cs0(space, (uint32_t) 0, (uint32_t) 0xffff) );
n_address += 2;
n_size--;
}
@ -1299,11 +1299,11 @@ READ16_MEMBER(zn_state::vt83c461_16_r)
}
else if( offset >= 0x1f0 / 2 && offset < 0x1f8 / 2 )
{
return m_vt83c461->read_cs0( space, ( offset / 2 ) & 1, (uint32_t) mem_mask << shift ) >> shift;
return m_vt83c461->read32_cs0( space, ( offset / 2 ) & 1, (uint32_t) mem_mask << shift ) >> shift;
}
else if( offset >= 0x3f0 / 2 && offset < 0x3f8 / 2 )
{
return m_vt83c461->read_cs1( space, ( offset / 2 ) & 1, (uint32_t) mem_mask << shift ) >> shift;
return m_vt83c461->read32_cs1( space, ( offset / 2 ) & 1, (uint32_t) mem_mask << shift ) >> shift;
}
else
{
@ -1322,11 +1322,11 @@ WRITE16_MEMBER(zn_state::vt83c461_16_w)
}
else if( offset >= 0x1f0 / 2 && offset < 0x1f8 / 2 )
{
m_vt83c461->write_cs0( space, ( offset / 2 ) & 1, (uint32_t) data << shift, (uint32_t) mem_mask << shift );
m_vt83c461->write32_cs0( space, ( offset / 2 ) & 1, (uint32_t) data << shift, (uint32_t) mem_mask << shift );
}
else if( offset >= 0x3f0 / 2 && offset < 0x3f8 / 2 )
{
m_vt83c461->write_cs1( space, ( offset / 2 ) & 1, (uint32_t) data << shift, (uint32_t) mem_mask << shift );
m_vt83c461->write32_cs1( space, ( offset / 2 ) & 1, (uint32_t) data << shift, (uint32_t) mem_mask << shift );
}
else
{
@ -1338,7 +1338,7 @@ READ16_MEMBER(zn_state::vt83c461_32_r)
{
if( offset == 0x1f0/2 )
{
uint32_t data = m_vt83c461->read_cs0(space, 0, 0xffffffff);
uint32_t data = m_vt83c461->read32_cs0(space, 0, 0xffffffff);
m_vt83c461_latch = data >> 16;
return data & 0xffff;
}
@ -2026,8 +2026,8 @@ DRIVER_INIT_MEMBER(zn_state,jdredd)
static ADDRESS_MAP_START(jdredd_map, AS_PROGRAM, 32, zn_state)
AM_RANGE(0x1f000000, 0x1f1fffff) AM_ROM AM_REGION("roms", 0)
AM_RANGE(0x1fbfff80, 0x1fbfff8f) AM_DEVREADWRITE16("ata", ata_interface_device, read_cs1, write_cs1, 0xffffffff)
AM_RANGE(0x1fbfff90, 0x1fbfff9f) AM_DEVREADWRITE16("ata", ata_interface_device, read_cs0, write_cs0, 0xffffffff)
AM_RANGE(0x1fbfff80, 0x1fbfff8f) AM_DEVREADWRITE16("ata", ata_interface_device, read16_cs1, write16_cs1, 0xffffffff)
AM_RANGE(0x1fbfff90, 0x1fbfff9f) AM_DEVREADWRITE16("ata", ata_interface_device, read16_cs0, write16_cs0, 0xffffffff)
AM_IMPORT_FROM(coh1000a_map)
ADDRESS_MAP_END

8
src/mame/machine/swtpc09.cpp
View File

@ -420,13 +420,13 @@ WRITE8_MEMBER( swtpc09_state::piaide_b_w )
{
if (!(data & 0x02)) //rd line bit 1
{
tempidedata = m_ide->read_cs0(space, (data&0x1c)>>2, 0xffff);
tempidedata = m_ide->read16_cs0(space, (data&0x1c)>>2, 0xffff);
LOG(("swtpc09_ide_bus_r: offset $%02X data %04X\n", (data&0x1c)>>2, tempidedata));
m_piaide_porta = tempidedata & 0x00ff;
}
else if (!(data & 0x01)) //wr line bit 0
{
m_ide->write_cs0(space, (data&0x1c)>>2, m_piaide_porta, 0xffff);
m_ide->write16_cs0(space, (data&0x1c)>>2, m_piaide_porta, 0xffff);
LOG(("swtpc09_ide_bus_w: offset $%02X data %04X\n", (data&0x1c)>>2, m_piaide_porta));
}
}
@ -434,13 +434,13 @@ WRITE8_MEMBER( swtpc09_state::piaide_b_w )
{
if (!(data & 0x02)) //rd line bit 1
{
tempidedata = m_ide->read_cs1(space, (data&0x1c)>>2, 0xffff);
tempidedata = m_ide->read16_cs1(space, (data&0x1c)>>2, 0xffff);
LOG(("swtpc09_ide_bus_r: offset $%02X data %04X\n", (data&0x1c)>>2, tempidedata));
m_piaide_porta = tempidedata & 0x00ff;
}
else if (!(data & 0x01)) //wr line bit 0
{
m_ide->write_cs1(space, (data&0x1c)>>2, m_piaide_porta, 0xffff);
m_ide->write16_cs1(space, (data&0x1c)>>2, m_piaide_porta, 0xffff);
LOG(("swtpc09_ide_bus_w: offset $%02X data %04X\n", (data&0x1c)>>2, m_piaide_porta));
}
}

2
src/mame/machine/xbox.cpp
View File

@ -844,7 +844,7 @@ ADDRESS_MAP_START(xbox_base_map_io, AS_IO, 32, xbox_base_state)
AM_RANGE(0x002c, 0x002f) AM_READWRITE8(superio_read, superio_write, 0xffff0000)
AM_RANGE(0x0040, 0x0043) AM_DEVREADWRITE8("pit8254", pit8254_device, read, write, 0xffffffff)
AM_RANGE(0x00a0, 0x00a3) AM_DEVREADWRITE8("pic8259_2", pic8259_device, read, write, 0xffffffff)
AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE(":pci:09.0:ide", bus_master_ide_controller_device, read_cs0, write_cs0)
AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE(":pci:09.0:ide", bus_master_ide_controller_device, read32_cs0, write32_cs0)
AM_RANGE(0x03f8, 0x03ff) AM_READWRITE8(superiors232_read, superiors232_write, 0xffffffff)
#if 0
AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)

4
src/mame/video/turrett.cpp
View File

@ -312,7 +312,7 @@ WRITE32_MEMBER( turrett_state::dma_w )
while (words--)
{
ram[addr & DIMM_BANK_MASK] = m_ata->read_cs0(space, 0, 0xffff);
ram[addr & DIMM_BANK_MASK] = m_ata->read16_cs0(space, 0, 0xffff);
++addr;
}
@ -324,7 +324,7 @@ WRITE32_MEMBER( turrett_state::dma_w )
{
while (words--)
{
uint16_t data = m_ata->read_cs0(space, 0, 0xffff);
uint16_t data = m_ata->read16_cs0(space, 0, 0xffff);
// TODO: Verify if this is correct
if ((data & 0xc400) == 0xc400)