mirror of
https://github.com/holub/mame
synced 2025-10-05 08:41:31 +03:00
explicit sizes for enums used in save states - one should always do this to maximise save state compatibility - also enum class (nw)
This commit is contained in:
Vas Crabb
parent
fa2e531321
commit
779ff8ac42
@ -283,8 +283,8 @@ cosmac_device::cosmac_device(const machine_config &mconfig, device_type type, co
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m_write_dma(*this),
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m_write_sc(*this),
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m_op(0),
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m_state(COSMAC_STATE_1_RESET),
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m_mode(COSMAC_MODE_RESET),
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m_state(cosmac_state::STATE_1_RESET),
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m_mode(cosmac_mode::RESET),
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m_irq(CLEAR_LINE),
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m_dmain(CLEAR_LINE),
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m_dmaout(CLEAR_LINE),
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@ -664,17 +664,17 @@ void cosmac_device::execute_run()
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switch (m_mode)
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{
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case COSMAC_MODE_LOAD:
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if (m_pmode == COSMAC_MODE_RESET)
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case cosmac_mode::LOAD:
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if (m_pmode == cosmac_mode::RESET)
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{
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m_pmode = COSMAC_MODE_LOAD;
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m_pmode = cosmac_mode::LOAD;
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// execute initialization cycle
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m_state = COSMAC_STATE_1_INIT;
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m_state = cosmac_state::STATE_1_INIT;
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run();
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// next state is IDLE
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m_state = COSMAC_STATE_1_EXECUTE;
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m_state = cosmac_state::STATE_1_EXECUTE;
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}
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else
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{
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@ -686,37 +686,37 @@ void cosmac_device::execute_run()
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}
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break;
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case COSMAC_MODE_RESET:
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m_state = COSMAC_STATE_1_RESET;
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case cosmac_mode::RESET:
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m_state = cosmac_state::STATE_1_RESET;
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run();
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break;
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case COSMAC_MODE_PAUSE:
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case cosmac_mode::PAUSE:
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m_icount--;
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break;
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case COSMAC_MODE_RUN:
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case cosmac_mode::RUN:
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switch (m_pmode)
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{
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case COSMAC_MODE_LOAD:
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case cosmac_mode::LOAD:
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// RUN mode cannot be initiated from LOAD mode
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logerror("COSMAC '%s' Tried to initiate RUN mode from LOAD mode\n", tag());
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m_mode = COSMAC_MODE_LOAD;
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m_mode = cosmac_mode::LOAD;
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break;
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case COSMAC_MODE_RESET:
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m_pmode = COSMAC_MODE_RUN;
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m_state = COSMAC_STATE_1_INIT;
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case cosmac_mode::RESET:
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m_pmode = cosmac_mode::RUN;
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m_state = cosmac_state::STATE_1_INIT;
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run();
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break;
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case COSMAC_MODE_PAUSE:
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m_pmode = COSMAC_MODE_RUN;
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m_state = COSMAC_STATE_0_FETCH;
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case cosmac_mode::PAUSE:
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m_pmode = cosmac_mode::RUN;
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m_state = cosmac_state::STATE_0_FETCH;
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run();
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break;
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case COSMAC_MODE_RUN:
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case cosmac_mode::RUN:
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run();
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break;
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}
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@ -737,35 +737,35 @@ inline void cosmac_device::run()
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switch (m_state)
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{
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case COSMAC_STATE_0_FETCH:
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case cosmac_state::STATE_0_FETCH:
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fetch_instruction();
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break;
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case COSMAC_STATE_1_RESET:
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case cosmac_state::STATE_1_RESET:
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reset();
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debug();
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break;
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case COSMAC_STATE_1_INIT:
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case cosmac_state::STATE_1_INIT:
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initialize();
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debug();
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break;
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case COSMAC_STATE_1_EXECUTE:
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case cosmac_state::STATE_1_EXECUTE:
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sample_ef_lines();
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execute_instruction();
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debug();
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break;
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case COSMAC_STATE_2_DMA_IN:
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case cosmac_state::STATE_2_DMA_IN:
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dma_input();
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break;
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case COSMAC_STATE_2_DMA_OUT:
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case cosmac_state::STATE_2_DMA_OUT:
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dma_output();
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break;
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case COSMAC_STATE_3_INT:
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case cosmac_state::STATE_3_INT:
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interrupt();
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debug();
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break;
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@ -819,7 +819,7 @@ inline void cosmac_device::sample_ef_lines()
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inline void cosmac_device::output_state_code()
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{
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m_write_sc((offs_t)0, COSMAC_STATE_CODE[m_state]);
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m_write_sc(offs_t(0), COSMAC_STATE_CODE[std::underlying_type_t<cosmac_state>(m_state)]);
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}
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@ -851,7 +851,7 @@ inline void cosmac_device::fetch_instruction()
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m_icount -= CLOCKS_FETCH;
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m_state = COSMAC_STATE_1_EXECUTE;
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m_state = cosmac_state::STATE_1_EXECUTE;
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}
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@ -885,15 +885,15 @@ inline void cosmac_device::initialize()
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if (m_dmain)
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{
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m_state = COSMAC_STATE_2_DMA_IN;
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m_state = cosmac_state::STATE_2_DMA_IN;
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}
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else if (m_dmaout)
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{
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m_state = COSMAC_STATE_2_DMA_OUT;
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m_state = cosmac_state::STATE_2_DMA_OUT;
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}
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else
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{
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m_state = COSMAC_STATE_0_FETCH;
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m_state = cosmac_state::STATE_0_FETCH;
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}
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}
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@ -911,19 +911,19 @@ inline void cosmac_device::execute_instruction()
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if (m_dmain)
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{
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m_state = COSMAC_STATE_2_DMA_IN;
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m_state = cosmac_state::STATE_2_DMA_IN;
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}
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else if (m_dmaout)
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{
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m_state = COSMAC_STATE_2_DMA_OUT;
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m_state = cosmac_state::STATE_2_DMA_OUT;
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}
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else if (IE && m_irq)
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{
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m_state = COSMAC_STATE_3_INT;
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m_state = cosmac_state::STATE_3_INT;
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}
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else if ((I > 0) || (N > 0)) // not idling
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{
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m_state = COSMAC_STATE_0_FETCH;
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m_state = cosmac_state::STATE_0_FETCH;
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}
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}
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@ -942,23 +942,23 @@ inline void cosmac_device::dma_input()
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if (m_dmain)
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{
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m_state = COSMAC_STATE_2_DMA_IN;
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m_state = cosmac_state::STATE_2_DMA_IN;
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}
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else if (m_dmaout)
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{
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m_state = COSMAC_STATE_2_DMA_OUT;
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m_state = cosmac_state::STATE_2_DMA_OUT;
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}
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else if (IE && m_irq)
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{
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m_state = COSMAC_STATE_3_INT;
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m_state = cosmac_state::STATE_3_INT;
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}
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else if (m_mode == COSMAC_MODE_LOAD)
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else if (m_mode == cosmac_mode::LOAD)
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{
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m_state = COSMAC_STATE_1_EXECUTE;
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m_state = cosmac_state::STATE_1_EXECUTE;
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}
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else
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{
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m_state = COSMAC_STATE_0_FETCH;
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m_state = cosmac_state::STATE_0_FETCH;
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}
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standard_irq_callback(COSMAC_INPUT_LINE_DMAIN);
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@ -979,19 +979,19 @@ inline void cosmac_device::dma_output()
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if (m_dmain)
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{
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m_state = COSMAC_STATE_2_DMA_IN;
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m_state = cosmac_state::STATE_2_DMA_IN;
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}
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else if (m_dmaout)
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{
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m_state = COSMAC_STATE_2_DMA_OUT;
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m_state = cosmac_state::STATE_2_DMA_OUT;
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}
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else if (IE && m_irq)
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{
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m_state = COSMAC_STATE_3_INT;
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m_state = cosmac_state::STATE_3_INT;
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}
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else
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{
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m_state = COSMAC_STATE_0_FETCH;
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m_state = cosmac_state::STATE_0_FETCH;
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}
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standard_irq_callback(COSMAC_INPUT_LINE_DMAOUT);
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@ -1013,15 +1013,15 @@ inline void cosmac_device::interrupt()
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if (m_dmain)
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{
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m_state = COSMAC_STATE_2_DMA_IN;
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m_state = cosmac_state::STATE_2_DMA_IN;
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}
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else if (m_dmaout)
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{
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m_state = COSMAC_STATE_2_DMA_OUT;
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m_state = cosmac_state::STATE_2_DMA_OUT;
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}
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else
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{
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m_state = COSMAC_STATE_0_FETCH;
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m_state = cosmac_state::STATE_0_FETCH;
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}
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standard_irq_callback(COSMAC_INPUT_LINE_INT);
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@ -384,24 +384,24 @@ protected:
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devcb_write8 m_write_sc;
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// control modes
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enum cosmac_mode
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enum class cosmac_mode : u8
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{
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COSMAC_MODE_LOAD = 0,
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COSMAC_MODE_RESET,
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COSMAC_MODE_PAUSE,
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COSMAC_MODE_RUN
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LOAD = 0,
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RESET,
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PAUSE,
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RUN
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};
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// execution states
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enum cosmac_state
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enum class cosmac_state : u8
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{
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COSMAC_STATE_0_FETCH = 0,
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COSMAC_STATE_1_RESET,
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COSMAC_STATE_1_INIT,
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COSMAC_STATE_1_EXECUTE,
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COSMAC_STATE_2_DMA_IN,
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COSMAC_STATE_2_DMA_OUT,
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COSMAC_STATE_3_INT
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STATE_0_FETCH = 0,
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STATE_1_RESET,
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STATE_1_INIT,
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STATE_1_EXECUTE,
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STATE_2_DMA_IN,
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STATE_2_DMA_OUT,
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STATE_3_INT
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};
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// internal state
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@ -146,7 +146,7 @@ public:
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AS_RAM_PORTS,
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AS_PROGRAM_MEMORY
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};
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enum class phase { A1, A2, A3, M1, M2, X1, X2, X3 };
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enum class phase : u8 { A1, A2, A3, M1, M2, X1, X2, X3 };
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// step isn't a real signal, but realistically anything watching the bus will have a counter to track it
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typedef device_delegate<void (phase step, u8 sync, u8 data)> bus_cycle_delegate;
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@ -170,8 +170,8 @@ public:
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DECLARE_READ_LINE_MEMBER(get_4289_f_l) const { return BIT(m_4289_f_l, 0); } // 1 = odd, 0 = even
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protected:
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enum class cycle { OP, IM, IN };
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enum class pmem { NONE, READ, WRITE };
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enum class cycle : u8 { OP, IM, IN };
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enum class pmem : u8 { NONE, READ, WRITE };
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mcs40_cpu_device_base(
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machine_config const &mconfig,
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@ -201,22 +201,22 @@ static const char *const cc_names[] = { "f", "lt", "le", "ule", "ov"
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#define OPCC( X,CF,CT ) OP( X, CT ) m_cyc_f = (CF*2);
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#define OPCC16( X,CF,CT ) OPCC( (X)|OP_16,CF,CT )
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#define BIT8( N,I ) m_mode##N = MODE_BIT8; m_r##N = I;
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#define I8( N,I ) m_mode##N = MODE_I8; m_r##N = I;
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#define D8( N,I ) m_mode##N = MODE_D8; m_r##N = I;
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#define I16( N,I ) m_mode##N = MODE_I16; m_r##N = I;
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#define D16( N,I ) m_mode##N = MODE_D16; m_r##N = I;
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#define R8( N,R ) m_mode##N = MODE_R8; m_r##N = R;
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#define R16( N,R ) m_mode##N = MODE_R16; m_r##N = R;
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#define Q16( N,R ) m_mode##N = MODE_R16; m_r##N = R; if (m_r##N == SP) m_r##N = AF;
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#define MI16( N,I ) m_mode##N = MODE_MI16; m_r##N = I;
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#define MR16( N,R ) m_mode##N = MODE_MR16; m_r##N = R;
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#define MR16D8( N,R,I ) m_mode##N = MODE_MR16D8; m_r##N = R; m_r##N##b = I;
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#define MR16R8( N,R,g ) m_mode##N = MODE_MR16R8; m_r##N = R; m_r##N##b = g;
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#define NONE( N ) m_mode##N = MODE_NONE;
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#define CC( N,cc ) m_mode##N = MODE_CC; m_r##N = cc;
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#define R16D8( N,R,I ) m_mode##N = MODE_R16D8; m_r##N = R; m_r##N##b = I;
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#define R16R8( N,R,g ) m_mode##N = MODE_R16R8; m_r##N = R; m_r##N##b = g;
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#define BIT8( N,I ) m_mode##N = e_mode::BIT8; m_r##N = I;
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#define I8( N,I ) m_mode##N = e_mode::I8; m_r##N = I;
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#define D8( N,I ) m_mode##N = e_mode::D8; m_r##N = I;
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#define I16( N,I ) m_mode##N = e_mode::I16; m_r##N = I;
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#define D16( N,I ) m_mode##N = e_mode::D16; m_r##N = I;
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#define R8( N,R ) m_mode##N = e_mode::R8; m_r##N = R;
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#define R16( N,R ) m_mode##N = e_mode::R16; m_r##N = R;
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#define Q16( N,R ) m_mode##N = e_mode::R16; m_r##N = R; if (m_r##N == SP) m_r##N = AF;
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#define MI16( N,I ) m_mode##N = e_mode::MI16; m_r##N = I;
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#define MR16( N,R ) m_mode##N = e_mode::MR16; m_r##N = R;
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#define MR16D8( N,R,I ) m_mode##N = e_mode::MR16D8; m_r##N = R; m_r##N##b = I;
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#define MR16R8( N,R,g ) m_mode##N = e_mode::MR16R8; m_r##N = R; m_r##N##b = g;
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#define NONE( N ) m_mode##N = e_mode::NONE;
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#define CC( N,cc ) m_mode##N = e_mode::CC; m_r##N = cc;
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#define R16D8( N,R,I ) m_mode##N = e_mode::R16D8; m_r##N = R; m_r##N##b = I;
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#define R16R8( N,R,g ) m_mode##N = e_mode::R16R8; m_r##N = R; m_r##N##b = g;
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uint8_t tlcs90_device::RM8 (uint32_t a) { return m_program->read_byte( a ); }
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uint16_t tlcs90_device::RM16(uint32_t a) { return RM8(a) | (RM8( (a+1) & 0xffff ) << 8); }
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@ -1017,34 +1017,34 @@ bool tlcs90_device::stream_arg(std::ostream &stream, uint32_t pc, const char *pr
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const char *reg_name;
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switch ( mode )
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{
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case MODE_NONE: return false;
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case e_mode::NONE: return false;
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case MODE_BIT8: util::stream_format(stream, "%s%d", pre, r ); return true;
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case MODE_I8: util::stream_format(stream, "%s$%02X", pre, r ); return true;
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case MODE_D8: util::stream_format(stream, "%s$%04X", pre, (pc+2+(r&0x7f)-(r&0x80))&0xffff ); return true;
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case MODE_I16: util::stream_format(stream, "%s$%04X", pre, r ); return true;
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case MODE_D16: util::stream_format(stream, "%s$%04X", pre, (pc+2+(r&0x7fff)-(r&0x8000))&0xffff ); return true;
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case MODE_MI16:
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reg_name = internal_registers_names(r);
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if (reg_name)
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util::stream_format(stream, "%s(%s)", pre, reg_name);
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else
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util::stream_format(stream, "%s($%04X)", pre, r );
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return true;
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case MODE_R8: util::stream_format(stream, "%s%s", pre, r8_names[r] ); return true;
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case MODE_R16: util::stream_format(stream, "%s%s", pre, r16_names[r] ); return true;
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case MODE_MR16: util::stream_format(stream, "%s(%s)", pre, r16_names[r] ); return true;
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case e_mode::BIT8: util::stream_format(stream, "%s%d", pre, r ); return true;
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case e_mode::I8: util::stream_format(stream, "%s$%02X", pre, r ); return true;
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case e_mode::D8: util::stream_format(stream, "%s$%04X", pre, (pc+2+(r&0x7f)-(r&0x80))&0xffff ); return true;
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case e_mode::I16: util::stream_format(stream, "%s$%04X", pre, r ); return true;
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case e_mode::D16: util::stream_format(stream, "%s$%04X", pre, (pc+2+(r&0x7fff)-(r&0x8000))&0xffff ); return true;
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case e_mode::MI16:
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reg_name = internal_registers_names(r);
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if (reg_name)
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util::stream_format(stream, "%s(%s)", pre, reg_name);
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else
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util::stream_format(stream, "%s($%04X)", pre, r );
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return true;
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case e_mode::R8: util::stream_format(stream, "%s%s", pre, r8_names[r] ); return true;
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case e_mode::R16: util::stream_format(stream, "%s%s", pre, r16_names[r] ); return true;
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case e_mode::MR16: util::stream_format(stream, "%s(%s)", pre, r16_names[r] ); return true;
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|
||||
case MODE_MR16R8: util::stream_format(stream, "%s(%s+%s)", pre, r16_names[r], r8_names[rb] ); return true;
|
||||
case MODE_MR16D8: util::stream_format(stream, "%s(%s%c$%02X)", pre, r16_names[r], (rb&0x80)?'-':'+', (rb&0x80)?((rb^0xff)+1):rb ); return true;
|
||||
case e_mode::MR16R8: util::stream_format(stream, "%s(%s+%s)", pre, r16_names[r], r8_names[rb] ); return true;
|
||||
case e_mode::MR16D8: util::stream_format(stream, "%s(%s%c$%02X)", pre, r16_names[r], (rb&0x80)?'-':'+', (rb&0x80)?((rb^0xff)+1):rb ); return true;
|
||||
|
||||
case MODE_CC: util::stream_format(stream, "%s%s", pre, cc_names[r] ); return true;
|
||||
case e_mode::CC: util::stream_format(stream, "%s%s", pre, cc_names[r] ); return true;
|
||||
|
||||
case MODE_R16R8: util::stream_format(stream, "%s%s+%s", pre, r16_names[r], r8_names[rb] ); return true;
|
||||
case MODE_R16D8: util::stream_format(stream, "%s%s%c$%02X", pre, r16_names[r], (rb&0x80)?'-':'+', (rb&0x80)?((rb^0xff)+1):rb ); return true;
|
||||
case e_mode::R16R8: util::stream_format(stream, "%s%s+%s", pre, r16_names[r], r8_names[rb] ); return true;
|
||||
case e_mode::R16D8: util::stream_format(stream, "%s%s%c$%02X", pre, r16_names[r], (rb&0x80)?'-':'+', (rb&0x80)?((rb^0xff)+1):rb ); return true;
|
||||
|
||||
default:
|
||||
fatalerror("%04x: unimplemented addr mode = %d\n",pc,mode);
|
||||
default:
|
||||
fatalerror("%04x: unimplemented addr mode = %d\n",pc,std::underlying_type_t<e_mode>(mode));
|
||||
}
|
||||
|
||||
// never executed
|
||||
@ -1144,53 +1144,53 @@ void tlcs90_device::w16( const uint16_t r, uint16_t value )
|
||||
#define READ_FN( N ) \
|
||||
uint8_t tlcs90_device::Read##N##_8() { \
|
||||
switch ( m_mode##N ) { \
|
||||
case MODE_CC: \
|
||||
case MODE_BIT8: \
|
||||
case MODE_I8: return (uint8_t)m_r##N; \
|
||||
case MODE_D8: return (uint8_t)m_r##N; \
|
||||
case MODE_R8: return (uint8_t)r8(m_r##N); \
|
||||
case MODE_MI16: return RM8(m_r##N); \
|
||||
case MODE_MR16R8: return RM8((uint16_t)(r16(m_r##N) + (int8_t)r8(m_r##N##b))); \
|
||||
case MODE_MR16: \
|
||||
case e_mode::CC: \
|
||||
case e_mode::BIT8: \
|
||||
case e_mode::I8: return (uint8_t)m_r##N; \
|
||||
case e_mode::D8: return (uint8_t)m_r##N; \
|
||||
case e_mode::R8: return (uint8_t)r8(m_r##N); \
|
||||
case e_mode::MI16: return RM8(m_r##N); \
|
||||
case e_mode::MR16R8: return RM8((uint16_t)(r16(m_r##N) + (int8_t)r8(m_r##N##b))); \
|
||||
case e_mode::MR16: \
|
||||
switch( m_r##N ) { \
|
||||
case IX: return RX8(m_ix.w.l,m_ixbase); \
|
||||
case IY: return RX8(m_iy.w.l,m_iybase); \
|
||||
} \
|
||||
return RM8(r16(m_r##N)); \
|
||||
case MODE_MR16D8: \
|
||||
case e_mode::MR16D8: \
|
||||
switch( m_r##N ) { \
|
||||
case IX: return RX8((uint16_t)(m_ix.w.l + (int8_t)m_r##N##b),m_ixbase); \
|
||||
case IY: return RX8((uint16_t)(m_iy.w.l + (int8_t)m_r##N##b),m_iybase); \
|
||||
} \
|
||||
return RM8((uint16_t)(r16(m_r##N) + (int8_t)m_r##N##b)); \
|
||||
default: \
|
||||
fatalerror("%04x: unimplemented Read%d_8 mode = %d\n",m_pc.w.l,N,m_mode##N); \
|
||||
fatalerror("%04x: unimplemented Read%d_8 mode = %d\n",m_pc.w.l,N,std::underlying_type_t<e_mode>(m_mode##N)); \
|
||||
} \
|
||||
return 0; \
|
||||
} \
|
||||
uint16_t tlcs90_device::Read##N##_16() { \
|
||||
switch ( m_mode##N ) { \
|
||||
case MODE_I16: return m_r##N; \
|
||||
case MODE_D16: return m_r##N - 1; \
|
||||
case MODE_R16: return r16(m_r##N); \
|
||||
case MODE_R16D8: return r16(m_r##N) + (int8_t)m_r##N##b; \
|
||||
case MODE_R16R8: return r16(m_r##N) + (int8_t)r8(m_r##N##b); \
|
||||
case MODE_MI16: return RM16(m_r##N); \
|
||||
case MODE_MR16R8: return RM16((uint16_t)(r16(m_r##N) + (int8_t)r8(m_r##N##b))); \
|
||||
case MODE_MR16: \
|
||||
case e_mode::I16: return m_r##N; \
|
||||
case e_mode::D16: return m_r##N - 1; \
|
||||
case e_mode::R16: return r16(m_r##N); \
|
||||
case e_mode::R16D8: return r16(m_r##N) + (int8_t)m_r##N##b; \
|
||||
case e_mode::R16R8: return r16(m_r##N) + (int8_t)r8(m_r##N##b); \
|
||||
case e_mode::MI16: return RM16(m_r##N); \
|
||||
case e_mode::MR16R8: return RM16((uint16_t)(r16(m_r##N) + (int8_t)r8(m_r##N##b))); \
|
||||
case e_mode::MR16: \
|
||||
switch( m_r##N ) { \
|
||||
case IX: return RX16(m_ix.w.l,m_ixbase); \
|
||||
case IY: return RX16(m_iy.w.l,m_iybase); \
|
||||
} \
|
||||
return RM16(r16(m_r##N)); \
|
||||
case MODE_MR16D8: \
|
||||
case e_mode::MR16D8: \
|
||||
switch( m_r##N ) { \
|
||||
case IX: return RX16((uint16_t)(m_ix.w.l + (int8_t)m_r##N##b),m_ixbase); \
|
||||
case IY: return RX16((uint16_t)(m_iy.w.l + (int8_t)m_r##N##b),m_iybase); \
|
||||
} \
|
||||
return RM16((uint16_t)(r16(m_r##N) + (int8_t)m_r##N##b)); \
|
||||
default: \
|
||||
fatalerror("%04x: unimplemented Read%d_16 modes = %d\n",m_pc.w.l,N,m_mode##N); \
|
||||
fatalerror("%04x: unimplemented Read%d_16 modes = %d\n",m_pc.w.l,N,std::underlying_type_t<e_mode>(m_mode##N)); \
|
||||
} \
|
||||
return 0; \
|
||||
}
|
||||
@ -1200,45 +1200,45 @@ uint16_t tlcs90_device::Read##N##_16() { \
|
||||
#define WRITE_FN( N ) \
|
||||
void tlcs90_device::Write##N##_8( uint8_t value ) { \
|
||||
switch ( m_mode##N ) { \
|
||||
case MODE_R8: w8(m_r##N,value); return; \
|
||||
case MODE_MI16: WM8(m_r##N, value); return; \
|
||||
case MODE_MR16R8: WM8((uint16_t)(r16(m_r##N) + (int8_t)r8(m_r##N##b)), value); return; \
|
||||
case MODE_MR16: \
|
||||
case e_mode::R8: w8(m_r##N,value); return; \
|
||||
case e_mode::MI16: WM8(m_r##N, value); return; \
|
||||
case e_mode::MR16R8: WM8((uint16_t)(r16(m_r##N) + (int8_t)r8(m_r##N##b)), value); return; \
|
||||
case e_mode::MR16: \
|
||||
switch( m_r##N ) { \
|
||||
case IX: WX8(m_ix.w.l,value,m_ixbase); return; \
|
||||
case IY: WX8(m_iy.w.l,value,m_iybase); return; \
|
||||
} \
|
||||
WM8(r16(m_r##N), value); return; \
|
||||
case MODE_MR16D8: \
|
||||
case e_mode::MR16D8: \
|
||||
switch( m_r##N ) { \
|
||||
case IX: WX8((uint16_t)(m_ix.w.l + (int8_t)m_r##N##b),value,m_ixbase); return; \
|
||||
case IY: WX8((uint16_t)(m_iy.w.l + (int8_t)m_r##N##b),value,m_iybase); return; \
|
||||
} \
|
||||
WM8((uint16_t)(r16(m_r##N) + (int8_t)m_r##N##b), value); return; \
|
||||
default: \
|
||||
fatalerror("%04x: unimplemented Write%d_8 mode = %d\n",m_pc.w.l,N,m_mode##N); \
|
||||
fatalerror("%04x: unimplemented Write%d_8 mode = %d\n",m_pc.w.l,N,std::underlying_type_t<e_mode>(m_mode##N)); \
|
||||
} \
|
||||
} \
|
||||
void tlcs90_device::Write##N##_16( uint16_t value ) \
|
||||
{ \
|
||||
switch ( m_mode##N ) { \
|
||||
case MODE_R16: w16(m_r##N,value); return; \
|
||||
case MODE_MI16: WM16(m_r##N, value); return; \
|
||||
case MODE_MR16R8: WM16((uint16_t)(r16(m_r##N) + (int8_t)r8(m_r##N##b)), value); return; \
|
||||
case MODE_MR16: \
|
||||
case e_mode::R16: w16(m_r##N,value); return; \
|
||||
case e_mode::MI16: WM16(m_r##N, value); return; \
|
||||
case e_mode::MR16R8: WM16((uint16_t)(r16(m_r##N) + (int8_t)r8(m_r##N##b)), value); return; \
|
||||
case e_mode::MR16: \
|
||||
switch( m_r##N ) { \
|
||||
case IX: WX16(m_ix.w.l,value,m_ixbase); return; \
|
||||
case IY: WX16(m_iy.w.l,value,m_iybase); return; \
|
||||
} \
|
||||
WM16(r16(m_r##N), value); return; \
|
||||
case MODE_MR16D8: \
|
||||
case e_mode::MR16D8: \
|
||||
switch( m_r##N ) { \
|
||||
case IX: WX16((uint16_t)(m_ix.w.l + (int8_t)m_r##N##b),value,m_ixbase); return; \
|
||||
case IY: WX16((uint16_t)(m_iy.w.l + (int8_t)m_r##N##b),value,m_iybase); return; \
|
||||
} \
|
||||
WM16((uint16_t)(r16(m_r##N) + (int8_t)m_r##N##b), value); return; \
|
||||
default: \
|
||||
fatalerror("%04x: unimplemented Write%d_16 mode = %d\n",m_pc.w.l,N,m_mode##N); \
|
||||
fatalerror("%04x: unimplemented Write%d_16 mode = %d\n",m_pc.w.l,N,std::underlying_type_t<e_mode>(m_mode##N)); \
|
||||
} \
|
||||
}
|
||||
|
||||
@ -1802,7 +1802,7 @@ void tlcs90_device::execute_run()
|
||||
a32 = a16 + b16;
|
||||
if ( (m_op == (ADC | OP_16)) && (F & CF) ) a32 += 1;
|
||||
Write1_16( a32 );
|
||||
if ( (m_op == (ADD | OP_16)) && m_mode2 == MODE_R16 )
|
||||
if ( (m_op == (ADD | OP_16)) && m_mode2 == e_mode::R16 )
|
||||
{
|
||||
F &= SF | ZF | IF | VF;
|
||||
}
|
||||
@ -1898,7 +1898,7 @@ void tlcs90_device::execute_run()
|
||||
a8 = Read1_8();
|
||||
a8 = (a8 << 1) | (a8 >> 7);
|
||||
Write1_8( a8 );
|
||||
if ( m_mode1 == MODE_R8 && m_r1 == A ) F &= SF | ZF | IF | PF;
|
||||
if ( m_mode1 == e_mode::R8 && m_r1 == A ) F &= SF | ZF | IF | PF;
|
||||
else F = (F & IF) | SZP[a8];
|
||||
if (a8 & 0x01) F |= CF | XCF; // X?
|
||||
Cyc();
|
||||
@ -1907,7 +1907,7 @@ void tlcs90_device::execute_run()
|
||||
a8 = Read1_8();
|
||||
a8 = (a8 >> 1) | (a8 << 7);
|
||||
Write1_8( a8 );
|
||||
if ( m_mode1 == MODE_R8 && m_r1 == A ) F &= SF | ZF | IF | PF;
|
||||
if ( m_mode1 == e_mode::R8 && m_r1 == A ) F &= SF | ZF | IF | PF;
|
||||
else F = (F & IF) | SZP[a8];
|
||||
if (a8 & 0x80) F |= CF | XCF; // X?
|
||||
Cyc();
|
||||
@ -1918,7 +1918,7 @@ void tlcs90_device::execute_run()
|
||||
a8 <<= 1;
|
||||
if (F & CF) a8 |= 0x01;
|
||||
Write1_8( a8 );
|
||||
if ( m_mode1 == MODE_R8 && m_r1 == A ) F &= SF | ZF | IF | PF;
|
||||
if ( m_mode1 == e_mode::R8 && m_r1 == A ) F &= SF | ZF | IF | PF;
|
||||
else F = (F & IF) | SZP[a8];
|
||||
if (b8) F |= CF | XCF; // X?
|
||||
Cyc();
|
||||
@ -1929,7 +1929,7 @@ void tlcs90_device::execute_run()
|
||||
a8 >>= 1;
|
||||
if (F & CF) a8 |= 0x80;
|
||||
Write1_8( a8 );
|
||||
if ( m_mode1 == MODE_R8 && m_r1 == A ) F &= SF | ZF | IF | PF;
|
||||
if ( m_mode1 == e_mode::R8 && m_r1 == A ) F &= SF | ZF | IF | PF;
|
||||
else F = (F & IF) | SZP[a8];
|
||||
if (b8) F |= CF | XCF; // X?
|
||||
Cyc();
|
||||
@ -1941,7 +1941,7 @@ void tlcs90_device::execute_run()
|
||||
b8 = a8 & 0x80;
|
||||
a8 <<= 1;
|
||||
Write1_8( a8 );
|
||||
if ( m_mode1 == MODE_R8 && m_r1 == A ) F &= SF | ZF | IF | PF;
|
||||
if ( m_mode1 == e_mode::R8 && m_r1 == A ) F &= SF | ZF | IF | PF;
|
||||
else F = (F & IF) | SZP[a8];
|
||||
if (b8) F |= CF | XCF; // X?
|
||||
Cyc();
|
||||
@ -1951,7 +1951,7 @@ void tlcs90_device::execute_run()
|
||||
b8 = a8 & 0x01;
|
||||
a8 = (a8 & 0x80) | (a8 >> 1);
|
||||
Write1_8( a8 );
|
||||
if ( m_mode1 == MODE_R8 && m_r1 == A ) F &= SF | ZF | IF | PF;
|
||||
if ( m_mode1 == e_mode::R8 && m_r1 == A ) F &= SF | ZF | IF | PF;
|
||||
else F = (F & IF) | SZP[a8];
|
||||
if (b8) F |= CF | XCF; // X?
|
||||
Cyc();
|
||||
@ -1961,7 +1961,7 @@ void tlcs90_device::execute_run()
|
||||
b8 = a8 & 0x01;
|
||||
a8 >>= 1;
|
||||
Write1_8( a8 );
|
||||
if ( m_mode1 == MODE_R8 && m_r1 == A ) F &= SF | ZF | IF | PF;
|
||||
if ( m_mode1 == e_mode::R8 && m_r1 == A ) F &= SF | ZF | IF | PF;
|
||||
else F = (F & IF) | SZP[a8];
|
||||
if (b8) F |= CF | XCF; // X?
|
||||
Cyc();
|
||||
@ -2750,9 +2750,9 @@ void tlcs90_device::device_start()
|
||||
m_timer_value[0] = m_timer_value[1] = m_timer_value[2] = m_timer_value[3] = 0;
|
||||
m_timer4_value = 0;
|
||||
m_op = 0;
|
||||
m_mode1 = MODE_NONE;
|
||||
m_mode1 = e_mode::NONE;
|
||||
m_r1 = m_r1b = 0;
|
||||
m_mode2 = MODE_NONE;
|
||||
m_mode2 = e_mode::NONE;
|
||||
m_r2 = m_r2b = 0;
|
||||
m_cyc_t = m_cyc_f = 0;
|
||||
m_addr = 0;
|
||||
|
||||
@ -136,12 +136,12 @@ protected:
|
||||
virtual offs_t disasm_disassemble(std::ostream &stream, offs_t pc, const uint8_t *oprom, const uint8_t *opram, uint32_t options) override;
|
||||
|
||||
private:
|
||||
enum e_mode {
|
||||
MODE_NONE, MODE_BIT8, MODE_CC,
|
||||
MODE_I8, MODE_D8, MODE_R8,
|
||||
MODE_I16, MODE_D16, MODE_R16,
|
||||
MODE_MI16, MODE_MR16, MODE_MR16D8, MODE_MR16R8,
|
||||
MODE_R16D8, MODE_R16R8
|
||||
enum class e_mode : u8 {
|
||||
NONE, BIT8, CC,
|
||||
I8, D8, R8,
|
||||
I16, D16, R16,
|
||||
MI16, MR16, MR16D8, MR16R8,
|
||||
R16D8, R16R8
|
||||
};
|
||||
|
||||
address_space_config m_program_config;
|
||||
|
||||
@ -50,17 +50,6 @@ enum ay31015_output_pin_t
|
||||
class ay31015_device : public device_t
|
||||
{
|
||||
public:
|
||||
enum state_t
|
||||
{
|
||||
IDLE,
|
||||
START_BIT,
|
||||
PROCESSING,
|
||||
PARITY_BIT,
|
||||
FIRST_STOP_BIT,
|
||||
SECOND_STOP_BIT,
|
||||
PREP_TIME
|
||||
};
|
||||
|
||||
ay31015_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
static void set_tx_clock(device_t &device, double tx_clock) { downcast<ay31015_device &>(device).m_tx_clock = tx_clock; }
|
||||
@ -93,6 +82,17 @@ public:
|
||||
void tx_process();
|
||||
|
||||
protected:
|
||||
enum state_t : u8
|
||||
{
|
||||
IDLE,
|
||||
START_BIT,
|
||||
PROCESSING,
|
||||
PARITY_BIT,
|
||||
FIRST_STOP_BIT,
|
||||
SECOND_STOP_BIT,
|
||||
PREP_TIME
|
||||
};
|
||||
|
||||
static constexpr device_timer_id TIMER_RX = 0;
|
||||
static constexpr device_timer_id TIMER_TX = 1;
|
||||
|
||||
|
||||
@ -24,12 +24,6 @@
|
||||
class ds1315_device : public device_t
|
||||
{
|
||||
public:
|
||||
enum mode_t
|
||||
{
|
||||
DS_SEEK_MATCHING,
|
||||
DS_CALENDAR_IO
|
||||
};
|
||||
|
||||
ds1315_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
~ds1315_device() {}
|
||||
|
||||
@ -47,6 +41,12 @@ protected:
|
||||
virtual void device_reset() override;
|
||||
|
||||
private:
|
||||
enum mode_t : u8
|
||||
{
|
||||
DS_SEEK_MATCHING,
|
||||
DS_CALENDAR_IO
|
||||
};
|
||||
|
||||
// internal state
|
||||
mode_t m_mode;
|
||||
|
||||
|
||||
@ -119,7 +119,7 @@ protected:
|
||||
// read interfaces differ between implementations
|
||||
|
||||
// commands
|
||||
enum eeprom_command
|
||||
enum eeprom_command : u8
|
||||
{
|
||||
COMMAND_INVALID,
|
||||
COMMAND_READ,
|
||||
@ -134,7 +134,7 @@ protected:
|
||||
};
|
||||
|
||||
// states
|
||||
enum eeprom_state
|
||||
enum eeprom_state : u8
|
||||
{
|
||||
STATE_IN_RESET,
|
||||
STATE_WAIT_FOR_START_BIT,
|
||||
@ -145,7 +145,7 @@ protected:
|
||||
};
|
||||
|
||||
// events
|
||||
enum eeprom_event
|
||||
enum eeprom_event : u8
|
||||
{
|
||||
EVENT_CS_RISING_EDGE = 1 << 0,
|
||||
EVENT_CS_FALLING_EDGE = 1 << 1,
|
||||
|
||||
@ -27,7 +27,7 @@
|
||||
#define LOGOCW(...) LOGMASKED(LOG_OCW, __VA_ARGS__)
|
||||
|
||||
|
||||
ALLOW_SAVE_TYPE(pic8259_device::pic8259_state_t); // allow save_item on a non-fundamental type
|
||||
ALLOW_SAVE_TYPE(pic8259_device::state_t); // allow save_item on a non-fundamental type
|
||||
|
||||
void pic8259_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
|
||||
{
|
||||
@ -44,7 +44,7 @@ void pic8259_device::device_timer(emu_timer &timer, device_timer_id id, int para
|
||||
}
|
||||
|
||||
/* is this IRQ pending and enabled? */
|
||||
if ((m_state == STATE_READY) && (m_irr & mask) && !(m_imr & mask))
|
||||
if ((m_state == state_t::READY) && (m_irr & mask) && !(m_imr & mask))
|
||||
{
|
||||
LOG("pic8259_timerproc(): PIC triggering IRQ #%d\n", irq);
|
||||
m_out_int_func(1);
|
||||
@ -205,10 +205,10 @@ WRITE8_MEMBER( pic8259_device::write )
|
||||
m_cascade = (data & 0x02) ? 0 : 1;
|
||||
m_icw4_needed = (data & 0x01) ? 1 : 0;
|
||||
m_vector_addr_low = (data & 0xe0);
|
||||
m_state = STATE_ICW2;
|
||||
m_state = state_t::ICW2;
|
||||
m_out_int_func(0);
|
||||
}
|
||||
else if (m_state == STATE_READY)
|
||||
else if (m_state == state_t::READY)
|
||||
{
|
||||
if ((data & 0x98) == 0x08)
|
||||
{
|
||||
@ -280,10 +280,10 @@ WRITE8_MEMBER( pic8259_device::write )
|
||||
case 1:
|
||||
switch(m_state)
|
||||
{
|
||||
case STATE_ICW1:
|
||||
case state_t::ICW1:
|
||||
break;
|
||||
|
||||
case STATE_ICW2:
|
||||
case state_t::ICW2:
|
||||
/* write ICW2 */
|
||||
LOGICW("pic8259_device::write(): ICW2; data=0x%02X\n", data);
|
||||
|
||||
@ -291,23 +291,23 @@ WRITE8_MEMBER( pic8259_device::write )
|
||||
m_vector_addr_high = data ;
|
||||
if (m_cascade)
|
||||
{
|
||||
m_state = STATE_ICW3;
|
||||
m_state = state_t::ICW3;
|
||||
}
|
||||
else
|
||||
{
|
||||
m_state = m_icw4_needed ? STATE_ICW4 : STATE_READY;
|
||||
m_state = m_icw4_needed ? state_t::ICW4 : state_t::READY;
|
||||
}
|
||||
break;
|
||||
|
||||
case STATE_ICW3:
|
||||
case state_t::ICW3:
|
||||
/* write ICW3 */
|
||||
LOGICW("pic8259_device::write(): ICW3; data=0x%02X\n", data);
|
||||
|
||||
m_slave = data;
|
||||
m_state = m_icw4_needed ? STATE_ICW4 : STATE_READY;
|
||||
m_state = m_icw4_needed ? state_t::ICW4 : state_t::READY;
|
||||
break;
|
||||
|
||||
case STATE_ICW4:
|
||||
case state_t::ICW4:
|
||||
/* write ICW4 */
|
||||
LOGICW("pic8259_device::write(): ICW4; data=0x%02X\n", data);
|
||||
|
||||
@ -315,10 +315,10 @@ WRITE8_MEMBER( pic8259_device::write )
|
||||
m_mode = (data >> 2) & 3;
|
||||
m_auto_eoi = (data & 0x02) ? 1 : 0;
|
||||
m_is_x86 = (data & 0x01) ? 1 : 0;
|
||||
m_state = STATE_READY;
|
||||
m_state = state_t::READY;
|
||||
break;
|
||||
|
||||
case STATE_READY:
|
||||
case state_t::READY:
|
||||
/* write OCW1 - set interrupt mask register */
|
||||
LOGOCW("pic8259_device::write(): OCW1; data=0x%02X\n", data);
|
||||
|
||||
@ -374,7 +374,7 @@ void pic8259_device::device_start()
|
||||
|
||||
void pic8259_device::device_reset()
|
||||
{
|
||||
m_state = STATE_READY;
|
||||
m_state = state_t::READY;
|
||||
m_isr = 0;
|
||||
m_irr = 0;
|
||||
m_irq_lines = 0;
|
||||
|
||||
@ -79,20 +79,20 @@ private:
|
||||
void set_irq_line(int irq, int state);
|
||||
|
||||
|
||||
enum pic8259_state_t
|
||||
enum class state_t : u8
|
||||
{
|
||||
STATE_ICW1,
|
||||
STATE_ICW2,
|
||||
STATE_ICW3,
|
||||
STATE_ICW4,
|
||||
STATE_READY
|
||||
ICW1,
|
||||
ICW2,
|
||||
ICW3,
|
||||
ICW4,
|
||||
READY
|
||||
};
|
||||
|
||||
devcb_write_line m_out_int_func;
|
||||
devcb_read_line m_sp_en_func;
|
||||
devcb_read8 m_read_slave_ack_func;
|
||||
|
||||
pic8259_state_t m_state;
|
||||
state_t m_state;
|
||||
|
||||
uint8_t m_isr;
|
||||
uint8_t m_irr;
|
||||
|
||||
@ -106,7 +106,7 @@ void rtc9701_device::device_start()
|
||||
m_rtc.min = ((systime.local_time.minute / 10)<<4) | ((systime.local_time.minute % 10) & 0xf);
|
||||
m_rtc.sec = ((systime.local_time.second / 10)<<4) | ((systime.local_time.second % 10) & 0xf);
|
||||
|
||||
rtc_state = RTC9701_CMD_WAIT;
|
||||
rtc_state = state_t::CMD_WAIT;
|
||||
cmd_stream_pos = 0;
|
||||
current_cmd = 0;
|
||||
|
||||
@ -228,13 +228,13 @@ WRITE_LINE_MEMBER( rtc9701_device::write_bit )
|
||||
|
||||
READ_LINE_MEMBER( rtc9701_device::read_bit )
|
||||
{
|
||||
if (rtc_state == RTC9701_RTC_READ)
|
||||
if (rtc_state == state_t::RTC_READ)
|
||||
{
|
||||
//printf("RTC data bits left c9701_data_pos %02x\n", rtc9701_data_pos);
|
||||
return ((rtc9701_current_data) >> (rtc9701_data_pos-1))&1;
|
||||
|
||||
}
|
||||
else if (rtc_state == RTC9701_EEPROM_READ)
|
||||
else if (rtc_state == state_t::EEPROM_READ)
|
||||
{
|
||||
//printf("EEPROM data bits left c9701_data_pos %02x\n", rtc9701_data_pos);
|
||||
return ((rtc9701_current_data) >> (rtc9701_data_pos-1))&1;
|
||||
@ -258,7 +258,7 @@ WRITE_LINE_MEMBER( rtc9701_device::set_cs_line )
|
||||
|
||||
if (m_reset_line != CLEAR_LINE)
|
||||
{
|
||||
rtc_state = RTC9701_CMD_WAIT;
|
||||
rtc_state = state_t::CMD_WAIT;
|
||||
cmd_stream_pos = 0;
|
||||
current_cmd = 0;
|
||||
rtc9701_address_pos = 0;
|
||||
@ -283,7 +283,7 @@ WRITE_LINE_MEMBER( rtc9701_device::set_clock_line )
|
||||
|
||||
switch (rtc_state)
|
||||
{
|
||||
case RTC9701_CMD_WAIT:
|
||||
case state_t::CMD_WAIT:
|
||||
|
||||
//logerror("xx\n");
|
||||
current_cmd = (current_cmd << 1) | (m_latch&1);
|
||||
@ -297,7 +297,7 @@ WRITE_LINE_MEMBER( rtc9701_device::set_clock_line )
|
||||
if (current_cmd==0x00) /* 0000 */
|
||||
{
|
||||
//logerror("WRITE RTC MODE\n");
|
||||
rtc_state = RTC9701_RTC_WRITE;
|
||||
rtc_state = state_t::RTC_WRITE;
|
||||
cmd_stream_pos = 0;
|
||||
rtc9701_address_pos = 0;
|
||||
rtc9701_current_address = 0;
|
||||
@ -307,7 +307,7 @@ WRITE_LINE_MEMBER( rtc9701_device::set_clock_line )
|
||||
else if (current_cmd==0x02) /* 0010 */
|
||||
{
|
||||
//logerror("WRITE EEPROM MODE\n");
|
||||
rtc_state = RTC9701_EEPROM_WRITE;
|
||||
rtc_state = state_t::EEPROM_WRITE;
|
||||
cmd_stream_pos = 0;
|
||||
rtc9701_address_pos = 0;
|
||||
rtc9701_current_address = 0;
|
||||
@ -318,13 +318,13 @@ WRITE_LINE_MEMBER( rtc9701_device::set_clock_line )
|
||||
else if (current_cmd==0x06) /* 0110 */
|
||||
{
|
||||
//logerror("WRITE ENABLE\n");
|
||||
rtc_state = RTC9701_AFTER_WRITE_ENABLE;
|
||||
rtc_state = state_t::AFTER_WRITE_ENABLE;
|
||||
cmd_stream_pos = 0;
|
||||
}
|
||||
else if (current_cmd==0x08) /* 1000 */
|
||||
{
|
||||
//logerror("READ RTC MODE\n");
|
||||
rtc_state = RTC9701_RTC_READ;
|
||||
rtc_state = state_t::RTC_READ;
|
||||
cmd_stream_pos = 0;
|
||||
rtc9701_address_pos = 0;
|
||||
rtc9701_current_address = 0;
|
||||
@ -334,7 +334,7 @@ WRITE_LINE_MEMBER( rtc9701_device::set_clock_line )
|
||||
else if (current_cmd==0x0a) /* 1010 */
|
||||
{
|
||||
//logerror("READ EEPROM MODE\n");
|
||||
rtc_state = RTC9701_EEPROM_READ;
|
||||
rtc_state = state_t::EEPROM_READ;
|
||||
cmd_stream_pos = 0;
|
||||
rtc9701_address_pos = 0;
|
||||
rtc9701_current_address = 0;
|
||||
@ -352,17 +352,17 @@ WRITE_LINE_MEMBER( rtc9701_device::set_clock_line )
|
||||
}
|
||||
break;
|
||||
|
||||
case RTC9701_AFTER_WRITE_ENABLE:
|
||||
case state_t::AFTER_WRITE_ENABLE:
|
||||
cmd_stream_pos++;
|
||||
if (cmd_stream_pos==12)
|
||||
{
|
||||
cmd_stream_pos = 0;
|
||||
//logerror("Written 12 bits, going back to WAIT mode\n");
|
||||
rtc_state = RTC9701_CMD_WAIT;
|
||||
rtc_state = state_t::CMD_WAIT;
|
||||
}
|
||||
break;
|
||||
|
||||
case RTC9701_RTC_WRITE:
|
||||
case state_t::RTC_WRITE:
|
||||
cmd_stream_pos++;
|
||||
if (cmd_stream_pos<=4)
|
||||
{
|
||||
@ -385,13 +385,13 @@ WRITE_LINE_MEMBER( rtc9701_device::set_clock_line )
|
||||
cmd_stream_pos = 0;
|
||||
rtc_write(rtc9701_current_address,rtc9701_current_data);
|
||||
//logerror("Written 12 bits, going back to WAIT mode\n");
|
||||
rtc_state = RTC9701_CMD_WAIT;
|
||||
rtc_state = state_t::CMD_WAIT;
|
||||
}
|
||||
break;
|
||||
|
||||
|
||||
|
||||
case RTC9701_EEPROM_READ:
|
||||
case state_t::EEPROM_READ:
|
||||
cmd_stream_pos++;
|
||||
if (cmd_stream_pos<=12)
|
||||
{
|
||||
@ -416,13 +416,13 @@ WRITE_LINE_MEMBER( rtc9701_device::set_clock_line )
|
||||
{
|
||||
cmd_stream_pos = 0;
|
||||
// //logerror("accesed 28 bits, going back to WAIT mode\n");
|
||||
// rtc_state = RTC9701_CMD_WAIT;
|
||||
// rtc_state = state_t::CMD_WAIT;
|
||||
}
|
||||
break;
|
||||
|
||||
|
||||
|
||||
case RTC9701_EEPROM_WRITE:
|
||||
case state_t::EEPROM_WRITE:
|
||||
cmd_stream_pos++;
|
||||
|
||||
if (cmd_stream_pos<=12)
|
||||
@ -446,11 +446,11 @@ WRITE_LINE_MEMBER( rtc9701_device::set_clock_line )
|
||||
cmd_stream_pos = 0;
|
||||
//printf("written 28 bits - writing data %04x to %04x and going back to WAIT mode\n", rtc9701_current_data, (rtc9701_current_address>>1)&0xff);
|
||||
rtc9701_data[(rtc9701_current_address>>1)&0xff] = rtc9701_current_data;
|
||||
rtc_state = RTC9701_CMD_WAIT;
|
||||
rtc_state = state_t::CMD_WAIT;
|
||||
}
|
||||
break;
|
||||
|
||||
case RTC9701_RTC_READ:
|
||||
case state_t::RTC_READ:
|
||||
cmd_stream_pos++;
|
||||
if (cmd_stream_pos<=4)
|
||||
{
|
||||
@ -474,7 +474,7 @@ WRITE_LINE_MEMBER( rtc9701_device::set_clock_line )
|
||||
{
|
||||
cmd_stream_pos = 0;
|
||||
// //logerror("accessed 12 bits, going back to WAIT mode\n");
|
||||
// rtc_state = RTC9701_CMD_WAIT;
|
||||
// rtc_state = state_t::CMD_WAIT;
|
||||
}
|
||||
break;
|
||||
|
||||
|
||||
@ -45,14 +45,14 @@ public:
|
||||
TIMER_CALLBACK_MEMBER(timer_callback);
|
||||
|
||||
protected:
|
||||
enum state_t
|
||||
enum class state_t : u8
|
||||
{
|
||||
RTC9701_CMD_WAIT = 0,
|
||||
RTC9701_RTC_READ,
|
||||
RTC9701_RTC_WRITE,
|
||||
RTC9701_EEPROM_READ,
|
||||
RTC9701_EEPROM_WRITE,
|
||||
RTC9701_AFTER_WRITE_ENABLE
|
||||
CMD_WAIT = 0,
|
||||
RTC_READ,
|
||||
RTC_WRITE,
|
||||
EEPROM_READ,
|
||||
EEPROM_WRITE,
|
||||
AFTER_WRITE_ENABLE
|
||||
|
||||
};
|
||||
|
||||
|
||||
@ -139,7 +139,7 @@ void serflash_device::flash_hard_reset()
|
||||
{
|
||||
// logerror("%08x FLASH: RESET\n", cpuexec_describe_context(machine));
|
||||
|
||||
m_flash_state = STATE_READ;
|
||||
m_flash_state = flash_state_t::READ;
|
||||
|
||||
m_flash_cmd_prev = -1;
|
||||
m_flash_cmd_seq = 0;
|
||||
@ -196,7 +196,7 @@ WRITE8_MEMBER( serflash_device::flash_cmd_w )
|
||||
break;
|
||||
|
||||
case 0x70: // READ STATUS
|
||||
flash_change_state( STATE_READ_STATUS );
|
||||
flash_change_state( flash_state_t::READ_STATUS );
|
||||
break;
|
||||
|
||||
case 0x80: // PAGE / CACHE PROGRAM
|
||||
@ -206,11 +206,11 @@ WRITE8_MEMBER( serflash_device::flash_cmd_w )
|
||||
break;
|
||||
|
||||
case 0x90: // READ ID
|
||||
flash_change_state( STATE_READ_ID );
|
||||
flash_change_state( flash_state_t::READ_ID );
|
||||
break;
|
||||
|
||||
case 0xff: // RESET
|
||||
flash_change_state( STATE_IDLE );
|
||||
flash_change_state( flash_state_t::IDLE );
|
||||
break;
|
||||
|
||||
default:
|
||||
@ -230,7 +230,7 @@ WRITE8_MEMBER( serflash_device::flash_cmd_w )
|
||||
m_flash_page_addr = m_flash_col;
|
||||
m_flash_page_index = m_flash_row;
|
||||
|
||||
flash_change_state( STATE_READ );
|
||||
flash_change_state( flash_state_t::READ );
|
||||
|
||||
//logerror("%08x FLASH: caching page = %04X\n", m_maincpu->pc(), m_flash_row);
|
||||
}
|
||||
@ -239,7 +239,7 @@ WRITE8_MEMBER( serflash_device::flash_cmd_w )
|
||||
case 0x60: // BLOCK ERASE
|
||||
if (data==0xd0)
|
||||
{
|
||||
flash_change_state( STATE_BLOCK_ERASE );
|
||||
flash_change_state( flash_state_t::BLOCK_ERASE );
|
||||
m_flashwritemap[m_flash_col] |= 1;
|
||||
memset(m_region + m_flash_col * FLASH_PAGE_SIZE, 0xff, FLASH_PAGE_SIZE);
|
||||
//logerror("erased block %04x (%08x - %08x)\n", m_flash_col, m_flash_col * FLASH_PAGE_SIZE, ((m_flash_col+1) * FLASH_PAGE_SIZE)-1);
|
||||
@ -252,7 +252,7 @@ WRITE8_MEMBER( serflash_device::flash_cmd_w )
|
||||
case 0x80:
|
||||
if (data==0x10)
|
||||
{
|
||||
flash_change_state( STATE_PAGE_PROGRAM );
|
||||
flash_change_state( flash_state_t::PAGE_PROGRAM );
|
||||
m_flashwritemap[m_flash_row] |= (memcmp(m_region + m_flash_row * FLASH_PAGE_SIZE, m_flash_page_data, FLASH_PAGE_SIZE) != 0);
|
||||
memcpy(m_region + m_flash_row * FLASH_PAGE_SIZE, m_flash_page_data, FLASH_PAGE_SIZE);
|
||||
//logerror("re-written block %04x (%08x - %08x)\n", m_flash_row, m_flash_row * FLASH_PAGE_SIZE, ((m_flash_row+1) * FLASH_PAGE_SIZE)-1);
|
||||
@ -318,7 +318,7 @@ READ8_MEMBER( serflash_device::flash_io_r )
|
||||
|
||||
switch (m_flash_state)
|
||||
{
|
||||
case STATE_READ_ID:
|
||||
case flash_state_t::READ_ID:
|
||||
//old = m_flash_read_seq;
|
||||
|
||||
switch( m_flash_read_seq++ )
|
||||
@ -341,7 +341,7 @@ READ8_MEMBER( serflash_device::flash_io_r )
|
||||
//logerror("%08x FLASH: read %02X from id(%02X)\n", m_maincpu->pc(), data, old);
|
||||
break;
|
||||
|
||||
case STATE_READ:
|
||||
case flash_state_t::READ:
|
||||
if (m_flash_page_addr > FLASH_PAGE_SIZE-1)
|
||||
m_flash_page_addr = FLASH_PAGE_SIZE-1;
|
||||
|
||||
@ -352,7 +352,7 @@ READ8_MEMBER( serflash_device::flash_io_r )
|
||||
//logerror("%08x FLASH: read data %02X from addr %03X (page %04X)\n", m_maincpu->pc(), data, old, m_flash_page_index);
|
||||
break;
|
||||
|
||||
case STATE_READ_STATUS:
|
||||
case flash_state_t::READ_STATUS:
|
||||
// bit 7 = writeable, bit 6 = ready, bit 5 = ready/true ready, bit 1 = fail(N-1), bit 0 = fail
|
||||
data = 0xe0;
|
||||
//logerror("%08x FLASH: read status %02X\n", m_maincpu->pc(), data);
|
||||
|
||||
@ -48,7 +48,7 @@ public:
|
||||
protected:
|
||||
static constexpr unsigned FLASH_PAGE_SIZE = 2048+64;
|
||||
|
||||
enum flash_state_t { STATE_IDLE = 0, STATE_READ, STATE_READ_ID, STATE_READ_STATUS, STATE_BLOCK_ERASE, STATE_PAGE_PROGRAM };
|
||||
enum class flash_state_t : u8 { IDLE = 0, READ, READ_ID, READ_STATUS, BLOCK_ERASE, PAGE_PROGRAM };
|
||||
|
||||
// device-level overrides
|
||||
virtual void device_start() override;
|
||||
|
||||
@ -173,7 +173,7 @@ void mea8000_device::device_start()
|
||||
|
||||
int mea8000_device::accept_byte()
|
||||
{
|
||||
return m_state == MEA8000_STOPPED || m_state == MEA8000_WAIT_FIRST || (m_state == MEA8000_STARTED && m_bufpos < 4);
|
||||
return m_state == mea8000_state::STOPPED || m_state == mea8000_state::WAIT_FIRST || (m_state == mea8000_state::STARTED && m_bufpos < 4);
|
||||
}
|
||||
|
||||
void mea8000_device::update_req()
|
||||
@ -415,7 +415,7 @@ void mea8000_device::stop_frame()
|
||||
{
|
||||
/* enter stop mode */
|
||||
m_timer->reset();
|
||||
m_state = MEA8000_STOPPED;
|
||||
m_state = mea8000_state::STOPPED;
|
||||
m_stream->update();
|
||||
m_output = 0;
|
||||
}
|
||||
@ -470,14 +470,14 @@ TIMER_CALLBACK_MEMBER( mea8000_device::timer_expire )
|
||||
start_frame();
|
||||
}
|
||||
/* slow stop */
|
||||
else if (m_state == MEA8000_STARTED)
|
||||
else if (m_state == mea8000_state::STARTED)
|
||||
{
|
||||
m_ampl = 0;
|
||||
LOG("%f mea8000_timer_expire: fade frame\n", machine().time().as_double());
|
||||
start_frame();
|
||||
m_state = MEA8000_SLOWING;
|
||||
m_state = mea8000_state::SLOWING;
|
||||
}
|
||||
else if (m_state == MEA8000_SLOWING)
|
||||
else if (m_state == mea8000_state::SLOWING)
|
||||
{
|
||||
LOG("%f mea8000_timer_expire: stop frame\n", machine().time().as_double());
|
||||
stop_frame();
|
||||
@ -518,12 +518,12 @@ WRITE8_MEMBER( mea8000_device::write )
|
||||
switch (offset)
|
||||
{
|
||||
case 0: /* data register */
|
||||
if (m_state == MEA8000_STOPPED)
|
||||
if (m_state == mea8000_state::STOPPED)
|
||||
{
|
||||
/* got pitch byte before first frame */
|
||||
m_pitch = 2 * data;
|
||||
LOG("%s %f: mea8000_w pitch %i\n", machine().describe_context(), machine().time().as_double(), m_pitch);
|
||||
m_state = MEA8000_WAIT_FIRST;
|
||||
m_state = mea8000_state::WAIT_FIRST;
|
||||
m_bufpos = 0;
|
||||
}
|
||||
else if (m_bufpos == 4)
|
||||
@ -538,7 +538,7 @@ WRITE8_MEMBER( mea8000_device::write )
|
||||
data, m_bufpos);
|
||||
m_buf[m_bufpos] = data;
|
||||
m_bufpos++;
|
||||
if (m_bufpos == 4 && m_state == MEA8000_WAIT_FIRST)
|
||||
if (m_bufpos == 4 && m_state == mea8000_state::WAIT_FIRST)
|
||||
{
|
||||
/* fade-in first frame */
|
||||
int old_pitch = m_pitch;
|
||||
@ -548,7 +548,7 @@ WRITE8_MEMBER( mea8000_device::write )
|
||||
m_last_pitch = old_pitch;
|
||||
m_ampl = 0;
|
||||
start_frame();
|
||||
m_state = MEA8000_STARTED;
|
||||
m_state = mea8000_state::STARTED;
|
||||
}
|
||||
}
|
||||
update_req();
|
||||
|
||||
@ -43,12 +43,12 @@ private:
|
||||
static constexpr unsigned NOISE_LEN = 8192;
|
||||
|
||||
/* finite machine state controlling frames */
|
||||
enum mea8000_state
|
||||
enum class mea8000_state : u8
|
||||
{
|
||||
MEA8000_STOPPED, /* nothing to do, timer disabled */
|
||||
MEA8000_WAIT_FIRST, /* received pitch, wait for first full trame, timer disabled */
|
||||
MEA8000_STARTED, /* playing a frame, timer on */
|
||||
MEA8000_SLOWING /* repeating last frame with decreasing amplitude, timer on */
|
||||
STOPPED, /* nothing to do, timer disabled */
|
||||
WAIT_FIRST, /* received pitch, wait for first full trame, timer disabled */
|
||||
STARTED, /* playing a frame, timer on */
|
||||
SLOWING /* repeating last frame with decreasing amplitude, timer on */
|
||||
};
|
||||
|
||||
struct filter_t
|
||||
|
||||
@ -95,19 +95,19 @@ int32_t multipcm_device::envelope_generator_update(slot_t *slot)
|
||||
{
|
||||
switch(slot->m_envelope_gen.m_state)
|
||||
{
|
||||
case ATTACK:
|
||||
case state_t::ATTACK:
|
||||
slot->m_envelope_gen.m_volume += slot->m_envelope_gen.m_attack_rate;
|
||||
if (slot->m_envelope_gen.m_volume >= (0x3ff << EG_SHIFT))
|
||||
{
|
||||
slot->m_envelope_gen.m_state = DECAY1;
|
||||
slot->m_envelope_gen.m_state = state_t::DECAY1;
|
||||
if (slot->m_envelope_gen.m_decay1_rate >= (0x400 << EG_SHIFT)) //Skip DECAY1, go directly to DECAY2
|
||||
{
|
||||
slot->m_envelope_gen.m_state = DECAY2;
|
||||
slot->m_envelope_gen.m_state = state_t::DECAY2;
|
||||
}
|
||||
slot->m_envelope_gen.m_volume = 0x3ff << EG_SHIFT;
|
||||
}
|
||||
break;
|
||||
case DECAY1:
|
||||
case state_t::DECAY1:
|
||||
slot->m_envelope_gen.m_volume -= slot->m_envelope_gen.m_decay1_rate;
|
||||
if (slot->m_envelope_gen.m_volume <= 0)
|
||||
{
|
||||
@ -115,17 +115,17 @@ int32_t multipcm_device::envelope_generator_update(slot_t *slot)
|
||||
}
|
||||
if (slot->m_envelope_gen.m_volume >> EG_SHIFT <= (slot->m_envelope_gen.m_decay_level << 6))
|
||||
{
|
||||
slot->m_envelope_gen.m_state = DECAY2;
|
||||
slot->m_envelope_gen.m_state = state_t::DECAY2;
|
||||
}
|
||||
break;
|
||||
case DECAY2:
|
||||
case state_t::DECAY2:
|
||||
slot->m_envelope_gen.m_volume -= slot->m_envelope_gen.m_decay2_rate;
|
||||
if (slot->m_envelope_gen.m_volume <= 0)
|
||||
{
|
||||
slot->m_envelope_gen.m_volume = 0;
|
||||
}
|
||||
break;
|
||||
case RELEASE:
|
||||
case state_t::RELEASE:
|
||||
slot->m_envelope_gen.m_volume -= slot->m_envelope_gen.m_release_rate;
|
||||
if (slot->m_envelope_gen.m_volume <= 0)
|
||||
{
|
||||
@ -367,7 +367,7 @@ void multipcm_device::write_slot(slot_t *slot, int32_t reg, uint8_t data)
|
||||
slot->m_total_level = slot->m_dest_total_level << TL_SHIFT;
|
||||
|
||||
envelope_generator_calc(slot);
|
||||
slot->m_envelope_gen.m_state = ATTACK;
|
||||
slot->m_envelope_gen.m_state = state_t::ATTACK;
|
||||
slot->m_envelope_gen.m_volume = 0;
|
||||
|
||||
if (slot->m_base >= 0x100000)
|
||||
@ -389,7 +389,7 @@ void multipcm_device::write_slot(slot_t *slot, int32_t reg, uint8_t data)
|
||||
{
|
||||
if (slot->m_sample.m_release_reg != 0xf)
|
||||
{
|
||||
slot->m_envelope_gen.m_state = RELEASE;
|
||||
slot->m_envelope_gen.m_state = state_t::RELEASE;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
||||
@ -43,7 +43,7 @@ private:
|
||||
uint8_t m_lfo_amplitude_reg;
|
||||
};
|
||||
|
||||
enum state_t
|
||||
enum class state_t : u8
|
||||
{
|
||||
ATTACK,
|
||||
DECAY1,
|
||||
|
||||
@ -326,7 +326,7 @@ WRITE_LINE_MEMBER(s14001a_device::start_w)
|
||||
{
|
||||
m_stream->update();
|
||||
m_bStart = (state != 0);
|
||||
if (m_bStart) m_uStateP1 = WORDWAIT;
|
||||
if (m_bStart) m_uStateP1 = states::WORDWAIT;
|
||||
}
|
||||
|
||||
void s14001a_device::set_clock(uint32_t clock)
|
||||
@ -391,31 +391,31 @@ bool s14001a_device::Clock()
|
||||
// logic done during phase 1
|
||||
switch (m_uStateP1)
|
||||
{
|
||||
case IDLE:
|
||||
case states::IDLE:
|
||||
m_uOutputP1 = 7;
|
||||
if (m_bStart) m_uStateP1 = WORDWAIT;
|
||||
if (m_bStart) m_uStateP1 = states::WORDWAIT;
|
||||
|
||||
if (m_bBusyP1 && !m_bsy_handler.isnull())
|
||||
m_bsy_handler(0);
|
||||
m_bBusyP1 = false;
|
||||
break;
|
||||
|
||||
case WORDWAIT:
|
||||
case states::WORDWAIT:
|
||||
// the delta address register latches the word number into bits 03 to 08
|
||||
// all other bits forced to 0. 04 to 08 makes a multiply by two.
|
||||
m_uDAR13To05P1 = (m_uWord&0x3C)>>2;
|
||||
m_uDAR04To00P1 = (m_uWord&0x03)<<3;
|
||||
m_RomAddrP1 = (m_uDAR13To05P1<<3)|(m_uDAR04To00P1>>2); // remove lower two bits
|
||||
m_uOutputP1 = 7;
|
||||
if (m_bStart) m_uStateP1 = WORDWAIT;
|
||||
else m_uStateP1 = CWARMSB;
|
||||
if (m_bStart) m_uStateP1 = states::WORDWAIT;
|
||||
else m_uStateP1 = states::CWARMSB;
|
||||
|
||||
if (!m_bBusyP1 && !m_bsy_handler.isnull())
|
||||
m_bsy_handler(1);
|
||||
m_bBusyP1 = true;
|
||||
break;
|
||||
|
||||
case CWARMSB:
|
||||
case states::CWARMSB:
|
||||
if (m_uPrintLevel >= 1)
|
||||
printf("\n speaking word %02x",m_uWord);
|
||||
|
||||
@ -427,20 +427,20 @@ bool s14001a_device::Clock()
|
||||
m_RomAddrP1 = (m_uDAR13To05P1<<3)|(m_uDAR04To00P1>>2); // remove lower two bits
|
||||
|
||||
m_uOutputP1 = 7;
|
||||
if (m_bStart) m_uStateP1 = WORDWAIT;
|
||||
else m_uStateP1 = CWARLSB;
|
||||
if (m_bStart) m_uStateP1 = states::WORDWAIT;
|
||||
else m_uStateP1 = states::CWARLSB;
|
||||
break;
|
||||
|
||||
case CWARLSB:
|
||||
case states::CWARLSB:
|
||||
m_uCWARP1 = m_uCWARP2|(readmem(m_uRomAddrP2,m_bPhase1)>>4); // setup in previous state
|
||||
m_RomAddrP1 = m_uCWARP1;
|
||||
|
||||
m_uOutputP1 = 7;
|
||||
if (m_bStart) m_uStateP1 = WORDWAIT;
|
||||
else m_uStateP1 = DARMSB;
|
||||
if (m_bStart) m_uStateP1 = states::WORDWAIT;
|
||||
else m_uStateP1 = states::DARMSB;
|
||||
break;
|
||||
|
||||
case DARMSB:
|
||||
case states::DARMSB:
|
||||
m_uDAR13To05P1 = readmem(m_uRomAddrP2,m_bPhase1)<<1; // 9 bit counter, 8 MSBs from ROM, lsb zeroed
|
||||
m_uDAR04To00P1 = 0;
|
||||
m_uCWARP1++;
|
||||
@ -448,11 +448,11 @@ bool s14001a_device::Clock()
|
||||
m_uNControlWords++; // statistics
|
||||
|
||||
m_uOutputP1 = 7;
|
||||
if (m_bStart) m_uStateP1 = WORDWAIT;
|
||||
else m_uStateP1 = CTRLBITS;
|
||||
if (m_bStart) m_uStateP1 = states::WORDWAIT;
|
||||
else m_uStateP1 = states::CTRLBITS;
|
||||
break;
|
||||
|
||||
case CTRLBITS:
|
||||
case states::CTRLBITS:
|
||||
m_bStopP1 = readmem(m_uRomAddrP2,m_bPhase1)&0x80? true: false;
|
||||
m_bVoicedP1 = readmem(m_uRomAddrP2,m_bPhase1)&0x40? true: false;
|
||||
m_bSilenceP1 = readmem(m_uRomAddrP2,m_bPhase1)&0x20? true: false;
|
||||
@ -463,15 +463,15 @@ bool s14001a_device::Clock()
|
||||
m_RomAddrP1 = (m_uDAR13To05P1<<3)|(m_uDAR04To00P1>>2); // remove lower two bits
|
||||
|
||||
m_uOutputP1 = 7;
|
||||
if (m_bStart) m_uStateP1 = WORDWAIT;
|
||||
else m_uStateP1 = PLAY;
|
||||
if (m_bStart) m_uStateP1 = states::WORDWAIT;
|
||||
else m_uStateP1 = states::PLAY;
|
||||
|
||||
if (m_uPrintLevel >= 2)
|
||||
printf("\n cw %d %d %d %d %d",m_bStopP1,m_bVoicedP1,m_bSilenceP1,m_uLengthP1>>4,m_uXRepeatP1);
|
||||
|
||||
break;
|
||||
|
||||
case PLAY:
|
||||
case states::PLAY:
|
||||
{
|
||||
// statistics
|
||||
if (m_bPPQCarryP2)
|
||||
@ -549,21 +549,21 @@ bool s14001a_device::Clock()
|
||||
m_RomAddrP1 = (m_uDAR13To05P1<<3) | m_RomAddrP1>>2;
|
||||
|
||||
// next state
|
||||
if (m_bStart) m_uStateP1 = WORDWAIT;
|
||||
else if (m_bStopP2 && m_bLengthCarryP2) m_uStateP1 = DELAY;
|
||||
if (m_bStart) m_uStateP1 = states::WORDWAIT;
|
||||
else if (m_bStopP2 && m_bLengthCarryP2) m_uStateP1 = states::DELAY;
|
||||
else if (m_bLengthCarryP2)
|
||||
{
|
||||
m_uStateP1 = DARMSB;
|
||||
m_uStateP1 = states::DARMSB;
|
||||
m_RomAddrP1 = m_uCWARP1; // output correct address
|
||||
}
|
||||
else m_uStateP1 = PLAY;
|
||||
else m_uStateP1 = states::PLAY;
|
||||
break;
|
||||
}
|
||||
|
||||
case DELAY:
|
||||
case states::DELAY:
|
||||
m_uOutputP1 = 7;
|
||||
if (m_bStart) m_uStateP1 = WORDWAIT;
|
||||
else m_uStateP1 = IDLE;
|
||||
if (m_bStart) m_uStateP1 = states::WORDWAIT;
|
||||
else m_uStateP1 = states::IDLE;
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
@ -48,7 +48,7 @@ private:
|
||||
void GetStatistics(uint32_t &uNPitchPeriods, uint32_t &uNVoiced, uint32_t &uNControlWords);
|
||||
void SetPrintLevel(uint32_t uPrintLevel) { m_uPrintLevel = uPrintLevel; }
|
||||
|
||||
enum states
|
||||
enum class states : u8
|
||||
{
|
||||
IDLE = 0,
|
||||
WORDWAIT,
|
||||
|
||||
@ -79,8 +79,8 @@ enum {
|
||||
DVSSR = 0x13
|
||||
};
|
||||
|
||||
ALLOW_SAVE_TYPE(huc6270_device::huc6270_v_state);
|
||||
ALLOW_SAVE_TYPE(huc6270_device::huc6270_h_state);
|
||||
ALLOW_SAVE_TYPE(huc6270_device::v_state);
|
||||
ALLOW_SAVE_TYPE(huc6270_device::h_state);
|
||||
|
||||
|
||||
/* Bits in the VDC status register */
|
||||
@ -331,26 +331,26 @@ inline void huc6270_device::next_vert_state()
|
||||
{
|
||||
switch ( m_vert_state )
|
||||
{
|
||||
case HUC6270_VSW:
|
||||
m_vert_state = HUC6270_VDS;
|
||||
case v_state::VSW:
|
||||
m_vert_state = v_state::VDS;
|
||||
m_vert_to_go = ( ( m_vpr >> 8 ) & 0xFF ) + 2;
|
||||
break;
|
||||
|
||||
case HUC6270_VDS:
|
||||
m_vert_state = HUC6270_VDW;
|
||||
case v_state::VDS:
|
||||
m_vert_state = v_state::VDW;
|
||||
m_vert_to_go = ( m_vdw & 0x1FF ) + 1;
|
||||
m_byr_latched = m_byr;
|
||||
m_vd_triggered = 0;
|
||||
break;
|
||||
|
||||
case HUC6270_VDW:
|
||||
m_vert_state = HUC6270_VCR;
|
||||
case v_state::VDW:
|
||||
m_vert_state = v_state::VCR;
|
||||
m_vert_to_go = ( m_vcr & 0xFF );
|
||||
handle_vblank();
|
||||
break;
|
||||
|
||||
case HUC6270_VCR:
|
||||
m_vert_state = HUC6270_VSW;
|
||||
case v_state::VCR:
|
||||
m_vert_state = v_state::VSW;
|
||||
m_vert_to_go = ( m_vpr & 0x1F ) + 1;
|
||||
break;
|
||||
}
|
||||
@ -361,10 +361,10 @@ inline void huc6270_device::next_horz_state()
|
||||
{
|
||||
switch ( m_horz_state )
|
||||
{
|
||||
case HUC6270_HDS:
|
||||
case h_state::HDS:
|
||||
m_bxr_latched = m_bxr;
|
||||
//LOG("latched bxr vpos=%d, hpos=%d\n", video_screen_get_vpos(device->machine->first_screen()), video_screen_get_hpos(device->machine->first_screen()));
|
||||
m_horz_state = HUC6270_HDW;
|
||||
m_horz_state = h_state::HDW;
|
||||
m_horz_to_go = ( m_hdr & 0x7F ) + 1;
|
||||
{
|
||||
static const int width_shift[4] = { 5, 6, 7, 7 };
|
||||
@ -380,18 +380,18 @@ inline void huc6270_device::next_horz_state()
|
||||
}
|
||||
break;
|
||||
|
||||
case HUC6270_HDW:
|
||||
m_horz_state = HUC6270_HDE;
|
||||
case h_state::HDW:
|
||||
m_horz_state = h_state::HDE;
|
||||
m_horz_to_go = ( ( m_hdr >> 8 ) & 0x7F ) + 1;
|
||||
break;
|
||||
|
||||
case HUC6270_HDE:
|
||||
m_horz_state = HUC6270_HSW;
|
||||
case h_state::HDE:
|
||||
m_horz_state = h_state::HSW;
|
||||
m_horz_to_go = ( m_hsr & 0x1F ) + 1;
|
||||
break;
|
||||
|
||||
case HUC6270_HSW:
|
||||
m_horz_state = HUC6270_HDS;
|
||||
case h_state::HSW:
|
||||
m_horz_state = h_state::HDS;
|
||||
m_horz_to_go = std::max( ( ( m_hsr >> 8 ) & 0x7F ), 2 ) + 1;
|
||||
|
||||
/* If section has ended, advance to next vertical state */
|
||||
@ -411,10 +411,10 @@ READ16_MEMBER( huc6270_device::next_pixel )
|
||||
uint16_t data = HUC6270_SPRITE;
|
||||
|
||||
/* Check if we're on an active display line */
|
||||
if ( m_vert_state == HUC6270_VDW )
|
||||
if ( m_vert_state == v_state::VDW )
|
||||
{
|
||||
/* Check if we're in active display area */
|
||||
if ( m_horz_state == HUC6270_HDW )
|
||||
if ( m_horz_state == h_state::HDW )
|
||||
{
|
||||
uint8_t sprite_data = m_sprite_row[ m_sprite_row_index ] & 0x00FF;
|
||||
int collission = ( m_sprite_row[ m_sprite_row_index ] & 0x8000 ) ? 1 : 0;
|
||||
@ -489,7 +489,7 @@ WRITE_LINE_MEMBER( huc6270_device::vsync_changed )
|
||||
/* Check for low->high VSYNC transition */
|
||||
if ( state )
|
||||
{
|
||||
m_vert_state = HUC6270_VCR;
|
||||
m_vert_state = v_state::VCR;
|
||||
m_vert_to_go = 0;
|
||||
|
||||
while ( m_vert_to_go == 0 )
|
||||
@ -550,12 +550,12 @@ WRITE_LINE_MEMBER( huc6270_device::hsync_changed )
|
||||
}
|
||||
}
|
||||
|
||||
m_horz_state = HUC6270_HSW;
|
||||
m_horz_state = h_state::HSW;
|
||||
m_horz_to_go = 0;
|
||||
m_horz_steps = 0;
|
||||
m_byr_latched += 1;
|
||||
m_raster_count += 1;
|
||||
if ( m_vert_to_go == 1 && m_vert_state == HUC6270_VDS )
|
||||
if ( m_vert_to_go == 1 && m_vert_state == v_state::VDS )
|
||||
{
|
||||
m_raster_count = 0x40;
|
||||
}
|
||||
@ -881,10 +881,10 @@ void huc6270_device::device_reset()
|
||||
m_satb_countdown = 0;
|
||||
m_raster_count = 0x4000;
|
||||
m_vert_to_go = 0;
|
||||
m_vert_state = HUC6270_VSW;
|
||||
m_vert_state = v_state::VSW;
|
||||
m_horz_steps = 0;
|
||||
m_horz_to_go = 0;
|
||||
m_horz_state = HUC6270_HDS;
|
||||
m_horz_state = h_state::HDS;
|
||||
m_hsync = 0;
|
||||
m_vsync = 0;
|
||||
m_dma_enabled = 0;
|
||||
|
||||
@ -54,18 +54,18 @@ protected:
|
||||
inline void next_horz_state();
|
||||
|
||||
private:
|
||||
enum huc6270_v_state {
|
||||
HUC6270_VSW,
|
||||
HUC6270_VDS,
|
||||
HUC6270_VDW,
|
||||
HUC6270_VCR
|
||||
enum class v_state : u8 {
|
||||
VSW,
|
||||
VDS,
|
||||
VDW,
|
||||
VCR
|
||||
};
|
||||
|
||||
enum huc6270_h_state {
|
||||
HUC6270_HDS,
|
||||
HUC6270_HDW,
|
||||
HUC6270_HDE,
|
||||
HUC6270_HSW
|
||||
enum class h_state : u8 {
|
||||
HDS,
|
||||
HDW,
|
||||
HDE,
|
||||
HSW
|
||||
};
|
||||
|
||||
|
||||
@ -104,8 +104,8 @@ private:
|
||||
int m_vsync;
|
||||
|
||||
/* internal variables */
|
||||
huc6270_v_state m_vert_state;
|
||||
huc6270_h_state m_horz_state;
|
||||
v_state m_vert_state;
|
||||
h_state m_horz_state;
|
||||
int m_vd_triggered;
|
||||
int m_vert_to_go;
|
||||
int m_horz_to_go;
|
||||
|
||||
@ -80,7 +80,7 @@ protected:
|
||||
void interrupt_start_vblank(void);
|
||||
|
||||
private:
|
||||
enum dma_mode_tt { dma_read, dma_write };
|
||||
enum dma_mode_tt : u8 { dma_read, dma_write };
|
||||
|
||||
static constexpr uint8_t MODE_OFF = 0;
|
||||
static constexpr uint8_t MODE_TEXT = 1;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user