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https://github.com/holub/mame
synced 2025-04-20 23:42:22 +03:00
video/pc_vga_paradise.cpp: add basic extended GC interface
This commit is contained in:
angelosa
parent
3868cf5d69
commit
77cc71b932
@ -22,14 +22,22 @@ TODO:
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#include "screen.h"
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#define VERBOSE (LOG_GENERAL)
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#define LOG_BANK (1U << 2) // log banking r/ws
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#define LOG_LOCKED (1U << 8) // log locking mechanism
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#define VERBOSE (LOG_GENERAL | LOG_LOCKED)
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//#define LOG_OUTPUT_FUNC osd_printf_info
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#include "logmacro.h"
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#define LOGBANK(...) LOGMASKED(LOG_BANK, __VA_ARGS__)
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#define LOGLOCKED(...) LOGMASKED(LOG_LOCKED, __VA_ARGS__)
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DEFINE_DEVICE_TYPE(PVGA1A, pvga1a_vga_device, "pvga1a_vga", "Paradise Systems PVGA1A")
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pvga1a_vga_device::pvga1a_vga_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: svga_device(mconfig, PVGA1A, tag, owner, clock)
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, m_ext_view(*this, "ext_view")
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{
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m_gc_space_config = address_space_config("gc_regs", ENDIANNESS_LITTLE, 8, 8, 0, address_map_constructor(FUNC(pvga1a_vga_device::gc_map), this));
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}
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@ -51,12 +59,199 @@ void pvga1a_vga_device::device_reset()
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{
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svga_device::device_reset();
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// ...
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m_memory_size = 0;
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m_video_control = 0; // &= 0x8;
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m_video_select = 0;
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m_crtc_lock = 0;
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m_ext_unlock = false;
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m_ext_view.select(0);
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}
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uint8_t pvga1a_vga_device::mem_r(offs_t offset)
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{
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if (svga.rgb8_en)
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return svga_device::mem_linear_r(offset + (svga.bank_w * 0x1000));
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return svga_device::mem_r(offset);
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}
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void pvga1a_vga_device::mem_w(offs_t offset, uint8_t data)
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{
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// TODO: Address Offset B, not extensively tested
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if (svga.rgb8_en)
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{
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svga_device::mem_linear_w(offset + (svga.bank_w * 0x1000), data);
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return;
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}
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svga_device::mem_w(offset, data);
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}
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void pvga1a_vga_device::gc_map(address_map &map)
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{
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svga_device::gc_map(map);
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// TODO: temp hack so the card boots
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map(0x09, 0x0f).ram();
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map(0x09, 0x0e).view(m_ext_view);
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m_ext_view[0](0x09, 0x0e).lr8(
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NAME([this] (offs_t offset) {
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LOGLOCKED("Attempt to R ext. register offset %02x while locked\n", offset + 9);
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return 0;
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})
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);
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m_ext_view[1](0x09, 0x0a).rw(FUNC(pvga1a_vga_device::address_offset_r), FUNC(pvga1a_vga_device::address_offset_w));
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m_ext_view[1](0x0b, 0x0b).rw(FUNC(pvga1a_vga_device::memory_size_r), FUNC(pvga1a_vga_device::memory_size_w));
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m_ext_view[1](0x0c, 0x0c).rw(FUNC(pvga1a_vga_device::video_select_r), FUNC(pvga1a_vga_device::video_select_w));
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m_ext_view[1](0x0d, 0x0d).rw(FUNC(pvga1a_vga_device::crtc_lock_r), FUNC(pvga1a_vga_device::crtc_lock_w));
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m_ext_view[1](0x0e, 0x0e).rw(FUNC(pvga1a_vga_device::video_control_r), FUNC(pvga1a_vga_device::video_control_w));
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map(0x0f, 0x0f).rw(FUNC(pvga1a_vga_device::ext_status_r), FUNC(pvga1a_vga_device::ext_unlock_w));
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}
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/*
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* [0x09] PR0A Address Offset A
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* [0x0a] PR0B Address Offset B
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*
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* -xxx xxxx bank selects, in 4KB units
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*/
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u8 pvga1a_vga_device::address_offset_r(offs_t offset)
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{
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if (!offset)
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{
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LOGBANK("PR0A read Address Offset A\n");
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return svga.bank_w & 0x7f;
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}
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// Address Offset B, TBD
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LOGBANK("PR0A read Address Offset B\n");
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return 0;
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}
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void pvga1a_vga_device::address_offset_w(offs_t offset, u8 data)
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{
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if (!offset)
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{
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LOG("PR0A write Address Offset A %02x\n", data);
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svga.bank_w = data & 0x7f;
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}
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else
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{
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LOG("PR0B write Address Offset B %02x\n", data);
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// ...
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}
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}
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/*
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* [0x0b] PR1 Memory Size
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*
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* xx-- ---- Memory Size
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* 11-- ---- 1MB
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* 10-- ---- 512KB
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* 0x-- ---- 256KB
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* --xx ---- Memory Map Select
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* ---- x--- Enable PR0B
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* ---- -x-- Enable 16-bit memory bus
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* ---- --x- Enable 16-bit BIOS ROM reads (MD1)
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* ---- ---x BIOS ROM mapped (MD0)
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*/
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u8 pvga1a_vga_device::memory_size_r(offs_t offset)
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{
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LOG("PR1 Memory Size R\n");
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return 0xc0 | (m_memory_size & 0x3f);
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}
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void pvga1a_vga_device::memory_size_w(offs_t offset, u8 data)
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{
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LOG("PR1 Memory Size W %02x\n", data);
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m_memory_size = data;
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}
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// m_ext_view[1](0x0d, 0x0d) PR3 CRT Control [locks groups in CRTC]
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/*
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* [0x0c] PR2 Video Select
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*
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* x--- ---- M24 Mode Enable
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* -x-- ---- 6845 Compatiblity Mode
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* --x- -x-- Character Map Select
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* ---- -1-- \- also enables special underline effect (?)
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* ---x x--- Character Clock Period Control
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* ---0 0--- VGA 8/9 dots
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* ---0 1--- 7 dots
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* ---1 0--- 9 dots
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* ---1 1--- 10 dots
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* ---- --x- external clock select 3
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* ---- ---x Set horizontal sync timing (0) doubled?
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*/
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u8 pvga1a_vga_device::video_select_r(offs_t offset)
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{
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LOG("PR2 Video Select R\n");
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return m_video_select;
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}
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void pvga1a_vga_device::video_select_w(offs_t offset, u8 data)
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{
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LOG("PR2 Video Select W %02x\n", data);
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m_video_select = data;
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}
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/*
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* [0x0d] PR3 CRT Control [locks groups in CRTC]
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*
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* x--- ---- Lock VSYNC polarity
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* -x-- ---- Lock HSYNC polarity
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* --x- ---- Lock horizontal timing (group 0 & 4)
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* ---x ---- bit 9 of CRTC Start Memory Address
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* ---- x--- bit 8 of CRTC Start Memory Address
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* ---- -x-- CRT Control cursor start, cursor stop, preset row scan, maximum scan line x2 (??)
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* ---- --x- Lock vertical display enable end (group 1)
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* ---- ---x Lock vertical total/retrace (group 2 & 3)
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*/
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u8 pvga1a_vga_device::crtc_lock_r(offs_t offset)
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{
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LOG("PR3 CRTC lock R\n");
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return m_crtc_lock;
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}
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void pvga1a_vga_device::crtc_lock_w(offs_t offset, u8 data)
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{
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LOG("PR3 CRTC lock W\n", data);
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m_crtc_lock = data;
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}
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/*
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* [0x0e] PR4 Video Control
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*
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* x--- ---- BLNKN (0) enables external Video DAC
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* -x-- ---- Tristate HSYNC, VSYNC, BLNKN
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* --x- ---- Tristate VID7-VID0
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* ---x ---- Tristate Memory Control outputs
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* ---- x--- Disable CGA (unaffected by POR)
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* ---- -x-- Lock palette and overscan regs
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* ---- --x- Enable EGA compatible mode
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* ---- ---x Enable 640x400x8bpp
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*/
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u8 pvga1a_vga_device::video_control_r(offs_t offset)
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{
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LOG("PR4 Video Control R\n");
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return m_video_control;
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}
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void pvga1a_vga_device::video_control_w(offs_t offset, u8 data)
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{
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LOG("PR4 Video Control W %02x\n", data);
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m_video_control = data;
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svga.rgb8_en = BIT(data, 0);
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}
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/*
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* [0x0f] PR5 Lock/Status
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*
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* xxxx ---- MD7/MD4 config reads
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* ---- -xxx lock register
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* ---- -101 unlock, any other value locks r/w to the extensions
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*/
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u8 pvga1a_vga_device::ext_status_r(offs_t offset)
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{
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return m_ext_unlock ? 0x05 : 0x00;
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}
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void pvga1a_vga_device::ext_unlock_w(offs_t offset, u8 data)
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{
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m_ext_unlock = (data & 0x7) == 5;
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LOGLOCKED("PR5 %s state (%02x)\n", m_ext_unlock ? "unlock" : "lock", data);
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m_ext_view.select(m_ext_unlock);
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}
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@ -11,13 +11,37 @@
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class pvga1a_vga_device : public svga_device
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{
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public:
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static constexpr feature_type imperfect_features() { return feature::GRAPHICS; }
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pvga1a_vga_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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virtual uint8_t mem_r(offs_t offset) override;
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virtual void mem_w(offs_t offset, uint8_t data) override;
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protected:
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virtual void device_start() override;
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virtual void device_reset() override;
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virtual void gc_map(address_map &map) override;
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memory_view m_ext_view;
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private:
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u8 address_offset_r(offs_t offset);
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void address_offset_w(offs_t offset, u8 data);
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u8 memory_size_r(offs_t offset);
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void memory_size_w(offs_t offset, u8 data);
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u8 video_select_r(offs_t offset);
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void video_select_w(offs_t offset, u8 data);
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u8 crtc_lock_r(offs_t offset);
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void crtc_lock_w(offs_t offset, u8 data);
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u8 video_control_r(offs_t offset);
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void video_control_w(offs_t offset, u8 data);
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u8 ext_status_r(offs_t offset);
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void ext_unlock_w(offs_t offset, u8 data);
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u8 m_memory_size = 0;
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u8 m_video_control = 0;
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bool m_ext_unlock = false;
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u8 m_video_select = 0;
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u8 m_crtc_lock = 0;
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};
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DECLARE_DEVICE_TYPE(PVGA1A, pvga1a_vga_device)
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