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https://github.com/holub/mame
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mega32x.cpp: refactor and convert read/write handlers to 16-bit space [Angelo Salese]
This commit is contained in:
Angelo Salese
parent
8f197619a9
commit
78d20c4dad
2
.gitignore
vendored
2
.gitignore
vendored
@ -5,6 +5,8 @@
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*.pyc
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*.pyo
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*.rej
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*.L68
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*.S68
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.DS_Store
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/*
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@ -134,8 +134,8 @@ void sh2_device::sh7604_map(address_map &map)
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// map(0xe0000000, 0xe00001ff).mirror(0x1ffffe00).rw(FUNC(sh2_device::sh7604_r), FUNC(sh2_device::sh7604_w));
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// TODO: internal map takes way too much resources if mirrored with 0x1ffffe00
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// we eventually internalize again via trampoline & sh7604_device
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// additionally SH7604 doc mentions that there's a DRAM located at 0xffff8000,
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// so this is not a full mirror? (needs confirmation)
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// Also area 0xffff8000-0xffffbfff is for synchronous DRAM mode,
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// so this isn't actually a full mirror
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// SCI
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map(0xfffffe00, 0xfffffe00).rw(FUNC(sh2_device::smr_r), FUNC(sh2_device::smr_w));
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map(0xfffffe01, 0xfffffe01).rw(FUNC(sh2_device::brr_r), FUNC(sh2_device::brr_w));
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@ -729,6 +729,10 @@ WRITE32_MEMBER( sh2_device::vcrdiv_w )
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sh2_recalc_irq();
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}
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/*
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* DIVU
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*/
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READ32_MEMBER( sh2_device::dvcr_r )
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{
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return (m_divu_ovfie == true ? 2 : 0) | (m_divu_ovf == true ? 1 : 0);
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@ -744,16 +748,12 @@ WRITE32_MEMBER( sh2_device::dvcr_w )
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{
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m_divu_ovfie = bool(BIT(data, 1));
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if (m_divu_ovfie == true)
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LOG("SH2: unemulated DIVU OVF interrupt enable\n");
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logerror("SH2: unemulated DIVU OVF interrupt enable\n");
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}
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sh2_recalc_irq();
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}
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}
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/*
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* DMAC
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*/
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READ32_MEMBER( sh2_device::dvsr_r )
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{
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return m_dvsr;
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@ -583,19 +583,19 @@ DEVICE_IMAGE_LOAD_MEMBER( md_cons_state, _32x_cart )
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void md_cons_state::_32x_scanline_callback(int x, uint32_t priority, uint32_t &lineptr)
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{
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if (m_32x)
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m_32x->_32x_render_videobuffer_to_screenbuffer(x, priority, lineptr);
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m_32x->render_videobuffer_to_screenbuffer(x, priority, lineptr);
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}
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void md_cons_state::_32x_interrupt_callback(int scanline, int irq6)
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{
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if (m_32x)
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m_32x->_32x_interrupt_cb(scanline, irq6);
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m_32x->interrupt_cb(scanline, irq6);
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}
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void md_cons_state::_32x_scanline_helper_callback(int scanline)
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{
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if (m_32x)
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m_32x->_32x_render_videobuffer_to_screenbuffer_helper(scanline);
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m_32x->render_videobuffer_to_screenbuffer_helper(scanline);
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}
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MACHINE_CONFIG_START(md_cons_state::genesis_32x)
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@ -19,7 +19,6 @@
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- tmek: gameplay is clearly too fast
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- vrdxu: has 3d geometry bugs, caused by a SH-2 DRC bug;
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- vrdxu: crashes if you attempt to enter into main menu;
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- wwfraw: writes fb data to the cart area and expects it to be read back, kludging the cart area to be writeable makes the 32x gfxs to appear, why?
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- wwfwre: no 32x gfxs
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- xmen: black screen after that you choose the level, needs bare minimum SH-2 SCI support
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@ -246,22 +245,22 @@ sega_32x_pal_device::sega_32x_pal_device(const machine_config &mconfig, const ch
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{
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}
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READ16_MEMBER( sega_32x_device::_32x_68k_palette_r )
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READ16_MEMBER( sega_32x_device::m68k_palette_r )
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{
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return m_32x_palette[offset];
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}
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WRITE16_MEMBER( sega_32x_device::_32x_68k_palette_w )
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WRITE16_MEMBER( sega_32x_device::m68k_palette_w )
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{
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COMBINE_DATA(&m_32x_palette[offset]);
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}
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READ16_MEMBER( sega_32x_device::_32x_68k_dram_r )
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READ16_MEMBER( sega_32x_device::m68k_dram_r )
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{
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return m_32x_access_dram[offset];
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}
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WRITE16_MEMBER( sega_32x_device::_32x_68k_dram_w )
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WRITE16_MEMBER( sega_32x_device::m68k_dram_w )
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{
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if ((mem_mask&0xffff) == 0xffff)
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{
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@ -291,12 +290,12 @@ WRITE16_MEMBER( sega_32x_device::_32x_68k_dram_w )
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}
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}
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READ16_MEMBER( sega_32x_device::_32x_68k_dram_overwrite_r )
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READ16_MEMBER( sega_32x_device::m68k_dram_overwrite_r )
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{
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return m_32x_access_dram[offset];
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}
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WRITE16_MEMBER( sega_32x_device::_32x_68k_dram_overwrite_w )
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WRITE16_MEMBER( sega_32x_device::m68k_dram_overwrite_w )
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{
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//COMBINE_DATA(&m_32x_access_dram[offset+0x10000]);
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@ -341,7 +340,7 @@ WRITE16_MEMBER( sega_32x_device::_32x_68k_dram_overwrite_w )
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READ16_MEMBER( sega_32x_device::_32x_68k_a15106_r )
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READ16_MEMBER( sega_32x_device::m68k_a15106_r )
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{
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uint16_t retval;
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@ -352,7 +351,7 @@ READ16_MEMBER( sega_32x_device::_32x_68k_a15106_r )
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return retval;
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}
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WRITE16_MEMBER( sega_32x_device::_32x_68k_a15106_w )
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WRITE16_MEMBER( sega_32x_device::m68k_a15106_w )
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{
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if (ACCESSING_BITS_0_7)
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{
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@ -383,7 +382,7 @@ WRITE16_MEMBER( sega_32x_device::_32x_68k_a15106_w )
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m_fifo_block_b_full = 0;
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}
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//printf("_32x_68k_a15106_w %04x\n", data);
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//printf("m68k_a15106_w %04x\n", data);
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/*
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if (m_a15106_reg & 0x4)
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printf(" --- 68k Write Mode enabled\n");
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@ -401,7 +400,7 @@ WRITE16_MEMBER( sega_32x_device::_32x_68k_a15106_w )
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READ16_MEMBER( sega_32x_device::_32x_dreq_common_r )
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READ16_MEMBER( sega_32x_device::dreq_common_r )
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{
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address_space& _68kspace = m_main_cpu->space(AS_PROGRAM);
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@ -472,7 +471,7 @@ READ16_MEMBER( sega_32x_device::_32x_dreq_common_r )
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return 0x0000;
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}
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WRITE16_MEMBER( sega_32x_device::_32x_dreq_common_w )
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WRITE16_MEMBER( sega_32x_device::dreq_common_w )
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{
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address_space& _68kspace = m_main_cpu->space(AS_PROGRAM);
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@ -577,7 +576,6 @@ WRITE16_MEMBER( sega_32x_device::_32x_dreq_common_w )
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// incase we have a stalled DMA in progress, let the SH2 know there is data available
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m_master_cpu->sh2_notify_dma_data_available();
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m_slave_cpu->sh2_notify_dma_data_available();
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}
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m_current_fifo_write_pos = 0;
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@ -591,12 +589,12 @@ WRITE16_MEMBER( sega_32x_device::_32x_dreq_common_w )
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READ16_MEMBER( sega_32x_device::_32x_68k_a1511a_r )
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READ16_MEMBER( sega_32x_device::m68k_a1511a_r )
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{
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return m_sega_tv;
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}
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WRITE16_MEMBER( sega_32x_device::_32x_68k_a1511a_w )
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WRITE16_MEMBER( sega_32x_device::m68k_a1511a_w )
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{
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m_sega_tv = data & 1;
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@ -609,18 +607,18 @@ WRITE16_MEMBER( sega_32x_device::_32x_68k_a1511a_w )
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READ16_MEMBER( sega_32x_device::_32x_68k_m_hint_vector_r )
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READ16_MEMBER( sega_32x_device::m68k_m_hint_vector_r )
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{
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return m_hint_vector[offset];
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}
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WRITE16_MEMBER( sega_32x_device::_32x_68k_m_hint_vector_w )
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WRITE16_MEMBER( sega_32x_device::m68k_m_hint_vector_w )
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{
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m_hint_vector[offset] = data;
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}
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// returns MARS, the system ID of the 32x
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READ16_MEMBER( sega_32x_device::_32x_68k_MARS_r )
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READ16_MEMBER( sega_32x_device::m68k_MARS_r )
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{
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switch (offset)
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{
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@ -642,12 +640,12 @@ READ16_MEMBER( sega_32x_device::_32x_68k_MARS_r )
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READ16_MEMBER( sega_32x_device::_32x_68k_a15100_r )
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READ16_MEMBER( sega_32x_device::m68k_a15100_r )
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{
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return (m_32x_access_auth<<15) | 0x0080;
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}
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WRITE16_MEMBER( sega_32x_device::_32x_68k_a15100_w )
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WRITE16_MEMBER( sega_32x_device::m68k_a15100_w )
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{
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if (ACCESSING_BITS_0_7)
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{
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@ -670,21 +668,21 @@ WRITE16_MEMBER( sega_32x_device::_32x_68k_a15100_w )
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space.install_rom(0x0000000, 0x03fffff, machine().root_device().memregion("32x_68k_bios")->base());
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/* VDP area */
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space.install_readwrite_handler(0x0a15180, 0x0a1518b, read16_delegate(FUNC(sega_32x_device::_32x_common_vdp_regs_r), this), write16_delegate(FUNC(sega_32x_device::_32x_common_vdp_regs_w),this)); // common / shared VDP regs
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space.install_readwrite_handler(0x0a15200, 0x0a153ff, read16_delegate(FUNC(sega_32x_device::_32x_68k_palette_r), this), write16_delegate(FUNC(sega_32x_device::_32x_68k_palette_w),this)); // access to 'palette' xRRRRRGGGGGBBBBB
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space.install_readwrite_handler(0x0840000, 0x085ffff, read16_delegate(FUNC(sega_32x_device::_32x_68k_dram_r), this), write16_delegate(FUNC(sega_32x_device::_32x_68k_dram_w),this)); // access to 'display ram' (framebuffer)
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space.install_readwrite_handler(0x0860000, 0x087ffff, read16_delegate(FUNC(sega_32x_device::_32x_68k_dram_overwrite_r),this), write16_delegate(FUNC(sega_32x_device::_32x_68k_dram_overwrite_w),this)); // access to 'display ram' (framebuffer)
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space.install_readwrite_handler(0x0a15180, 0x0a1518b, read16_delegate(FUNC(sega_32x_device::common_vdp_regs_r), this), write16_delegate(FUNC(sega_32x_device::common_vdp_regs_w),this)); // common / shared VDP regs
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space.install_readwrite_handler(0x0a15200, 0x0a153ff, read16_delegate(FUNC(sega_32x_device::m68k_palette_r), this), write16_delegate(FUNC(sega_32x_device::m68k_palette_w),this)); // access to 'palette' xRRRRRGGGGGBBBBB
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space.install_readwrite_handler(0x0840000, 0x085ffff, read16_delegate(FUNC(sega_32x_device::m68k_dram_r), this), write16_delegate(FUNC(sega_32x_device::m68k_dram_w),this)); // access to 'display ram' (framebuffer)
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space.install_readwrite_handler(0x0860000, 0x087ffff, read16_delegate(FUNC(sega_32x_device::m68k_dram_overwrite_r),this), write16_delegate(FUNC(sega_32x_device::m68k_dram_overwrite_w),this)); // access to 'display ram' (framebuffer)
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m_main_cpu->space(AS_PROGRAM).install_readwrite_handler(0x000070, 0x000073, read16_delegate(FUNC(sega_32x_device::_32x_68k_m_hint_vector_r),this), write16_delegate(FUNC(sega_32x_device::_32x_68k_m_hint_vector_w),this)); // h interrupt vector
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m_main_cpu->space(AS_PROGRAM).install_readwrite_handler(0x000070, 0x000073, read16_delegate(FUNC(sega_32x_device::m68k_m_hint_vector_r),this), write16_delegate(FUNC(sega_32x_device::m68k_m_hint_vector_w),this)); // h interrupt vector
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}
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else
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{
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m_32x_adapter_enabled = 0;
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space.install_rom(0x0000000, 0x03fffff, machine().root_device().memregion("gamecart")->base());
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m_main_cpu->space(AS_PROGRAM).install_readwrite_handler(0x000070, 0x000073, read16_delegate(FUNC(sega_32x_device::_32x_68k_m_hint_vector_r),this), write16_delegate(FUNC(sega_32x_device::_32x_68k_m_hint_vector_w),this)); // h interrupt vector
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m_main_cpu->space(AS_PROGRAM).install_readwrite_handler(0x000070, 0x000073, read16_delegate(FUNC(sega_32x_device::m68k_m_hint_vector_r),this), write16_delegate(FUNC(sega_32x_device::m68k_m_hint_vector_w),this)); // h interrupt vector
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}
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}
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@ -702,13 +700,13 @@ WRITE16_MEMBER( sega_32x_device::_32x_68k_a15100_w )
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READ16_MEMBER( sega_32x_device::_32x_68k_a15102_r )
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READ16_MEMBER( sega_32x_device::m68k_a15102_r )
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{
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//printf("_32x_68k_a15102_r\n");
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return m_32x_68k_a15102_reg;
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}
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WRITE16_MEMBER( sega_32x_device::_32x_68k_a15102_w )
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WRITE16_MEMBER( sega_32x_device::m68k_a15102_w )
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{
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if (ACCESSING_BITS_0_7)
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{
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@ -734,12 +732,12 @@ WRITE16_MEMBER( sega_32x_device::_32x_68k_a15102_w )
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/**********************************************************************************************/
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READ16_MEMBER( sega_32x_device::_32x_68k_a15104_r )
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READ16_MEMBER( sega_32x_device::m68k_a15104_r )
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{
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return m_32x_68k_a15104_reg;
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}
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WRITE16_MEMBER( sega_32x_device::_32x_68k_a15104_w )
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WRITE16_MEMBER( sega_32x_device::m68k_a15104_w )
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{
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if (ACCESSING_BITS_0_7)
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{
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@ -764,14 +762,14 @@ WRITE16_MEMBER( sega_32x_device::_32x_68k_a15104_w )
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/**********************************************************************************************/
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// reads
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READ16_MEMBER( sega_32x_device::_32x_68k_m_commsram_r )
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READ16_MEMBER( sega_32x_device::m68k_m_commsram_r )
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{
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if (_32X_COMMS_PORT_SYNC) machine().scheduler().synchronize();
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return m_commsram[offset];
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}
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// writes
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WRITE16_MEMBER( sega_32x_device::_32x_68k_m_commsram_w )
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WRITE16_MEMBER( sega_32x_device::m68k_m_commsram_w )
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{
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COMBINE_DATA(&m_commsram[offset]);
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if (_32X_COMMS_PORT_SYNC) machine().scheduler().synchronize();
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@ -787,6 +785,7 @@ WRITE16_MEMBER( sega_32x_device::_32x_68k_m_commsram_w )
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TODO:
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- noticeable static noise on Virtua Fighter Sega logo at start-up
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- Understand if Speaker OFF makes the FIFO to advance or not
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- move inside a device
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*/
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@ -867,7 +866,7 @@ TIMER_CALLBACK_MEMBER(sega_32x_device::handle_pwm_callback)
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m_32x_pwm_timer->adjust(attotime::from_hz(clock() / (m_pwm_cycle - 1)));
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}
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READ16_MEMBER( sega_32x_device::_32x_pwm_r )
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READ16_MEMBER( sega_32x_device::pwm_r )
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{
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switch(offset)
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{
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@ -882,7 +881,7 @@ READ16_MEMBER( sega_32x_device::_32x_pwm_r )
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return 0xffff;
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}
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WRITE16_MEMBER( sega_32x_device::_32x_pwm_w )
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WRITE16_MEMBER( sega_32x_device::pwm_w )
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{
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switch(offset)
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{
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@ -927,12 +926,12 @@ WRITE16_MEMBER( sega_32x_device::_32x_pwm_w )
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}
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}
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WRITE16_MEMBER( sega_32x_device::_32x_68k_pwm_w )
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WRITE16_MEMBER( sega_32x_device::m68k_pwm_w )
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{
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if(offset == 0/2)
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_32x_pwm_w(space,offset,(data & 0x7f) | (m_pwm_ctrl & 0xff80),mem_mask);
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pwm_w(space,offset,(data & 0x7f) | (m_pwm_ctrl & 0xff80),mem_mask);
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else
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_32x_pwm_w(space,offset,data,mem_mask);
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pwm_w(space,offset,data,mem_mask);
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}
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/**********************************************************************************************/
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@ -960,7 +959,7 @@ uint16_t sega_32x_device::get_hposition(void)
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return value4;
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}
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READ16_MEMBER( sega_32x_device::_32x_common_vdp_regs_r )
|
||||
READ16_MEMBER( sega_32x_device::common_vdp_regs_r )
|
||||
{
|
||||
// what happens if the z80 accesses it, what authorization do we use?
|
||||
|
||||
@ -1016,7 +1015,7 @@ READ16_MEMBER( sega_32x_device::_32x_common_vdp_regs_r )
|
||||
}
|
||||
|
||||
|
||||
void sega_32x_device::_32x_check_framebuffer_swap(bool enabled)
|
||||
void sega_32x_device::check_framebuffer_swap(bool enabled)
|
||||
{
|
||||
// this logic should be correct, but makes things worse?
|
||||
// enabled = (genesis_scanline_counter >= megadrive_irq6_scanline) from video/315_5313.c
|
||||
@ -1024,8 +1023,6 @@ void sega_32x_device::_32x_check_framebuffer_swap(bool enabled)
|
||||
{
|
||||
m_32x_a1518a_reg = m_32x_fb_swap & 1;
|
||||
|
||||
|
||||
|
||||
if (m_32x_fb_swap & 1)
|
||||
{
|
||||
m_32x_access_dram = m_32x_dram0.get();
|
||||
@ -1040,7 +1037,7 @@ void sega_32x_device::_32x_check_framebuffer_swap(bool enabled)
|
||||
}
|
||||
|
||||
|
||||
WRITE16_MEMBER( sega_32x_device::_32x_common_vdp_regs_w )
|
||||
WRITE16_MEMBER( sega_32x_device::common_vdp_regs_w )
|
||||
{
|
||||
// what happens if the z80 accesses it, what authorization do we use? which address space do we get?? the z80 *can* write here and to the framebuffer via the window
|
||||
|
||||
@ -1134,7 +1131,7 @@ WRITE16_MEMBER( sega_32x_device::_32x_common_vdp_regs_w )
|
||||
{
|
||||
m_32x_fb_swap = data & 1;
|
||||
|
||||
_32x_check_framebuffer_swap(true);
|
||||
check_framebuffer_swap(true);
|
||||
}
|
||||
|
||||
break;
|
||||
@ -1169,7 +1166,7 @@ P = PWM Interrupt Mask (0 masked, 1 allowed)
|
||||
/**********************************************************************************************/
|
||||
|
||||
/* MASTER */
|
||||
READ16_MEMBER( sega_32x_device::_32x_sh2_master_4000_r )
|
||||
READ16_MEMBER( sega_32x_device::master_4000_r )
|
||||
{
|
||||
uint16_t retvalue = 0x0200;
|
||||
retvalue |= m_32x_access_auth << 15;
|
||||
@ -1183,7 +1180,7 @@ READ16_MEMBER( sega_32x_device::_32x_sh2_master_4000_r )
|
||||
return retvalue;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER( sega_32x_device::_32x_sh2_master_4000_w )
|
||||
WRITE16_MEMBER( sega_32x_device::master_4000_w )
|
||||
{
|
||||
if (ACCESSING_BITS_8_15)
|
||||
{
|
||||
@ -1201,13 +1198,13 @@ WRITE16_MEMBER( sega_32x_device::_32x_sh2_master_4000_w )
|
||||
//if (m_sh2_master_hint_enable) printf("m_sh2_master_hint_enable enable!\n");
|
||||
//if (sh2_master_pwmint_enable) printf("sh2_master_pwn_enable enable!\n");
|
||||
|
||||
_32x_check_irqs();
|
||||
check_irqs();
|
||||
}
|
||||
}
|
||||
|
||||
/* SLAVE */
|
||||
|
||||
READ16_MEMBER( sega_32x_device::_32x_sh2_slave_4000_r )
|
||||
READ16_MEMBER( sega_32x_device::slave_4000_r )
|
||||
{
|
||||
uint16_t retvalue = 0x0200;
|
||||
retvalue |= m_32x_access_auth << 15;
|
||||
@ -1221,7 +1218,7 @@ READ16_MEMBER( sega_32x_device::_32x_sh2_slave_4000_r )
|
||||
}
|
||||
|
||||
|
||||
WRITE16_MEMBER( sega_32x_device::_32x_sh2_slave_4000_w )
|
||||
WRITE16_MEMBER( sega_32x_device::slave_4000_w )
|
||||
{
|
||||
if (ACCESSING_BITS_8_15)
|
||||
{
|
||||
@ -1239,7 +1236,7 @@ WRITE16_MEMBER( sega_32x_device::_32x_sh2_slave_4000_w )
|
||||
//if (m_sh2_slave_hint_enable) printf("m_sh2_slave_hint_enable enable!\n");
|
||||
//if (sh2_slave_pwmint_enable) printf("sh2_slave_pwm_enable enable!\n");
|
||||
|
||||
_32x_check_irqs();
|
||||
check_irqs();
|
||||
}
|
||||
}
|
||||
|
||||
@ -1249,13 +1246,13 @@ WRITE16_MEMBER( sega_32x_device::_32x_sh2_slave_4000_w )
|
||||
// Shouldn't be used
|
||||
/**********************************************************************************************/
|
||||
|
||||
READ16_MEMBER( sega_32x_device::_32x_sh2_common_4002_r )
|
||||
READ16_MEMBER( sega_32x_device::common_4002_r )
|
||||
{
|
||||
printf("reading 4002!\n");
|
||||
return 0x0000;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER( sega_32x_device::_32x_sh2_common_4002_w )
|
||||
WRITE16_MEMBER( sega_32x_device::common_4002_w )
|
||||
{
|
||||
printf("write 4002!\n");
|
||||
}
|
||||
@ -1266,12 +1263,12 @@ WRITE16_MEMBER( sega_32x_device::_32x_sh2_common_4002_w )
|
||||
// H Count Register (H Interrupt)
|
||||
// 0 = every line
|
||||
/**********************************************************************************************/
|
||||
READ16_MEMBER( sega_32x_device::_32x_sh2_common_4004_r )
|
||||
READ16_MEMBER( sega_32x_device::common_4004_r )
|
||||
{
|
||||
return m_32x_hcount_reg;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER( sega_32x_device::_32x_sh2_common_4004_w )
|
||||
WRITE16_MEMBER( sega_32x_device::common_4004_w )
|
||||
{
|
||||
m_32x_hcount_reg = data & 0xff;
|
||||
}
|
||||
@ -1282,13 +1279,13 @@ WRITE16_MEMBER( sega_32x_device::_32x_sh2_common_4004_w )
|
||||
// DReq Control Register
|
||||
/**********************************************************************************************/
|
||||
|
||||
READ16_MEMBER( sega_32x_device::_32x_sh2_common_4006_r )
|
||||
READ16_MEMBER( sega_32x_device::common_4006_r )
|
||||
{
|
||||
//printf("DREQ read!\n"); // tempo reads it, shut up for now
|
||||
return _32x_68k_a15106_r(space,offset,mem_mask);
|
||||
return m68k_a15106_r(space,offset,mem_mask);
|
||||
}
|
||||
|
||||
WRITE16_MEMBER( sega_32x_device::_32x_sh2_common_4006_w )
|
||||
WRITE16_MEMBER( sega_32x_device::common_4006_w )
|
||||
{
|
||||
printf("DREQ write!\n"); //register is read only on SH-2 side
|
||||
}
|
||||
@ -1299,24 +1296,24 @@ WRITE16_MEMBER( sega_32x_device::_32x_sh2_common_4006_w )
|
||||
// VRES (md reset button interrupt) clear
|
||||
/**********************************************************************************************/
|
||||
|
||||
WRITE16_MEMBER( sega_32x_device::_32x_sh2_master_4014_w ){ m_master_cpu->set_input_line(SH2_VRES_IRQ_LEVEL,CLEAR_LINE);}
|
||||
WRITE16_MEMBER( sega_32x_device::_32x_sh2_slave_4014_w ) { m_slave_cpu->set_input_line(SH2_VRES_IRQ_LEVEL,CLEAR_LINE);}
|
||||
WRITE16_MEMBER( sega_32x_device::master_4014_w ){ m_master_cpu->set_input_line(SH2_VRES_IRQ_LEVEL,CLEAR_LINE);}
|
||||
WRITE16_MEMBER( sega_32x_device::slave_4014_w ) { m_slave_cpu->set_input_line(SH2_VRES_IRQ_LEVEL,CLEAR_LINE);}
|
||||
|
||||
/**********************************************************************************************/
|
||||
// SH2 side 4016
|
||||
// VINT (vertical interrupt) clear
|
||||
/**********************************************************************************************/
|
||||
|
||||
WRITE16_MEMBER( sega_32x_device::_32x_sh2_master_4016_w ){ m_sh2_master_vint_pending = 0; _32x_check_irqs(); }
|
||||
WRITE16_MEMBER( sega_32x_device::_32x_sh2_slave_4016_w ) { m_sh2_slave_vint_pending = 0; _32x_check_irqs(); }
|
||||
WRITE16_MEMBER( sega_32x_device::master_4016_w ){ m_sh2_master_vint_pending = 0; check_irqs(); }
|
||||
WRITE16_MEMBER( sega_32x_device::slave_4016_w ) { m_sh2_slave_vint_pending = 0; check_irqs(); }
|
||||
|
||||
/**********************************************************************************************/
|
||||
// SH2 side 4018
|
||||
// HINT (horizontal interrupt) clear
|
||||
/**********************************************************************************************/
|
||||
|
||||
WRITE16_MEMBER( sega_32x_device::_32x_sh2_master_4018_w ){ m_master_cpu->set_input_line(SH2_HINT_IRQ_LEVEL,CLEAR_LINE);}
|
||||
WRITE16_MEMBER( sega_32x_device::_32x_sh2_slave_4018_w ) { m_slave_cpu->set_input_line(SH2_HINT_IRQ_LEVEL,CLEAR_LINE);}
|
||||
WRITE16_MEMBER( sega_32x_device::master_4018_w ){ m_master_cpu->set_input_line(SH2_HINT_IRQ_LEVEL,CLEAR_LINE);}
|
||||
WRITE16_MEMBER( sega_32x_device::slave_4018_w ) { m_slave_cpu->set_input_line(SH2_HINT_IRQ_LEVEL,CLEAR_LINE);}
|
||||
|
||||
/**********************************************************************************************/
|
||||
// SH2 side 401A
|
||||
@ -1324,30 +1321,30 @@ WRITE16_MEMBER( sega_32x_device::_32x_sh2_slave_4018_w ) { m_slave_cpu->set_inpu
|
||||
// Note: flag cleared here is a guess, according to After Burner behaviour
|
||||
/**********************************************************************************************/
|
||||
|
||||
WRITE16_MEMBER( sega_32x_device::_32x_sh2_master_401a_w ){ m_32x_68k_a15102_reg &= ~1; m_master_cpu->set_input_line(SH2_CINT_IRQ_LEVEL,CLEAR_LINE);}
|
||||
WRITE16_MEMBER( sega_32x_device::_32x_sh2_slave_401a_w ) { m_32x_68k_a15102_reg &= ~2; m_slave_cpu->set_input_line(SH2_CINT_IRQ_LEVEL,CLEAR_LINE);}
|
||||
WRITE16_MEMBER( sega_32x_device::master_401a_w ){ m_32x_68k_a15102_reg &= ~1; m_master_cpu->set_input_line(SH2_CINT_IRQ_LEVEL,CLEAR_LINE);}
|
||||
WRITE16_MEMBER( sega_32x_device::slave_401a_w ) { m_32x_68k_a15102_reg &= ~2; m_slave_cpu->set_input_line(SH2_CINT_IRQ_LEVEL,CLEAR_LINE);}
|
||||
|
||||
/**********************************************************************************************/
|
||||
// SH2 side 401C
|
||||
// PINT (PWM timer interrupt) clear
|
||||
/**********************************************************************************************/
|
||||
|
||||
WRITE16_MEMBER( sega_32x_device::_32x_sh2_master_401c_w ){ m_master_cpu->set_input_line(SH2_PINT_IRQ_LEVEL,CLEAR_LINE);}
|
||||
WRITE16_MEMBER( sega_32x_device::_32x_sh2_slave_401c_w ) { m_slave_cpu->set_input_line(SH2_PINT_IRQ_LEVEL,CLEAR_LINE);}
|
||||
WRITE16_MEMBER( sega_32x_device::master_401c_w ){ m_master_cpu->set_input_line(SH2_PINT_IRQ_LEVEL,CLEAR_LINE);}
|
||||
WRITE16_MEMBER( sega_32x_device::slave_401c_w ) { m_slave_cpu->set_input_line(SH2_PINT_IRQ_LEVEL,CLEAR_LINE);}
|
||||
|
||||
/**********************************************************************************************/
|
||||
// SH2 side 401E
|
||||
// ?? unknown / unused
|
||||
/**********************************************************************************************/
|
||||
|
||||
WRITE16_MEMBER( sega_32x_device::_32x_sh2_master_401e_w )
|
||||
WRITE16_MEMBER( sega_32x_device::master_401e_w )
|
||||
{
|
||||
printf("_32x_sh2_master_401e_w\n");
|
||||
printf("master_401e_w\n");
|
||||
}
|
||||
|
||||
WRITE16_MEMBER( sega_32x_device::_32x_sh2_slave_401e_w )
|
||||
WRITE16_MEMBER( sega_32x_device::slave_401e_w )
|
||||
{
|
||||
printf("_32x_sh2_slave_401e_w\n");
|
||||
printf("slave_401e_w\n");
|
||||
}
|
||||
|
||||
/**********************************************************************************************/
|
||||
@ -1411,131 +1408,66 @@ WRITE16_MEMBER( sega_32x_device::_32x_sh2_slave_401e_w )
|
||||
|
||||
/* handled directly */
|
||||
|
||||
/**********************************************************************************************/
|
||||
// SH2 access Macros
|
||||
/**********************************************************************************************/
|
||||
|
||||
|
||||
/* the 32x treats everything as 16-bit registers, so we remap the 32-bit read & writes
|
||||
to 2x 16-bit handlers here (TODO: nuke this eventually) */
|
||||
|
||||
#define _32X_MAP_READHANDLERS(NAMEA,NAMEB) \
|
||||
READ32_MEMBER( sega_32x_device::_32x_sh2_##NAMEA##_##NAMEB##_r ) \
|
||||
{ \
|
||||
uint32_t retvalue = 0x00000000; \
|
||||
if (ACCESSING_BITS_16_31) \
|
||||
{ \
|
||||
uint16_t ret = _32x_sh2_##NAMEA##_r(space,0,(mem_mask>>16)&0xffff); \
|
||||
retvalue |= ret << 16; \
|
||||
} \
|
||||
if (ACCESSING_BITS_0_15) \
|
||||
{ \
|
||||
uint16_t ret = _32x_sh2_##NAMEB##_r(space,0,(mem_mask>>0)&0xffff); \
|
||||
retvalue |= ret << 0; \
|
||||
} \
|
||||
\
|
||||
return retvalue; \
|
||||
}
|
||||
#define _32X_MAP_WRITEHANDLERS(NAMEA,NAMEB) \
|
||||
WRITE32_MEMBER( sega_32x_device::_32x_sh2_##NAMEA##_##NAMEB##_w) \
|
||||
{ \
|
||||
if (ACCESSING_BITS_16_31) \
|
||||
{ \
|
||||
_32x_sh2_##NAMEA##_w(space,0,(data>>16)&0xffff,(mem_mask>>16)&0xffff); \
|
||||
} \
|
||||
if (ACCESSING_BITS_0_15) \
|
||||
{ \
|
||||
_32x_sh2_##NAMEB##_w(space,0,(data>>0)&0xffff,(mem_mask>>0)&0xffff); \
|
||||
} \
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**********************************************************************************************/
|
||||
// SH2 access for Memory Map
|
||||
/**********************************************************************************************/
|
||||
|
||||
_32X_MAP_READHANDLERS(master_4000,common_4002) // _32x_sh2_master_4000_common_4002_r
|
||||
_32X_MAP_WRITEHANDLERS(master_4000,common_4002) // _32x_sh2_master_4000_common_4002_w
|
||||
|
||||
_32X_MAP_READHANDLERS(slave_4000,common_4002) // _32x_sh2_slave_4000_common_4002_r
|
||||
_32X_MAP_WRITEHANDLERS(slave_4000,common_4002) // _32x_sh2_slave_4000_common_4002_w
|
||||
|
||||
_32X_MAP_READHANDLERS(common_4004,common_4006)
|
||||
_32X_MAP_WRITEHANDLERS(common_4004,common_4006)
|
||||
|
||||
_32X_MAP_WRITEHANDLERS(master_4014,master_4016) // _32x_sh2_master_4014_master_4016_w
|
||||
_32X_MAP_WRITEHANDLERS(master_4018,master_401a) // _32x_sh2_master_4018_master_401a_w
|
||||
_32X_MAP_WRITEHANDLERS(master_401c,master_401e) // _32x_sh2_master_401c_master_401e_w
|
||||
|
||||
_32X_MAP_WRITEHANDLERS(slave_4014,slave_4016) // _32x_sh2_slave_4014_slave_4016_w
|
||||
_32X_MAP_WRITEHANDLERS(slave_4018,slave_401a) // _32x_sh2_slave_4018_slave_401a_w
|
||||
_32X_MAP_WRITEHANDLERS(slave_401c,slave_401e) // _32x_sh2_slave_401c_slave_401e_w
|
||||
|
||||
|
||||
|
||||
/**********************************************************************************************/
|
||||
// SH2 memory maps
|
||||
/**********************************************************************************************/
|
||||
|
||||
void sega_32x_device::sh2_main_map(address_map &map)
|
||||
void sega_32x_device::sh2_common_map(address_map &map)
|
||||
{
|
||||
map(0x00000000, 0x00003fff).bankr("masterbios");
|
||||
map(0x00004002, 0x00004003).rw(FUNC(sega_32x_device::common_4002_r), FUNC(sega_32x_device::common_4002_w));
|
||||
map(0x00004004, 0x00004005).rw(FUNC(sega_32x_device::common_4004_r), FUNC(sega_32x_device::common_4004_w));
|
||||
map(0x00004006, 0x00004007).rw(FUNC(sega_32x_device::common_4006_r), FUNC(sega_32x_device::common_4006_w));
|
||||
|
||||
map(0x00004000, 0x00004003).rw(FUNC(sega_32x_device::_32x_sh2_master_4000_common_4002_r), FUNC(sega_32x_device::_32x_sh2_master_4000_common_4002_w));
|
||||
map(0x00004004, 0x00004007).rw(FUNC(sega_32x_device::_32x_sh2_common_4004_common_4006_r), FUNC(sega_32x_device::_32x_sh2_common_4004_common_4006_w));
|
||||
map(0x00004008, 0x00004013).rw(FUNC(sega_32x_device::dreq_common_r), FUNC(sega_32x_device::dreq_common_w));
|
||||
|
||||
map(0x00004008, 0x00004013).rw(FUNC(sega_32x_device::_32x_dreq_common_r), FUNC(sega_32x_device::_32x_dreq_common_w));
|
||||
map(0x00004014, 0x0000401f).nopr();
|
||||
|
||||
map(0x00004014, 0x00004017).nopr().w(FUNC(sega_32x_device::_32x_sh2_master_4014_master_4016_w)); // IRQ clear
|
||||
map(0x00004018, 0x0000401b).nopr().w(FUNC(sega_32x_device::_32x_sh2_master_4018_master_401a_w)); // IRQ clear
|
||||
map(0x0000401c, 0x0000401f).nopr().w(FUNC(sega_32x_device::_32x_sh2_master_401c_master_401e_w)); // IRQ clear
|
||||
map(0x00004020, 0x0000402f).rw(FUNC(sega_32x_device::m68k_m_commsram_r), FUNC(sega_32x_device::m68k_m_commsram_w));
|
||||
map(0x00004030, 0x0000403f).rw(FUNC(sega_32x_device::pwm_r), FUNC(sega_32x_device::pwm_w));
|
||||
|
||||
map(0x00004020, 0x0000402f).rw(FUNC(sega_32x_device::_32x_68k_m_commsram_r), FUNC(sega_32x_device::_32x_68k_m_commsram_w));
|
||||
map(0x00004030, 0x0000403f).rw(FUNC(sega_32x_device::_32x_pwm_r), FUNC(sega_32x_device::_32x_pwm_w));
|
||||
map(0x00004100, 0x0000410b).rw(FUNC(sega_32x_device::common_vdp_regs_r), FUNC(sega_32x_device::common_vdp_regs_w));
|
||||
map(0x00004200, 0x000043ff).rw(FUNC(sega_32x_device::m68k_palette_r), FUNC(sega_32x_device::m68k_palette_w));
|
||||
|
||||
map(0x00004100, 0x0000410b).rw(FUNC(sega_32x_device::_32x_common_vdp_regs_r), FUNC(sega_32x_device::_32x_common_vdp_regs_w));
|
||||
map(0x00004200, 0x000043ff).rw(FUNC(sega_32x_device::_32x_68k_palette_r), FUNC(sega_32x_device::_32x_68k_palette_w));
|
||||
|
||||
map(0x04000000, 0x0401ffff).rw(FUNC(sega_32x_device::_32x_68k_dram_r), FUNC(sega_32x_device::_32x_68k_dram_w));
|
||||
map(0x04020000, 0x0403ffff).rw(FUNC(sega_32x_device::_32x_68k_dram_overwrite_r), FUNC(sega_32x_device::_32x_68k_dram_overwrite_w));
|
||||
map(0x04000000, 0x0401ffff).rw(FUNC(sega_32x_device::m68k_dram_r), FUNC(sega_32x_device::m68k_dram_w));
|
||||
map(0x04020000, 0x0403ffff).rw(FUNC(sega_32x_device::m68k_dram_overwrite_r), FUNC(sega_32x_device::m68k_dram_overwrite_w));
|
||||
|
||||
map(0x06000000, 0x0603ffff).ram().share("sh2_shared");
|
||||
map(0x02000000, 0x023fffff).rom().region(":gamecart_sh2", 0); // program is writeable (wwfraw)
|
||||
|
||||
map(0x02000000, 0x023fffff).rom().region(":gamecart_sh2", 0);
|
||||
map(0x22000000, 0x223fffff).rom().region(":gamecart_sh2", 0); // cart mirror (fifa96)
|
||||
|
||||
map(0xc0000000, 0xc0000fff).ram();
|
||||
}
|
||||
|
||||
void sega_32x_device::sh2_main_map(address_map &map)
|
||||
{
|
||||
sh2_common_map(map);
|
||||
map(0x00000000, 0x00003fff).bankr("masterbios");
|
||||
|
||||
map(0x00004000, 0x00004001).rw(FUNC(sega_32x_device::master_4000_r), FUNC(sega_32x_device::master_4000_w));
|
||||
|
||||
map(0x00004014, 0x00004015).w(FUNC(sega_32x_device::master_4014_w));
|
||||
map(0x00004016, 0x00004017).w(FUNC(sega_32x_device::master_4016_w));
|
||||
map(0x00004018, 0x00004019).w(FUNC(sega_32x_device::master_4018_w));
|
||||
map(0x0000401a, 0x0000401b).w(FUNC(sega_32x_device::master_401a_w));
|
||||
map(0x0000401c, 0x0000401d).w(FUNC(sega_32x_device::master_401c_w));
|
||||
map(0x0000401e, 0x0000401f).w(FUNC(sega_32x_device::master_401e_w));
|
||||
}
|
||||
|
||||
void sega_32x_device::sh2_slave_map(address_map &map)
|
||||
{
|
||||
sh2_common_map(map);
|
||||
map(0x00000000, 0x00003fff).bankr("slavebios");
|
||||
|
||||
map(0x00004000, 0x00004003).rw(FUNC(sega_32x_device::_32x_sh2_slave_4000_common_4002_r), FUNC(sega_32x_device::_32x_sh2_slave_4000_common_4002_w));
|
||||
map(0x00004004, 0x00004007).rw(FUNC(sega_32x_device::_32x_sh2_common_4004_common_4006_r), FUNC(sega_32x_device::_32x_sh2_common_4004_common_4006_w));
|
||||
map(0x00004000, 0x00004001).rw(FUNC(sega_32x_device::slave_4000_r), FUNC(sega_32x_device::slave_4000_w));
|
||||
|
||||
map(0x00004008, 0x00004013).rw(FUNC(sega_32x_device::_32x_dreq_common_r), FUNC(sega_32x_device::_32x_dreq_common_w));
|
||||
|
||||
map(0x00004014, 0x00004017).nopr().w(FUNC(sega_32x_device::_32x_sh2_slave_4014_slave_4016_w)); // IRQ clear
|
||||
map(0x00004018, 0x0000401b).nopr().w(FUNC(sega_32x_device::_32x_sh2_slave_4018_slave_401a_w)); // IRQ clear
|
||||
map(0x0000401c, 0x0000401f).nopr().w(FUNC(sega_32x_device::_32x_sh2_slave_401c_slave_401e_w)); // IRQ clear
|
||||
|
||||
map(0x00004020, 0x0000402f).rw(FUNC(sega_32x_device::_32x_68k_m_commsram_r), FUNC(sega_32x_device::_32x_68k_m_commsram_w));
|
||||
map(0x00004030, 0x0000403f).rw(FUNC(sega_32x_device::_32x_pwm_r), FUNC(sega_32x_device::_32x_pwm_w));
|
||||
|
||||
map(0x00004100, 0x0000410b).rw(FUNC(sega_32x_device::_32x_common_vdp_regs_r), FUNC(sega_32x_device::_32x_common_vdp_regs_w));
|
||||
map(0x00004200, 0x000043ff).rw(FUNC(sega_32x_device::_32x_68k_palette_r), FUNC(sega_32x_device::_32x_68k_palette_w));
|
||||
|
||||
map(0x04000000, 0x0401ffff).rw(FUNC(sega_32x_device::_32x_68k_dram_r), FUNC(sega_32x_device::_32x_68k_dram_w));
|
||||
map(0x04020000, 0x0403ffff).rw(FUNC(sega_32x_device::_32x_68k_dram_overwrite_r), FUNC(sega_32x_device::_32x_68k_dram_overwrite_w));
|
||||
|
||||
map(0x06000000, 0x0603ffff).ram().share("sh2_shared");
|
||||
map(0x02000000, 0x023fffff).rom().region(":gamecart_sh2", 0); // program is writeable (wwfraw)
|
||||
|
||||
map(0x22000000, 0x223fffff).rom().region(":gamecart_sh2", 0); // cart mirror (fifa96)
|
||||
|
||||
map(0xc0000000, 0xc0000fff).ram();
|
||||
map(0x00004014, 0x00004015).w(FUNC(sega_32x_device::slave_4014_w));
|
||||
map(0x00004016, 0x00004017).w(FUNC(sega_32x_device::slave_4016_w));
|
||||
map(0x00004018, 0x00004019).w(FUNC(sega_32x_device::slave_4018_w));
|
||||
map(0x0000401a, 0x0000401b).w(FUNC(sega_32x_device::slave_401a_w));
|
||||
map(0x0000401c, 0x0000401d).w(FUNC(sega_32x_device::slave_401c_w));
|
||||
map(0x0000401e, 0x0000401f).w(FUNC(sega_32x_device::slave_401e_w));
|
||||
}
|
||||
|
||||
/****************************************** END 32X related *************************************/
|
||||
@ -1543,7 +1475,7 @@ void sega_32x_device::sh2_slave_map(address_map &map)
|
||||
|
||||
|
||||
|
||||
void sega_32x_device::_32x_check_irqs()
|
||||
void sega_32x_device::check_irqs()
|
||||
{
|
||||
if (m_sh2_master_vint_enable && m_sh2_master_vint_pending) m_master_cpu->set_input_line(SH2_VINT_IRQ_LEVEL,ASSERT_LINE);
|
||||
else m_master_cpu->set_input_line(SH2_VINT_IRQ_LEVEL,CLEAR_LINE);
|
||||
@ -1552,17 +1484,17 @@ void sega_32x_device::_32x_check_irqs()
|
||||
else m_slave_cpu->set_input_line(SH2_VINT_IRQ_LEVEL,CLEAR_LINE);
|
||||
}
|
||||
|
||||
void sega_32x_device::_32x_interrupt_cb(int scanline, int irq6)
|
||||
void sega_32x_device::interrupt_cb(int scanline, int irq6)
|
||||
{
|
||||
if (scanline == irq6)
|
||||
{
|
||||
m_32x_vblank_flag = 1;
|
||||
m_sh2_master_vint_pending = 1;
|
||||
m_sh2_slave_vint_pending = 1;
|
||||
_32x_check_irqs();
|
||||
check_irqs();
|
||||
}
|
||||
|
||||
_32x_check_framebuffer_swap(scanline >= irq6);
|
||||
check_framebuffer_swap(scanline >= irq6);
|
||||
|
||||
m_32x_hcount_compare_val++;
|
||||
|
||||
@ -1599,7 +1531,7 @@ SH2_DMA_FIFO_DATA_AVAILABLE_CB(sega_32x_device::_32x_fifo_available_callback)
|
||||
|
||||
|
||||
|
||||
void sega_32x_device::_32x_render_videobuffer_to_screenbuffer_helper(int scanline)
|
||||
void sega_32x_device::render_videobuffer_to_screenbuffer_helper(int scanline)
|
||||
{
|
||||
int x;
|
||||
|
||||
@ -1692,7 +1624,7 @@ void sega_32x_device::_32x_render_videobuffer_to_screenbuffer_helper(int scanlin
|
||||
}
|
||||
}
|
||||
|
||||
void sega_32x_device::_32x_render_videobuffer_to_screenbuffer(int x, uint32_t priority, uint32_t &lineptr)
|
||||
void sega_32x_device::render_videobuffer_to_screenbuffer(int x, uint32_t priority, uint32_t &lineptr)
|
||||
{
|
||||
if (m_32x_displaymode != 0)
|
||||
{
|
||||
@ -1866,23 +1798,23 @@ void sega_32x_device::device_reset()
|
||||
if (m_32x_adapter_enabled == 0)
|
||||
{
|
||||
m_main_cpu->space(AS_PROGRAM).install_rom(0x0000000, 0x03fffff, machine().root_device().memregion(":gamecart")->base());
|
||||
m_main_cpu->space(AS_PROGRAM).install_readwrite_handler(0x000070, 0x000073, read16_delegate(FUNC(sega_32x_device::_32x_68k_m_hint_vector_r),this), write16_delegate(FUNC(sega_32x_device::_32x_68k_m_hint_vector_w),this)); // h interrupt vector
|
||||
m_main_cpu->space(AS_PROGRAM).install_readwrite_handler(0x000070, 0x000073, read16_delegate(FUNC(sega_32x_device::m68k_m_hint_vector_r),this), write16_delegate(FUNC(sega_32x_device::m68k_m_hint_vector_w),this)); // h interrupt vector
|
||||
};
|
||||
|
||||
|
||||
m_a15100_reg = 0x0000;
|
||||
m_main_cpu->space(AS_PROGRAM).install_readwrite_handler(0xa15100, 0xa15101, read16_delegate(FUNC(sega_32x_device::_32x_68k_a15100_r),this), write16_delegate(FUNC(sega_32x_device::_32x_68k_a15100_w),this)); // framebuffer control regs
|
||||
m_main_cpu->space(AS_PROGRAM).install_readwrite_handler(0xa15102, 0xa15103, read16_delegate(FUNC(sega_32x_device::_32x_68k_a15102_r),this), write16_delegate(FUNC(sega_32x_device::_32x_68k_a15102_w),this)); // send irq to sh2
|
||||
m_main_cpu->space(AS_PROGRAM).install_readwrite_handler(0xa15104, 0xa15105, read16_delegate(FUNC(sega_32x_device::_32x_68k_a15104_r),this), write16_delegate(FUNC(sega_32x_device::_32x_68k_a15104_w),this)); // 68k BANK rom set
|
||||
m_main_cpu->space(AS_PROGRAM).install_readwrite_handler(0xa15106, 0xa15107, read16_delegate(FUNC(sega_32x_device::_32x_68k_a15106_r),this), write16_delegate(FUNC(sega_32x_device::_32x_68k_a15106_w),this)); // dreq stuff
|
||||
m_main_cpu->space(AS_PROGRAM).install_readwrite_handler(0xa15108, 0xa15113, read16_delegate(FUNC(sega_32x_device::_32x_dreq_common_r),this), write16_delegate(FUNC(sega_32x_device::_32x_dreq_common_w),this)); // dreq src / dst / length /fifo
|
||||
m_main_cpu->space(AS_PROGRAM).install_readwrite_handler(0xa15100, 0xa15101, read16_delegate(FUNC(sega_32x_device::m68k_a15100_r),this), write16_delegate(FUNC(sega_32x_device::m68k_a15100_w),this)); // framebuffer control regs
|
||||
m_main_cpu->space(AS_PROGRAM).install_readwrite_handler(0xa15102, 0xa15103, read16_delegate(FUNC(sega_32x_device::m68k_a15102_r),this), write16_delegate(FUNC(sega_32x_device::m68k_a15102_w),this)); // send irq to sh2
|
||||
m_main_cpu->space(AS_PROGRAM).install_readwrite_handler(0xa15104, 0xa15105, read16_delegate(FUNC(sega_32x_device::m68k_a15104_r),this), write16_delegate(FUNC(sega_32x_device::m68k_a15104_w),this)); // 68k BANK rom set
|
||||
m_main_cpu->space(AS_PROGRAM).install_readwrite_handler(0xa15106, 0xa15107, read16_delegate(FUNC(sega_32x_device::m68k_a15106_r),this), write16_delegate(FUNC(sega_32x_device::m68k_a15106_w),this)); // dreq stuff
|
||||
m_main_cpu->space(AS_PROGRAM).install_readwrite_handler(0xa15108, 0xa15113, read16_delegate(FUNC(sega_32x_device::dreq_common_r),this), write16_delegate(FUNC(sega_32x_device::dreq_common_w),this)); // dreq src / dst / length /fifo
|
||||
|
||||
m_main_cpu->space(AS_PROGRAM).install_readwrite_handler(0xa1511a, 0xa1511b, read16_delegate(FUNC(sega_32x_device::_32x_68k_a1511a_r),this), write16_delegate(FUNC(sega_32x_device::_32x_68k_a1511a_w),this)); // SEGA TV
|
||||
m_main_cpu->space(AS_PROGRAM).install_readwrite_handler(0xa1511a, 0xa1511b, read16_delegate(FUNC(sega_32x_device::m68k_a1511a_r),this), write16_delegate(FUNC(sega_32x_device::m68k_a1511a_w),this)); // SEGA TV
|
||||
|
||||
m_main_cpu->space(AS_PROGRAM).install_readwrite_handler(0xa15120, 0xa1512f, read16_delegate(FUNC(sega_32x_device::_32x_68k_m_commsram_r),this), write16_delegate(FUNC(sega_32x_device::_32x_68k_m_commsram_w),this)); // comms reg 0-7
|
||||
m_main_cpu->space(AS_PROGRAM).install_readwrite_handler(0xa15130, 0xa1513f, read16_delegate(FUNC(sega_32x_device::_32x_pwm_r),this), write16_delegate(FUNC(sega_32x_device::_32x_68k_pwm_w),this));
|
||||
m_main_cpu->space(AS_PROGRAM).install_readwrite_handler(0xa15120, 0xa1512f, read16_delegate(FUNC(sega_32x_device::m68k_m_commsram_r),this), write16_delegate(FUNC(sega_32x_device::m68k_m_commsram_w),this)); // comms reg 0-7
|
||||
m_main_cpu->space(AS_PROGRAM).install_readwrite_handler(0xa15130, 0xa1513f, read16_delegate(FUNC(sega_32x_device::pwm_r),this), write16_delegate(FUNC(sega_32x_device::m68k_pwm_w),this));
|
||||
|
||||
m_main_cpu->space(AS_PROGRAM).install_read_handler(0x0a130ec, 0x0a130ef, read16_delegate(FUNC(sega_32x_device::_32x_68k_MARS_r),this)); // system ID
|
||||
m_main_cpu->space(AS_PROGRAM).install_read_handler(0x0a130ec, 0x0a130ef, read16_delegate(FUNC(sega_32x_device::m68k_MARS_r),this)); // system ID
|
||||
|
||||
|
||||
|
||||
|
||||
@ -30,83 +30,70 @@ public:
|
||||
update_total_scanlines(mode3);
|
||||
}
|
||||
|
||||
DECLARE_READ32_MEMBER( _32x_sh2_master_4000_common_4002_r );
|
||||
DECLARE_READ32_MEMBER( _32x_sh2_slave_4000_common_4002_r );
|
||||
DECLARE_READ32_MEMBER( _32x_sh2_common_4004_common_4006_r );
|
||||
DECLARE_WRITE32_MEMBER( _32x_sh2_master_4000_common_4002_w );
|
||||
DECLARE_WRITE32_MEMBER( _32x_sh2_slave_4000_common_4002_w );
|
||||
DECLARE_WRITE32_MEMBER( _32x_sh2_common_4004_common_4006_w );
|
||||
DECLARE_WRITE32_MEMBER( _32x_sh2_master_4014_master_4016_w );
|
||||
DECLARE_WRITE32_MEMBER( _32x_sh2_master_4018_master_401a_w );
|
||||
DECLARE_WRITE32_MEMBER( _32x_sh2_master_401c_master_401e_w );
|
||||
DECLARE_WRITE32_MEMBER( _32x_sh2_slave_4014_slave_4016_w );
|
||||
DECLARE_WRITE32_MEMBER( _32x_sh2_slave_4018_slave_401a_w );
|
||||
DECLARE_WRITE32_MEMBER( _32x_sh2_slave_401c_slave_401e_w );
|
||||
|
||||
|
||||
DECLARE_READ16_MEMBER( _32x_68k_palette_r );
|
||||
DECLARE_WRITE16_MEMBER( _32x_68k_palette_w );
|
||||
DECLARE_READ16_MEMBER( _32x_68k_dram_r );
|
||||
DECLARE_WRITE16_MEMBER( _32x_68k_dram_w );
|
||||
DECLARE_READ16_MEMBER( _32x_68k_dram_overwrite_r );
|
||||
DECLARE_WRITE16_MEMBER( _32x_68k_dram_overwrite_w );
|
||||
DECLARE_READ16_MEMBER( _32x_68k_a15106_r );
|
||||
DECLARE_WRITE16_MEMBER( _32x_68k_a15106_w );
|
||||
DECLARE_READ16_MEMBER( _32x_dreq_common_r );
|
||||
DECLARE_WRITE16_MEMBER( _32x_dreq_common_w );
|
||||
DECLARE_READ16_MEMBER( _32x_68k_a1511a_r );
|
||||
DECLARE_WRITE16_MEMBER( _32x_68k_a1511a_w );
|
||||
DECLARE_READ16_MEMBER( _32x_68k_m_hint_vector_r );
|
||||
DECLARE_WRITE16_MEMBER( _32x_68k_m_hint_vector_w );
|
||||
DECLARE_READ16_MEMBER( _32x_68k_MARS_r );
|
||||
DECLARE_READ16_MEMBER( _32x_68k_a15100_r );
|
||||
DECLARE_WRITE16_MEMBER( _32x_68k_a15100_w );
|
||||
DECLARE_READ16_MEMBER( _32x_68k_a15102_r );
|
||||
DECLARE_WRITE16_MEMBER( _32x_68k_a15102_w );
|
||||
DECLARE_READ16_MEMBER( _32x_68k_a15104_r );
|
||||
DECLARE_WRITE16_MEMBER( _32x_68k_a15104_w );
|
||||
DECLARE_READ16_MEMBER( _32x_68k_m_commsram_r );
|
||||
DECLARE_WRITE16_MEMBER( _32x_68k_m_commsram_w );
|
||||
DECLARE_READ16_MEMBER( _32x_pwm_r );
|
||||
DECLARE_WRITE16_MEMBER( _32x_pwm_w );
|
||||
DECLARE_WRITE16_MEMBER( _32x_68k_pwm_w );
|
||||
DECLARE_READ16_MEMBER( _32x_common_vdp_regs_r );
|
||||
DECLARE_WRITE16_MEMBER( _32x_common_vdp_regs_w );
|
||||
DECLARE_READ16_MEMBER( _32x_sh2_master_4000_r );
|
||||
DECLARE_WRITE16_MEMBER( _32x_sh2_master_4000_w );
|
||||
DECLARE_READ16_MEMBER( _32x_sh2_slave_4000_r );
|
||||
DECLARE_WRITE16_MEMBER( _32x_sh2_slave_4000_w );
|
||||
DECLARE_READ16_MEMBER( _32x_sh2_common_4002_r );
|
||||
DECLARE_WRITE16_MEMBER( _32x_sh2_common_4002_w );
|
||||
DECLARE_READ16_MEMBER( _32x_sh2_common_4004_r );
|
||||
DECLARE_WRITE16_MEMBER( _32x_sh2_common_4004_w );
|
||||
DECLARE_READ16_MEMBER( _32x_sh2_common_4006_r );
|
||||
DECLARE_WRITE16_MEMBER( _32x_sh2_common_4006_w );
|
||||
DECLARE_WRITE16_MEMBER( _32x_sh2_master_4014_w );
|
||||
DECLARE_WRITE16_MEMBER( _32x_sh2_slave_4014_w );
|
||||
DECLARE_WRITE16_MEMBER( _32x_sh2_master_4016_w );
|
||||
DECLARE_WRITE16_MEMBER( _32x_sh2_slave_4016_w );
|
||||
DECLARE_WRITE16_MEMBER( _32x_sh2_master_4018_w );
|
||||
DECLARE_WRITE16_MEMBER( _32x_sh2_slave_4018_w ) ;
|
||||
DECLARE_WRITE16_MEMBER( _32x_sh2_master_401a_w );
|
||||
DECLARE_WRITE16_MEMBER( _32x_sh2_slave_401a_w );
|
||||
DECLARE_WRITE16_MEMBER( _32x_sh2_master_401c_w );
|
||||
DECLARE_WRITE16_MEMBER( _32x_sh2_slave_401c_w );
|
||||
DECLARE_WRITE16_MEMBER( _32x_sh2_master_401e_w );
|
||||
DECLARE_WRITE16_MEMBER( _32x_sh2_slave_401e_w );
|
||||
DECLARE_READ16_MEMBER( m68k_palette_r );
|
||||
DECLARE_WRITE16_MEMBER( m68k_palette_w );
|
||||
DECLARE_READ16_MEMBER( m68k_dram_r );
|
||||
DECLARE_WRITE16_MEMBER( m68k_dram_w );
|
||||
DECLARE_READ16_MEMBER( m68k_dram_overwrite_r );
|
||||
DECLARE_WRITE16_MEMBER( m68k_dram_overwrite_w );
|
||||
DECLARE_READ16_MEMBER( m68k_a15106_r );
|
||||
DECLARE_WRITE16_MEMBER( m68k_a15106_w );
|
||||
DECLARE_READ16_MEMBER( dreq_common_r );
|
||||
DECLARE_WRITE16_MEMBER( dreq_common_w );
|
||||
DECLARE_READ16_MEMBER( m68k_a1511a_r );
|
||||
DECLARE_WRITE16_MEMBER( m68k_a1511a_w );
|
||||
DECLARE_READ16_MEMBER( m68k_m_hint_vector_r );
|
||||
DECLARE_WRITE16_MEMBER( m68k_m_hint_vector_w );
|
||||
DECLARE_READ16_MEMBER( m68k_MARS_r );
|
||||
DECLARE_READ16_MEMBER( m68k_a15100_r );
|
||||
DECLARE_WRITE16_MEMBER( m68k_a15100_w );
|
||||
DECLARE_READ16_MEMBER( m68k_a15102_r );
|
||||
DECLARE_WRITE16_MEMBER( m68k_a15102_w );
|
||||
DECLARE_READ16_MEMBER( m68k_a15104_r );
|
||||
DECLARE_WRITE16_MEMBER( m68k_a15104_w );
|
||||
DECLARE_READ16_MEMBER( m68k_m_commsram_r );
|
||||
DECLARE_WRITE16_MEMBER( m68k_m_commsram_w );
|
||||
DECLARE_READ16_MEMBER( pwm_r );
|
||||
DECLARE_WRITE16_MEMBER( pwm_w );
|
||||
DECLARE_WRITE16_MEMBER( m68k_pwm_w );
|
||||
DECLARE_READ16_MEMBER( common_vdp_regs_r );
|
||||
DECLARE_WRITE16_MEMBER( common_vdp_regs_w );
|
||||
DECLARE_READ16_MEMBER( master_4000_r );
|
||||
DECLARE_WRITE16_MEMBER( master_4000_w );
|
||||
DECLARE_READ16_MEMBER( slave_4000_r );
|
||||
DECLARE_WRITE16_MEMBER( slave_4000_w );
|
||||
DECLARE_READ16_MEMBER( common_4002_r );
|
||||
DECLARE_WRITE16_MEMBER( common_4002_w );
|
||||
DECLARE_READ16_MEMBER( common_4004_r );
|
||||
DECLARE_WRITE16_MEMBER( common_4004_w );
|
||||
DECLARE_READ16_MEMBER( common_4006_r );
|
||||
DECLARE_WRITE16_MEMBER( common_4006_w );
|
||||
DECLARE_WRITE16_MEMBER( master_4014_w );
|
||||
DECLARE_WRITE16_MEMBER( slave_4014_w );
|
||||
DECLARE_WRITE16_MEMBER( master_4016_w );
|
||||
DECLARE_WRITE16_MEMBER( slave_4016_w );
|
||||
DECLARE_WRITE16_MEMBER( master_4018_w );
|
||||
DECLARE_WRITE16_MEMBER( slave_4018_w ) ;
|
||||
DECLARE_WRITE16_MEMBER( master_401a_w );
|
||||
DECLARE_WRITE16_MEMBER( slave_401a_w );
|
||||
DECLARE_WRITE16_MEMBER( master_401c_w );
|
||||
DECLARE_WRITE16_MEMBER( slave_401c_w );
|
||||
DECLARE_WRITE16_MEMBER( master_401e_w );
|
||||
DECLARE_WRITE16_MEMBER( slave_401e_w );
|
||||
|
||||
SH2_DMA_FIFO_DATA_AVAILABLE_CB(_32x_fifo_available_callback);
|
||||
|
||||
void _32x_render_videobuffer_to_screenbuffer_helper(int scanline);
|
||||
void _32x_render_videobuffer_to_screenbuffer(int x, uint32_t priority, uint32_t &lineptr);
|
||||
void render_videobuffer_to_screenbuffer_helper(int scanline);
|
||||
void render_videobuffer_to_screenbuffer(int x, uint32_t priority, uint32_t &lineptr);
|
||||
int sh2_master_pwmint_enable, sh2_slave_pwmint_enable;
|
||||
|
||||
void _32x_check_framebuffer_swap(bool enabled);
|
||||
void _32x_check_irqs();
|
||||
void _32x_interrupt_cb(int scanline, int irq6);
|
||||
void check_framebuffer_swap(bool enabled);
|
||||
void check_irqs();
|
||||
void interrupt_cb(int scanline, int irq6);
|
||||
|
||||
void sh2_main_map(address_map &map);
|
||||
void sh2_slave_map(address_map &map);
|
||||
void sh2_common_map(address_map &map);
|
||||
|
||||
protected:
|
||||
sega_32x_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user