mirror of
https://github.com/holub/mame
synced 2025-07-04 17:38:08 +03:00
Add M68HC11 internal EEPROM for relevant models
This commit is contained in:
AJR
parent
44343b8f3f
commit
78e33c5479
@ -34,8 +34,9 @@ void cdd2000_device::mem_map(address_map &map)
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void cdd2000_device::device_add_mconfig(machine_config &config)
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{
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MC68HC11F1(config, m_cdcpu, 8'000'000); // type and clock guessed
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m_cdcpu->set_addrmap(AS_PROGRAM, &cdd2000_device::mem_map);
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mc68hc11f1_device &cdcpu(MC68HC11F1(config, m_cdcpu, 8'000'000)); // type and clock guessed
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cdcpu.set_addrmap(AS_PROGRAM, &cdd2000_device::mem_map);
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cdcpu.set_default_config(0x0b);
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NCR53CF94(config, "scsic", 25'000'000); // type and clock guessed
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}
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@ -55,6 +55,7 @@ DEFINE_DEVICE_TYPE(MC68HC11M0, mc68hc11m0_device, "mc68hc11m0", "Motorola MC68HC
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mc68hc11_cpu_device::mc68hc11_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, uint16_t ram_size, uint16_t reg_block_size, uint16_t rom_size, uint16_t eeprom_size, uint8_t init_value, uint8_t config_mask, uint8_t option_mask)
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: cpu_device(mconfig, type, tag, owner, clock)
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, device_nvram_interface(mconfig, *this)
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, m_program_config("program", ENDIANNESS_BIG, 8, 16, 0, address_map_constructor(FUNC(mc68hc11_cpu_device::internal_map), this))
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, m_port_input_cb(*this)
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, m_port_output_cb(*this)
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@ -63,6 +64,8 @@ mc68hc11_cpu_device::mc68hc11_cpu_device(const machine_config &mconfig, device_t
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, m_spi2_data_output_cb(*this)
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, m_ram_view(*this, "ram")
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, m_reg_view(*this, "regs")
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, m_eeprom_view(*this, "eeprom")
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, m_eeprom_data(*this, "eeprom")
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, m_internal_ram_size(ram_size)
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, m_reg_block_size(reg_block_size)
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, m_internal_rom_size(rom_size)
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@ -70,17 +73,13 @@ mc68hc11_cpu_device::mc68hc11_cpu_device(const machine_config &mconfig, device_t
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, m_init_value(init_value)
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, m_config_mask(config_mask)
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, m_option_mask(option_mask)
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, m_config(config_mask)
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, m_config(config_mask & (m_internal_rom_size == 0 ? 0xfd : 0xff) & (m_internal_eeprom_size == 0 ? 0xfe : 0xff))
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{
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if (m_internal_rom_size == 0)
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m_config &= 0xfd;
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if (m_internal_eeprom_size == 0)
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m_config &= 0xfe;
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}
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void mc68hc11_cpu_device::internal_map(address_map &map)
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{
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// TODO: internal ROM & EEPROM
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// TODO: internal ROM
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map(0x0000, 0xffff).view(m_ram_view);
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for (int pos = 0; pos < 16; pos++)
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@ -89,6 +88,17 @@ void mc68hc11_cpu_device::internal_map(address_map &map)
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for (int pos = 0; pos < 16; pos++)
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m_ram_view[pos + 16]((pos << 12) + m_reg_block_size, (pos << 12) + m_reg_block_size + m_internal_ram_size - 1).ram().share("ram");
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if (m_internal_eeprom_size != 0)
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{
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// TODO: allow EEPROM writes in programming mode only, latching address and data
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map(0x0000, 0xffff).view(m_eeprom_view);
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if ((m_config_mask & 0xf0) == 0)
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m_eeprom_view[0](0xb600, 0xb7ff).ram().share(m_eeprom_data);
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else
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for (int pos = 0; pos < 16; pos++)
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m_eeprom_view[pos](((pos + 1) << 12) - m_internal_eeprom_size, ((pos + 1) << 12) - 1).ram().share(m_eeprom_data);
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}
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map(0x0000, 0xffff).view(m_reg_view);
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for (int pos = 0; pos < 16; pos++)
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{
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@ -120,6 +130,7 @@ mc68hc811e2_device::mc68hc811e2_device(const machine_config &mconfig, const char
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mc68hc11f1_device::mc68hc11f1_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: mc68hc11_cpu_device(mconfig, MC68HC11F1, tag, owner, clock, 1024, 96, 0, 512, 0x01, 0xf5, 0xff)
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{
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m_config &= 0x0f;
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}
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mc68hc11k1_device::mc68hc11k1_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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@ -154,6 +165,54 @@ std::unique_ptr<util::disasm_interface> mc68hc11_cpu_device::create_disassembler
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}
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bool mc68hc11_cpu_device::nvram_can_write()
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{
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return (m_config_mask & 0xf9) != 0;
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}
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bool mc68hc11_cpu_device::nvram_read(util::read_stream &file)
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{
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size_t actual;
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if (file.read(&m_eeprom_data[0], m_internal_eeprom_size, actual) || actual != m_internal_eeprom_size)
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return false;
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if (file.read(&m_config, 1, actual) || actual != 1)
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return false;
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return true;
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}
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bool mc68hc11_cpu_device::nvram_write(util::write_stream &file)
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{
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size_t actual;
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if (file.write(&m_eeprom_data[0], m_internal_eeprom_size, actual) || actual != m_internal_eeprom_size)
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return false;
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if (file.write(&m_config, 1, actual) || actual != 1)
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return false;
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return true;
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}
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void mc68hc11_cpu_device::nvram_default()
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{
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if ((m_config_mask & 0xf9) == 0)
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return;
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if (m_internal_eeprom_size != 0)
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{
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// use region if it exists
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memory_region *region = memregion("eeprom");
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if (region != nullptr)
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std::copy_n(®ion->as_u8(), m_internal_eeprom_size, &m_eeprom_data[0]);
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else
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std::fill_n(&m_eeprom_data[0], m_internal_eeprom_size, 0xff);
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}
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}
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#define HC11OP(XX) mc68hc11_cpu_device::hc11_##XX
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/*****************************************************************************/
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@ -374,7 +433,15 @@ uint8_t mc68hc11_cpu_device::config_1s_r()
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void mc68hc11_cpu_device::config_w(uint8_t data)
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{
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// TODO: CONFIG also has EEPROM protection
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m_config = data & m_config_mask;
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if (m_internal_eeprom_size != 0)
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{
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if (BIT(m_config, 0))
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m_eeprom_view.select(((m_config_mask & 0xf0) == 0xb0 ? m_init2 : m_config) >> 4);
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else
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m_eeprom_view.disable();
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}
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}
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uint8_t mc68hc11_cpu_device::init_r()
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@ -402,6 +469,19 @@ void mc68hc11_cpu_device::init_w(uint8_t data)
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}
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}
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uint8_t mc68hc11_cpu_device::init2_r()
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{
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return m_init2;
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}
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void mc68hc11_cpu_device::init2_w(uint8_t data)
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{
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m_init2 = data & 0xf0;
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assert(m_internal_eeprom_size != 0);
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if (BIT(m_config, 0))
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m_eeprom_view.select(data >> 4);
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}
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uint8_t mc68hc11_cpu_device::option_r()
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{
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return m_option;
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@ -665,6 +745,7 @@ void mc68hc11k1_device::mc68hc11_reg_map(memory_view::memory_view_entry &block,
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block(base + 0x2a, base + 0x2a).rw(FUNC(mc68hc11k1_device::spdr_r<0>), FUNC(mc68hc11k1_device::spdr_w<0>)); // SPDR
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block(base + 0x30, base + 0x30).rw(FUNC(mc68hc11k1_device::adctl_r), FUNC(mc68hc11k1_device::adctl_w)); // ADCTL
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block(base + 0x31, base + 0x34).r(FUNC(mc68hc11k1_device::adr_r)); // ADR1-ADR4
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block(base + 0x37, base + 0x37).rw(FUNC(mc68hc11k1_device::init2_r), FUNC(mc68hc11k1_device::init2_w)); // INIT2
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block(base + 0x38, base + 0x38).r(FUNC(mc68hc11k1_device::opt2_r)).nopw(); // OPT2
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block(base + 0x39, base + 0x39).rw(FUNC(mc68hc11k1_device::option_r), FUNC(mc68hc11k1_device::option_w)); // OPTION
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block(base + 0x3a, base + 0x3a).nopw(); // COPRST (watchdog)
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@ -835,6 +916,8 @@ void mc68hc11_cpu_device::device_start()
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save_item(NAME(m_port_dir));
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save_item(NAME(m_config));
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save_item(NAME(m_option));
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if ((m_config_mask & 0xf0) == 0xb0)
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save_item(NAME(m_init2));
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m_pc = 0;
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m_d.d16 = 0;
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@ -846,6 +929,7 @@ void mc68hc11_cpu_device::device_start()
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m_ad_channel = 0;
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std::fill(std::begin(m_irq_state), std::end(m_irq_state), CLEAR_LINE);
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m_init = 0;
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m_init2 = 0;
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m_option = 0;
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m_tflg1 = 0;
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m_tmsk1 = 0;
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@ -894,6 +978,25 @@ void mc68hc11_cpu_device::state_string_export(const device_state_entry &entry, s
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void mc68hc11_cpu_device::device_reset()
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{
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if ((m_config_mask & 0xf9) == 0)
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{
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m_config = m_config_mask;
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if (m_internal_rom_size == 0)
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m_config &= 0xfd;
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}
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else
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{
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if ((m_config_mask & 0xf0) == 0xb0)
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m_init2 = 0;
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if (m_internal_eeprom_size != 0)
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{
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if (BIT(m_config, 0))
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m_eeprom_view.select(m_config_mask < 0xf0 ? 0 : m_config >> 4);
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else
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m_eeprom_view.disable();
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}
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}
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m_pc = READ16(0xfffe); // TODO: vectors differ in bootstrap and special test modes
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m_wait_state = 0;
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m_stop_state = 0;
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@ -929,7 +1032,6 @@ void mc68hc11d0_device::device_reset()
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m_port_data[0] &= 0x8f;
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ddr_w<0>(0x70);
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m_config = 0x00;
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}
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void mc68hc11e1_device::device_reset()
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@ -959,13 +1061,6 @@ void mc68hc11f1_device::device_reset()
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m_option = 0x00;
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}
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void mc68hc11m0_device::device_reset()
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{
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mc68hc11_cpu_device::device_reset();
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m_config = 0x04;
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}
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/*
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IRQ table vectors:
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0xffd6: SCI
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@ -20,7 +20,7 @@ DECLARE_DEVICE_TYPE(MC68HC11F1, mc68hc11f1_device)
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DECLARE_DEVICE_TYPE(MC68HC11K1, mc68hc11k1_device)
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DECLARE_DEVICE_TYPE(MC68HC11M0, mc68hc11m0_device)
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class mc68hc11_cpu_device : public cpu_device
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class mc68hc11_cpu_device : public cpu_device, public device_nvram_interface
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{
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public:
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// port configuration
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@ -51,6 +51,8 @@ public:
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auto in_spi2_data_callback() { return m_spi2_data_input_cb.bind(); }
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auto out_spi2_data_callback() { return m_spi2_data_output_cb.bind(); }
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void set_default_config(uint8_t data) { assert(!configured()); m_config = data & m_config_mask; }
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protected:
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mc68hc11_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, uint16_t ram_size, uint16_t reg_block_size, uint16_t rom_size, uint16_t eeprom_size, uint8_t init_value, uint8_t config_mask, uint8_t option_mask);
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@ -71,6 +73,12 @@ protected:
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// device_memory_interface overrides
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virtual space_config_vector memory_space_config() const override;
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// device_nvram_interface overrides
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virtual bool nvram_can_write() override;
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virtual bool nvram_read(util::read_stream &file) override;
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virtual bool nvram_write(util::write_stream &file) override;
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virtual void nvram_default() override;
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// device_state_interface overrides
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virtual void state_string_export(const device_state_entry &entry, std::string &str) const override;
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@ -117,6 +125,8 @@ protected:
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void config_w(uint8_t data);
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uint8_t init_r();
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void init_w(uint8_t data);
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uint8_t init2_r();
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void init2_w(uint8_t data);
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uint8_t option_r();
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void option_w(uint8_t data);
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uint8_t scbd_r(offs_t offset);
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@ -169,6 +179,8 @@ private:
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memory_view m_ram_view;
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memory_view m_reg_view;
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memory_view m_eeprom_view;
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optional_shared_ptr<uint8_t> m_eeprom_data;
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const uint16_t m_internal_ram_size;
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const uint16_t m_reg_block_size; // size of internal I/O space
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@ -192,6 +204,7 @@ private:
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uint8_t m_tmsk2;
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uint8_t m_pactl;
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uint8_t m_init;
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uint8_t m_init2;
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protected:
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uint8_t m_config;
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@ -627,8 +640,6 @@ public:
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mc68hc11m0_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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protected:
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virtual void device_reset() override;
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virtual void mc68hc11_reg_map(memory_view::memory_view_entry &block, offs_t base) override;
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};
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@ -10,8 +10,7 @@ Many thanks to Olivier Galibert for the CPU identify effort ;-)
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TODO:
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- CPU core bugs?
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- Protection controls inputs;
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- Understand & fix EEPROM emulation;
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- Hangs during attract mode, eeprom or protection?
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- Hangs during attract mode due to unemulated PIC protection;
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- complete video HW (unknown bits and hblank);
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- 24Khz monitor isn't supported, it changes the resolution to 648 x 480 and
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changes the register 9 (raster lines x character lines) from 7 to 0xf.
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@ -61,8 +60,7 @@ public:
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: driver_device(mconfig, type, tag),
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m_maincpu(*this, "maincpu"),
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m_gfxdecode(*this, "gfxdecode"),
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m_palette(*this, "palette"),
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m_eeprom(*this, "eeprom")
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m_palette(*this, "palette")
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{
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}
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@ -71,8 +69,6 @@ public:
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void init_hitpoker();
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private:
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uint8_t m_sys_regs = 0;
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uint8_t m_pic_data = 0;
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std::unique_ptr<uint8_t[]> m_videoram;
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std::unique_ptr<uint8_t[]> m_paletteram;
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@ -84,14 +80,13 @@ private:
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void hitpoker_cram_w(offs_t offset, uint8_t data);
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uint8_t hitpoker_paletteram_r(offs_t offset);
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void hitpoker_paletteram_w(offs_t offset, uint8_t data);
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uint8_t hitpoker_pic_r(offs_t offset);
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void hitpoker_pic_w(offs_t offset, uint8_t data);
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uint8_t hitpoker_pic_r();
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void hitpoker_pic_w(uint8_t data);
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virtual void video_start() override;
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uint32_t screen_update_hitpoker(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
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required_device<mc68hc11_cpu_device> m_maincpu;
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required_device<gfxdecode_device> m_gfxdecode;
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required_device<palette_device> m_palette;
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required_shared_ptr<uint8_t> m_eeprom;
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void hitpoker_map(address_map &map);
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};
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@ -190,30 +185,23 @@ void hitpoker_state::hitpoker_paletteram_w(offs_t offset, uint8_t data)
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}
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uint8_t hitpoker_state::hitpoker_pic_r(offs_t offset)
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uint8_t hitpoker_state::hitpoker_pic_r()
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{
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// logerror("R\n");
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if(offset == 0)
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{
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if(m_maincpu->pc() == 0x3143 ||
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m_maincpu->pc() == 0x314e ||
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m_maincpu->pc() == 0x3164 ||
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m_maincpu->pc() == 0x3179)
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return m_pic_data;
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if(m_maincpu->pc() == 0x3143 ||
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m_maincpu->pc() == 0x314e ||
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m_maincpu->pc() == 0x3164 ||
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m_maincpu->pc() == 0x3179)
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return m_pic_data;
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return (m_pic_data & 0x7f) | (m_pic_data & 0x40 ? 0x80 : 0x00);
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}
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return m_sys_regs;
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return (m_pic_data & 0x7f) | (m_pic_data & 0x40 ? 0x80 : 0x00);
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}
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void hitpoker_state::hitpoker_pic_w(offs_t offset, uint8_t data)
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void hitpoker_state::hitpoker_pic_w(uint8_t data)
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{
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if(offset == 0)
|
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m_pic_data = (data & 0xff);// | (data & 0x40) ? 0x80 : 0x00;
|
||||
m_pic_data = (data & 0xff);// | (data & 0x40) ? 0x80 : 0x00;
|
||||
// logerror("%02x W\n",data);
|
||||
m_sys_regs = data;
|
||||
}
|
||||
|
||||
#if 0
|
||||
@ -230,7 +218,7 @@ void hitpoker_state::hitpoker_map(address_map &map)
|
||||
map(0xbf00, 0xffff).rom();
|
||||
|
||||
map(0x8000, 0xb5ff).rw(FUNC(hitpoker_state::hitpoker_vram_r), FUNC(hitpoker_state::hitpoker_vram_w));
|
||||
map(0xb600, 0xbdff).ram().share("eeprom");
|
||||
map(0xb800, 0xbdff).ram();
|
||||
map(0xbe00, 0xbe7f).rw("rtc", FUNC(ds17x85_device::read_direct), FUNC(ds17x85_device::write_direct));
|
||||
map(0xbe80, 0xbe80).w("crtc", FUNC(mc6845_device::address_w));
|
||||
map(0xbe81, 0xbe81).w("crtc", FUNC(mc6845_device::register_w));
|
||||
@ -395,16 +383,19 @@ void hitpoker_state::init_hitpoker()
|
||||
ROM[0x10c7] = 0x01; //patch the checksum routine
|
||||
|
||||
// must match RTC serial number
|
||||
m_eeprom[3] = 'M';
|
||||
m_eeprom[2] = 'A';
|
||||
m_eeprom[1] = 'M';
|
||||
m_eeprom[0] = 'E';
|
||||
}
|
||||
|
||||
ROM_START( hitpoker )
|
||||
ROM_REGION( 0x10000, "maincpu", 0 )
|
||||
ROM_LOAD( "u4.bin", 0x00000, 0x10000, CRC(0016497a) SHA1(017320bfe05fea8a48e26a66c0412415846cee7c) )
|
||||
|
||||
ROM_REGION( 0x200, "maincpu:eeprom", ROMREGION_ERASEFF )
|
||||
// must match RTC serial number
|
||||
ROM_FILL( 0x003, 1, 0x4d )
|
||||
ROM_FILL( 0x002, 1, 0x41 )
|
||||
ROM_FILL( 0x001, 1, 0x4d )
|
||||
ROM_FILL( 0x000, 1, 0x45 )
|
||||
|
||||
ROM_REGION( 0x10000, "pic", 0 )
|
||||
ROM_LOAD( "pic", 0x00000, 0x1000, NO_DUMP ) // unknown type
|
||||
|
||||
|
||||
@ -46,6 +46,7 @@ void slsstars_state::slsstars(machine_config &config)
|
||||
{
|
||||
MC68HC11F1(config, m_maincpu, 8'000'000); // unknown clock
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &slsstars_state::mem_map);
|
||||
m_maincpu->set_default_config(0x3f);
|
||||
|
||||
M48T58(config, "timekpr"); // U3
|
||||
}
|
||||
|
||||
@ -23,7 +23,6 @@ private:
|
||||
|
||||
void vanguardmk1_state::mcu_map(address_map &map)
|
||||
{
|
||||
map(0xf800, 0xffff).rom().region("mcu", 0);
|
||||
}
|
||||
|
||||
|
||||
@ -34,11 +33,12 @@ void vanguardmk1_state::vanguardmk1(machine_config &config)
|
||||
{
|
||||
mc68hc811e2_device &mcu(MC68HC811E2(config, "mcu", 8000000)); // unknown clock
|
||||
mcu.set_addrmap(AS_PROGRAM, &vanguardmk1_state::mcu_map);
|
||||
mcu.set_default_config(0xff);
|
||||
}
|
||||
|
||||
|
||||
ROM_START(vngrdmk1)
|
||||
ROM_REGION(0x800, "mcu", 0)
|
||||
ROM_REGION(0x800, "mcu:eeprom", 0)
|
||||
ROM_LOAD( "van24_aug04", 0x000, 0x800, CRC(ce63fcb9) SHA1(8f688e866e8fea888c77aa5be92ad09f684afd59) )
|
||||
ROM_END
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user