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dmac_0448: sony news dmac (nw)
This commit is contained in:
Patrick Mackinlay
parent
8b057af7a9
commit
7912047486
@ -2939,6 +2939,8 @@ files {
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createMESSProjects(_target, _subtarget, "news_r3k")
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files {
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MAME_DIR .. "src/mame/drivers/news_r3k.cpp",
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MAME_DIR .. "src/mame/machine/dmac_0448.cpp",
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MAME_DIR .. "src/mame/machine/dmac_0448.h",
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MAME_DIR .. "src/mame/machine/news_kbd.cpp",
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MAME_DIR .. "src/mame/machine/news_kbd.h",
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}
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189
src/mame/machine/dmac_0448.cpp
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189
src/mame/machine/dmac_0448.cpp
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@ -0,0 +1,189 @@
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// license:BSD-3-Clause
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// copyright-holders:Patrick Mackinlay
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/*
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* Sony NEWS DMAC 0448 device.
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*
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* Sources:
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* - https://github.com/NetBSD/src/blob/trunk/sys/arch/newsmips/dev/dmac_0448.h
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*
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* TODO:
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* - 16 and 32 bit transfers
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* - terminal count handling
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* - save state
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*/
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#include "emu.h"
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#include "dmac_0448.h"
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#define VERBOSE 0
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#include "logmacro.h"
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DEFINE_DEVICE_TYPE(DMAC_0448, dmac_0448_device, "dmac_0448", "Sony DMA Controller 0448")
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dmac_0448_device::dmac_0448_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock)
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: device_t(mconfig, DMAC_0448, tag, owner, clock)
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, m_bus(*this, finder_base::DUMMY_TAG, -1, 32)
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, m_out_int(*this)
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, m_dma_r(*this)
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, m_dma_w(*this)
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{
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}
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void dmac_0448_device::map(address_map &map)
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{
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map(0x2, 0x2).r(FUNC(dmac_0448_device::cstat_r));
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map(0x3, 0x3).w(FUNC(dmac_0448_device::cctl_w));
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map(0x4, 0x4).rw(FUNC(dmac_0448_device::ctrcl_r), FUNC(dmac_0448_device::ctrcl_w));
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map(0x5, 0x5).rw(FUNC(dmac_0448_device::ctrcm_r), FUNC(dmac_0448_device::ctrcm_w));
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map(0x6, 0x6).rw(FUNC(dmac_0448_device::ctrch_r), FUNC(dmac_0448_device::ctrch_w));
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map(0x7, 0x7).rw(FUNC(dmac_0448_device::ctag_r), FUNC(dmac_0448_device::ctag_w));
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map(0x8, 0x8).rw(FUNC(dmac_0448_device::cwid_r), FUNC(dmac_0448_device::cwid_w));
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map(0x9, 0x9).rw(FUNC(dmac_0448_device::cofsl_r), FUNC(dmac_0448_device::cofsl_w));
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map(0xa, 0xa).rw(FUNC(dmac_0448_device::cofsh_r), FUNC(dmac_0448_device::cofsh_w));
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map(0xc, 0xd).rw(FUNC(dmac_0448_device::cmap_r), FUNC(dmac_0448_device::cmap_w));
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map(0xe, 0xe).w(FUNC(dmac_0448_device::gsel_w));
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map(0xf, 0xf).r(FUNC(dmac_0448_device::gstat_r));
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}
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void dmac_0448_device::device_start()
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{
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m_out_int.resolve();
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m_dma_r.resolve_all_safe(0);
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m_dma_w.resolve_all_safe();
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m_irq_check = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(dmac_0448_device::irq_check), this));
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m_dma_check = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(dmac_0448_device::dma_check), this));
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m_out_int_state = false;
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m_gsel = 0;
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m_gstat = 0;
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}
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void dmac_0448_device::device_reset()
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{
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m_irq_check->adjust(attotime::zero);
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}
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void dmac_0448_device::set_irq_line(int number, int state)
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{
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u8 const mask = 1U << (number * 2);
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if (state)
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m_gstat |= mask;
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else
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m_gstat &= ~mask;
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m_irq_check->adjust(attotime::zero);
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}
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void dmac_0448_device::irq_check(void *ptr, s32 param)
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{
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bool const out_int_stat = bool(m_gstat & 0x55);
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if (out_int_stat != m_out_int_state)
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{
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m_out_int_state = out_int_stat;
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m_out_int(m_out_int_state);
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}
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}
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void dmac_0448_device::set_drq_line(int channel, int state)
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{
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u8 const mask = 1U << ((channel * 2) + 1);
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if (state)
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m_gstat |= mask;
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else
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m_gstat &= ~mask;
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if (state)
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m_dma_check->adjust(attotime::zero);
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}
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void dmac_0448_device::cctl_w(u8 data)
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{
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if ((data & CS_ENABLE) && !(m_channel[m_gsel].cctl & CS_ENABLE))
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{
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LOG("transfer started address 0x%08x count 0x%x\n",
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u32(m_channel[m_gsel].cmap[m_channel[m_gsel].ctag]) << 12 | m_channel[m_gsel].cofs, m_channel[m_gsel].ctrc);
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}
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m_channel[m_gsel].cctl = data;
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m_dma_check->adjust(attotime::zero);
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}
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void dmac_0448_device::dma_check(void *ptr, s32 param)
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{
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bool active = false;
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for (unsigned channel = 0; channel < 4; channel++)
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{
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// check drq active
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if (!BIT(m_gstat, (channel * 2) + 1))
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continue;
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dma_channel &dma = m_channel[channel];
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// check channel enabled
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if (!(dma.cctl & CS_ENABLE))
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return;
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// check transfer count
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if (!dma.ctrc)
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return;
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// TODO: confirm if this is correct
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u32 const address = u32(dma.cmap[dma.ctag]) << 12 | dma.cofs;
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// perform dma transfer
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if (dma.cctl & CS_MODE)
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{
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// device to memory
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u8 const data = m_dma_r[channel]();
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LOG("dma_r data 0x%02x address 0x%08x\n", data, address);
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m_bus->write_byte(address, data);
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}
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else
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{
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// memory to device
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u8 const data = m_bus->read_byte(address);
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LOG("dma_w data 0x%02x address 0x%08x\n", data, address);
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m_dma_w[channel](data);
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}
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// increment offset
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if (dma.cofs == 0xfff)
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{
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// advance to next page
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dma.cofs = 0;
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dma.ctag++;
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}
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else
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dma.cofs++;
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// decrement count
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dma.ctrc--;
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// set terminal count flag
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if (!dma.ctrc)
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{
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LOG("transfer complete\n");
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dma.cstat |= CS_TCZ;
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// TODO: terminal count interrupt?
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}
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if (BIT(m_gstat, (channel * 2) + 1))
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active = true;
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}
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if (active)
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m_dma_check->adjust(attotime::zero);
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}
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99
src/mame/machine/dmac_0448.h
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99
src/mame/machine/dmac_0448.h
Normal file
@ -0,0 +1,99 @@
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// license:BSD-3-Clause
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// copyright-holders:Patrick Mackinlay
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#ifndef MAME_MACHINE_DMAC_0448_H
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#define MAME_MACHINE_DMAC_0448_H
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#pragma once
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class dmac_0448_device : public device_t
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{
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public:
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dmac_0448_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock);
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// configuration
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template <typename T> void set_bus(T &&tag, int spacenum) { m_bus.set_tag(std::forward<T>(tag), spacenum); }
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auto out_int_cb() { return m_out_int.bind(); }
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template <unsigned Channel> auto dma_r_cb() { return m_dma_r[Channel].bind(); }
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template <unsigned Channel> auto dma_w_cb() { return m_dma_w[Channel].bind(); }
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// line handlers
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template <unsigned IRQ> void irq(int state) { set_irq_line(IRQ, state); }
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template <unsigned DRQ> void drq(int state) { set_drq_line(DRQ, state); }
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void map(address_map &map);
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protected:
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// device_t overrides
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virtual void device_start() override;
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virtual void device_reset() override;
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void set_irq_line(int number, int state);
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void set_drq_line(int channel, int state);
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u8 cstat_r() { return m_channel[m_gsel].cstat; }
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u8 ctrcl_r() { return u8(m_channel[m_gsel].ctrc >> 0); }
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u8 ctrcm_r() { return u8(m_channel[m_gsel].ctrc >> 8); }
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u8 ctrch_r() { return u8(m_channel[m_gsel].ctrc >> 16); }
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u8 ctag_r() { return m_channel[m_gsel].ctag; }
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u8 cwid_r() { return m_channel[m_gsel].cwid; }
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u8 cofsl_r() { return u8(m_channel[m_gsel].cofs >> 0); }
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u8 cofsh_r() { return u8(m_channel[m_gsel].cofs >> 8); }
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u16 cmap_r() { return m_channel[m_gsel].cmap[m_channel[m_gsel].ctag]; }
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u8 gstat_r() { return m_gstat; }
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void cctl_w(u8 data);
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void ctrcl_w(u8 data) { m_channel[m_gsel].ctrc = (m_channel[m_gsel].ctrc & 0xffff00U) | (u32(data) << 0); }
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void ctrcm_w(u8 data) { m_channel[m_gsel].ctrc = (m_channel[m_gsel].ctrc & 0xff00ffU) | (u32(data) << 8); }
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void ctrch_w(u8 data) { m_channel[m_gsel].ctrc = (m_channel[m_gsel].ctrc & 0x00ffffU) | (u32(data) << 16); }
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void ctag_w(u8 data) { m_channel[m_gsel].ctag = data; }
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void cwid_w(u8 data) { m_channel[m_gsel].cwid = data; }
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void cofsl_w(u8 data) { m_channel[m_gsel].cofs = (m_channel[m_gsel].cofs & 0xff00U) | (u16(data) << 0); }
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void cofsh_w(u8 data) { m_channel[m_gsel].cofs = (m_channel[m_gsel].cofs & 0x00ffU) | (u16(data & 0x0f) << 8); }
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void cmap_w(offs_t offset, u16 data, u16 mem_mask) { COMBINE_DATA(&m_channel[m_gsel].cmap[m_channel[m_gsel].ctag]); }
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void gsel_w(u8 data) { m_gsel = data; }
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void irq_check(void *ptr = nullptr, s32 param = 0);
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void dma_check(void *ptr = nullptr, s32 param = 0);
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required_address_space m_bus;
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devcb_write_line m_out_int;
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devcb_read8::array<4> m_dma_r;
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devcb_write8::array<4> m_dma_w;
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emu_timer *m_irq_check;
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emu_timer *m_dma_check;
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enum cstat_mask : u8
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{
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CS_ENABLE = 0x01, // channel enable
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CS_MODE = 0x02, // transfer to memory
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CS_RESET = 0x04, // reset channel
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CS_ZINTEN = 0x08, // terminal count interrupt?
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CS_APAD = 0x10, // auto pad
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CS_AFIX = 0x20,
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CS_A28 = 0x40,
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CS_TCZ = 0x80, // transfer count zero?
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};
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struct dma_channel
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{
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u8 cstat; // channel status
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u8 cctl; // channel control
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u32 ctrc; // channel counter
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u8 ctag; // channel tag
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u8 cwid; // channel width
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u16 cofs; // channel offset
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u16 cmap[256];
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}
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m_channel[4];
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u8 m_gsel; // channel select
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u8 m_gstat; // general status
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bool m_out_int_state;
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};
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DECLARE_DEVICE_TYPE(DMAC_0448, dmac_0448_device)
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#endif // MAME_MACHINE_DMAC_0448_H
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