From 794cc6ef69d3eeac760dc69f2fd6499750a88013 Mon Sep 17 00:00:00 2001 From: AJR Date: Tue, 23 Jan 2018 20:45:44 -0500 Subject: [PATCH] mcs51: Add DPTR, P0, P1, P2 and P3 to debug state registration --- src/devices/cpu/mcs51/mcs51.cpp | 9 +++++++-- src/devices/cpu/mcs51/mcs51.h | 3 ++- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/src/devices/cpu/mcs51/mcs51.cpp b/src/devices/cpu/mcs51/mcs51.cpp index 536565bbbe7..baccf731e14 100644 --- a/src/devices/cpu/mcs51/mcs51.cpp +++ b/src/devices/cpu/mcs51/mcs51.cpp @@ -2138,9 +2138,14 @@ void mcs51_cpu_device::device_start() state_add( MCS51_PSW, "PSW", PSW).formatstr("%02X"); state_add( MCS51_ACC, "A", ACC).formatstr("%02X"); state_add( MCS51_B, "B", B).formatstr("%02X"); - state_add( MCS51_DPH, "DPH", DPH).formatstr("%02X"); - state_add( MCS51_DPL, "DPL", DPL).formatstr("%02X"); + state_add( MCS51_DPTR, "DPTR", [this](){ return DPTR; }, [this](uint16_t dp){ SET_DPTR(dp); }).formatstr("%04X"); + state_add( MCS51_DPH, "DPH", DPH).noshow(); + state_add( MCS51_DPL, "DPL", DPL).noshow(); state_add( MCS51_IE, "IE", IE).formatstr("%02X"); + state_add( MCS51_P0, "P0", [this](){ return P0; }, [this](uint8_t p){ SET_P0(p); }).formatstr("%02X"); + state_add( MCS51_P1, "P1", [this](){ return P1; }, [this](uint8_t p){ SET_P1(p); }).formatstr("%02X"); + state_add( MCS51_P2, "P2", [this](){ return P2; }, [this](uint8_t p){ SET_P2(p); }).formatstr("%02X"); + state_add( MCS51_P3, "P3", [this](){ return P3; }, [this](uint8_t p){ SET_P3(p); }).formatstr("%02X"); state_add( MCS51_R0, "R0", m_rtemp).callimport().callexport().formatstr("%02X"); state_add( MCS51_R1, "R1", m_rtemp).callimport().callexport().formatstr("%02X"); state_add( MCS51_R2, "R2", m_rtemp).callimport().callexport().formatstr("%02X"); diff --git a/src/devices/cpu/mcs51/mcs51.h b/src/devices/cpu/mcs51/mcs51.h index f324e428ad5..698b424cf6d 100644 --- a/src/devices/cpu/mcs51/mcs51.h +++ b/src/devices/cpu/mcs51/mcs51.h @@ -41,7 +41,8 @@ enum { - MCS51_PC=1, MCS51_SP, MCS51_PSW, MCS51_ACC, MCS51_B, MCS51_DPH, MCS51_DPL, MCS51_IE, + MCS51_PC=1, MCS51_SP, MCS51_PSW, MCS51_ACC, MCS51_B, MCS51_DPTR, MCS51_DPH, MCS51_DPL, MCS51_IE, + MCS51_P0, MCS51_P1, MCS51_P2, MCS51_P3, MCS51_R0, MCS51_R1, MCS51_R2, MCS51_R3, MCS51_R4, MCS51_R5, MCS51_R6, MCS51_R7, MCS51_RB };