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Add preliminary emulation of the Rockwell A17XX chips
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src/emu/machine/ra17xx.c
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133
src/emu/machine/ra17xx.c
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/**********************************************************************
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Rockwell A17XX ROM, RAM and I/O chip
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Copyright Nicola Salmoria and the MAME Team.
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Visit http://mamedev.org for licensing and usage restrictions.
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A ROM of 2048 x 8 bits is addressed whenever the RRSEL line
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(ROM/RAM select) is 0. A RAM of 128 x 4 bit is addressed when
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RRSEL is 1. The 16 I/O ports are addressed when the WI/O line
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is 1, i.e. whenever the CPU executes an IOL instruction.
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There are two basic I/O instructions:
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SES = Select Enable Status and SOS = Select Output Status
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The lower 4 bits of the I/O address select one of 16 I/O lines.
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There are at most two A17XX per system, one for the lower
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ROM and RAM portion and one for the higher.
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I/O section instructions
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Menmonic I/O bus Accu Description
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------------------------------------------------------------------
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SES 0 S S 0 X X X 0 1 X X X Enable all outputs
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Acuu:3 <- I/O(BL)
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------------------------------------------------------------------
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SES 0 S S 0 X X X 0 0 X X X Disable all outputs
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Acuu:3 <- I/O(BL)
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------------------------------------------------------------------
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SOS 0 S S 0 X X X 1 1 X X X I/O(BL) <- 1
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Acuu:3 <- I/O(BL)
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------------------------------------------------------------------
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SOS 0 S S 0 X X X 1 0 X X X I/O(BL) <- 0
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Acuu:3 <- I/O(BL)
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This device emulation takes care of the I/O commands, not the
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ROM and RAM, because these are emulated using the generic MAME
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memory system.
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**********************************************************************/
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#include "emu.h"
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#include "machine/ra17xx.h"
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#define VERBOSE 1
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#if VERBOSE
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#define LOG(x) logerror x
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#else
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#define LOG(x)
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#endif
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/*************************************
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*
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* Device interface
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*
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*************************************/
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const device_type RA17XX = &device_creator<ra17xx_device>;
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ra17xx_device::ra17xx_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: device_t(mconfig, RA17XX, "Rockwell A17XX", tag, owner, clock, "ra17xx", __FILE__),
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m_line(),
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m_enable(false),
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m_iord(*this),
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m_iowr(*this)
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{
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}
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/**
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* @brief ra17xx_device::device_start device-specific startup
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*/
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void ra17xx_device::device_start()
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{
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m_iord.resolve();
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m_iowr.resolve();
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save_item(NAME(m_line));
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}
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/**
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* @brief ra17xx_device::device_reset device-specific reset
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*/
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void ra17xx_device::device_reset()
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{
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memset(m_line, 0, sizeof(m_line));
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}
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/*************************************
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*
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* Constants
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*
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*************************************/
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/*************************************
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*
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* Command access handlers
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*
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*************************************/
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WRITE8_MEMBER( ra17xx_device::io_w )
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{
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assert(offset < 16);
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m_bl = (data >> 4) & 15; // BL on the data bus most significant bits
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if (offset & 1) {
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// SOS command
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if (data & (1 << 3)) {
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m_line[m_bl] = 1; // enable output
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if (m_enable)
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m_iowr(m_bl, 1);
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} else {
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m_line[m_bl] = 0; // disable output
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if (m_enable)
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m_iowr(m_bl, 0);
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}
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} else {
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// SES command
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if (data & (1 << 3)) {
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// enable all outputs
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m_enable = true;
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for (int i = 0; i < 16; i++)
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m_iowr(i, m_line[i], 1);
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} else {
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// disable all outputs
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m_enable = false;
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}
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}
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}
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READ8_MEMBER( ra17xx_device::io_r )
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{
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assert(offset < 16);
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return (m_iord(m_bl) & 1) ? 0x0f : 0x07;
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}
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58
src/emu/machine/ra17xx.h
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58
src/emu/machine/ra17xx.h
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/**********************************************************************
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Rockwell RA17xx (e.g. A1752, A1753) ROM, RAM and I/O chip
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Juergen Buchmueller <pullmoll@t-online.de>
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The device integrates a 2048 x 8 ROM, a 128 x 4 RAM and
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and 16 I/O ports at one of the port ranges 00 ... 0f,
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20 ... 2f, 40 ... 4f or 60 ... 6f.
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**********************************************************************/
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#ifndef __RA17XX_H__
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#define __RA17XX_H__
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#include "device.h"
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/*************************************
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*
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* Device configuration macros
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*
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*************************************/
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/* Set the read line handler */
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#define MCFG_RA17XX_READ(_devcb) \
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ra17xx_device::set_iord(*device, DEVCB_##_devcb); \
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/* Set the write line handler */
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#define MCFG_RA17XX_WRITE(_devcb) \
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ra17xx_device::set_iowr(*device, DEVCB_##_devcb); \
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class ra17xx_device : public device_t
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{
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public:
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ra17xx_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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~ra17xx_device() {}
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DECLARE_READ8_MEMBER ( io_r );
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DECLARE_WRITE8_MEMBER( io_w );
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template<class _Object> static devcb_base &set_iord(device_t &device, _Object object) { return downcast<ra17xx_device &>(device).m_iord.set_callback(object); }
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template<class _Object> static devcb_base &set_iowr(device_t &device, _Object object) { return downcast<ra17xx_device &>(device).m_iowr.set_callback(object); }
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protected:
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// device-level overrides
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virtual void device_start();
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virtual void device_reset();
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private:
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UINT8 m_line[16]; //!< input/output flip-flops for 16 I/O lines
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UINT8 m_bl; //!< value of BL during the most recent output
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bool m_enable; //!< true if outputs are enabled
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devcb_read8 m_iord; //!< input line (read, offset = line, data = 0/1)
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devcb_write8 m_iowr; //!< output line (write, offset = line, data = 0/1)
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};
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extern const device_type RA17XX;
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#endif /* __RA17XX_H__ */
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