mirror of
https://github.com/holub/mame
synced 2025-04-23 08:49:55 +03:00
SH2: convert context struct to go through a pointer
This commit is contained in:
R. Belmont
parent
96d3879704
commit
7a3449f968
File diff suppressed because it is too large
Load Diff
@ -11,7 +11,7 @@
|
||||
#include "sh2.h"
|
||||
#include "sh2comn.h"
|
||||
|
||||
extern SH2 sh2;
|
||||
extern SH2 *sh2;
|
||||
|
||||
#define VERBOSE 0
|
||||
|
||||
@ -58,12 +58,12 @@ INLINE void WL(offs_t A, UINT32 V)
|
||||
|
||||
static void sh2_timer_resync(void)
|
||||
{
|
||||
int divider = div_tab[(sh2.m[5] >> 8) & 3];
|
||||
UINT64 cur_time = cpunum_gettotalcycles(sh2.cpu_number);
|
||||
int divider = div_tab[(sh2->m[5] >> 8) & 3];
|
||||
UINT64 cur_time = cpunum_gettotalcycles(sh2->cpu_number);
|
||||
|
||||
if(divider)
|
||||
sh2.frc += (cur_time - sh2.frc_base) >> divider;
|
||||
sh2.frc_base = cur_time;
|
||||
sh2->frc += (cur_time - sh2->frc_base) >> divider;
|
||||
sh2->frc_base = cur_time;
|
||||
}
|
||||
|
||||
static void sh2_timer_activate(void)
|
||||
@ -71,35 +71,35 @@ static void sh2_timer_activate(void)
|
||||
int max_delta = 0xfffff;
|
||||
UINT16 frc;
|
||||
|
||||
timer_adjust_oneshot(sh2.timer, attotime_never, 0);
|
||||
timer_adjust_oneshot(sh2->timer, attotime_never, 0);
|
||||
|
||||
frc = sh2.frc;
|
||||
if(!(sh2.m[4] & OCFA)) {
|
||||
UINT16 delta = sh2.ocra - frc;
|
||||
frc = sh2->frc;
|
||||
if(!(sh2->m[4] & OCFA)) {
|
||||
UINT16 delta = sh2->ocra - frc;
|
||||
if(delta < max_delta)
|
||||
max_delta = delta;
|
||||
}
|
||||
|
||||
if(!(sh2.m[4] & OCFB) && (sh2.ocra <= sh2.ocrb || !(sh2.m[4] & 0x010000))) {
|
||||
UINT16 delta = sh2.ocrb - frc;
|
||||
if(!(sh2->m[4] & OCFB) && (sh2->ocra <= sh2->ocrb || !(sh2->m[4] & 0x010000))) {
|
||||
UINT16 delta = sh2->ocrb - frc;
|
||||
if(delta < max_delta)
|
||||
max_delta = delta;
|
||||
}
|
||||
|
||||
if(!(sh2.m[4] & OVF) && !(sh2.m[4] & 0x010000)) {
|
||||
if(!(sh2->m[4] & OVF) && !(sh2->m[4] & 0x010000)) {
|
||||
int delta = 0x10000 - frc;
|
||||
if(delta < max_delta)
|
||||
max_delta = delta;
|
||||
}
|
||||
|
||||
if(max_delta != 0xfffff) {
|
||||
int divider = div_tab[(sh2.m[5] >> 8) & 3];
|
||||
int divider = div_tab[(sh2->m[5] >> 8) & 3];
|
||||
if(divider) {
|
||||
max_delta <<= divider;
|
||||
sh2.frc_base = cpunum_gettotalcycles(sh2.cpu_number);
|
||||
timer_adjust_oneshot(sh2.timer, ATTOTIME_IN_CYCLES(max_delta, sh2.cpu_number), sh2.cpu_number);
|
||||
sh2->frc_base = cpunum_gettotalcycles(sh2->cpu_number);
|
||||
timer_adjust_oneshot(sh2->timer, ATTOTIME_IN_CYCLES(max_delta, sh2->cpu_number), sh2->cpu_number);
|
||||
} else {
|
||||
logerror("SH2.%d: Timer event in %d cycles of external clock", sh2.cpu_number, max_delta);
|
||||
logerror("SH2.%d: Timer event in %d cycles of external clock", sh2->cpu_number, max_delta);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -112,20 +112,20 @@ TIMER_CALLBACK( sh2_timer_callback )
|
||||
cpuintrf_push_context(cpunum);
|
||||
sh2_timer_resync();
|
||||
|
||||
frc = sh2.frc;
|
||||
frc = sh2->frc;
|
||||
|
||||
if(frc == sh2.ocrb)
|
||||
sh2.m[4] |= OCFB;
|
||||
if(frc == sh2->ocrb)
|
||||
sh2->m[4] |= OCFB;
|
||||
|
||||
if(frc == 0x0000)
|
||||
sh2.m[4] |= OVF;
|
||||
sh2->m[4] |= OVF;
|
||||
|
||||
if(frc == sh2.ocra)
|
||||
if(frc == sh2->ocra)
|
||||
{
|
||||
sh2.m[4] |= OCFA;
|
||||
sh2->m[4] |= OCFA;
|
||||
|
||||
if(sh2.m[4] & 0x010000)
|
||||
sh2.frc = 0;
|
||||
if(sh2->m[4] & 0x010000)
|
||||
sh2->frc = 0;
|
||||
}
|
||||
|
||||
sh2_recalc_irq();
|
||||
@ -141,38 +141,38 @@ TIMER_CALLBACK( sh2_dmac_callback )
|
||||
|
||||
cpuintrf_push_context(cpunum);
|
||||
LOG(("SH2.%d: DMA %d complete\n", cpunum, dma));
|
||||
sh2.m[0x63+4*dma] |= 2;
|
||||
sh2.dma_timer_active[dma] = 0;
|
||||
sh2->m[0x63+4*dma] |= 2;
|
||||
sh2->dma_timer_active[dma] = 0;
|
||||
sh2_recalc_irq();
|
||||
cpuintrf_pop_context();
|
||||
}
|
||||
|
||||
static void sh2_dmac_check(int dma)
|
||||
{
|
||||
if(sh2.m[0x63+4*dma] & sh2.m[0x6c] & 1)
|
||||
if(sh2->m[0x63+4*dma] & sh2->m[0x6c] & 1)
|
||||
{
|
||||
if(!sh2.dma_timer_active[dma] && !(sh2.m[0x63+4*dma] & 2))
|
||||
if(!sh2->dma_timer_active[dma] && !(sh2->m[0x63+4*dma] & 2))
|
||||
{
|
||||
int incs, incd, size;
|
||||
UINT32 src, dst, count;
|
||||
incd = (sh2.m[0x63+4*dma] >> 14) & 3;
|
||||
incs = (sh2.m[0x63+4*dma] >> 12) & 3;
|
||||
size = (sh2.m[0x63+4*dma] >> 10) & 3;
|
||||
incd = (sh2->m[0x63+4*dma] >> 14) & 3;
|
||||
incs = (sh2->m[0x63+4*dma] >> 12) & 3;
|
||||
size = (sh2->m[0x63+4*dma] >> 10) & 3;
|
||||
if(incd == 3 || incs == 3)
|
||||
{
|
||||
logerror("SH2: DMA: bad increment values (%d, %d, %d, %04x)\n", incd, incs, size, sh2.m[0x63+4*dma]);
|
||||
logerror("SH2: DMA: bad increment values (%d, %d, %d, %04x)\n", incd, incs, size, sh2->m[0x63+4*dma]);
|
||||
return;
|
||||
}
|
||||
src = sh2.m[0x60+4*dma];
|
||||
dst = sh2.m[0x61+4*dma];
|
||||
count = sh2.m[0x62+4*dma];
|
||||
src = sh2->m[0x60+4*dma];
|
||||
dst = sh2->m[0x61+4*dma];
|
||||
count = sh2->m[0x62+4*dma];
|
||||
if(!count)
|
||||
count = 0x1000000;
|
||||
|
||||
LOG(("SH2: DMA %d start %x, %x, %x, %04x, %d, %d, %d\n", dma, src, dst, count, sh2.m[0x63+4*dma], incs, incd, size));
|
||||
LOG(("SH2: DMA %d start %x, %x, %x, %04x, %d, %d, %d\n", dma, src, dst, count, sh2->m[0x63+4*dma], incs, incd, size));
|
||||
|
||||
sh2.dma_timer_active[dma] = 1;
|
||||
timer_adjust_oneshot(sh2.dma_timer[dma], ATTOTIME_IN_CYCLES(2*count+1, sh2.cpu_number), (sh2.cpu_number<<1)|dma);
|
||||
sh2->dma_timer_active[dma] = 1;
|
||||
timer_adjust_oneshot(sh2->dma_timer[dma], ATTOTIME_IN_CYCLES(2*count+1, sh2->cpu_number), (sh2->cpu_number<<1)|dma);
|
||||
|
||||
src &= AM;
|
||||
dst &= AM;
|
||||
@ -248,19 +248,19 @@ static void sh2_dmac_check(int dma)
|
||||
}
|
||||
else
|
||||
{
|
||||
if(sh2.dma_timer_active[dma])
|
||||
if(sh2->dma_timer_active[dma])
|
||||
{
|
||||
logerror("SH2: DMA %d cancelled in-flight", dma);
|
||||
timer_adjust_oneshot(sh2.dma_timer[dma], attotime_never, 0);
|
||||
sh2.dma_timer_active[dma] = 0;
|
||||
timer_adjust_oneshot(sh2->dma_timer[dma], attotime_never, 0);
|
||||
sh2->dma_timer_active[dma] = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
WRITE32_HANDLER( sh2_internal_w )
|
||||
{
|
||||
UINT32 old = sh2.m[offset];
|
||||
COMBINE_DATA(sh2.m+offset);
|
||||
UINT32 old = sh2->m[offset];
|
||||
COMBINE_DATA(sh2->m+offset);
|
||||
|
||||
// if(offset != 0x20)
|
||||
// logerror("sh2_internal_w: Write %08x (%x), %08x @ %08x\n", 0xfffffe00+offset*4, offset, data, mem_mask);
|
||||
@ -271,20 +271,20 @@ WRITE32_HANDLER( sh2_internal_w )
|
||||
case 0x04: // TIER, FTCSR, FRC
|
||||
if((mem_mask & 0x00ffffff) != 0)
|
||||
sh2_timer_resync();
|
||||
logerror("SH2.%d: TIER write %04x @ %04x\n", sh2.cpu_number, data >> 16, mem_mask>>16);
|
||||
sh2.m[4] = (sh2.m[4] & ~(ICF|OCFA|OCFB|OVF)) | (old & sh2.m[4] & (ICF|OCFA|OCFB|OVF));
|
||||
COMBINE_DATA(&sh2.frc);
|
||||
logerror("SH2.%d: TIER write %04x @ %04x\n", sh2->cpu_number, data >> 16, mem_mask>>16);
|
||||
sh2->m[4] = (sh2->m[4] & ~(ICF|OCFA|OCFB|OVF)) | (old & sh2->m[4] & (ICF|OCFA|OCFB|OVF));
|
||||
COMBINE_DATA(&sh2->frc);
|
||||
if((mem_mask & 0x00ffffff) != 0)
|
||||
sh2_timer_activate();
|
||||
sh2_recalc_irq();
|
||||
break;
|
||||
case 0x05: // OCRx, TCR, TOCR
|
||||
logerror("SH2.%d: TCR write %08x @ %08x\n", sh2.cpu_number, data, mem_mask);
|
||||
logerror("SH2.%d: TCR write %08x @ %08x\n", sh2->cpu_number, data, mem_mask);
|
||||
sh2_timer_resync();
|
||||
if(sh2.m[5] & 0x10)
|
||||
sh2.ocrb = (sh2.ocrb & (~mem_mask >> 16)) | ((data & mem_mask) >> 16);
|
||||
if(sh2->m[5] & 0x10)
|
||||
sh2->ocrb = (sh2->ocrb & (~mem_mask >> 16)) | ((data & mem_mask) >> 16);
|
||||
else
|
||||
sh2.ocra = (sh2.ocra & (~mem_mask >> 16)) | ((data & mem_mask) >> 16);
|
||||
sh2->ocra = (sh2->ocra & (~mem_mask >> 16)) | ((data & mem_mask) >> 16);
|
||||
sh2_timer_activate();
|
||||
break;
|
||||
|
||||
@ -321,25 +321,25 @@ WRITE32_HANDLER( sh2_internal_w )
|
||||
break;
|
||||
case 0x41: // DVDNT
|
||||
{
|
||||
INT32 a = sh2.m[0x41];
|
||||
INT32 b = sh2.m[0x40];
|
||||
INT32 a = sh2->m[0x41];
|
||||
INT32 b = sh2->m[0x40];
|
||||
LOG(("SH2 #%d div+mod %d/%d\n", cpu_getactivecpu(), a, b));
|
||||
if (b)
|
||||
{
|
||||
sh2.m[0x45] = a / b;
|
||||
sh2.m[0x44] = a % b;
|
||||
sh2->m[0x45] = a / b;
|
||||
sh2->m[0x44] = a % b;
|
||||
}
|
||||
else
|
||||
{
|
||||
sh2.m[0x42] |= 0x00010000;
|
||||
sh2.m[0x45] = 0x7fffffff;
|
||||
sh2.m[0x44] = 0x7fffffff;
|
||||
sh2->m[0x42] |= 0x00010000;
|
||||
sh2->m[0x45] = 0x7fffffff;
|
||||
sh2->m[0x44] = 0x7fffffff;
|
||||
sh2_recalc_irq();
|
||||
}
|
||||
break;
|
||||
}
|
||||
case 0x42: // DVCR
|
||||
sh2.m[0x42] = (sh2.m[0x42] & ~0x00001000) | (old & sh2.m[0x42] & 0x00010000);
|
||||
sh2->m[0x42] = (sh2->m[0x42] & ~0x00001000) | (old & sh2->m[0x42] & 0x00010000);
|
||||
sh2_recalc_irq();
|
||||
break;
|
||||
case 0x43: // VCRDIV
|
||||
@ -349,30 +349,30 @@ WRITE32_HANDLER( sh2_internal_w )
|
||||
break;
|
||||
case 0x45: // DVDNTL
|
||||
{
|
||||
INT64 a = sh2.m[0x45] | ((UINT64)(sh2.m[0x44]) << 32);
|
||||
INT64 b = (INT32)sh2.m[0x40];
|
||||
INT64 a = sh2->m[0x45] | ((UINT64)(sh2->m[0x44]) << 32);
|
||||
INT64 b = (INT32)sh2->m[0x40];
|
||||
LOG(("SH2 #%d div+mod %lld/%lld\n", cpu_getactivecpu(), a, b));
|
||||
if (b)
|
||||
{
|
||||
INT64 q = a / b;
|
||||
if (q != (INT32)q)
|
||||
{
|
||||
sh2.m[0x42] |= 0x00010000;
|
||||
sh2.m[0x45] = 0x7fffffff;
|
||||
sh2.m[0x44] = 0x7fffffff;
|
||||
sh2->m[0x42] |= 0x00010000;
|
||||
sh2->m[0x45] = 0x7fffffff;
|
||||
sh2->m[0x44] = 0x7fffffff;
|
||||
sh2_recalc_irq();
|
||||
}
|
||||
else
|
||||
{
|
||||
sh2.m[0x45] = q;
|
||||
sh2.m[0x44] = a % b;
|
||||
sh2->m[0x45] = q;
|
||||
sh2->m[0x44] = a % b;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
sh2.m[0x42] |= 0x00010000;
|
||||
sh2.m[0x45] = 0x7fffffff;
|
||||
sh2.m[0x44] = 0x7fffffff;
|
||||
sh2->m[0x42] |= 0x00010000;
|
||||
sh2->m[0x45] = 0x7fffffff;
|
||||
sh2->m[0x44] = 0x7fffffff;
|
||||
sh2_recalc_irq();
|
||||
}
|
||||
break;
|
||||
@ -383,20 +383,20 @@ WRITE32_HANDLER( sh2_internal_w )
|
||||
case 0x61: // DAR0
|
||||
break;
|
||||
case 0x62: // DTCR0
|
||||
sh2.m[0x62] &= 0xffffff;
|
||||
sh2->m[0x62] &= 0xffffff;
|
||||
break;
|
||||
case 0x63: // CHCR0
|
||||
sh2.m[0x63] = (sh2.m[0x63] & ~2) | (old & sh2.m[0x63] & 2);
|
||||
sh2->m[0x63] = (sh2->m[0x63] & ~2) | (old & sh2->m[0x63] & 2);
|
||||
sh2_dmac_check(0);
|
||||
break;
|
||||
case 0x64: // SAR1
|
||||
case 0x65: // DAR1
|
||||
break;
|
||||
case 0x66: // DTCR1
|
||||
sh2.m[0x66] &= 0xffffff;
|
||||
sh2->m[0x66] &= 0xffffff;
|
||||
break;
|
||||
case 0x67: // CHCR1
|
||||
sh2.m[0x67] = (sh2.m[0x67] & ~2) | (old & sh2.m[0x67] & 2);
|
||||
sh2->m[0x67] = (sh2->m[0x67] & ~2) | (old & sh2->m[0x67] & 2);
|
||||
sh2_dmac_check(1);
|
||||
break;
|
||||
case 0x68: // VCRDMA0
|
||||
@ -404,7 +404,7 @@ WRITE32_HANDLER( sh2_internal_w )
|
||||
sh2_recalc_irq();
|
||||
break;
|
||||
case 0x6c: // DMAOR
|
||||
sh2.m[0x6c] = (sh2.m[0x6c] & ~6) | (old & sh2.m[0x6c] & 6);
|
||||
sh2->m[0x6c] = (sh2->m[0x6c] & ~6) | (old & sh2->m[0x6c] & 6);
|
||||
sh2_dmac_check(0);
|
||||
sh2_dmac_check(1);
|
||||
break;
|
||||
@ -432,32 +432,32 @@ READ32_HANDLER( sh2_internal_r )
|
||||
{
|
||||
case 0x04: // TIER, FTCSR, FRC
|
||||
if ( mem_mask == 0x00ff0000 )
|
||||
if ( sh2.ftcsr_read_callback != NULL )
|
||||
sh2.ftcsr_read_callback( (sh2.m[4] & 0xffff0000) | sh2.frc );
|
||||
if ( sh2->ftcsr_read_callback != NULL )
|
||||
sh2->ftcsr_read_callback( (sh2->m[4] & 0xffff0000) | sh2->frc );
|
||||
sh2_timer_resync();
|
||||
return (sh2.m[4] & 0xffff0000) | sh2.frc;
|
||||
return (sh2->m[4] & 0xffff0000) | sh2->frc;
|
||||
case 0x05: // OCRx, TCR, TOCR
|
||||
if(sh2.m[5] & 0x10)
|
||||
return (sh2.ocrb << 16) | (sh2.m[5] & 0xffff);
|
||||
if(sh2->m[5] & 0x10)
|
||||
return (sh2->ocrb << 16) | (sh2->m[5] & 0xffff);
|
||||
else
|
||||
return (sh2.ocra << 16) | (sh2.m[5] & 0xffff);
|
||||
return (sh2->ocra << 16) | (sh2->m[5] & 0xffff);
|
||||
case 0x06: // ICR
|
||||
return sh2.icr << 16;
|
||||
return sh2->icr << 16;
|
||||
|
||||
case 0x38: // ICR, IPRA
|
||||
return (sh2.m[0x38] & 0x7fffffff) | (sh2.nmi_line_state == ASSERT_LINE ? 0 : 0x80000000);
|
||||
return (sh2->m[0x38] & 0x7fffffff) | (sh2->nmi_line_state == ASSERT_LINE ? 0 : 0x80000000);
|
||||
|
||||
case 0x78: // BCR1
|
||||
return sh2.is_slave ? 0x00008000 : 0;
|
||||
return sh2->is_slave ? 0x00008000 : 0;
|
||||
|
||||
case 0x41: // dvdntl mirrors
|
||||
case 0x47:
|
||||
return sh2.m[0x45];
|
||||
return sh2->m[0x45];
|
||||
|
||||
case 0x46: // dvdnth mirror
|
||||
return sh2.m[0x44];
|
||||
return sh2->m[0x44];
|
||||
}
|
||||
return sh2.m[offset];
|
||||
return sh2->m[offset];
|
||||
}
|
||||
|
||||
void sh2_set_frt_input(int cpunum, int state)
|
||||
@ -471,14 +471,14 @@ void sh2_set_frt_input(int cpunum, int state)
|
||||
|
||||
cpuintrf_push_context(cpunum);
|
||||
|
||||
if(sh2.frt_input == state) {
|
||||
if(sh2->frt_input == state) {
|
||||
cpuintrf_pop_context();
|
||||
return;
|
||||
}
|
||||
|
||||
sh2.frt_input = state;
|
||||
sh2->frt_input = state;
|
||||
|
||||
if(sh2.m[5] & 0x8000) {
|
||||
if(sh2->m[5] & 0x8000) {
|
||||
if(state == CLEAR_LINE) {
|
||||
cpuintrf_pop_context();
|
||||
return;
|
||||
@ -491,9 +491,9 @@ void sh2_set_frt_input(int cpunum, int state)
|
||||
}
|
||||
|
||||
sh2_timer_resync();
|
||||
sh2.icr = sh2.frc;
|
||||
sh2.m[4] |= ICF;
|
||||
logerror("SH2.%d: ICF activated (%x)\n", sh2.cpu_number, sh2.pc & AM);
|
||||
sh2->icr = sh2->frc;
|
||||
sh2->m[4] |= ICF;
|
||||
logerror("SH2.%d: ICF activated (%x)\n", sh2->cpu_number, sh2->pc & AM);
|
||||
sh2_recalc_irq();
|
||||
cpuintrf_pop_context();
|
||||
}
|
||||
@ -502,9 +502,9 @@ void sh2_set_irq_line(int irqline, int state)
|
||||
{
|
||||
if (irqline == INPUT_LINE_NMI)
|
||||
{
|
||||
if (sh2.nmi_line_state == state)
|
||||
if (sh2->nmi_line_state == state)
|
||||
return;
|
||||
sh2.nmi_line_state = state;
|
||||
sh2->nmi_line_state = state;
|
||||
|
||||
if( state == CLEAR_LINE )
|
||||
{
|
||||
@ -518,21 +518,21 @@ void sh2_set_irq_line(int irqline, int state)
|
||||
}
|
||||
else
|
||||
{
|
||||
if (sh2.irq_line_state[irqline] == state)
|
||||
if (sh2->irq_line_state[irqline] == state)
|
||||
return;
|
||||
sh2.irq_line_state[irqline] = state;
|
||||
sh2->irq_line_state[irqline] = state;
|
||||
|
||||
if( state == CLEAR_LINE )
|
||||
{
|
||||
LOG(("SH-2 #%d cleared irq #%d\n", cpu_getactivecpu(), irqline));
|
||||
sh2.pending_irq &= ~(1 << irqline);
|
||||
sh2->pending_irq &= ~(1 << irqline);
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG(("SH-2 #%d assert irq #%d\n", cpu_getactivecpu(), irqline));
|
||||
sh2.pending_irq |= 1 << irqline;
|
||||
if(sh2.delay)
|
||||
sh2.test_irq = 1;
|
||||
sh2->pending_irq |= 1 << irqline;
|
||||
if(sh2->delay)
|
||||
sh2->test_irq = 1;
|
||||
else
|
||||
CHECK_PENDING_IRQ("sh2_set_irq_line");
|
||||
}
|
||||
@ -545,43 +545,43 @@ void sh2_recalc_irq(void)
|
||||
int level;
|
||||
|
||||
// Timer irqs
|
||||
if((sh2.m[4]>>8) & sh2.m[4] & (ICF|OCFA|OCFB|OVF))
|
||||
if((sh2->m[4]>>8) & sh2->m[4] & (ICF|OCFA|OCFB|OVF))
|
||||
{
|
||||
level = (sh2.m[0x18] >> 24) & 15;
|
||||
level = (sh2->m[0x18] >> 24) & 15;
|
||||
if(level > irq)
|
||||
{
|
||||
int mask = (sh2.m[4]>>8) & sh2.m[4];
|
||||
int mask = (sh2->m[4]>>8) & sh2->m[4];
|
||||
irq = level;
|
||||
if(mask & ICF)
|
||||
vector = (sh2.m[0x19] >> 8) & 0x7f;
|
||||
vector = (sh2->m[0x19] >> 8) & 0x7f;
|
||||
else if(mask & (OCFA|OCFB))
|
||||
vector = sh2.m[0x19] & 0x7f;
|
||||
vector = sh2->m[0x19] & 0x7f;
|
||||
else
|
||||
vector = (sh2.m[0x1a] >> 24) & 0x7f;
|
||||
vector = (sh2->m[0x1a] >> 24) & 0x7f;
|
||||
}
|
||||
}
|
||||
|
||||
// DMA irqs
|
||||
if((sh2.m[0x63] & 6) == 6) {
|
||||
level = (sh2.m[0x38] >> 8) & 15;
|
||||
if((sh2->m[0x63] & 6) == 6) {
|
||||
level = (sh2->m[0x38] >> 8) & 15;
|
||||
if(level > irq) {
|
||||
irq = level;
|
||||
vector = (sh2.m[0x68] >> 24) & 0x7f;
|
||||
vector = (sh2->m[0x68] >> 24) & 0x7f;
|
||||
}
|
||||
}
|
||||
|
||||
if((sh2.m[0x67] & 6) == 6) {
|
||||
level = (sh2.m[0x38] >> 8) & 15;
|
||||
if((sh2->m[0x67] & 6) == 6) {
|
||||
level = (sh2->m[0x38] >> 8) & 15;
|
||||
if(level > irq) {
|
||||
irq = level;
|
||||
vector = (sh2.m[0x6a] >> 24) & 0x7f;
|
||||
vector = (sh2->m[0x6a] >> 24) & 0x7f;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
sh2.internal_irq_level = irq;
|
||||
sh2.internal_irq_vector = vector;
|
||||
sh2.test_irq = 1;
|
||||
sh2->internal_irq_level = irq;
|
||||
sh2->internal_irq_vector = vector;
|
||||
sh2->test_irq = 1;
|
||||
}
|
||||
|
||||
void sh2_exception(const char *message, int irqline)
|
||||
@ -590,25 +590,25 @@ void sh2_exception(const char *message, int irqline)
|
||||
|
||||
if (irqline != 16)
|
||||
{
|
||||
if (irqline <= ((sh2.sr >> 4) & 15)) /* If the cpu forbids this interrupt */
|
||||
if (irqline <= ((sh2->sr >> 4) & 15)) /* If the cpu forbids this interrupt */
|
||||
return;
|
||||
|
||||
// if this is an sh2 internal irq, use its vector
|
||||
if (sh2.internal_irq_level == irqline)
|
||||
if (sh2->internal_irq_level == irqline)
|
||||
{
|
||||
vector = sh2.internal_irq_vector;
|
||||
vector = sh2->internal_irq_vector;
|
||||
LOG(("SH-2 #%d exception #%d (internal vector: $%x) after [%s]\n", cpu_getactivecpu(), irqline, vector, message));
|
||||
}
|
||||
else
|
||||
{
|
||||
if(sh2.m[0x38] & 0x00010000)
|
||||
if(sh2->m[0x38] & 0x00010000)
|
||||
{
|
||||
vector = sh2.irq_callback(irqline);
|
||||
vector = sh2->irq_callback(irqline);
|
||||
LOG(("SH-2 #%d exception #%d (external vector: $%x) after [%s]\n", cpu_getactivecpu(), irqline, vector, message));
|
||||
}
|
||||
else
|
||||
{
|
||||
sh2.irq_callback(irqline);
|
||||
sh2->irq_callback(irqline);
|
||||
vector = 64 + irqline/2;
|
||||
LOG(("SH-2 #%d exception #%d (autovector: $%x) after [%s]\n", cpu_getactivecpu(), irqline, vector, message));
|
||||
}
|
||||
@ -620,68 +620,71 @@ void sh2_exception(const char *message, int irqline)
|
||||
LOG(("SH-2 #%d nmi exception (autovector: $%x) after [%s]\n", cpu_getactivecpu(), vector, message));
|
||||
}
|
||||
|
||||
sh2.r[15] -= 4;
|
||||
WL( sh2.r[15], sh2.sr ); /* push SR onto stack */
|
||||
sh2.r[15] -= 4;
|
||||
WL( sh2.r[15], sh2.pc ); /* push PC onto stack */
|
||||
sh2->r[15] -= 4;
|
||||
WL( sh2->r[15], sh2->sr ); /* push SR onto stack */
|
||||
sh2->r[15] -= 4;
|
||||
WL( sh2->r[15], sh2->pc ); /* push PC onto stack */
|
||||
|
||||
/* set I flags in SR */
|
||||
if (irqline > SH2_INT_15)
|
||||
sh2.sr = sh2.sr | I;
|
||||
sh2->sr = sh2->sr | I;
|
||||
else
|
||||
sh2.sr = (sh2.sr & ~I) | (irqline << 4);
|
||||
sh2->sr = (sh2->sr & ~I) | (irqline << 4);
|
||||
|
||||
/* fetch PC */
|
||||
sh2.pc = RL( sh2.vbr + vector * 4 );
|
||||
change_pc(sh2.pc & AM);
|
||||
sh2->pc = RL( sh2->vbr + vector * 4 );
|
||||
change_pc(sh2->pc & AM);
|
||||
}
|
||||
|
||||
void sh2_common_init(int index, int clock, const void *config, int (*irqcallback)(int))
|
||||
{
|
||||
const struct sh2_config *conf = config;
|
||||
|
||||
sh2.timer = timer_alloc(sh2_timer_callback, NULL);
|
||||
timer_adjust_oneshot(sh2.timer, attotime_never, 0);
|
||||
sh2 = (SH2 *)auto_malloc(sizeof(SH2));
|
||||
memset(sh2, 0, sizeof(SH2));
|
||||
|
||||
sh2.dma_timer[0] = timer_alloc(sh2_dmac_callback, NULL);
|
||||
timer_adjust_oneshot(sh2.dma_timer[0], attotime_never, 0);
|
||||
sh2->timer = timer_alloc(sh2_timer_callback, NULL);
|
||||
timer_adjust_oneshot(sh2->timer, attotime_never, 0);
|
||||
|
||||
sh2.dma_timer[1] = timer_alloc(sh2_dmac_callback, NULL);
|
||||
timer_adjust_oneshot(sh2.dma_timer[1], attotime_never, 0);
|
||||
sh2->dma_timer[0] = timer_alloc(sh2_dmac_callback, NULL);
|
||||
timer_adjust_oneshot(sh2->dma_timer[0], attotime_never, 0);
|
||||
|
||||
sh2.m = auto_malloc(0x200);
|
||||
sh2->dma_timer[1] = timer_alloc(sh2_dmac_callback, NULL);
|
||||
timer_adjust_oneshot(sh2->dma_timer[1], attotime_never, 0);
|
||||
|
||||
sh2->m = auto_malloc(0x200);
|
||||
|
||||
if(conf)
|
||||
sh2.is_slave = conf->is_slave;
|
||||
sh2->is_slave = conf->is_slave;
|
||||
else
|
||||
sh2.is_slave = 0;
|
||||
sh2->is_slave = 0;
|
||||
|
||||
sh2.cpu_number = index;
|
||||
sh2.irq_callback = irqcallback;
|
||||
sh2->cpu_number = index;
|
||||
sh2->irq_callback = irqcallback;
|
||||
|
||||
state_save_register_item("sh2", index, sh2.pc);
|
||||
state_save_register_item("sh2", index, sh2.r[15]);
|
||||
state_save_register_item("sh2", index, sh2.sr);
|
||||
state_save_register_item("sh2", index, sh2.pr);
|
||||
state_save_register_item("sh2", index, sh2.gbr);
|
||||
state_save_register_item("sh2", index, sh2.vbr);
|
||||
state_save_register_item("sh2", index, sh2.mach);
|
||||
state_save_register_item("sh2", index, sh2.macl);
|
||||
state_save_register_item("sh2", index, sh2.r[ 0]);
|
||||
state_save_register_item("sh2", index, sh2.r[ 1]);
|
||||
state_save_register_item("sh2", index, sh2.r[ 2]);
|
||||
state_save_register_item("sh2", index, sh2.r[ 3]);
|
||||
state_save_register_item("sh2", index, sh2.r[ 4]);
|
||||
state_save_register_item("sh2", index, sh2.r[ 5]);
|
||||
state_save_register_item("sh2", index, sh2.r[ 6]);
|
||||
state_save_register_item("sh2", index, sh2.r[ 7]);
|
||||
state_save_register_item("sh2", index, sh2.r[ 8]);
|
||||
state_save_register_item("sh2", index, sh2.r[ 9]);
|
||||
state_save_register_item("sh2", index, sh2.r[10]);
|
||||
state_save_register_item("sh2", index, sh2.r[11]);
|
||||
state_save_register_item("sh2", index, sh2.r[12]);
|
||||
state_save_register_item("sh2", index, sh2.r[13]);
|
||||
state_save_register_item("sh2", index, sh2.r[14]);
|
||||
state_save_register_item("sh2", index, sh2.ea);
|
||||
state_save_register_item("sh2", index, sh2->pc);
|
||||
state_save_register_item("sh2", index, sh2->r[15]);
|
||||
state_save_register_item("sh2", index, sh2->sr);
|
||||
state_save_register_item("sh2", index, sh2->pr);
|
||||
state_save_register_item("sh2", index, sh2->gbr);
|
||||
state_save_register_item("sh2", index, sh2->vbr);
|
||||
state_save_register_item("sh2", index, sh2->mach);
|
||||
state_save_register_item("sh2", index, sh2->macl);
|
||||
state_save_register_item("sh2", index, sh2->r[ 0]);
|
||||
state_save_register_item("sh2", index, sh2->r[ 1]);
|
||||
state_save_register_item("sh2", index, sh2->r[ 2]);
|
||||
state_save_register_item("sh2", index, sh2->r[ 3]);
|
||||
state_save_register_item("sh2", index, sh2->r[ 4]);
|
||||
state_save_register_item("sh2", index, sh2->r[ 5]);
|
||||
state_save_register_item("sh2", index, sh2->r[ 6]);
|
||||
state_save_register_item("sh2", index, sh2->r[ 7]);
|
||||
state_save_register_item("sh2", index, sh2->r[ 8]);
|
||||
state_save_register_item("sh2", index, sh2->r[ 9]);
|
||||
state_save_register_item("sh2", index, sh2->r[10]);
|
||||
state_save_register_item("sh2", index, sh2->r[11]);
|
||||
state_save_register_item("sh2", index, sh2->r[12]);
|
||||
state_save_register_item("sh2", index, sh2->r[13]);
|
||||
state_save_register_item("sh2", index, sh2->r[14]);
|
||||
state_save_register_item("sh2", index, sh2->ea);
|
||||
}
|
||||
|
||||
|
||||
@ -38,23 +38,23 @@ enum {
|
||||
#define CHECK_PENDING_IRQ(message) \
|
||||
do { \
|
||||
int irq = -1; \
|
||||
if (sh2.pending_irq & (1 << 0)) irq = 0; \
|
||||
if (sh2.pending_irq & (1 << 1)) irq = 1; \
|
||||
if (sh2.pending_irq & (1 << 2)) irq = 2; \
|
||||
if (sh2.pending_irq & (1 << 3)) irq = 3; \
|
||||
if (sh2.pending_irq & (1 << 4)) irq = 4; \
|
||||
if (sh2.pending_irq & (1 << 5)) irq = 5; \
|
||||
if (sh2.pending_irq & (1 << 6)) irq = 6; \
|
||||
if (sh2.pending_irq & (1 << 7)) irq = 7; \
|
||||
if (sh2.pending_irq & (1 << 8)) irq = 8; \
|
||||
if (sh2.pending_irq & (1 << 9)) irq = 9; \
|
||||
if (sh2.pending_irq & (1 << 10)) irq = 10; \
|
||||
if (sh2.pending_irq & (1 << 11)) irq = 11; \
|
||||
if (sh2.pending_irq & (1 << 12)) irq = 12; \
|
||||
if (sh2.pending_irq & (1 << 13)) irq = 13; \
|
||||
if (sh2.pending_irq & (1 << 14)) irq = 14; \
|
||||
if (sh2.pending_irq & (1 << 15)) irq = 15; \
|
||||
if ((sh2.internal_irq_level != -1) && (sh2.internal_irq_level > irq)) irq = sh2.internal_irq_level; \
|
||||
if (sh2->pending_irq & (1 << 0)) irq = 0; \
|
||||
if (sh2->pending_irq & (1 << 1)) irq = 1; \
|
||||
if (sh2->pending_irq & (1 << 2)) irq = 2; \
|
||||
if (sh2->pending_irq & (1 << 3)) irq = 3; \
|
||||
if (sh2->pending_irq & (1 << 4)) irq = 4; \
|
||||
if (sh2->pending_irq & (1 << 5)) irq = 5; \
|
||||
if (sh2->pending_irq & (1 << 6)) irq = 6; \
|
||||
if (sh2->pending_irq & (1 << 7)) irq = 7; \
|
||||
if (sh2->pending_irq & (1 << 8)) irq = 8; \
|
||||
if (sh2->pending_irq & (1 << 9)) irq = 9; \
|
||||
if (sh2->pending_irq & (1 << 10)) irq = 10; \
|
||||
if (sh2->pending_irq & (1 << 11)) irq = 11; \
|
||||
if (sh2->pending_irq & (1 << 12)) irq = 12; \
|
||||
if (sh2->pending_irq & (1 << 13)) irq = 13; \
|
||||
if (sh2->pending_irq & (1 << 14)) irq = 14; \
|
||||
if (sh2->pending_irq & (1 << 15)) irq = 15; \
|
||||
if ((sh2->internal_irq_level != -1) && (sh2->internal_irq_level > irq)) irq = sh2->internal_irq_level; \
|
||||
if (irq >= 0) \
|
||||
sh2_exception(message,irq); \
|
||||
} while(0)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user