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arm: Eliminate spurious LSL #32 shifts from disassembly (nw)
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7a3a0a4243
@ -21,7 +21,7 @@ void arm_disassembler::WriteImmediateOperand( std::ostream &stream, uint32_t opc
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util::stream_format( stream, ", #$%x", imm );
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}
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void arm_disassembler::WriteDataProcessingOperand( std::ostream &stream, uint32_t opcode, int printOp0, int printOp1, int printOp2 ) const
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void arm_disassembler::WriteDataProcessingOperand( std::ostream &stream, uint32_t opcode, bool printOp0, bool printOp1) const
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{
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/* ccccctttmmmm */
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static const char *const pRegOp[4] = { "LSL","LSR","ASR","ROR" };
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@ -40,20 +40,23 @@ void arm_disassembler::WriteDataProcessingOperand( std::ostream &stream, uint32_
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}
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/* Register Op2 */
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if (printOp2)
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util::stream_format(stream, "R%d, ", (opcode>>0)&0xf);
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util::stream_format(stream, "%s ", pRegOp[(opcode>>5)&3]);
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util::stream_format(stream, "R%d", (opcode>>0)&0xf);
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int shiftop = (opcode >> 5) & 3;
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if( opcode&0x10 ) /* Shift amount specified in bottom bits of RS */
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{
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util::stream_format( stream, "R%d", (opcode>>8)&0xf );
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util::stream_format(stream, ", %s R%d", pRegOp[shiftop], (opcode >> 8) & 0xf);
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}
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else /* Shift amount immediate 5 bit unsigned integer */
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{
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int c=(opcode>>7)&0x1f;
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if( c==0 ) c = 32;
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util::stream_format( stream, "#%d", c );
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int c = (opcode >> 7) & 0x1f;
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if (c == 0)
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{
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if (shiftop == 0)
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return;
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c = 32;
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}
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util::stream_format( stream, ", %s #%d", pRegOp[shiftop], c);
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}
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}
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@ -62,21 +65,26 @@ void arm_disassembler::WriteRegisterOperand1( std::ostream &stream, uint32_t opc
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/* ccccctttmmmm */
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static const char *const pRegOp[4] = { "LSL","LSR","ASR","ROR" };
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int shiftop = (opcode >> 5) & 3;
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util::stream_format(
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stream,
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", R%d %s ", /* Operand 1 register, Operand 2 register, shift type */
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(opcode>> 0)&0xf,
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pRegOp[(opcode>>5)&3]);
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", R%d", /* Operand 1 register, Operand 2 register */
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(opcode >> 0) & 0xf);
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if( opcode&0x10 ) /* Shift amount specified in bottom bits of RS */
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{
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util::stream_format( stream, "R%d", (opcode>>7)&0xf );
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util::stream_format(stream, " %s R%d", pRegOp[shiftop], (opcode >> 7) & 0xf);
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}
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else /* Shift amount immediate 5 bit unsigned integer */
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{
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int c=(opcode>>7)&0x1f;
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if( c==0 ) c = 32;
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util::stream_format( stream, "#%d", c );
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int c = (opcode >> 7) & 0x1f;
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if (c == 0)
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{
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if (shiftop == 0)
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return;
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c = 32;
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}
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util::stream_format(stream, " %s #%d", pRegOp[shiftop], c);
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}
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} /* WriteRegisterOperand */
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@ -184,20 +192,20 @@ offs_t arm_disassembler::disassemble(std::ostream &stream, offs_t pc, const data
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case 0x07:
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case 0x0c:
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case 0x0e:
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WriteDataProcessingOperand(stream, opcode, 1, 1, 1);
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WriteDataProcessingOperand(stream, opcode, true, true);
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break;
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case 0x08:
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case 0x09:
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case 0x0a:
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case 0x0b:
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WriteDataProcessingOperand(stream, opcode, 0, 1, 1);
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WriteDataProcessingOperand(stream, opcode, false, true);
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break;
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case 0x0d:
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/* look for mov pc,lr */
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if (((opcode >> 12) & 0x0f) == 15 && ((opcode >> 0) & 0x0f) == 14 && (opcode & 0x02000000) == 0)
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dasmflags = STEP_OUT;
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case 0x0f:
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WriteDataProcessingOperand(stream, opcode, 1, 0, 1);
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WriteDataProcessingOperand(stream, opcode, true, false);
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break;
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}
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}
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@ -12,10 +12,10 @@ public:
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virtual offs_t disassemble(std::ostream &stream, offs_t pc, const data_buffer &opcodes, const data_buffer ¶ms) override;
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private:
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void WriteImmediateOperand( std::ostream &stream, uint32_t opcode ) const;
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void WriteDataProcessingOperand( std::ostream &stream, uint32_t opcode, int printOp0, int printOp1, int printOp2 ) const;
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void WriteRegisterOperand1( std::ostream &stream, uint32_t opcode ) const;
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void WriteBranchAddress( std::ostream &stream, uint32_t pc, uint32_t opcode ) const;
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void WriteImmediateOperand(std::ostream &stream, uint32_t opcode) const;
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void WriteDataProcessingOperand(std::ostream &stream, uint32_t opcode, bool printOp0, bool printOp1) const;
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void WriteRegisterOperand1(std::ostream &stream, uint32_t opcode) const;
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void WriteBranchAddress(std::ostream &stream, uint32_t pc, uint32_t opcode) const;
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void WritePadding(std::ostream &stream, std::streampos start_position) const;
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};
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