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arm: Eliminate spurious LSL #32 shifts from disassembly (nw)

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This commit is contained in:
AJR 2018-04-07 18:43:39 -04:00
parent 1a0fae9b4c
commit 7a3a0a4243
2 changed files with 31 additions and 23 deletions
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46
src/devices/cpu/arm/armdasm.cpp
View File

@ -21,7 +21,7 @@ void arm_disassembler::WriteImmediateOperand( std::ostream &stream, uint32_t opc
util::stream_format( stream, ", #$%x", imm ); util::stream_format( stream, ", #$%x", imm );
} }
void arm_disassembler::WriteDataProcessingOperand( std::ostream &stream, uint32_t opcode, int printOp0, int printOp1, int printOp2 ) const void arm_disassembler::WriteDataProcessingOperand( std::ostream &stream, uint32_t opcode, bool printOp0, bool printOp1) const
{ {
/* ccccctttmmmm */ /* ccccctttmmmm */
static const char *const pRegOp[4] = { "LSL","LSR","ASR","ROR" }; static const char *const pRegOp[4] = { "LSL","LSR","ASR","ROR" };
@ -40,20 +40,23 @@ void arm_disassembler::WriteDataProcessingOperand( std::ostream &stream, uint32_
} }
/* Register Op2 */ /* Register Op2 */
if (printOp2) util::stream_format(stream, "R%d", (opcode>>0)&0xf);
util::stream_format(stream, "R%d, ", (opcode>>0)&0xf);
util::stream_format(stream, "%s ", pRegOp[(opcode>>5)&3]);
int shiftop = (opcode >> 5) & 3;
if( opcode&0x10 ) /* Shift amount specified in bottom bits of RS */ if( opcode&0x10 ) /* Shift amount specified in bottom bits of RS */
{ {
util::stream_format( stream, "R%d", (opcode>>8)&0xf ); util::stream_format(stream, ", %s R%d", pRegOp[shiftop], (opcode >> 8) & 0xf);
} }
else /* Shift amount immediate 5 bit unsigned integer */ else /* Shift amount immediate 5 bit unsigned integer */
{ {
int c=(opcode>>7)&0x1f; int c = (opcode >> 7) & 0x1f;
if( c==0 ) c = 32; if (c == 0)
util::stream_format( stream, "#%d", c ); {
if (shiftop == 0)
return;
c = 32;
}
util::stream_format( stream, ", %s #%d", pRegOp[shiftop], c);
} }
} }
@ -62,21 +65,26 @@ void arm_disassembler::WriteRegisterOperand1( std::ostream &stream, uint32_t opc
/* ccccctttmmmm */ /* ccccctttmmmm */
static const char *const pRegOp[4] = { "LSL","LSR","ASR","ROR" }; static const char *const pRegOp[4] = { "LSL","LSR","ASR","ROR" };
int shiftop = (opcode >> 5) & 3;
util::stream_format( util::stream_format(
stream, stream,
", R%d %s ", /* Operand 1 register, Operand 2 register, shift type */ ", R%d", /* Operand 1 register, Operand 2 register */
(opcode>> 0)&0xf, (opcode >> 0) & 0xf);
pRegOp[(opcode>>5)&3]);
if( opcode&0x10 ) /* Shift amount specified in bottom bits of RS */ if( opcode&0x10 ) /* Shift amount specified in bottom bits of RS */
{ {
util::stream_format( stream, "R%d", (opcode>>7)&0xf ); util::stream_format(stream, " %s R%d", pRegOp[shiftop], (opcode >> 7) & 0xf);
} }
else /* Shift amount immediate 5 bit unsigned integer */ else /* Shift amount immediate 5 bit unsigned integer */
{ {
int c=(opcode>>7)&0x1f; int c = (opcode >> 7) & 0x1f;
if( c==0 ) c = 32; if (c == 0)
util::stream_format( stream, "#%d", c ); {
if (shiftop == 0)
return;
c = 32;
}
util::stream_format(stream, " %s #%d", pRegOp[shiftop], c);
} }
} /* WriteRegisterOperand */ } /* WriteRegisterOperand */
@ -184,20 +192,20 @@ offs_t arm_disassembler::disassemble(std::ostream &stream, offs_t pc, const data
case 0x07: case 0x07:
case 0x0c: case 0x0c:
case 0x0e: case 0x0e:
WriteDataProcessingOperand(stream, opcode, 1, 1, 1); WriteDataProcessingOperand(stream, opcode, true, true);
break; break;
case 0x08: case 0x08:
case 0x09: case 0x09:
case 0x0a: case 0x0a:
case 0x0b: case 0x0b:
WriteDataProcessingOperand(stream, opcode, 0, 1, 1); WriteDataProcessingOperand(stream, opcode, false, true);
break; break;
case 0x0d: case 0x0d:
/* look for mov pc,lr */ /* look for mov pc,lr */
if (((opcode >> 12) & 0x0f) == 15 && ((opcode >> 0) & 0x0f) == 14 && (opcode & 0x02000000) == 0) if (((opcode >> 12) & 0x0f) == 15 && ((opcode >> 0) & 0x0f) == 14 && (opcode & 0x02000000) == 0)
dasmflags = STEP_OUT; dasmflags = STEP_OUT;
case 0x0f: case 0x0f:
WriteDataProcessingOperand(stream, opcode, 1, 0, 1); WriteDataProcessingOperand(stream, opcode, true, false);
break; break;
} }
} }

8
src/devices/cpu/arm/armdasm.h
View File

@ -12,10 +12,10 @@ public:
virtual offs_t disassemble(std::ostream &stream, offs_t pc, const data_buffer &opcodes, const data_buffer &params) override; virtual offs_t disassemble(std::ostream &stream, offs_t pc, const data_buffer &opcodes, const data_buffer &params) override;
private: private:
void WriteImmediateOperand( std::ostream &stream, uint32_t opcode ) const; void WriteImmediateOperand(std::ostream &stream, uint32_t opcode) const;
void WriteDataProcessingOperand( std::ostream &stream, uint32_t opcode, int printOp0, int printOp1, int printOp2 ) const; void WriteDataProcessingOperand(std::ostream &stream, uint32_t opcode, bool printOp0, bool printOp1) const;
void WriteRegisterOperand1( std::ostream &stream, uint32_t opcode ) const; void WriteRegisterOperand1(std::ostream &stream, uint32_t opcode) const;
void WriteBranchAddress( std::ostream &stream, uint32_t pc, uint32_t opcode ) const; void WriteBranchAddress(std::ostream &stream, uint32_t pc, uint32_t opcode) const;
void WritePadding(std::ostream &stream, std::streampos start_position) const; void WritePadding(std::ostream &stream, std::streampos start_position) const;
}; };