Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-04-19 23:12:11 +03:00
Code Issues Actions 6 Packages Projects Releases Wiki Activity

vrc4373: Added correct PCI config map (nw)

Browse Source 
iteagle_fpga: Cleaned up eeprom initialization and rtc names (nw)
This commit is contained in:
Ted Green 2016-05-20 10:17:14 -06:00
parent 2a16c60648
commit 7a68b6504b
3 changed files with 58 additions and 74 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/devices/machine/vrc4373.cpp
View File

@ -10,7 +10,7 @@ const device_type VRC4373 = &device_creator<vrc4373_device>;
DEVICE_ADDRESS_MAP_START(config_map, 32, vrc4373_device)
AM_RANGE(0x40, 0x43) AM_READWRITE (pcictrl_r, pcictrl_w)
AM_INHERIT_FROM(pci_host_device::config_map)
AM_INHERIT_FROM(pci_bridge_device::config_map)
ADDRESS_MAP_END
// cpu i/f map

114
src/mame/machine/iteagle_fpga.cpp
View File

@ -12,6 +12,10 @@
const device_type ITEAGLE_FPGA = &device_creator<iteagle_fpga_device>;
MACHINE_CONFIG_FRAGMENT(iteagle_fpga)
MCFG_NVRAM_ADD_0FILL("eagle2_rtc")
MACHINE_CONFIG_END
DEVICE_ADDRESS_MAP_START(fpga_map, 32, iteagle_fpga_device)
AM_RANGE(0x000, 0x01f) AM_READWRITE(fpga_r, fpga_w)
ADDRESS_MAP_END
@ -26,12 +30,21 @@ ADDRESS_MAP_END
iteagle_fpga_device::iteagle_fpga_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: pci_device(mconfig, ITEAGLE_FPGA, "ITEagle FPGA", tag, owner, clock, "iteagle_fpga", __FILE__),
device_nvram_interface(mconfig, *this), m_version(0), m_seq_init(0)
m_rtc(*this, "eagle2_rtc"), m_version(0), m_seq_init(0)
{
}
machine_config_constructor iteagle_fpga_device::device_mconfig_additions() const
{
return MACHINE_CONFIG_NAME(iteagle_fpga);
}
void iteagle_fpga_device::device_start()
{
// RTC M48T02
m_rtc_regs.resize(0x800 / 4);
m_rtc->set_base(m_rtc_regs.data(), m_rtc_regs.size() * sizeof(UINT32));
pci_device::device_start();
status = 0x5555;
command = 0x5555;
@ -40,7 +53,7 @@ void iteagle_fpga_device::device_start()
// fpga defaults to base address 0x00000300
bank_infos[0].adr = 0x00000300 & (~(bank_infos[0].size - 1));
add_map(sizeof(m_rtc_regs), M_MEM, FUNC(iteagle_fpga_device::rtc_map));
add_map(m_rtc_regs.size() * sizeof(UINT32), M_MEM, FUNC(iteagle_fpga_device::rtc_map));
// RTC defaults to base address 0x000c0000
bank_infos[1].adr = 0x000c0000 & (~(bank_infos[1].size - 1));
@ -380,35 +393,6 @@ WRITE32_MEMBER( iteagle_fpga_device::fpga_w )
//*************************************
//* RTC M48T02
//*************************************
//-------------------------------------------------
// nvram_default - called to initialize NVRAM to
// its default state
//-------------------------------------------------
void iteagle_fpga_device::nvram_default()
{
memset(m_rtc_regs, 0x0, sizeof(m_rtc_regs));
}
//-------------------------------------------------
// nvram_read - called to read NVRAM from the
// .nv file
//-------------------------------------------------
void iteagle_fpga_device::nvram_read(emu_file &file)
{
file.read(m_rtc_regs, sizeof(m_rtc_regs));
}
//-------------------------------------------------
// nvram_write - called to write NVRAM to the
// .nv file
//-------------------------------------------------
void iteagle_fpga_device::nvram_write(emu_file &file)
{
file.write(m_rtc_regs, sizeof(m_rtc_regs));
}
READ32_MEMBER( iteagle_fpga_device::rtc_r )
{
UINT32 result = m_rtc_regs[offset];
@ -483,33 +467,11 @@ WRITE32_MEMBER( iteagle_fpga_device::ram_w )
const device_type ITEAGLE_EEPROM = &device_creator<iteagle_eeprom_device>;
DEVICE_ADDRESS_MAP_START(eeprom_map, 32, iteagle_eeprom_device)
AM_RANGE(0x0000, 0x000F) AM_READWRITE(eeprom_r, eeprom_w) AM_SHARE("eeprom")
AM_RANGE(0x0000, 0x000F) AM_READWRITE(eeprom_r, eeprom_w)
ADDRESS_MAP_END
// When corrupt writes 0x3=2, 0x3e=2, 0xa=0, 0x30=0
// 0x4 = HW Version - 6-8 is GREEN board PCB, 9 is RED board PCB
// 0x5 = Serial Num + top byte of 0x4
// 0x6 = OperID
// 0xe = SW Version
// 0xf = 0x01 for extra courses
// 0x3e = 0x0002 for good nvram
// 0x3f = checksum
static const UINT16 iteagle_default_eeprom[0x40] =
{
0xd000,0x0022,0x0000,0x0003,0x1209,0x1111,0x2222,0x1234,
0x0000,0x0000,0x0000,0x0000,0xcd00,0x0000,0x0000,0x0001,
0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0002,0x0000
};
static MACHINE_CONFIG_FRAGMENT( iteagle_eeprom )
MACHINE_CONFIG_FRAGMENT( iteagle_eeprom )
MCFG_EEPROM_SERIAL_93C46_ADD("eeprom")
MCFG_EEPROM_SERIAL_DATA(iteagle_default_eeprom, 0x80)
MACHINE_CONFIG_END
machine_config_constructor iteagle_eeprom_device::device_mconfig_additions() const
@ -521,10 +483,41 @@ iteagle_eeprom_device::iteagle_eeprom_device(const machine_config &mconfig, cons
: pci_device(mconfig, ITEAGLE_EEPROM, "ITEagle EEPROM AT93C46", tag, owner, clock, "eeprom", __FILE__),
m_eeprom(*this, "eeprom"), m_sw_version(0), m_hw_version(0)
{
// When corrupt writes 0x3=2, 0x3e=2, 0xa=0, 0x30=0
// 0x4 = HW Version - 6-8 is GREEN board PCB, 9 is RED board PCB
// 0x5 = Serial Num + top byte of 0x4
// 0x6 = OperID
// 0xe = SW Version
// 0xf = 0x01 for extra courses
// 0x3e = 0x0002 for good nvram
// 0x3f = checksum
iteagle_default_eeprom =
{
0xd000,0x0022,0x0000,0x0003,0x1209,0x1111,0x2222,0x1234,
0x0000,0x0000,0x0000,0x0000,0xcd00,0x0000,0x0000,0x0001,
0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0002,0x0000
};
}
void iteagle_eeprom_device::device_start()
{
// EEPROM: Set software version and calc crc
iteagle_default_eeprom[0xe] = m_sw_version;
iteagle_default_eeprom[0x4] = (iteagle_default_eeprom[0x4] & 0xff00) | m_hw_version;
UINT16 checkSum = 0;
for (int i=0; i<0x3f; i++) {
checkSum += iteagle_default_eeprom[i];
//logerror("eeprom init i: %x data: %04x\n", i, iteagle_default_eeprom[i]);
}
iteagle_default_eeprom[0x3f] = checkSum;
eeprom_base_device::static_set_default_data(m_eeprom, iteagle_default_eeprom.data(), 0x80);
pci_device::device_start();
skip_map_regs(1);
add_map(0x10, M_IO, FUNC(iteagle_eeprom_device::eeprom_map));
@ -532,15 +525,6 @@ void iteagle_eeprom_device::device_start()
void iteagle_eeprom_device::device_reset()
{
// Set software version and calc crc
m_eeprom->write(0xe, m_sw_version);
m_eeprom->write(0x4, (m_eeprom->read(0x4)&0xff00) | m_hw_version);
UINT16 checkSum = 0;
for (int i=0; i<0x3f; i++) {
checkSum += m_eeprom->read(i);
//logerror("eeprom init i: %x data: %04x\n", i, m_eeprom->read(i));
}
m_eeprom->write(0x3f, checkSum);
pci_device::device_reset();
}
@ -604,7 +588,7 @@ WRITE32_MEMBER( iteagle_eeprom_device::eeprom_w )
// Attached Peripheral Controller
//************************************
static MACHINE_CONFIG_FRAGMENT(eagle1)
MACHINE_CONFIG_FRAGMENT(eagle1)
MCFG_NVRAM_ADD_0FILL("eagle1_rtc")
MACHINE_CONFIG_END

16
src/mame/machine/iteagle_fpga.h
View File

@ -30,11 +30,14 @@
MCFG_PCI_DEVICE_ADD(_tag, ITEAGLE_PERIPH, 0x1080C693, 0x00, 0x060100, 0x00)
class iteagle_fpga_device : public pci_device,
public device_nvram_interface
class iteagle_fpga_device : public pci_device
{
public:
iteagle_fpga_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
virtual machine_config_constructor device_mconfig_additions() const override;
required_device<nvram_device> m_rtc;
void set_init_info(int version, int seq_init) {m_version=version; m_seq_init=seq_init;}
void set_irq_info(const char *tag, const int irq_num, const int serial_num) {
m_cpu_tag = tag; m_irq_num = irq_num; m_serial_irq_num = serial_num;}
@ -44,11 +47,6 @@ protected:
virtual void device_reset() override;
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override;
// device_nvram_interface overrides
virtual void nvram_default() override;
virtual void nvram_read(emu_file &file) override;
virtual void nvram_write(emu_file &file) override;
private:
emu_timer * m_timer;
const char *m_cpu_tag;
@ -57,7 +55,7 @@ private:
int m_serial_irq_num;
UINT32 m_fpga_regs[0x20/4];
UINT32 m_rtc_regs[0x800/4];
std::vector<UINT32> m_rtc_regs;
UINT32 m_ram[0x20000/4];
UINT32 m_prev_reg;
@ -110,6 +108,8 @@ private:
UINT16 m_sw_version;
UINT8 m_hw_version;
std::vector<UINT16> iteagle_default_eeprom; // 0x40
DECLARE_ADDRESS_MAP(eeprom_map, 32);
DECLARE_READ32_MEMBER( eeprom_r );
DECLARE_WRITE32_MEMBER( eeprom_w );