diff --git a/scripts/src/cpu.lua b/scripts/src/cpu.lua index b3eaac479bf..f8503ac9056 100644 --- a/scripts/src/cpu.lua +++ b/scripts/src/cpu.lua @@ -1283,6 +1283,7 @@ if (CPUS["MIPS3"]~=null) then MAME_DIR .. "src/devices/cpu/mips/mips3fe.cpp", MAME_DIR .. "src/devices/cpu/mips/mips3fe.h", MAME_DIR .. "src/devices/cpu/mips/mips3drc.cpp", + MAME_DIR .. "src/devices/cpu/mips/o2dprintf.hxx", MAME_DIR .. "src/devices/cpu/mips/ps2vu.cpp", MAME_DIR .. "src/devices/cpu/mips/ps2vu.h", MAME_DIR .. "src/devices/cpu/mips/ps2vif1.cpp", diff --git a/scripts/target/mame/mess.lua b/scripts/target/mame/mess.lua index ebfd5317226..45b5d3d5224 100644 --- a/scripts/target/mame/mess.lua +++ b/scripts/target/mame/mess.lua @@ -3027,12 +3027,16 @@ files { MAME_DIR .. "src/mame/machine/hpc3.h", MAME_DIR .. "src/mame/machine/ioc2.cpp", MAME_DIR .. "src/mame/machine/ioc2.h", + MAME_DIR .. "src/mame/machine/mace.cpp", + MAME_DIR .. "src/mame/machine/mace.h", MAME_DIR .. "src/mame/drivers/iris3130.cpp", MAME_DIR .. "src/mame/drivers/4dpi.cpp", MAME_DIR .. "src/mame/drivers/indigo.cpp", MAME_DIR .. "src/mame/drivers/indy_indigo2.cpp", MAME_DIR .. "src/mame/video/newport.cpp", MAME_DIR .. "src/mame/video/newport.h", + MAME_DIR .. "src/mame/video/crime.cpp", + MAME_DIR .. "src/mame/video/crime.h", } createMESSProjects(_target, _subtarget, "sharp") diff --git a/src/devices/cpu/mips/mips3.cpp b/src/devices/cpu/mips/mips3.cpp index 6989e262492..cf76633abec 100644 --- a/src/devices/cpu/mips/mips3.cpp +++ b/src/devices/cpu/mips/mips3.cpp @@ -425,7 +425,7 @@ void mips3_device::device_start() uint32_t flags = 0; /* initialize the UML generator */ - m_drcuml = std::make_unique(*this, m_cache, flags, 8, m_data_bits, 2); + m_drcuml = std::make_unique(*this, m_cache, flags, 8, 32, 2); /* add symbols for our stuff */ m_drcuml->symbol_add(&m_core->pc, sizeof(m_core->pc), "pc"); @@ -5020,6 +5020,10 @@ void mips3_device::burn_cycles(int32_t cycles) execute_burn(cycles); } +#if ENABLE_O2_DPRINTF +#include "o2dprintf.hxx" +#endif + void mips3_device::execute_run() { if (m_isdrc) @@ -5110,7 +5114,9 @@ void mips3_device::execute_run() break; case 0x02: /* J */ ABSPC(LIMMVAL); break; - case 0x03: /* JAL */ ABSPCL(LIMMVAL,31); break; + case 0x03: /* JAL */ + ABSPCL(LIMMVAL,31); + break; case 0x04: /* BEQ */ if (RSVAL64 == RTVAL64) ADDPC(SIMMVAL); break; case 0x05: /* BNE */ if (RSVAL64 != RTVAL64) ADDPC(SIMMVAL); break; case 0x06: /* BLEZ */ if ((int64_t)RSVAL64 <= 0) ADDPC(SIMMVAL); break; @@ -5257,6 +5263,13 @@ void mips3_device::execute_run() m_delayslot = false; m_core->icount--; +#if ENABLE_O2_DPRINTF + if (m_core->pc == 0xbfc04d74) + { + do_o2_dprintf((uint32_t)m_core->r[4], (uint32_t)m_core->r[5], (uint32_t)m_core->r[6], (uint32_t)m_core->r[7], (uint32_t)m_core->r[29] + 16); + } +#endif + #if ENABLE_EE_ELF_LOADER static bool elf_loaded = false; if (had_delay && m_core->pc < 0x80000000 && m_core->pc >= 0x00100000 && !elf_loaded) diff --git a/src/devices/cpu/mips/mips3.h b/src/devices/cpu/mips/mips3.h index a5d603c15fb..fad1782d16a 100644 --- a/src/devices/cpu/mips/mips3.h +++ b/src/devices/cpu/mips/mips3.h @@ -20,6 +20,8 @@ MIPS III/IV emulator. #include "cpu/drcuml.h" #include "ps2vu.h" +#define ENABLE_O2_DPRINTF (0) + DECLARE_DEVICE_TYPE(R4000BE, r4000be_device) DECLARE_DEVICE_TYPE(R4000LE, r4000le_device) DECLARE_DEVICE_TYPE(R4400BE, r4400be_device) @@ -636,6 +638,9 @@ private: void log_opcode_desc(const opcode_desc *desclist, int indent); void load_elf(); +#if ENABLE_O2_DPRINTF + void do_o2_dprintf(uint32_t fmt_addr, uint32_t a1, uint32_t a2, uint32_t a3, uint32_t stack); +#endif }; @@ -643,7 +648,7 @@ class r4000be_device : public mips3_device { public: // construction/destruction r4000be_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) - : mips3_device(mconfig, R4000BE, tag, owner, clock, MIPS3_TYPE_R4000, ENDIANNESS_BIG, 32) + : mips3_device(mconfig, R4000BE, tag, owner, clock, MIPS3_TYPE_R4000, ENDIANNESS_BIG, 64) { } }; @@ -652,7 +657,7 @@ class r4000le_device : public mips3_device { public: // construction/destruction r4000le_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) - : mips3_device(mconfig, R4000LE, tag, owner, clock, MIPS3_TYPE_R4000, ENDIANNESS_LITTLE, 32) + : mips3_device(mconfig, R4000LE, tag, owner, clock, MIPS3_TYPE_R4000, ENDIANNESS_LITTLE, 64) { } }; @@ -661,7 +666,7 @@ class r4400be_device : public mips3_device { public: // construction/destruction r4400be_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) - : mips3_device(mconfig, R4400BE, tag, owner, clock, MIPS3_TYPE_R4400, ENDIANNESS_BIG, 32) + : mips3_device(mconfig, R4400BE, tag, owner, clock, MIPS3_TYPE_R4400, ENDIANNESS_BIG, 64) { } }; @@ -670,7 +675,7 @@ class r4400le_device : public mips3_device { public: // construction/destruction r4400le_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) - : mips3_device(mconfig, R4400LE, tag, owner, clock, MIPS3_TYPE_R4400, ENDIANNESS_LITTLE, 32) + : mips3_device(mconfig, R4400LE, tag, owner, clock, MIPS3_TYPE_R4400, ENDIANNESS_LITTLE, 32) // Should be 64 bits { } }; @@ -679,7 +684,7 @@ class vr4300be_device : public mips3_device { public: // construction/destruction vr4300be_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) - : mips3_device(mconfig, VR4300BE, tag, owner, clock, MIPS3_TYPE_VR4300, ENDIANNESS_BIG, 32) // checkme + : mips3_device(mconfig, VR4300BE, tag, owner, clock, MIPS3_TYPE_VR4300, ENDIANNESS_BIG, 32) { } }; @@ -688,7 +693,7 @@ class vr4300le_device : public mips3_device { public: // construction/destruction vr4300le_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) - : mips3_device(mconfig, VR4300LE, tag, owner, clock, MIPS3_TYPE_VR4300, ENDIANNESS_LITTLE, 32) // checkme + : mips3_device(mconfig, VR4300LE, tag, owner, clock, MIPS3_TYPE_VR4300, ENDIANNESS_LITTLE, 32) { } }; @@ -697,7 +702,7 @@ class vr4310be_device : public mips3_device { public: // construction/destruction vr4310be_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) - : mips3_device(mconfig, VR4310BE, tag, owner, clock, MIPS3_TYPE_VR4300, ENDIANNESS_BIG, 32) // checkme + : mips3_device(mconfig, VR4310BE, tag, owner, clock, MIPS3_TYPE_VR4300, ENDIANNESS_BIG, 32) { } }; @@ -706,7 +711,7 @@ class vr4310le_device : public mips3_device { public: // construction/destruction vr4310le_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) - : mips3_device(mconfig, VR4310LE, tag, owner, clock, MIPS3_TYPE_VR4300, ENDIANNESS_LITTLE, 32) // checkme + : mips3_device(mconfig, VR4310LE, tag, owner, clock, MIPS3_TYPE_VR4300, ENDIANNESS_LITTLE, 32) { } }; @@ -715,7 +720,7 @@ class r4600be_device : public mips3_device { public: // construction/destruction r4600be_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) - : mips3_device(mconfig, R4600BE, tag, owner, clock, MIPS3_TYPE_R4600, ENDIANNESS_BIG, 32) // checkme + : mips3_device(mconfig, R4600BE, tag, owner, clock, MIPS3_TYPE_R4600, ENDIANNESS_BIG, 64) { } }; @@ -724,7 +729,7 @@ class r4600le_device : public mips3_device { public: // construction/destruction r4600le_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) - : mips3_device(mconfig, R4600LE, tag, owner, clock, MIPS3_TYPE_R4600, ENDIANNESS_LITTLE, 32) // checkme + : mips3_device(mconfig, R4600LE, tag, owner, clock, MIPS3_TYPE_R4600, ENDIANNESS_LITTLE, 32) // Should be 64 bits { } }; @@ -733,7 +738,7 @@ class r4650be_device : public mips3_device { public: // construction/destruction r4650be_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) - : mips3_device(mconfig, R4650BE, tag, owner, clock, MIPS3_TYPE_R4650, ENDIANNESS_BIG, 32) // checkme + : mips3_device(mconfig, R4650BE, tag, owner, clock, MIPS3_TYPE_R4650, ENDIANNESS_BIG, 32) // Should be 64 bits { } }; @@ -742,7 +747,7 @@ class r4650le_device : public mips3_device { public: // construction/destruction r4650le_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) - : mips3_device(mconfig, R4650LE, tag, owner, clock, MIPS3_TYPE_R4650, ENDIANNESS_LITTLE, 32) // checkme + : mips3_device(mconfig, R4650LE, tag, owner, clock, MIPS3_TYPE_R4650, ENDIANNESS_LITTLE, 32) // Should be 64 bits { } }; @@ -751,7 +756,7 @@ class r4700be_device : public mips3_device { public: // construction/destruction r4700be_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) - : mips3_device(mconfig, R4700BE, tag, owner, clock, MIPS3_TYPE_R4700, ENDIANNESS_BIG, 32) // checkme + : mips3_device(mconfig, R4700BE, tag, owner, clock, MIPS3_TYPE_R4700, ENDIANNESS_BIG, 32) // Should be 64 bits { } }; @@ -760,7 +765,7 @@ class r4700le_device : public mips3_device { public: // construction/destruction r4700le_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) - : mips3_device(mconfig, R4700LE, tag, owner, clock, MIPS3_TYPE_R4700, ENDIANNESS_LITTLE, 32) // checkme + : mips3_device(mconfig, R4700LE, tag, owner, clock, MIPS3_TYPE_R4700, ENDIANNESS_LITTLE, 32) // Should be 64 bits { } }; @@ -769,7 +774,7 @@ class tx4925be_device : public mips3_device { public: // construction/destruction tx4925be_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) - : mips3_device(mconfig, TX4925BE, tag, owner, clock, MIPS3_TYPE_TX4925, ENDIANNESS_BIG, 32) // checkme + : mips3_device(mconfig, TX4925BE, tag, owner, clock, MIPS3_TYPE_TX4925, ENDIANNESS_BIG, 32) // Should be 64 bits { } }; @@ -778,7 +783,7 @@ class tx4925le_device : public mips3_device { public: // construction/destruction tx4925le_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) - : mips3_device(mconfig, TX4925LE, tag, owner, clock, MIPS3_TYPE_TX4925, ENDIANNESS_LITTLE, 32) // checkme + : mips3_device(mconfig, TX4925LE, tag, owner, clock, MIPS3_TYPE_TX4925, ENDIANNESS_LITTLE, 32) // Should be 64 bits { } }; @@ -787,7 +792,7 @@ class r5000be_device : public mips3_device { public: // construction/destruction r5000be_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) - : mips3_device(mconfig, R5000BE, tag, owner, clock, MIPS3_TYPE_R5000, ENDIANNESS_BIG, 32) // checkme + : mips3_device(mconfig, R5000BE, tag, owner, clock, MIPS3_TYPE_R5000, ENDIANNESS_BIG, 64) { } }; @@ -796,7 +801,7 @@ class r5000le_device : public mips3_device { public: // construction/destruction r5000le_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) - : mips3_device(mconfig, R5000LE, tag, owner, clock, MIPS3_TYPE_R5000, ENDIANNESS_LITTLE, 32) // checkme + : mips3_device(mconfig, R5000LE, tag, owner, clock, MIPS3_TYPE_R5000, ENDIANNESS_LITTLE, 32) // Should be 64 bits { } }; @@ -805,7 +810,8 @@ class vr5500be_device : public mips3_device { public: // construction/destruction vr5500be_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) - : mips3_device(mconfig, VR5500BE, tag, owner, clock, MIPS3_TYPE_R5000, ENDIANNESS_BIG, 32) { + : mips3_device(mconfig, VR5500BE, tag, owner, clock, MIPS3_TYPE_R5000, ENDIANNESS_BIG, 32) // Should be 64 bits + { } }; @@ -813,7 +819,7 @@ class vr5500le_device : public mips3_device { public: // construction/destruction vr5500le_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) - : mips3_device(mconfig, VR5500LE, tag, owner, clock, MIPS3_TYPE_R5000, ENDIANNESS_LITTLE, 32) // checkme + : mips3_device(mconfig, VR5500LE, tag, owner, clock, MIPS3_TYPE_R5000, ENDIANNESS_LITTLE, 32) // Should be 64 bits { } }; @@ -884,7 +890,7 @@ class qed5271be_device : public mips3_device { public: // construction/destruction qed5271be_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) - : mips3_device(mconfig, QED5271BE, tag, owner, clock, MIPS3_TYPE_QED5271, ENDIANNESS_BIG, 32) // checkme + : mips3_device(mconfig, QED5271BE, tag, owner, clock, MIPS3_TYPE_QED5271, ENDIANNESS_BIG, 32) // Should be 64 bits { } }; @@ -893,7 +899,7 @@ class qed5271le_device : public mips3_device { public: // construction/destruction qed5271le_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) - : mips3_device(mconfig, QED5271LE, tag, owner, clock, MIPS3_TYPE_QED5271, ENDIANNESS_LITTLE, 32) // checkme + : mips3_device(mconfig, QED5271LE, tag, owner, clock, MIPS3_TYPE_QED5271, ENDIANNESS_LITTLE, 32) // Should be 64 bits { } }; @@ -902,7 +908,7 @@ class rm7000be_device : public mips3_device { public: // construction/destruction rm7000be_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) - : mips3_device(mconfig, RM7000BE, tag, owner, clock, MIPS3_TYPE_RM7000, ENDIANNESS_BIG, 32) // checkme + : mips3_device(mconfig, RM7000BE, tag, owner, clock, MIPS3_TYPE_RM7000, ENDIANNESS_BIG, 32) // Should be 64 bits { } }; @@ -911,7 +917,7 @@ class rm7000le_device : public mips3_device { public: // construction/destruction rm7000le_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) - : mips3_device(mconfig, RM7000LE, tag, owner, clock, MIPS3_TYPE_RM7000, ENDIANNESS_LITTLE, 32) // checkme + : mips3_device(mconfig, RM7000LE, tag, owner, clock, MIPS3_TYPE_RM7000, ENDIANNESS_LITTLE, 32) // Should be 64 bits { } }; diff --git a/src/devices/cpu/mips/o2dprintf.hxx b/src/devices/cpu/mips/o2dprintf.hxx new file mode 100644 index 00000000000..6074c9d44dc --- /dev/null +++ b/src/devices/cpu/mips/o2dprintf.hxx @@ -0,0 +1,406 @@ +// license:BSD-3-Clause +// copyright-holders:Ryan Holtz + +static char digit[] = "0123456789abcdef"; + +static void dprintdec(int64_t val, bool zeropad, int size) +{ + if (val == 0 && !zeropad) + { + printf("0"); + return; + } + + char dc[22]; + for (int rem = 0; rem < 22; rem++) dc[rem] = '0'; + + int ptr = 0; + int64_t v = val; + char c = ' '; + if (val < 0) + { + c = '-'; + val = -val; + } + + int indx1 = 0; + while (v > 10) + { + int64_t rem = v / 10; + int indx = v - (rem * 10); + dc[ptr] = digit[indx]; + v = rem; + if (indx != 0) + indx1 = ptr; + ptr += 1; + } + + dc[ptr] = digit[v]; + + if (v != 0) + indx1 = ptr; // the leading non zero digit. + + if (zeropad && size != 0) + ptr = size; + else + ptr = indx1; // don't print leading 0s + + if (c == '-') + printf("-"); + + while (ptr >= 0) + { + printf("%c", dc[ptr]); + ptr -= 1; + } +} + +static void dprintudec(uint64_t val, bool zeropad, int size) +{ + if (val == 0 && !zeropad) + { + printf("0"); + return; + } + + char dc[22]; + for (int rem = 0; rem < 22; dc[rem++] = '0'); + + int ptr = 0; + uint64_t v = val; + int indx1 = 0; + while (v > 10) + { + uint64_t rem = v / 10; + int indx = v - (rem * 10); + dc[ptr] = digit[indx]; + v = rem; + if (indx != 0) + indx1 = ptr; + ptr += 1; + } + + dc[ptr] = digit[v]; + + if (v != 0) + indx1 = ptr; // the leading non zero digit. + + if (zeropad && size != 0) + ptr = size; + else + ptr = indx1; // don't print leading 0s + + while (ptr >= 0) + { + printf("%c", dc[ptr]); + ptr -= 1; + } +} + +static void dprinthex(uint64_t val, bool zeropad, int pos) +{ + if (val == 0 && !zeropad) + { + printf("0"); + return; + } + + int pcount = pos; + int indx = 0; + + char c; + while (pcount >= 0) + { + if (pcount == 0) + c = digit[val & 0xf]; + else + c = digit[(val >> pcount) & 0xf]; + + if ((c == 'X') && (c > '9')) + c = c - 'a' + 'A'; + + if (c != '0') + { + indx += 1; + printf("%c", c); + } + else + { + if (zeropad || indx != 0) + printf("%c", c); + } + pcount -= 4; + } +} + +void dprintoct(uint64_t val, bool zeropad, int pos) +{ + if (val == 0 && !zeropad) + { + printf("0"); + return; + } + + int pcount = pos; + int indx = 0; + + char c; + while (pcount >= 0) + { + if (pcount == 0) + c = digit[val & 0x7]; + else + c = digit[(val >> pcount) & 0x7]; + + if (c != '0') + { + indx += 1; + printf("%c", c); + } + else + { + if (zeropad || indx != 0) + printf("%c", c); + } + pcount -= 3; + } +} + +#define Bhex 4 +#define Shex 12 +#define Ihex 28 +#define Lhex 60 +#define Boct 3 +#define Soct 15 +#define Ioct 30 +#define Loct 63 + +static uint64_t dprintf_get_arg64(uint8_t *buf, uint32_t &curr) +{ + curr = (curr + 3) & ~3; + const uint64_t ret = ((uint64_t)buf[curr+0] << 56) | ((uint64_t)buf[curr+1] << 48) | ((uint64_t)buf[curr+2] << 40) | ((uint64_t)buf[curr+3] << 32) | + ((uint64_t)buf[curr+4] << 24) | ((uint64_t)buf[curr+5] << 16) | ((uint64_t)buf[curr+6] << 8) | buf[curr+7]; + curr += 8; + return ret; +} + +static uint32_t dprintf_get_arg32(uint8_t *buf, uint32_t &curr) +{ + curr = (curr + 3) & ~3; + const uint32_t ret = ((uint32_t)buf[curr+0] << 24) | ((uint32_t)buf[curr+1] << 16) | ((uint32_t)buf[curr+2] << 8) | buf[curr+3]; + curr += 4; + return ret; +} + +static uint16_t dprintf_get_arg16(uint8_t *buf, uint32_t &curr) +{ + curr = (curr + 1) & ~1; + const uint16_t ret = ((uint16_t)buf[curr+0] << 8) | buf[curr+1]; + curr += 2; + return ret; +} + +static uint8_t dprintf_get_arg8(uint8_t *buf, uint32_t &curr) +{ + const uint8_t ret = buf[curr++]; + return ret; +} + +void mips3_device::do_o2_dprintf(uint32_t fmt_addr, uint32_t a1, uint32_t a2, uint32_t a3, uint32_t stack) +{ + char buf[4096]; + uint8_t argbuf[4096]; + int idx = 0; + uint8_t byte_val = 0; + fmt_addr &= 0x1fffffff; + argbuf[0] = (uint8_t)(a1 >> 24); + argbuf[1] = (uint8_t)(a1 >> 16); + argbuf[2] = (uint8_t)(a1 >> 8); + argbuf[3] = (uint8_t)a1; + argbuf[4] = (uint8_t)(a2 >> 24); + argbuf[5] = (uint8_t)(a2 >> 16); + argbuf[6] = (uint8_t)(a2 >> 8); + argbuf[7] = (uint8_t)a2; + argbuf[8] = (uint8_t)(a3 >> 24); + argbuf[9] = (uint8_t)(a3 >> 16); + argbuf[10] = (uint8_t)(a3 >> 8); + argbuf[11] = (uint8_t)a3; + stack &= 0x1fffffff; + for (int i = 0; i < 4096-12; i++) + { + argbuf[i+12] = m_program->read_byte(i+stack); + } + uint32_t argcurr = 0; + do + { + byte_val = m_program->read_byte(fmt_addr++); + buf[idx++] = (char)byte_val; + } while(byte_val != 0); + + char *p = buf; + char errQ[3]; + int state = 0; + int size = 0; + int errP = 0; + bool zeropad = false; + while (*p) + { + switch (state) + { + case 0: + if (*p != '%') + { + printf("%c", *p); + } + else + { + errQ[errP++] = '%'; + state = 1; + } + p++; + break; + case 1: // check for zero padding + state = 2; + if (*p == '0') + { + errQ[errP++] = '0'; + zeropad = true; + p++; + } + else + { + zeropad = false; + } + break; + case 2: // check the size of the object to be printed + state = 3; + switch (*p) + { + case 'l': + errQ[errP++] = 'l'; + size = 64; + p++; + break; + case 'h': + errQ[errP++] = 'h'; + size = 16; + p++; + break; + case 'b': + errQ[errP++] = 'b'; + size = 8; + p++; + break; + default: + size = 32; + break; + } + break; + case 3: // do the print + switch (*p) + { + case '%': + printf("%c", '%'); + break; + case 'd': + case 'i': + switch (size) + { + case 64: + dprintdec((int64_t)dprintf_get_arg64(argbuf, argcurr), zeropad, 0); + break; + case 16: // short + dprintdec((int64_t)dprintf_get_arg16(argbuf, argcurr), zeropad, 4); + break; + case 8: // byte + dprintdec((int64_t)dprintf_get_arg8(argbuf, argcurr), zeropad, 3); + break; + default: // int + dprintdec((int64_t)dprintf_get_arg32(argbuf, argcurr), zeropad, 9); + break; + } + break; + case 'u': + switch (size) + { + case 64: + dprintudec((uint64_t)dprintf_get_arg64(argbuf, argcurr), zeropad, 0); + break; + case 16: + dprintudec((uint64_t)dprintf_get_arg16(argbuf, argcurr), zeropad, 4); + break; + case 8: + dprintudec((uint64_t)dprintf_get_arg8(argbuf, argcurr), zeropad, 3); + break; + default: + dprintudec((uint64_t)dprintf_get_arg32(argbuf, argcurr), zeropad, 9); + break; + } + break; + case 'o': + switch (size) + { + case 64: + dprintoct((uint64_t)dprintf_get_arg64(argbuf, argcurr), zeropad, Loct); + break; + case 16: // short + dprintoct((uint64_t)dprintf_get_arg16(argbuf, argcurr), zeropad, Soct); + break; + case 8: // byte + dprintoct((uint64_t)dprintf_get_arg8(argbuf, argcurr), zeropad, Boct); + break; + default: // int + dprintoct((uint64_t)dprintf_get_arg32(argbuf, argcurr), zeropad, Ioct); + break; + } + break; + case 'x': + case 'X': + switch (size) + { + case 64: + dprinthex((uint64_t)dprintf_get_arg64(argbuf, argcurr), zeropad, Lhex); + break; + case 16: + dprinthex((uint64_t)dprintf_get_arg16(argbuf, argcurr), zeropad, Shex); + break; + case 8: + dprinthex((uint64_t)dprintf_get_arg8(argbuf, argcurr), zeropad, Bhex); + break; + default: + dprinthex((uint64_t)dprintf_get_arg32(argbuf, argcurr), zeropad, Ihex); + break; + } + break; + case 'c': + printf("%c", (char)dprintf_get_arg8(argbuf, argcurr)); + break; + case 's': + { + uint64_t str_addr = dprintf_get_arg64(argbuf, argcurr); + uint8_t strbyte = 0; + do + { + strbyte = m_program->read_byte(str_addr); + str_addr++; + printf("%c", (char)strbyte); + } while(strbyte); + break; + } + case '0': // error + case 'l': // error + case 'h': // error + default: // error + for (int i = 0; i < 3; i++) + printf("%c", (char)errQ[i]); + printf("%c", *p++); + break; + } + state = 0; // reset the state machine + size = 0; // reset the size + zeropad = false; // reset the zero padding + errP = 0; // reset errQ + p++; + } + } +} diff --git a/src/mame/drivers/indy_indigo2.cpp b/src/mame/drivers/indy_indigo2.cpp index bb88f667315..09a9b1d8772 100644 --- a/src/mame/drivers/indy_indigo2.cpp +++ b/src/mame/drivers/indy_indigo2.cpp @@ -66,22 +66,15 @@ #include "cpu/mips/mips3.h" -#include "machine/ds1386.h" -#include "machine/eepromser.h" -#include "machine/hal2.h" #include "machine/hpc3.h" -#include "machine/ioc2.h" #include "machine/sgi.h" #include "sound/cdda.h" -#include "sound/dac.h" -#include "sound/volt_reg.h" #include "video/newport.h" #include "emupal.h" #include "screen.h" -#include "speaker.h" class ip22_state : public driver_device { @@ -92,14 +85,8 @@ public: , m_mainram(*this, "mainram") , m_mem_ctrl(*this, "memctrl") , m_scsi_ctrl(*this, "wd33c93") - , m_eeprom(*this, "eeprom") - , m_ldac(*this, "ldac") - , m_rdac(*this, "rdac") , m_newport(*this, "newport") - , m_hal2(*this, HAL2_TAG) - , m_hpc3(*this, HPC3_TAG) - , m_ioc2(*this, IOC2_TAG) - , m_rtc(*this, RTC_TAG) + , m_hpc3(*this, "hpc3") { } @@ -110,44 +97,22 @@ public: protected: virtual void machine_reset() override; - DECLARE_READ32_MEMBER(eeprom_r); - DECLARE_WRITE32_MEMBER(eeprom_w); - DECLARE_READ32_MEMBER(enet_r); - DECLARE_WRITE32_MEMBER(enet_w); DECLARE_READ32_MEMBER(eisa_io_r); - DECLARE_WRITE32_MEMBER(ip22_write_ram); + DECLARE_WRITE64_MEMBER(write_ram); void ip22_map(address_map &map); static void cdrom_config(device_t *device); - static char const *const HAL2_TAG; - static char const *const HPC3_TAG; - static char const *const IOC2_TAG; - static char const *const RTC_TAG; - required_device m_maincpu; - required_shared_ptr m_mainram; + required_shared_ptr m_mainram; required_device m_mem_ctrl; required_device m_scsi_ctrl; - required_device m_eeprom; - required_device m_ldac; - required_device m_rdac; required_device m_newport; - required_device m_hal2; required_device m_hpc3; - required_device m_ioc2; - required_device m_rtc; - - uint32_t m_cpu_aux_ctrl; }; -/*static*/ char const *const ip22_state::HAL2_TAG = "hal2"; -/*static*/ char const *const ip22_state::HPC3_TAG = "hpc3"; -/*static*/ char const *const ip22_state::IOC2_TAG = "ioc2"; -/*static*/ char const *const ip22_state::RTC_TAG = "rtc"; - class ip24_state : public ip22_state { public: @@ -160,71 +125,29 @@ public: void ip244415(machine_config &config); private: - void ip24_map(address_map &map); - required_device m_scsi_ctrl2; }; -READ32_MEMBER(ip22_state::eeprom_r) -{ - // Disabled - we don't have a dump from real hardware, and IRIX 5.x freaks out with default contents. - uint32_t ret = (m_cpu_aux_ctrl & ~0x10);// | m_eeprom->do_read() << 4; - logerror("%s: HPC Serial EEPROM Read: %08x & %08x\n", machine().describe_context(), ret, mem_mask); - return ret; -} - -WRITE32_MEMBER(ip22_state::eeprom_w) -{ - m_cpu_aux_ctrl = data; - logerror("%s: HPC Serial EEPROM Write: %08x & %08x\n", machine().describe_context(), data, mem_mask); - m_eeprom->di_write(BIT(data, 3)); - m_eeprom->cs_write(BIT(data, 1)); - m_eeprom->clk_write(BIT(data, 2)); -} - -READ32_MEMBER(ip22_state::enet_r) -{ - switch (offset) - { - case 0x000/4: - logerror("%s: enet_r: Read MAC Address bytes 0-3, 0x80675309 & %08x\n", machine().describe_context(), mem_mask); - return 0x80675309; - default: - logerror("%s: enet_r: Read Unknown Register %08x & %08x\n", machine().describe_context(), 0x1fbd4000 + (offset << 2), mem_mask); - return 0; - } -} - -WRITE32_MEMBER(ip22_state::enet_w) -{ - switch (offset) - { - default: - logerror("%s: enet_w: Write Unknown Register %08x = %08x & %08x\n", machine().describe_context(), 0x1fbd4000 + (offset << 2), data, mem_mask); - break; - } -} - READ32_MEMBER(ip22_state::eisa_io_r) { return 0xffffffff; } // a bit hackish, but makes the memory detection work properly and allows a big cleanup of the mapping -WRITE32_MEMBER(ip22_state::ip22_write_ram) +WRITE64_MEMBER(ip22_state::write_ram) { // if banks 2 or 3 are enabled, do nothing, we don't support that much memory - if (m_mem_ctrl->read(space, 0xc8/4, 0xffffffff) & 0x10001000) + if (m_mem_ctrl->get_mem_config(1) & 0x10001000) { // a random perturbation so the memory test fails - data ^= 0xffffffff; + data ^= 0xffffffffffffffffULL; } // if banks 0 or 1 have 2 membanks, also kill it, we only want 128 MB - if (m_mem_ctrl->read(space, 0xc0/4, 0xffffffff) & 0x40004000) + if (m_mem_ctrl->get_mem_config(0) & 0x40004000) { // a random perturbation so the memory test fails - data ^= 0xffffffff; + data ^= 0xffffffffffffffffULL; } COMBINE_DATA(&m_mainram[offset]); } @@ -233,31 +156,12 @@ void ip22_state::ip22_map(address_map &map) { map(0x00000000, 0x0007ffff).bankrw("bank1"); /* mirror of first 512k of main RAM */ map(0x00080000, 0x0009ffff).r(FUNC(ip22_state::eisa_io_r)); - map(0x08000000, 0x0fffffff).share("mainram").ram().w(FUNC(ip22_state::ip22_write_ram)); /* 128 MB of main RAM */ + map(0x08000000, 0x0fffffff).share("mainram").ram().w(FUNC(ip22_state::write_ram)); /* 128 MB of main RAM */ map(0x1f0f0000, 0x1f0f1fff).rw(m_newport, FUNC(newport_video_device::rex3_r), FUNC(newport_video_device::rex3_w)); map(0x1fa00000, 0x1fa1ffff).rw(m_mem_ctrl, FUNC(sgi_mc_device::read), FUNC(sgi_mc_device::write)); - - map(0x1fb80000, 0x1fb8ffff).rw(m_hpc3, FUNC(hpc3_device::pbusdma_r), FUNC(hpc3_device::pbusdma_w)); - map(0x1fb90000, 0x1fb9ffff).rw(m_hpc3, FUNC(hpc3_device::hd_enet_r), FUNC(hpc3_device::hd_enet_w)); - map(0x1fbb0008, 0x1fbb000b).rw(FUNC(ip22_state::eeprom_r), FUNC(ip22_state::eeprom_w)); - map(0x1fbc0000, 0x1fbc7fff).rw(m_hpc3, FUNC(hpc3_device::hd_r<0>), FUNC(hpc3_device::hd_w<0>)); - map(0x1fbd4000, 0x1fbd44ff).rw(FUNC(ip22_state::enet_r), FUNC(ip22_state::enet_w)); - map(0x1fbd8000, 0x1fbd83ff).rw(m_hal2, FUNC(hal2_device::read), FUNC(hal2_device::write)); - map(0x1fbd8400, 0x1fbd87ff).ram(); /* hack */ - map(0x1fbd9000, 0x1fbd93ff).rw(m_hpc3, FUNC(hpc3_device::pbus4_r), FUNC(hpc3_device::pbus4_w)); - map(0x1fbd9800, 0x1fbd9bff).rw(m_ioc2, FUNC(ioc2_device::read), FUNC(ioc2_device::write)); - map(0x1fbdc000, 0x1fbdcfff).rw(m_hpc3, FUNC(hpc3_device::dma_config_r), FUNC(hpc3_device::dma_config_w)); - map(0x1fbdd000, 0x1fbddfff).rw(m_hpc3, FUNC(hpc3_device::pio_config_r), FUNC(hpc3_device::pio_config_w)); - - map(0x1fbe0000, 0x1fbe04ff).rw(m_rtc, FUNC(ds1386_device::data_r), FUNC(ds1386_device::data_w)).umask32(0x000000ff); + map(0x1fb80000, 0x1fbfffff).m(m_hpc3, FUNC(hpc3_device::map)); map(0x1fc00000, 0x1fc7ffff).rom().region("user1", 0); - map(0x20000000, 0x27ffffff).share("mainram").ram().w(FUNC(ip22_state::ip22_write_ram)); -} - -void ip24_state::ip24_map(address_map &map) -{ - ip22_map(map); - map(0x1fbc8000, 0x1fbcffff).rw(m_hpc3, FUNC(hpc3_device::hd_r<1>), FUNC(hpc3_device::hd_w<1>)); + map(0x20000000, 0x27ffffff).share("mainram").ram().w(FUNC(ip22_state::write_ram)); } void ip22_state::machine_reset() @@ -279,8 +183,8 @@ INPUT_PORTS_END void ip22_state::cdrom_config(device_t *device) { cdda_device *cdda = device->subdevice("cdda"); - cdda->add_route(0, ":lspeaker", 1.0); - cdda->add_route(1, ":rspeaker", 1.0); + cdda->add_route(0, ":hpc3:lspeaker", 1.0); + cdda->add_route(1, ":hpc3:rspeaker", 1.0); } void ip22_state::ip22_base(machine_config &config) @@ -296,25 +200,9 @@ void ip22_state::ip22_base(machine_config &config) PALETTE(config, "palette", 65536); - NEWPORT_VIDEO(config, m_newport, m_maincpu, m_ioc2); + NEWPORT_VIDEO(config, m_newport, m_maincpu, m_hpc3); - SGI_MC(config, m_mem_ctrl, m_maincpu, m_eeprom); - - SPEAKER(config, "lspeaker").front_left(); - SPEAKER(config, "rspeaker").front_right(); - - DAC_16BIT_R2R_TWOS_COMPLEMENT(config, m_ldac, 0); - m_ldac->add_route(ALL_OUTPUTS, "lspeaker", 0.25); - - DAC_16BIT_R2R_TWOS_COMPLEMENT(config, m_rdac, 0); - m_rdac->add_route(ALL_OUTPUTS, "rspeaker", 0.25); - - voltage_regulator_device &vreg = VOLTAGE_REGULATOR(config, "vref"); - vreg.set_output(5.0); - vreg.add_route(0, "ldac", 1.0, DAC_VREF_POS_INPUT); - vreg.add_route(0, "rdac", 1.0, DAC_VREF_POS_INPUT); - vreg.add_route(0, "ldac", -1.0, DAC_VREF_NEG_INPUT); - vreg.add_route(0, "rdac", -1.0, DAC_VREF_NEG_INPUT); + SGI_MC(config, m_mem_ctrl, m_maincpu, ":hpc3:eeprom"); scsi_port_device &scsi(SCSI_PORT(config, "scsi")); scsi.set_slot_device(1, "harddisk", SCSIHD, DEVICE_INPUT_DEFAULTS_NAME(SCSI_ID_1)); @@ -325,13 +213,6 @@ void ip22_state::ip22_base(machine_config &config) m_scsi_ctrl->set_scsi_port("scsi"); m_scsi_ctrl->irq_cb().set(m_hpc3, FUNC(hpc3_device::scsi0_irq)); //m_scsi_ctrl->drq_cb().set(m_hpc3, FUNC(hpc3_device::scsi0_drq)); - - SGI_HAL2(config, m_hal2); - SGI_IOC2_GUINNESS(config, m_ioc2, m_maincpu); - - DS1386_8K(config, m_rtc, 32768); - - EEPROM_93C56_16BIT(config, m_eeprom); } void ip22_state::ip225015(machine_config &config) @@ -343,7 +224,7 @@ void ip22_state::ip225015(machine_config &config) m_maincpu->set_dcache_size(32768); m_maincpu->set_addrmap(AS_PROGRAM, &ip22_state::ip22_map); - SGI_HPC3(config, m_hpc3, m_maincpu, m_scsi_ctrl, m_ioc2, m_ldac, m_rdac); + SGI_HPC3(config, m_hpc3, m_maincpu, m_scsi_ctrl); } void ip22_state::ip224613(machine_config &config) @@ -355,7 +236,7 @@ void ip22_state::ip224613(machine_config &config) m_maincpu->set_dcache_size(32768); m_maincpu->set_addrmap(AS_PROGRAM, &ip22_state::ip22_map); - SGI_HPC3(config, m_hpc3, m_maincpu, m_scsi_ctrl, m_ioc2, m_ldac, m_rdac); + SGI_HPC3(config, m_hpc3, m_maincpu, m_scsi_ctrl); } void ip24_state::ip244415(machine_config &config) @@ -365,7 +246,7 @@ void ip24_state::ip244415(machine_config &config) R4400BE(config, m_maincpu, 50000000*3); m_maincpu->set_icache_size(32768); m_maincpu->set_dcache_size(32768); - m_maincpu->set_addrmap(AS_PROGRAM, &ip24_state::ip24_map); + m_maincpu->set_addrmap(AS_PROGRAM, &ip24_state::ip22_map); SCSI_PORT(config, "scsi2"); @@ -374,7 +255,7 @@ void ip24_state::ip244415(machine_config &config) m_scsi_ctrl->irq_cb().set(m_hpc3, FUNC(hpc3_device::scsi1_irq)); //m_scsi_ctrl->drq_cb().set(m_hpc3, FUNC(hpc3_device::scsi1_drq)); - SGI_HPC3(config, m_hpc3, m_maincpu, m_scsi_ctrl, m_scsi_ctrl2, m_ioc2, m_ldac, m_rdac); + SGI_HPC3(config, m_hpc3, m_maincpu, m_scsi_ctrl, m_scsi_ctrl2); } /* SCC init ip225015 @@ -407,18 +288,18 @@ void ip24_state::ip244415(machine_config &config) * 00 <- 10 Reset External/status IE */ ROM_START( ip225015 ) - ROM_REGION( 0x80000, "user1", 0 ) - ROM_LOAD( "ip225015.bin", 0x000000, 0x080000, CRC(aee5502e) SHA1(9243fef0a3508790651e0d6d2705c887629b1280) ) + ROM_REGION64_BE( 0x80000, "user1", 0 ) + ROMX_LOAD( "ip225015.bin", 0x000000, 0x080000, CRC(aee5502e) SHA1(9243fef0a3508790651e0d6d2705c887629b1280), ROM_GROUPDWORD | ROM_REVERSE ) ROM_END ROM_START( ip224613 ) - ROM_REGION( 0x80000, "user1", 0 ) - ROM_LOAD( "ip224613.bin", 0x000000, 0x080000, CRC(f1868b5b) SHA1(0dcbbd776e671785b9b65f3c6dbd609794a40157) ) + ROM_REGION64_BE( 0x80000, "user1", 0 ) + ROMX_LOAD( "ip224613.bin", 0x000000, 0x080000, CRC(f1868b5b) SHA1(0dcbbd776e671785b9b65f3c6dbd609794a40157), ROM_GROUPDWORD | ROM_REVERSE ) ROM_END ROM_START( ip244415 ) - ROM_REGION( 0x80000, "user1", 0 ) - ROM_LOAD( "ip244415.bin", 0x000000, 0x080000, CRC(2f37825a) SHA1(0d48c573b53a307478820b85aacb57b868297ca3) ) + ROM_REGION32_BE( 0x80000, "user1", 0 ) + ROMX_LOAD( "ip244415.bin", 0x000000, 0x080000, CRC(2f37825a) SHA1(0d48c573b53a307478820b85aacb57b868297ca3), ROM_GROUPDWORD | ROM_REVERSE ) ROM_END // YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS diff --git a/src/mame/drivers/magictg.cpp b/src/mame/drivers/magictg.cpp index 2a03f5eb501..b95338367fa 100644 --- a/src/mame/drivers/magictg.cpp +++ b/src/mame/drivers/magictg.cpp @@ -310,7 +310,7 @@ uint32_t magictg_state::screen_update_magictg(screen_device &screen, bitmap_rgb3 uint32_t magictg_state::pci_dev0_r(int function, int reg, uint32_t mem_mask) { - osd_printf_debug("PCI[0] READ: %x\n", reg); + logerror("PCI[0] READ: %x\n", reg); return 0x00000000; // TODO } @@ -335,7 +335,7 @@ uint32_t magictg_state::voodoo_0_pci_r(int function, int reg, uint32_t mem_mask) val = m_voodoo_pci_regs[0].init_enable; break; default: - osd_printf_debug("Voodoo[0] PCI R: %x\n", reg); + logerror("Voodoo[0] PCI R: %x\n", reg); } return val; } @@ -359,7 +359,7 @@ void magictg_state::voodoo_0_pci_w(int function, int reg, uint32_t data, uint32_ break; default: - osd_printf_debug("Voodoo [%x]: %x\n", reg, data); + logerror("Voodoo [%x]: %x\n", reg, data); } } @@ -380,7 +380,7 @@ uint32_t magictg_state::voodoo_1_pci_r(int function, int reg, uint32_t mem_mask) val = m_voodoo_pci_regs[1].init_enable; break; default: - osd_printf_debug("Voodoo[1] PCI R: %x\n", reg); + logerror("Voodoo[1] PCI R: %x\n", reg); } return val; } @@ -404,7 +404,7 @@ void magictg_state::voodoo_1_pci_w(int function, int reg, uint32_t data, uint32_ break; default: - osd_printf_debug("Voodoo [%x]: %x\n", reg, data); + logerror("Voodoo [%x]: %x\n", reg, data); } } #endif @@ -462,7 +462,7 @@ uint32_t magictg_state::zr36120_pci_r(int function, int reg, uint32_t mem_mask) val = m_zr36120.base_addr; break; default: - osd_printf_debug("ZR36120 R[%x]\n", reg); + logerror("ZR36120 R[%x]\n", reg); } return val; } @@ -478,7 +478,7 @@ void magictg_state::zr36120_pci_w(int function, int reg, uint32_t data, uint32_t m_zr36120.base_addr = data & 0xfffff000; break; default: - osd_printf_debug("ZR36120 [%x]: %x\n", reg, data); + logerror("ZR36120 [%x]: %x\n", reg, data); } } @@ -501,7 +501,7 @@ READ32_MEMBER( magictg_state::zr36120_r ) /* Post office */ res = 0;//mame_rand(machine);//m_zr36120.as_regs[0x48/4]; } - osd_printf_debug("PINKEYE_R[%x]\n", offset); + logerror("PINKEYE_R[%x]\n", offset); return res; } @@ -511,7 +511,7 @@ WRITE32_MEMBER( magictg_state::zr36120_w ) if (offset < 0x200) { - osd_printf_debug("PINKEYE_W[%x] %x\n", offset, data); + logerror("PINKEYE_W[%x] %x\n", offset, data); switch (offset) { case 0x00/4: @@ -534,7 +534,7 @@ WRITE32_MEMBER( magictg_state::zr36120_w ) // zr36120_guest_write(guest, g_data, g_reg); // 2 - ZR36050 JPEG decoder // 3 - ZR36016 color-space converter - osd_printf_debug("GUEST (%.8x): %d REG: %d DATA: %x\n", data, guest, g_reg, g_data); + logerror("GUEST (%.8x): %d REG: %d DATA: %x\n", data, guest, g_reg, g_data); } } @@ -582,21 +582,21 @@ WRITE32_MEMBER( magictg_state::f0_w ) case 0x808: case 0x80c: m_dma_ch[ch].count = data; -// osd_printf_debug("DMA%d COUNT: %.8x\n", ch, data); +// logerror("DMA%d COUNT: %.8x\n", ch, data); break; case 0x814: case 0x818: case 0x81c: m_dma_ch[ch].src_addr = data; -// osd_printf_debug("DMA%d SRC: %.8x\n", ch, data); +// logerror("DMA%d SRC: %.8x\n", ch, data); break; case 0x824: case 0x828: case 0x82c: m_dma_ch[ch].dst_addr = data; -// osd_printf_debug("DMA%d DST: %.8x\n", ch, data); +// logerror("DMA%d DST: %.8x\n", ch, data); break; case 0x844: @@ -604,7 +604,7 @@ WRITE32_MEMBER( magictg_state::f0_w ) case 0x84c: { m_dma_ch[ch].ctrl = data; -// osd_printf_debug("DMA%d CTRL: %.8x\n", ch, data); +// logerror("DMA%d CTRL: %.8x\n", ch, data); if (data & 0x1000) { @@ -650,7 +650,7 @@ WRITE32_MEMBER( magictg_state::f0_w ) break; } // default: -// osd_printf_debug("W: %.8x: %.8x\n", 0x0f000000 + offset, data); +// logerror("W: %.8x: %.8x\n", 0x0f000000 + offset, data); } } @@ -687,7 +687,7 @@ READ32_MEMBER( magictg_state::f0_r ) break; } // default: -// osd_printf_debug("R: %.8x\n", 0x0f000000 + offset); +// logerror("R: %.8x\n", 0x0f000000 + offset); } return swapendian_int32(val); @@ -713,7 +713,7 @@ READ32_MEMBER( magictg_state::adsp_idma_data_r ) // TODO: Set /IACK appropriately if (ACCESSING_BITS_0_15) { - //osd_printf_debug("RD %.8x %.8x\n", offset, mem_mask); + //logerror("RD %.8x %.8x\n", offset, mem_mask); return m_adsp->idma_addr_r(); } else @@ -728,7 +728,7 @@ WRITE32_MEMBER( magictg_state::adsp_idma_addr_w ) if (ACCESSING_BITS_16_31) { m_adsp->idma_addr_w(data >> 16); - //osd_printf_debug("WR %.8x %.8x %.8x\n", offset, mem_mask, data >> 16); + //logerror("WR %.8x %.8x %.8x\n", offset, mem_mask, data >> 16); } else fatalerror("????\n"); @@ -753,7 +753,7 @@ READ16_MEMBER( magictg_state::adsp_control_r ) res = machine().rand() & 0xff; break; default: - osd_printf_debug("Unhandled register: %x\n", 0x3fe0 + offset); + logerror("Unhandled register: %x\n", 0x3fe0 + offset); } return res; } @@ -831,10 +831,10 @@ WRITE16_MEMBER( magictg_state::adsp_control_w ) break; } case 5: - osd_printf_debug("PFLAGS: %x\n", data); + logerror("PFLAGS: %x\n", data); break; default: - osd_printf_debug("Unhandled register: %x %x\n", 0x3fe0 + offset, data); + logerror("Unhandled register: %x %x\n", 0x3fe0 + offset, data); } } @@ -968,7 +968,7 @@ MACHINE_CONFIG_END *************************************/ ROM_START( magictg ) - ROM_REGION32_BE( 0x400000, "mips", 0 ) + ROM_REGION64_BE( 0x400000, "mips", 0 ) ROM_LOAD16_BYTE( "magic.u34", 0x000000, 0x100000, CRC(2e8971e2) SHA1(9bdf433a7c7257389ebdf131317ef26a7d4e1ba2) ) ROM_LOAD16_BYTE( "magic.u35", 0x000001, 0x100000, CRC(e2202143) SHA1(f07b7da81508cd4594f66e34dabd904a21eb03f0) ) ROM_LOAD16_BYTE( "magic.u32", 0x200000, 0x100000, CRC(f1d530e3) SHA1(fcc392804cd6b98917a869cc5d3826278b7ba90b) ) @@ -994,7 +994,7 @@ ROM_START( magictg ) ROM_END ROM_START( magictga ) - ROM_REGION32_BE( 0x400000, "mips", 0 ) + ROM_REGION64_BE( 0x400000, "mips", 0 ) ROM_LOAD16_BYTE( "magic.u63", 0x000000, 0x100000, CRC(a10d45f1) SHA1(0ede10f19cf70baf7b43e3f672532b4be1a179f8) ) ROM_LOAD16_BYTE( "magic.u64", 0x000001, 0x100000, CRC(8fdb6060) SHA1(b638244cad86dc60435a4a9150a5b639f5d61a3f) ) ROM_LOAD16_BYTE( "magic.u61", 0x200000, 0x100000, CRC(968891d6) SHA1(67ab87039864bb148d20795333ffa7a23e3b84f2) ) diff --git a/src/mame/drivers/o2.cpp b/src/mame/drivers/o2.cpp index 5c2c28b6bb8..e51be7cf112 100644 --- a/src/mame/drivers/o2.cpp +++ b/src/mame/drivers/o2.cpp @@ -7,20 +7,18 @@ To Do: Everything Memory map: + 00000000 - 0fffffff RAM (256mbyte mirror) + 14000000 - 15ffffff CRIME + 1f000000 - 1f3fffff MACE 1fc00000 - 1fc7ffff Boot ROM + 40000000 - 7fffffff RAM **********************************************************************/ #include "emu.h" #include "cpu/mips/mips3.h" - -#define ENABLE_ENTRY_GFX (1) - -#define LOG_UNKNOWN (1 << 0) -#define LOG_ALL (LOG_UNKNOWN) - -#define VERBOSE (LOG_UNKNOWN) -#include "logmacro.h" +#include "machine/mace.h" +#include "video/crime.h" class o2_state : public driver_device { @@ -28,6 +26,8 @@ public: o2_state(const machine_config &mconfig, device_type type, const char *tag) : driver_device(mconfig, type, tag) , m_maincpu(*this, "maincpu") + , m_mace(*this, "mace") + , m_crime(*this, "crime") { } @@ -36,13 +36,30 @@ public: protected: void mem_map(address_map &map); - required_device m_maincpu; + required_device m_maincpu; + required_device m_mace; + required_device m_crime; }; void o2_state::mem_map(address_map &map) { + map(0x00000000, 0x01ffffff).ram().share("bank1"); map(0x00000000, 0x00000fff).ram(); + map(0x14000000, 0x15ffffff).m(m_crime, FUNC(crime_device::map)); + map(0x1f000000, 0x1f3fffff).m(m_mace, FUNC(mace_device::map)); map(0x1fc00000, 0x1fc7ffff).rom().region("user1", 0); + static const char* const bank_names[8] = { "bank1", "bank2", "bank3", "bank4", "bank5", "bank6", "bank7", "bank8" }; + for (uint32_t bank = 0; bank < 8; bank++) + { + const uint32_t base_addr = 0x40000000 + bank * 0x08000000; + const uint32_t bank_size_32m = 0x02000000; + for (uint32_t mirror = 0; mirror < 4; mirror++) + { + const uint32_t start_addr = base_addr + mirror * bank_size_32m; + const uint32_t end_addr = base_addr + (mirror + 1) * bank_size_32m - 1; + map(start_addr, end_addr).ram().share(bank_names[bank]); + } + } } static INPUT_PORTS_START( o2 ) @@ -50,14 +67,18 @@ INPUT_PORTS_END void o2_state::o2(machine_config &config) { - RM7000BE(config, m_maincpu, 50000000*6); // Unknown CPU speed - m_maincpu->set_icache_size(32768); // Unknown cache size + R5000BE(config, m_maincpu, 60000000*3); + m_maincpu->set_icache_size(32768); m_maincpu->set_dcache_size(32768); m_maincpu->set_addrmap(AS_PROGRAM, &o2_state::mem_map); + + SGI_MACE(config, m_mace, m_maincpu); + + SGI_CRIME(config, m_crime, m_maincpu); } ROM_START( o2 ) - ROM_REGION32_BE( 0x80000, "user1", 0 ) + ROM_REGION64_BE( 0x80000, "user1", 0 ) ROMX_LOAD( "ip32prom.rev4.18.bin", 0x000000, 0x080000, CRC(02b3c53d) SHA1(f2cfa7246d67f88fe5490e40dac6c04b1deb4d28), ROM_GROUPDWORD ) ROM_END diff --git a/src/mame/drivers/octane.cpp b/src/mame/drivers/octane.cpp index c5268adb2d5..adf7a4a622c 100644 --- a/src/mame/drivers/octane.cpp +++ b/src/mame/drivers/octane.cpp @@ -56,7 +56,7 @@ void octane_state::octane(machine_config &config) } ROM_START( octane ) - ROM_REGION32_BE( 0x100000, "user1", 0 ) + ROM_REGION64_BE( 0x100000, "user1", 0 ) ROMX_LOAD( "ip30prom.rev4.9.bin", 0x000000, 0x100000, CRC(10bafb52) SHA1(de250875c608add63749d3f9fb81a82cb58c3586), ROM_GROUPDWORD ) ROM_END diff --git a/src/mame/machine/hal2.cpp b/src/mame/machine/hal2.cpp index c62f88a3980..7bb6286ab12 100644 --- a/src/mame/machine/hal2.cpp +++ b/src/mame/machine/hal2.cpp @@ -9,32 +9,27 @@ #include "emu.h" #include "machine/hal2.h" +#define LOG_UNKNOWN (1 << 0U) +#define LOG_READS (1 << 1U) +#define LOG_WRITES (1 << 2U) +#define LOG_ALL (LOG_UNKNOWN | LOG_READS | LOG_WRITES) + +#define VERBOSE (0) +#include "logmacro.h" + DEFINE_DEVICE_TYPE(SGI_HAL2, hal2_device, "hal2", "SGI HAL2") hal2_device::hal2_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : device_t(mconfig, SGI_HAL2, tag, owner, clock) , m_iar(0) - , m_idr{ 0, 0, 0, 0 } + , m_idr{0, 0, 0, 0} { } -#define VERBOSE_LEVEL ( 0 ) - -inline void ATTR_PRINTF(3,4) hal2_device::verboselog(int n_level, const char *s_fmt, ... ) -{ - if( VERBOSE_LEVEL >= n_level ) - { - va_list v; - char buf[ 32768 ]; - va_start( v, s_fmt ); - vsprintf( buf, s_fmt, v ); - va_end( v ); - logerror("%s: %s", machine().describe_context(), buf); - } -} - void hal2_device::device_start() { + save_item(NAME(m_iar)); + save_item(NAME(m_idr)); } void hal2_device::device_reset() @@ -45,16 +40,16 @@ void hal2_device::device_reset() READ32_MEMBER(hal2_device::read) { - switch( offset ) + switch (offset) { case STATUS_REG: - //verboselog((machine, 0, "HAL2 Status read: 0x0004\n" ); + LOGMASKED(LOG_READS, "%s: HAL2 Status Read: 0x0004\n", machine().describe_context()); return 0x0004; case REVISION_REG: - //verboselog((machine, 0, "HAL2 Revision read: 0x4011\n" ); + LOGMASKED(LOG_READS, "%s: HAL2 Revision Read: 0x4011\n", machine().describe_context()); return 0x4011; } - //verboselog((machine, 0, "Unknown HAL2 read: 0x%08x (%08x)\n", 0x1fbd8000 + offset*4, mem_mask ); + LOGMASKED(LOG_READS | LOG_UNKNOWN, "%s: Unknown HAL2 read: %08x & %08x\n", machine().describe_context(), 0x1fbd8000 + offset*4, mem_mask); return 0; } @@ -63,77 +58,77 @@ WRITE32_MEMBER(hal2_device::write) switch (offset) { case STATUS_REG: - //verboselog((machine, 0, "HAL2 Status Write: 0x%08x (%08x)\n", data, mem_mask ); + LOGMASKED(LOG_WRITES, "%s: HAL2 Status Write: 0x%08x (%08x)\n", machine().describe_context(), data, mem_mask); if (data & ISR_GLOBAL_RESET) { - //verboselog((machine, 0, " HAL2 Global Reset\n" ); + LOGMASKED(LOG_WRITES, " HAL2 Global Reset\n"); } if (data & ISR_CODEC_RESET) { - //verboselog((machine, 0, " HAL2 Codec Reset\n" ); + LOGMASKED(LOG_WRITES, " HAL2 Codec Reset\n"); } break; case INDIRECT_ADDRESS_REG: - //verboselog((machine, 0, "HAL2 Indirect Address Register Write: 0x%08x (%08x)\n", data, mem_mask ); + LOGMASKED(LOG_WRITES, "%s: HAL2 Indirect Address Register Write: %08x & %08x\n", machine().describe_context(), data, mem_mask); m_iar = data; switch (data & IAR_TYPE) { case 0x1000: - //verboselog((machine, 0, " DMA Port\n" ); + LOGMASKED(LOG_WRITES, " DMA Port\n"); switch (data & IAR_NUM) { case 0x0100: - //verboselog((machine, 0, " Synth In\n" ); + LOGMASKED(LOG_WRITES, " Synth In\n"); break; case 0x0200: - //verboselog((machine, 0, " AES In\n" ); + LOGMASKED(LOG_WRITES, " AES In\n"); break; case 0x0300: - //verboselog((machine, 0, " AES Out\n" ); + LOGMASKED(LOG_WRITES, " AES Out\n"); break; case 0x0400: - //verboselog((machine, 0, " DAC Out\n" ); + LOGMASKED(LOG_WRITES, " DAC Out\n"); break; case 0x0500: - //verboselog((machine, 0, " ADC Out\n" ); + LOGMASKED(LOG_WRITES, " ADC Out\n"); break; case 0x0600: - //verboselog((machine, 0, " Synth Control\n" ); + LOGMASKED(LOG_WRITES, " Synth Control\n"); break; } break; case 0x2000: - //verboselog((machine, 0, " Bresenham\n" ); + LOGMASKED(LOG_WRITES, " Bresenham\n"); switch (data & IAR_NUM) { case 0x0100: - //verboselog((machine, 0, " Bresenham Clock Gen 1\n" ); + LOGMASKED(LOG_WRITES, " Bresenham Clock Gen 1\n"); break; case 0x0200: - //verboselog((machine, 0, " Bresenham Clock Gen 2\n" ); + LOGMASKED(LOG_WRITES, " Bresenham Clock Gen 2\n"); break; case 0x0300: - //verboselog((machine, 0, " Bresenham Clock Gen 3\n" ); + LOGMASKED(LOG_WRITES, " Bresenham Clock Gen 3\n"); break; } break; case 0x3000: - //verboselog((machine, 0, " Unix Timer\n" ); + LOGMASKED(LOG_WRITES, " Unix Timer\n"); switch (data & IAR_NUM) { case 0x0100: - //verboselog((machine, 0, " Unix Timer\n" ); + LOGMASKED(LOG_WRITES, " Unix Timer\n"); break; } break; case 0x9000: - //verboselog((machine, 0, " Global DMA Control\n" ); + LOGMASKED(LOG_WRITES, " Global DMA Control\n"); switch (data & IAR_NUM) { case 0x0100: - //verboselog((machine, 0, " DMA Control\n" ); + LOGMASKED(LOG_WRITES, " DMA Control\n"); break; } break; @@ -142,34 +137,34 @@ WRITE32_MEMBER(hal2_device::write) switch (data & IAR_ACCESS_SEL) { case 0x0000: - //verboselog((machine, 0, " Write\n" ); + LOGMASKED(LOG_WRITES, " Write\n"); break; case 0x0080: - //verboselog((machine, 0, " Read\n" ); + LOGMASKED(LOG_WRITES, " Read\n"); break; } - //verboselog((machine, 0, " Parameter: %01x\n", ( data & IAR_PARAM ) >> 2 ); + LOGMASKED(LOG_WRITES, " Parameter: %01x\n", (data & IAR_PARAM) >> 2); return; case INDIRECT_DATA0_REG: - //verboselog((machine, 0, "HAL2 Indirect Data Register 0 Write: 0x%08x (%08x)\n", data, mem_mask ); + LOGMASKED(LOG_WRITES, "%s: HAL2 Indirect Data Register 0 Write: %08x & %08x\n", machine().describe_context(), data, mem_mask); m_idr[0] = data; return; case INDIRECT_DATA1_REG: - //verboselog((machine, 0, "HAL2 Indirect Data Register 1 Write: 0x%08x (%08x)\n", data, mem_mask ); + LOGMASKED(LOG_WRITES, "%s: HAL2 Indirect Data Register 1 Write: %08x & %08x\n", machine().describe_context(), data, mem_mask); m_idr[1] = data; return; case INDIRECT_DATA2_REG: - //verboselog((machine, 0, "HAL2 Indirect Data Register 2 Write: 0x%08x (%08x)\n", data, mem_mask ); + LOGMASKED(LOG_WRITES, "%s: HAL2 Indirect Data Register 2 Write: %08x & %08x\n", machine().describe_context(), data, mem_mask); m_idr[2] = data; return; case INDIRECT_DATA3_REG: - //verboselog((machine, 0, "HAL2 Indirect Data Register 3 Write: 0x%08x (%08x)\n", data, mem_mask ); + LOGMASKED(LOG_WRITES, "%s: HAL2 Indirect Data Register 3 Write: %08x & %08x\n", machine().describe_context(), data, mem_mask); m_idr[3] = data; return; } - //verboselog((machine, 0, "Unknown HAL2 write: 0x%08x: 0x%08x (%08x)\n", 0x1fbd8000 + offset*4, data, mem_mask ); + LOGMASKED(LOG_WRITES, "%s: Unknown HAL2 Write: %08x = %08x & %08x\n", machine().describe_context(), 0x1fbd8000 + offset*4, data, mem_mask); } diff --git a/src/mame/machine/hal2.h b/src/mame/machine/hal2.h index 39929180aeb..4d78e1f5075 100644 --- a/src/mame/machine/hal2.h +++ b/src/mame/machine/hal2.h @@ -59,8 +59,6 @@ protected: uint32_t m_iar; uint32_t m_idr[4]; - - inline void ATTR_PRINTF(3,4) verboselog(int n_level, const char *s_fmt, ... ); }; DECLARE_DEVICE_TYPE(SGI_HAL2, hal2_device) diff --git a/src/mame/machine/hpc3.cpp b/src/mame/machine/hpc3.cpp index 9bf1d2bd35e..7b3e910843c 100644 --- a/src/mame/machine/hpc3.cpp +++ b/src/mame/machine/hpc3.cpp @@ -16,6 +16,7 @@ #define LOG_ETHERNET (1 << 4) #define LOG_PBUS4 (1 << 5) #define LOG_CHAIN (1 << 6) +#define LOG_ALL (LOG_UNKNOWN | LOG_PBUS_DMA | LOG_SCSI | LOG_SCSI_DMA | LOG_ETHERNET | LOG_PBUS4 | LOG_CHAIN) #define VERBOSE (0) #include "logmacro.h" @@ -27,10 +28,12 @@ hpc3_device::hpc3_device(const machine_config &mconfig, const char *tag, device_ , m_maincpu(*this, finder_base::DUMMY_TAG) , m_wd33c93(*this, finder_base::DUMMY_TAG) , m_wd33c93_2(*this, finder_base::DUMMY_TAG) - , m_ioc2(*this, finder_base::DUMMY_TAG) - , m_ldac(*this, finder_base::DUMMY_TAG) - , m_rdac(*this, finder_base::DUMMY_TAG) - , m_mainram(*this, ":mainram") + , m_eeprom(*this, "eeprom") + , m_rtc(*this, "rtc") + , m_ioc2(*this, "ioc2") + , m_hal2(*this, "hal2") + , m_ldac(*this, "ldac") + , m_rdac(*this, "rdac") { } @@ -38,6 +41,7 @@ void hpc3_device::device_start() { save_item(NAME(m_enetr_nbdp)); save_item(NAME(m_enetr_cbp)); + save_item(NAME(m_cpu_aux_ctrl)); save_item(NAME(m_pio_config)); for (uint32_t i = 0; i < 2; i++) @@ -73,6 +77,7 @@ void hpc3_device::device_reset() { m_enetr_nbdp = 0x80000000; m_enetr_cbp = 0x80000000; + m_cpu_aux_ctrl = 0; memset(m_scsi_dma, 0, sizeof(scsi_dma_t) * 2); @@ -94,6 +99,49 @@ void hpc3_device::device_reset() m_cpu_space = &m_maincpu->space(AS_PROGRAM); } +void hpc3_device::device_add_mconfig(machine_config &config) +{ + SPEAKER(config, "lspeaker").front_left(); + SPEAKER(config, "rspeaker").front_right(); + + DAC_16BIT_R2R_TWOS_COMPLEMENT(config, m_ldac, 0); + m_ldac->add_route(ALL_OUTPUTS, "lspeaker", 0.25); + + DAC_16BIT_R2R_TWOS_COMPLEMENT(config, m_rdac, 0); + m_rdac->add_route(ALL_OUTPUTS, "rspeaker", 0.25); + + voltage_regulator_device &vreg = VOLTAGE_REGULATOR(config, "vref"); + vreg.set_output(5.0); + vreg.add_route(0, "ldac", 1.0, DAC_VREF_POS_INPUT); + vreg.add_route(0, "rdac", 1.0, DAC_VREF_POS_INPUT); + vreg.add_route(0, "ldac", -1.0, DAC_VREF_NEG_INPUT); + vreg.add_route(0, "rdac", -1.0, DAC_VREF_NEG_INPUT); + + SGI_HAL2(config, m_hal2); + SGI_IOC2_GUINNESS(config, m_ioc2, m_maincpu); + + DS1386_8K(config, m_rtc, 32768); + + EEPROM_93C56_16BIT(config, m_eeprom); +} + +void hpc3_device::map(address_map &map) +{ + map(0x00000000, 0x0000ffff).rw(FUNC(hpc3_device::pbusdma_r), FUNC(hpc3_device::pbusdma_w)); + map(0x00010000, 0x0001ffff).rw(FUNC(hpc3_device::hd_enet_r), FUNC(hpc3_device::hd_enet_w)); + map(0x00030008, 0x0003000b).rw(FUNC(hpc3_device::eeprom_r), FUNC(hpc3_device::eeprom_w)); + map(0x00040000, 0x00047fff).rw(FUNC(hpc3_device::hd_r<0>), FUNC(hpc3_device::hd_w<0>)); + map(0x00048000, 0x0004ffff).rw(FUNC(hpc3_device::hd_r<1>), FUNC(hpc3_device::hd_w<1>)); + map(0x00054000, 0x000544ff).rw(FUNC(hpc3_device::enet_r), FUNC(hpc3_device::enet_w)); + map(0x00058000, 0x000583ff).rw(m_hal2, FUNC(hal2_device::read), FUNC(hal2_device::write)); + map(0x00058400, 0x000587ff).ram(); // hack + map(0x00059000, 0x000593ff).rw(FUNC(hpc3_device::pbus4_r), FUNC(hpc3_device::pbus4_w)); + map(0x00059800, 0x00059bff).rw(m_ioc2, FUNC(ioc2_device::read), FUNC(ioc2_device::write)); + map(0x0005c000, 0x0005cfff).rw(FUNC(hpc3_device::dma_config_r), FUNC(hpc3_device::dma_config_w)); + map(0x0005d000, 0x0005dfff).rw(FUNC(hpc3_device::pio_config_r), FUNC(hpc3_device::pio_config_w)); + map(0x00060000, 0x000604ff).rw(m_rtc, FUNC(ds1386_device::data_r), FUNC(ds1386_device::data_w)).umask32(0x000000ff); +} + void hpc3_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) { switch (id) @@ -161,6 +209,29 @@ void hpc3_device::do_pbus_dma(uint32_t channel) } } +READ32_MEMBER(hpc3_device::enet_r) +{ + switch (offset) + { + case 0x000/4: + logerror("%s: HPC3: enet_r: Read MAC Address bytes 0-3, 0x80675309 & %08x\n", machine().describe_context(), mem_mask); + return 0x80675309; + default: + logerror("%s: HPC3: enet_r: Read Unknown Register %08x & %08x\n", machine().describe_context(), 0x1fbd4000 + (offset << 2), mem_mask); + return 0; + } +} + +WRITE32_MEMBER(hpc3_device::enet_w) +{ + switch (offset) + { + default: + logerror("%s: HPC3: enet_w: Write Unknown Register %08x = %08x & %08x\n", machine().describe_context(), 0x1fbd4000 + (offset << 2), data, mem_mask); + break; + } +} + READ32_MEMBER(hpc3_device::hd_enet_r) { switch (offset) @@ -223,7 +294,7 @@ READ32_MEMBER(hpc3_device::hd_r) case 0x4000/4: if (ACCESSING_BITS_0_7) { - const uint8_t ret = index ? m_wd33c93_2->read(space, 0) : m_wd33c93->read(space, 0); + const uint8_t ret = index && m_wd33c93_2 ? m_wd33c93_2->read(space, 0) : m_wd33c93->read(space, 0); LOGMASKED(LOG_SCSI, "%s: SCSI%d Read 0: %02x\n", machine().describe_context(), index, ret); return ret; } @@ -232,7 +303,7 @@ READ32_MEMBER(hpc3_device::hd_r) case 0x4004/4: if (ACCESSING_BITS_0_7) { - const uint8_t ret = index ? m_wd33c93_2->read(space, 1) : m_wd33c93->read(space, 1); + const uint8_t ret = index && m_wd33c93_2 ? m_wd33c93_2->read(space, 1) : m_wd33c93->read(space, 1); LOGMASKED(LOG_SCSI, "%s: SCSI%d Read 1: %02x\n", machine().describe_context(), index, ret); return ret; } @@ -254,14 +325,14 @@ WRITE32_MEMBER(hpc3_device::hd_w) if (ACCESSING_BITS_0_7) { LOGMASKED(LOG_SCSI, "%s: SCSI%d Write 0 = %02x\n", machine().describe_context(), index, (uint8_t)data); - index ? m_wd33c93_2->write(space, 0, data & 0xff) : m_wd33c93->write(space, 0, data & 0xff); + index && m_wd33c93_2 ? m_wd33c93_2->write(space, 0, data & 0xff) : m_wd33c93->write(space, 0, data & 0xff); } break; case 0x0001: if (ACCESSING_BITS_0_7) { LOGMASKED(LOG_SCSI, "%s: SCSI%d Write 1 = %02x\n", machine().describe_context(), index, (uint8_t)data); - index ? m_wd33c93_2->write(space, 1, data & 0xff) : m_wd33c93->write(space, 1, data & 0xff); + index && m_wd33c93_2 ? m_wd33c93_2->write(space, 1, data & 0xff) : m_wd33c93->write(space, 1, data & 0xff); } break; default: @@ -271,10 +342,10 @@ WRITE32_MEMBER(hpc3_device::hd_w) } } -template DECLARE_READ32_MEMBER(hpc3_device::hd_r<0>); -template DECLARE_READ32_MEMBER(hpc3_device::hd_r<1>); -template DECLARE_WRITE32_MEMBER(hpc3_device::hd_w<0>); -template DECLARE_WRITE32_MEMBER(hpc3_device::hd_w<1>); +template READ32_MEMBER(hpc3_device::hd_r<0>); +template READ32_MEMBER(hpc3_device::hd_r<1>); +template WRITE32_MEMBER(hpc3_device::hd_w<0>); +template WRITE32_MEMBER(hpc3_device::hd_w<1>); READ32_MEMBER(hpc3_device::pbus4_r) { @@ -282,19 +353,19 @@ READ32_MEMBER(hpc3_device::pbus4_r) switch (offset) { case 0x0000/4: - ret = m_ioc2->get_local0_int_status(); + ret = m_ioc2->get_local_int_status(0); LOGMASKED(LOG_PBUS4, "%s: HPC3 INT3 Local0 Interrupt Status Read: %08x & %08x\n", machine().describe_context(), ret, mem_mask); break; case 0x0004/4: - ret = m_ioc2->get_local0_int_mask(); + ret = m_ioc2->get_local_int_mask(0); LOGMASKED(LOG_PBUS4, "%s: HPC3 INT3 Local0 Interrupt Mask Read: %08x & %08x\n", machine().describe_context(), ret, mem_mask); break; case 0x0008/4: - ret = m_ioc2->get_local1_int_status(); + ret = m_ioc2->get_local_int_status(1); LOGMASKED(LOG_PBUS4, "%s: HPC3 INT3 Local1 Interrupt Status Read: %08x & %08x\n", machine().describe_context(), ret, mem_mask); break; case 0x000c/4: - ret = m_ioc2->get_local1_int_mask(); + ret = m_ioc2->get_local_int_mask(1); LOGMASKED(LOG_PBUS4, "%s: HPC3 INT3 Local1 Interrupt Mask Read: %08x & %08x\n", machine().describe_context(), ret, mem_mask); break; case 0x0010/4: @@ -302,11 +373,11 @@ READ32_MEMBER(hpc3_device::pbus4_r) LOGMASKED(LOG_PBUS4, "%s: HPC3 INT3 Mappable Interrupt Status: %08x & %08x\n", machine().describe_context(), ret, mem_mask); break; case 0x0014/4: - ret = m_ioc2->get_map0_int_mask(); + ret = m_ioc2->get_map_int_mask(0); LOGMASKED(LOG_PBUS4, "%s: HPC3 INT3 Mapped Interrupt 0 Read: %08x & %08x\n", machine().describe_context(), ret, mem_mask); break; case 0x0018/4: - ret = m_ioc2->get_map1_int_mask(); + ret = m_ioc2->get_map_int_mask(1); LOGMASKED(LOG_PBUS4, "%s: HPC3 INT3 Mapped Interrupt 1 Read: %08x & %08x\n", machine().describe_context(), ret, mem_mask); break; case 0x0030/4: @@ -337,19 +408,19 @@ WRITE32_MEMBER(hpc3_device::pbus4_w) switch (offset) { case 0x0004/4: - m_ioc2->set_local0_int_mask(data); + m_ioc2->set_local_int_mask(0, data); LOGMASKED(LOG_PBUS4, "%s: HPC3 INT3 Local0 Interrupt Mask Write: %08x & %08x\n", machine().describe_context(), data, mem_mask); break; case 0x000c/4: - m_ioc2->set_local1_int_mask(data); + m_ioc2->set_local_int_mask(1, data); LOGMASKED(LOG_PBUS4, "%s: HPC3 INT3 Local1 Interrupt Mask Write: %08x & %08x\n", machine().describe_context(), data, mem_mask); break; case 0x0014/4: - m_ioc2->set_map0_int_mask(data); + m_ioc2->set_map_int_mask(0, data); LOGMASKED(LOG_PBUS4, "%s: HPC3 INT3 Mapped Interrupt 0 Write: %08x & %08x\n", machine().describe_context(), data, mem_mask); break; case 0x0018/4: - m_ioc2->set_map1_int_mask(data); + m_ioc2->set_map_int_mask(1, data); LOGMASKED(LOG_PBUS4, "%s: HPC3 INT3 Mapped Interrupt 1 Write: %08x & %08x\n", machine().describe_context(), data, mem_mask); break; case 0x0020/4: @@ -743,11 +814,11 @@ WRITE_LINE_MEMBER(hpc3_device::scsi0_irq) if (m_wd33c93->get_dma_count() && m_scsi_dma[0].m_active) scsi_dma(0); - m_ioc2->raise_local0_irq(ioc2_device::INT3_LOCAL0_SCSI0); + m_ioc2->raise_local_irq(0, ioc2_device::INT3_LOCAL0_SCSI0); } else { - m_ioc2->lower_local0_irq(ioc2_device::INT3_LOCAL0_SCSI0); + m_ioc2->lower_local_irq(0, ioc2_device::INT3_LOCAL0_SCSI0); } } @@ -758,10 +829,27 @@ WRITE_LINE_MEMBER(hpc3_device::scsi1_irq) if (m_wd33c93_2->get_dma_count() && m_scsi_dma[1].m_active) scsi_dma(1); - m_ioc2->raise_local0_irq(ioc2_device::INT3_LOCAL0_SCSI1); + m_ioc2->raise_local_irq(0, ioc2_device::INT3_LOCAL0_SCSI1); } else { - m_ioc2->lower_local0_irq(ioc2_device::INT3_LOCAL0_SCSI1); + m_ioc2->lower_local_irq(0, ioc2_device::INT3_LOCAL0_SCSI1); } } + +READ32_MEMBER(hpc3_device::eeprom_r) +{ + // Disabled - we don't have a dump from real hardware, and IRIX 5.x freaks out with default contents. + uint32_t ret = (m_cpu_aux_ctrl & ~0x10);// | m_eeprom->do_read() << 4; + logerror("%s: HPC Serial EEPROM Read: %08x & %08x\n", machine().describe_context(), ret, mem_mask); + return ret; +} + +WRITE32_MEMBER(hpc3_device::eeprom_w) +{ + m_cpu_aux_ctrl = data; + logerror("%s: HPC Serial EEPROM Write: %08x & %08x\n", machine().describe_context(), data, mem_mask); + m_eeprom->di_write(BIT(data, 3)); + m_eeprom->cs_write(BIT(data, 1)); + m_eeprom->clk_write(BIT(data, 2)); +} diff --git a/src/mame/machine/hpc3.h b/src/mame/machine/hpc3.h index d4d2a5af94b..94d6c65e595 100644 --- a/src/mame/machine/hpc3.h +++ b/src/mame/machine/hpc3.h @@ -12,40 +12,59 @@ #pragma once #include "cpu/mips/mips3.h" +#include "machine/ds1386.h" +#include "machine/eepromser.h" +#include "machine/hal2.h" #include "machine/ioc2.h" #include "machine/wd33c93.h" #include "sound/dac.h" +#include "sound/volt_reg.h" +#include "speaker.h" class hpc3_device : public device_t { public: - template - hpc3_device(const machine_config &mconfig, const char *tag, device_t *owner - , T &&cpu_tag, U &&scsi_tag, V &&ioc2_tag, W &&ldac_tag, X &&rdac_tag) + template + hpc3_device(const machine_config &mconfig, const char *tag, device_t *owner, T &&cpu_tag, U &&scsi_tag) : hpc3_device(mconfig, tag, owner, (uint32_t)0) { m_maincpu.set_tag(std::forward(cpu_tag)); m_wd33c93.set_tag(std::forward(scsi_tag)); - m_ioc2.set_tag(std::forward(ioc2_tag)); - m_ldac.set_tag(std::forward(ldac_tag)); - m_rdac.set_tag(std::forward(rdac_tag)); } - template - hpc3_device(const machine_config &mconfig, const char *tag, device_t *owner - , T &&cpu_tag, U &&scsi_tag, V &&scsi2_tag, W &&ioc2_tag, X &&ldac_tag, Y &&rdac_tag) - : hpc3_device(mconfig, tag, owner - , std::forward(cpu_tag), std::forward(scsi_tag), std::forward(ioc2_tag), std::forward(ldac_tag), std::forward(rdac_tag)) + template + hpc3_device(const machine_config &mconfig, const char *tag, device_t *owner, T &&cpu_tag, U &&scsi_tag, V &&scsi2_tag) + : hpc3_device(mconfig, tag, owner, std::forward(cpu_tag), std::forward(scsi_tag)) { m_wd33c93_2.set_tag(std::forward(scsi2_tag)); } hpc3_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + void map(address_map &map); + + void raise_local_irq(int channel, uint32_t mask) { m_ioc2->raise_local_irq(channel, mask); } + void lower_local_irq(int channel, uint32_t mask) { m_ioc2->lower_local_irq(channel, mask); } + + DECLARE_WRITE_LINE_MEMBER(scsi0_irq); + DECLARE_WRITE_LINE_MEMBER(scsi0_drq); + DECLARE_WRITE_LINE_MEMBER(scsi1_irq); + DECLARE_WRITE_LINE_MEMBER(scsi1_drq); + +protected: + virtual void device_start() override; + virtual void device_reset() override; + virtual void device_add_mconfig(machine_config &config) override; + virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override; + + DECLARE_READ32_MEMBER(enet_r); + DECLARE_WRITE32_MEMBER(enet_w); DECLARE_READ32_MEMBER(hd_enet_r); DECLARE_WRITE32_MEMBER(hd_enet_w); template DECLARE_READ32_MEMBER(hd_r); template DECLARE_WRITE32_MEMBER(hd_w); + DECLARE_READ32_MEMBER(eeprom_r); + DECLARE_WRITE32_MEMBER(eeprom_w); DECLARE_READ32_MEMBER(pbus4_r); DECLARE_WRITE32_MEMBER(pbus4_w); DECLARE_READ32_MEMBER(pbusdma_r); @@ -58,16 +77,6 @@ public: DECLARE_READ32_MEMBER(pio_config_r); DECLARE_WRITE32_MEMBER(pio_config_w); - DECLARE_WRITE_LINE_MEMBER(scsi0_irq); - DECLARE_WRITE_LINE_MEMBER(scsi0_drq); - DECLARE_WRITE_LINE_MEMBER(scsi1_irq); - DECLARE_WRITE_LINE_MEMBER(scsi1_drq); - -protected: - void device_start() override; - void device_reset() override; - void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override; - void do_pbus_dma(uint32_t channel); void dump_chain(uint32_t base); @@ -125,13 +134,16 @@ protected: required_device m_maincpu; required_device m_wd33c93; optional_device m_wd33c93_2; + required_device m_eeprom; + required_device m_rtc; required_device m_ioc2; + required_device m_hal2; required_device m_ldac; required_device m_rdac; - required_shared_ptr m_mainram; uint32_t m_enetr_nbdp; uint32_t m_enetr_cbp; + uint32_t m_cpu_aux_ctrl; struct scsi_dma_t { diff --git a/src/mame/machine/ioc2.cpp b/src/mame/machine/ioc2.cpp index 35d9da21278..4387f2a7ea2 100644 --- a/src/mame/machine/ioc2.cpp +++ b/src/mame/machine/ioc2.cpp @@ -118,13 +118,7 @@ ioc2_device::ioc2_device(const machine_config &mconfig, device_type type, const , m_dma_sel(0) , m_reset_reg(0) , m_write_reg(0) - , m_int3_local0_status_reg(0) - , m_int3_local0_mask_reg(0) - , m_int3_local1_status_reg(0) - , m_int3_local1_mask_reg(0) , m_int3_map_status_reg(0) - , m_int3_map_mask0_reg(0) - , m_int3_map_mask1_reg(0) , m_int3_map_pol_reg(0) , m_int3_err_status_reg(0) , m_par_read_cnt(0) @@ -146,13 +140,10 @@ void ioc2_device::device_start() save_item(NAME(m_reset_reg)); save_item(NAME(m_write_reg)); - save_item(NAME(m_int3_local0_status_reg)); - save_item(NAME(m_int3_local0_mask_reg)); - save_item(NAME(m_int3_local1_status_reg)); - save_item(NAME(m_int3_local1_mask_reg)); + save_item(NAME(m_int3_local_status_reg)); + save_item(NAME(m_int3_local_mask_reg)); save_item(NAME(m_int3_map_status_reg)); - save_item(NAME(m_int3_map_mask0_reg)); - save_item(NAME(m_int3_map_mask1_reg)); + save_item(NAME(m_int3_map_mask_reg)); save_item(NAME(m_int3_map_pol_reg)); save_item(NAME(m_int3_err_status_reg)); } @@ -171,39 +162,24 @@ void ioc2_device::device_reset() m_reset_reg = 0; m_write_reg = 0; - m_int3_local0_status_reg = 0; - m_int3_local0_mask_reg = 0; - m_int3_local1_status_reg = 0; - m_int3_local1_mask_reg = 0; + memset(m_int3_local_status_reg, 0, sizeof(uint8_t) * 2); + memset(m_int3_local_mask_reg, 0, sizeof(uint8_t) * 2); m_int3_map_status_reg = 0; - m_int3_map_mask0_reg = 0; - m_int3_map_mask1_reg = 0; + memset(m_int3_map_mask_reg, 0, sizeof(uint8_t) * 2); m_int3_map_pol_reg = 0; m_int3_err_status_reg = 0; } -void ioc2_device::raise_local0_irq(uint8_t source_mask) +void ioc2_device::raise_local_irq(int channel, uint8_t mask) { - m_int3_local0_status_reg |= source_mask; - m_maincpu->set_input_line(MIPS3_IRQ0, (m_int3_local0_mask_reg & m_int3_local0_status_reg) ? ASSERT_LINE : CLEAR_LINE); + m_int3_local_status_reg[channel] |= mask; + m_maincpu->set_input_line(MIPS3_IRQ0 + channel, (m_int3_local_mask_reg[channel] & m_int3_local_status_reg[channel]) ? ASSERT_LINE : CLEAR_LINE); } -void ioc2_device::lower_local0_irq(uint8_t source_mask) +void ioc2_device::lower_local_irq(int channel, uint8_t mask) { - m_int3_local0_status_reg &= ~source_mask; - m_maincpu->set_input_line(MIPS3_IRQ0, (m_int3_local0_mask_reg & m_int3_local0_status_reg) ? ASSERT_LINE : CLEAR_LINE); -} - -void ioc2_device::raise_local1_irq(uint8_t source_mask) -{ - m_int3_local1_status_reg |= source_mask; - m_maincpu->set_input_line(MIPS3_IRQ1, (m_int3_local1_mask_reg & m_int3_local1_status_reg) ? ASSERT_LINE : CLEAR_LINE); -} - -void ioc2_device::lower_local1_irq(uint8_t source_mask) -{ - m_int3_local1_status_reg &= ~source_mask; - m_maincpu->set_input_line(MIPS3_IRQ1, (m_int3_local1_mask_reg & m_int3_local1_status_reg) ? ASSERT_LINE : CLEAR_LINE); + m_int3_local_status_reg[channel] &= ~mask; + m_maincpu->set_input_line(MIPS3_IRQ0 + channel, (m_int3_local_mask_reg[channel] & m_int3_local_status_reg[channel]) ? ASSERT_LINE : CLEAR_LINE); } WRITE_LINE_MEMBER(ioc2_device::timer0_int) @@ -235,15 +211,15 @@ void ioc2_device::set_mappable_int(uint8_t mask, bool state) else m_int3_map_status_reg &= ~mask; - if (m_int3_map_mask0_reg & m_int3_map_status_reg) - raise_local0_irq(INT3_LOCAL0_MAPPABLE0); + if (m_int3_map_mask_reg[0] & m_int3_map_status_reg) + raise_local_irq(0, INT3_LOCAL0_MAPPABLE0); else - lower_local0_irq(INT3_LOCAL0_MAPPABLE0); + lower_local_irq(0, INT3_LOCAL0_MAPPABLE0); - if (m_int3_map_mask1_reg & m_int3_map_status_reg) - raise_local1_irq(INT3_LOCAL1_MAPPABLE1); + if (m_int3_map_mask_reg[1] & m_int3_map_status_reg) + raise_local_irq(1, INT3_LOCAL1_MAPPABLE1); else - lower_local1_irq(INT3_LOCAL1_MAPPABLE1); + lower_local_irq(1, INT3_LOCAL1_MAPPABLE1); } READ32_MEMBER(ioc2_device::read) @@ -374,26 +350,26 @@ READ32_MEMBER(ioc2_device::read) case INT3_LOCAL0_STATUS_REG: { - LOGMASKED(LOG_INT3, "%s: Read Interrupt Local0 Status Register: %02x\n", machine().describe_context(), m_int3_local0_status_reg); - return m_int3_local0_status_reg; + LOGMASKED(LOG_INT3, "%s: Read Interrupt Local0 Status Register: %02x\n", machine().describe_context(), m_int3_local_status_reg[0]); + return m_int3_local_status_reg[0]; } case INT3_LOCAL0_MASK_REG: { - LOGMASKED(LOG_INT3, "%s: Read Interrupt Local0 Mask Register: %02x\n", machine().describe_context(), m_int3_local0_mask_reg); - return m_int3_local0_mask_reg; + LOGMASKED(LOG_INT3, "%s: Read Interrupt Local0 Mask Register: %02x\n", machine().describe_context(), m_int3_local_mask_reg[0]); + return m_int3_local_mask_reg[0]; } case INT3_LOCAL1_STATUS_REG: { - LOGMASKED(LOG_INT3, "%s: Read Interrupt Local1 Status Register: %02x\n", machine().describe_context(), m_int3_local1_status_reg); - return m_int3_local1_status_reg; + LOGMASKED(LOG_INT3, "%s: Read Interrupt Local1 Status Register: %02x\n", machine().describe_context(), m_int3_local_status_reg[1]); + return m_int3_local_status_reg[1]; } case INT3_LOCAL1_MASK_REG: { - LOGMASKED(LOG_INT3, "%s: Read Interrupt Local1 Mask Register: %02x\n", machine().describe_context(), m_int3_local1_mask_reg); - return m_int3_local1_mask_reg; + LOGMASKED(LOG_INT3, "%s: Read Interrupt Local1 Mask Register: %02x\n", machine().describe_context(), m_int3_local_mask_reg[1]); + return m_int3_local_mask_reg[1]; } case INT3_MAP_STATUS_REG: @@ -404,14 +380,14 @@ READ32_MEMBER(ioc2_device::read) case INT3_MAP_MASK0_REG: { - LOGMASKED(LOG_INT3, "%s: Read Interrupt Map Mask0 Register: %02x\n", machine().describe_context(), m_int3_map_mask0_reg); - return m_int3_map_mask0_reg; + LOGMASKED(LOG_INT3, "%s: Read Interrupt Map Mask0 Register: %02x\n", machine().describe_context(), m_int3_map_mask_reg[0]); + return m_int3_map_mask_reg[0]; } case INT3_MAP_MASK1_REG: { - LOGMASKED(LOG_INT3, "%s: Read Interrupt Map Mask1 Register: %02x\n", machine().describe_context(), m_int3_map_mask1_reg); - return m_int3_map_mask1_reg; + LOGMASKED(LOG_INT3, "%s: Read Interrupt Map Mask1 Register: %02x\n", machine().describe_context(), m_int3_map_mask_reg[1]); + return m_int3_map_mask_reg[1]; } case INT3_MAP_POLARITY_REG: @@ -530,7 +506,7 @@ WRITE32_MEMBER( ioc2_device::write ) LOGMASKED(LOG_PANEL, "%s: Write Front Panel Register: %02x\n", machine().describe_context(), (uint8_t)data); m_front_panel_reg &= ~(data & (FRONT_PANEL_VOL_UP_INT | FRONT_PANEL_VOL_DOWN_INT | FRONT_PANEL_POWER_BUTTON_INT)); if (!(m_front_panel_reg & FRONT_PANEL_INT_MASK)) - lower_local1_irq(INT3_LOCAL1_PANEL); + lower_local_irq(1, INT3_LOCAL1_PANEL); return; case DMA_SEL_REG: @@ -577,27 +553,27 @@ WRITE32_MEMBER( ioc2_device::write ) case INT3_LOCAL0_MASK_REG: { LOGMASKED(LOG_INT3, "%s: Write Interrupt Local0 Mask Register: %02x\n", machine().describe_context(), (uint8_t)data); - set_local0_int_mask(data); + set_local_int_mask(0, data); return; } case INT3_LOCAL1_MASK_REG: { LOGMASKED(LOG_INT3, "%s: Write Interrupt Local1 Mask Register: %02x\n", machine().describe_context(), (uint8_t)data); - set_local1_int_mask(data); + set_local_int_mask(1, data); return; } case INT3_MAP_MASK0_REG: // TODO: Implement mappable interrupts LOGMASKED(LOG_INT3, "%s: Write Interrupt Map Mask0 Register: %02x\n", machine().describe_context(), (uint8_t)data); - set_map0_int_mask(data); + set_map_int_mask(0, data); return; case INT3_MAP_MASK1_REG: // TODO: Implement mappable interrupts LOGMASKED(LOG_INT3, "%s: Write Interrupt Map Mask1 Register: %02x\n", machine().describe_context(), (uint8_t)data); - set_map1_int_mask(data); + set_map_int_mask(1, data); return; case INT3_MAP_POLARITY_REG: @@ -632,40 +608,22 @@ WRITE32_MEMBER( ioc2_device::write ) } } -void ioc2_device::set_local0_int_mask(uint32_t data) +void ioc2_device::set_local_int_mask(int channel, uint32_t mask) { - uint8_t old = m_int3_local0_mask_reg; - m_int3_local0_mask_reg = (uint8_t)data; - bool old_line = (old & m_int3_local0_status_reg) != 0; - bool new_line = (m_int3_local0_mask_reg & m_int3_local0_status_reg) != 0; + uint8_t old = m_int3_local_mask_reg[channel]; + m_int3_local_mask_reg[channel] = (uint8_t)mask; + bool old_line = (old & m_int3_local_status_reg[channel]) != 0; + bool new_line = (m_int3_local_mask_reg[channel] & m_int3_local_status_reg[channel]) != 0; if (old_line != new_line) { - const uint32_t int_bits = (m_int3_local1_mask_reg & m_int3_local1_status_reg) | (m_int3_local0_mask_reg & m_int3_local0_status_reg); - m_maincpu->set_input_line(MIPS3_IRQ0, int_bits != 0 ? ASSERT_LINE : CLEAR_LINE); + const uint32_t int_bits = (m_int3_local_mask_reg[channel] & m_int3_local_status_reg[channel]); + m_maincpu->set_input_line(MIPS3_IRQ0 + channel, int_bits != 0 ? ASSERT_LINE : CLEAR_LINE); } } -void ioc2_device::set_local1_int_mask(uint32_t data) +void ioc2_device::set_map_int_mask(int channel, uint32_t mask) { - uint8_t old = m_int3_local1_mask_reg; - m_int3_local1_mask_reg = (uint8_t)data; - bool old_line = (old & m_int3_local1_status_reg) != 0; - bool new_line = (m_int3_local1_mask_reg & m_int3_local1_status_reg) != 0; - if (old_line != new_line) - { - const uint32_t int_bits = (m_int3_local1_mask_reg & m_int3_local1_status_reg) | (m_int3_local0_mask_reg & m_int3_local0_status_reg); - m_maincpu->set_input_line(MIPS3_IRQ0, int_bits != 0 ? ASSERT_LINE : CLEAR_LINE); - } -} - -void ioc2_device::set_map0_int_mask(uint32_t data) -{ - m_int3_map_mask0_reg = (uint8_t)data; -} - -void ioc2_device::set_map1_int_mask(uint32_t data) -{ - m_int3_map_mask1_reg = (uint8_t)data; + m_int3_map_mask_reg[channel] = (uint8_t)mask; } void ioc2_device::set_timer_int_clear(uint32_t data) @@ -694,7 +652,7 @@ INPUT_CHANGED_MEMBER( ioc2_device::power_button ) m_front_panel_reg &= ~FRONT_PANEL_POWER_BUTTON_INT; if (m_front_panel_reg & FRONT_PANEL_INT_MASK) - raise_local1_irq(INT3_LOCAL1_PANEL); + raise_local_irq(1, INT3_LOCAL1_PANEL); } INPUT_CHANGED_MEMBER( ioc2_device::volume_up ) @@ -710,7 +668,7 @@ INPUT_CHANGED_MEMBER( ioc2_device::volume_up ) } if (m_front_panel_reg & FRONT_PANEL_INT_MASK) - raise_local1_irq(INT3_LOCAL1_PANEL); + raise_local_irq(1, INT3_LOCAL1_PANEL); } INPUT_CHANGED_MEMBER( ioc2_device::volume_down ) @@ -726,5 +684,5 @@ INPUT_CHANGED_MEMBER( ioc2_device::volume_down ) } if (m_front_panel_reg & FRONT_PANEL_INT_MASK) - raise_local1_irq(INT3_LOCAL1_PANEL); + raise_local_irq(1, INT3_LOCAL1_PANEL); } diff --git a/src/mame/machine/ioc2.h b/src/mame/machine/ioc2.h index 387bd491880..fe2b1bc3fc7 100644 --- a/src/mame/machine/ioc2.h +++ b/src/mame/machine/ioc2.h @@ -30,10 +30,8 @@ public: DECLARE_INPUT_CHANGED_MEMBER( volume_down ); DECLARE_INPUT_CHANGED_MEMBER( volume_up ); - void lower_local0_irq(uint8_t source_mask); - void raise_local0_irq(uint8_t source_mask); - void lower_local1_irq(uint8_t source_mask); - void raise_local1_irq(uint8_t source_mask); + void raise_local_irq(int channel, uint8_t mask); + void lower_local_irq(int channel, uint8_t mask); enum { @@ -59,18 +57,13 @@ public: INT3_LOCAL1_RETRACE = 0x80, }; - uint32_t get_local0_int_status() const { return m_int3_local0_status_reg; } - uint32_t get_local0_int_mask() const { return m_int3_local0_mask_reg; } - uint32_t get_local1_int_status() const { return m_int3_local1_status_reg; } - uint32_t get_local1_int_mask() const { return m_int3_local1_mask_reg; } + uint32_t get_local_int_status(int channel) const { return m_int3_local_status_reg[channel]; } + uint32_t get_local_int_mask(int channel) const { return m_int3_local_mask_reg[channel]; } uint32_t get_map_int_status() const { return m_int3_map_status_reg; } - uint32_t get_map0_int_mask() const { return m_int3_map_mask0_reg; } - uint32_t get_map1_int_mask() const { return m_int3_map_mask1_reg; } + uint32_t get_map_int_mask(int channel) const { return m_int3_map_mask_reg[channel]; } - void set_local0_int_mask(const uint32_t data); - void set_local1_int_mask(const uint32_t data); - void set_map0_int_mask(const uint32_t data); - void set_map1_int_mask(const uint32_t data); + void set_local_int_mask(int channel, const uint32_t mask); + void set_map_int_mask(int channel, const uint32_t mask); void set_timer_int_clear(const uint32_t data); uint8_t get_pit_reg(uint32_t offset) { return m_pit->read(offset); } @@ -180,13 +173,10 @@ protected: uint8_t m_reset_reg; uint8_t m_write_reg; - uint8_t m_int3_local0_status_reg; - uint8_t m_int3_local0_mask_reg; - uint8_t m_int3_local1_status_reg; - uint8_t m_int3_local1_mask_reg; + uint8_t m_int3_local_status_reg[2]; + uint8_t m_int3_local_mask_reg[2]; uint8_t m_int3_map_status_reg; - uint8_t m_int3_map_mask0_reg; - uint8_t m_int3_map_mask1_reg; + uint8_t m_int3_map_mask_reg[2]; uint8_t m_int3_map_pol_reg; uint8_t m_int3_err_status_reg; diff --git a/src/mame/machine/mace.cpp b/src/mame/machine/mace.cpp new file mode 100644 index 00000000000..9767b86b31d --- /dev/null +++ b/src/mame/machine/mace.cpp @@ -0,0 +1,572 @@ +// license:BSD-3-Clause +// copyright-holders:Ryan Holtz +/********************************************************************** + + SGI MACE skeleton device + +**********************************************************************/ + +#include "emu.h" +#include "machine/mace.h" + +#define LOG_READ_PCI (1 << 0U) +#define LOG_READ_VIN1 (1 << 1U) +#define LOG_READ_VIN2 (1 << 2U) +#define LOG_READ_VOUT (1 << 3U) +#define LOG_READ_ENET (1 << 4U) +#define LOG_READ_AUDIO (1 << 5U) +#define LOG_READ_ISA (1 << 6U) +#define LOG_READ_KBDMS (1 << 7U) +#define LOG_READ_I2C (1 << 8U) +#define LOG_READ_UST_MSC (1 << 9U) +#define LOG_READ_ISA_EXT (1 << 10U) +#define LOG_READ_RTC (1 << 11U) +#define LOG_WRITE_PCI (1 << 12U) +#define LOG_WRITE_VIN1 (1 << 13U) +#define LOG_WRITE_VIN2 (1 << 14U) +#define LOG_WRITE_VOUT (1 << 15U) +#define LOG_WRITE_ENET (1 << 16U) +#define LOG_WRITE_AUDIO (1 << 17U) +#define LOG_WRITE_ISA (1 << 18U) +#define LOG_WRITE_KBDMS (1 << 19U) +#define LOG_WRITE_I2C (1 << 20U) +#define LOG_WRITE_UST_MSC (1 << 21U) +#define LOG_WRITE_ISA_EXT (1 << 22U) +#define LOG_WRITE_RTC (1 << 23U) +#define LOG_HIFREQ (1 << 24U) +#define LOG_PCI (LOG_READ_PCI | LOG_WRITE_PCI) +#define LOG_VIN1 (LOG_READ_VIN1 | LOG_WRITE_VIN1) +#define LOG_VIN2 (LOG_READ_VIN2 | LOG_WRITE_VIN2) +#define LOG_VOUT (LOG_READ_VOUT | LOG_WRITE_VOUT) +#define LOG_ENET (LOG_READ_ENET | LOG_WRITE_ENET) +#define LOG_AUDIO (LOG_READ_AUDIO | LOG_WRITE_AUDIO) +#define LOG_ISA (LOG_READ_ISA | LOG_WRITE_ISA) +#define LOG_KBDMS (LOG_READ_KBDMS | LOG_WRITE_KBDMS) +#define LOG_UST_MSC (LOG_READ_UST_MSC | LOG_WRITE_UST_MSC) +#define LOG_ISA_EXT (LOG_READ_ISA_EXT | LOG_WRITE_ISA_EXT) +#define LOG_RTC (LOG_READ_RTC | LOG_WRITE_RTC) +#define LOG_ALL (LOG_PCI | LOG_VIN1 | LOG_VIN2 | LOG_VOUT | LOG_ENET | LOG_AUDIO | LOG_ISA | LOG_KBDMS | LOG_UST_MSC | LOG_ISA_EXT | LOG_RTC) + +#define VERBOSE (LOG_ALL) +#include "logmacro.h" + +DEFINE_DEVICE_TYPE(SGI_MACE, mace_device, "sgimace", "SGI MACE") + +mace_device::mace_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) + : device_t(mconfig, SGI_MACE, tag, owner, clock) + , m_maincpu(*this, finder_base::DUMMY_TAG) +{ +} + +void mace_device::device_start() +{ + save_item(NAME(m_isa.m_ringbase_reset)); + save_item(NAME(m_isa.m_flash_nic_ctrl)); + save_item(NAME(m_isa.m_int_status)); + save_item(NAME(m_isa.m_int_mask)); + + save_item(NAME(m_ust_msc.m_msc)); + save_item(NAME(m_ust_msc.m_ust)); + save_item(NAME(m_ust_msc.m_ust_msc)); + save_item(NAME(m_ust_msc.m_compare1)); + save_item(NAME(m_ust_msc.m_compare2)); + save_item(NAME(m_ust_msc.m_compare3)); + save_item(NAME(m_ust_msc.m_ain_msc_ust)); + save_item(NAME(m_ust_msc.m_aout1_msc_ust)); + save_item(NAME(m_ust_msc.m_aout2_msc_ust)); + save_item(NAME(m_ust_msc.m_vin1_msc_ust)); + save_item(NAME(m_ust_msc.m_vin2_msc_ust)); + save_item(NAME(m_ust_msc.m_vout_msc_ust)); + + m_timer_ust = timer_alloc(TIMER_UST); + m_timer_msc = timer_alloc(TIMER_MSC); + m_timer_ust->adjust(attotime::never); + m_timer_msc->adjust(attotime::never); + + save_item(NAME(m_rtc.m_unknown)); +} + +void mace_device::device_reset() +{ + memset(&m_isa, 0, sizeof(isa_t)); + memset(&m_ust_msc, 0, sizeof(ust_msc_t)); + memset(&m_rtc, 0, sizeof(rtc_t)); + + m_timer_ust->adjust(attotime::from_nsec(960), 0, attotime::from_nsec(960)); + m_timer_msc->adjust(attotime::from_msec(1), 0, attotime::from_msec(1)); +} + +//************************************************************************** +// DEVICE HARDWARE +//************************************************************************** + +void mace_device::device_add_mconfig(machine_config &config) +{ +} + +void mace_device::map(address_map &map) +{ + map(0x00080000, 0x000fffff).rw(FUNC(mace_device::pci_r), FUNC(mace_device::pci_w)); + map(0x00100000, 0x0017ffff).rw(FUNC(mace_device::vin1_r), FUNC(mace_device::vin1_w)); + map(0x00180000, 0x001fffff).rw(FUNC(mace_device::vin2_r), FUNC(mace_device::vin2_w)); + map(0x00200000, 0x0027ffff).rw(FUNC(mace_device::vout_r), FUNC(mace_device::vout_w)); + map(0x00280000, 0x002fffff).rw(FUNC(mace_device::enet_r), FUNC(mace_device::enet_w)); + map(0x00300000, 0x0030ffff).rw(FUNC(mace_device::audio_r), FUNC(mace_device::audio_w)); + map(0x00310000, 0x0031ffff).rw(FUNC(mace_device::isa_r), FUNC(mace_device::isa_w)); + map(0x00320000, 0x0032ffff).rw(FUNC(mace_device::kbdms_r), FUNC(mace_device::kbdms_w)); + map(0x00330000, 0x0033ffff).rw(FUNC(mace_device::i2c_r), FUNC(mace_device::i2c_w)); + map(0x00340000, 0x0034ffff).rw(FUNC(mace_device::ust_msc_r), FUNC(mace_device::ust_msc_w)); + map(0x00380000, 0x0039ffff).rw(FUNC(mace_device::isa_ext_r), FUNC(mace_device::isa_ext_w)); + map(0x003a0000, 0x003a3fff).rw(FUNC(mace_device::rtc_r), FUNC(mace_device::rtc_w)); +} + +//************************************************************************** +// REGISTER ACCESS +//************************************************************************** + +READ64_MEMBER(mace_device::pci_r) +{ + uint64_t ret = 0ULL; + switch (offset) + { + default: + LOGMASKED(LOG_READ_PCI, "%s: MACE: PCI: Unknown Read: [%08x] & %08x%08x\n", machine().describe_context() + , 0x1f080000 + offset*8, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + break; + } + return ret; +} + +WRITE64_MEMBER(mace_device::pci_w) +{ + switch (offset) + { + default: + LOGMASKED(LOG_WRITE_PCI, "%s: MACE: PCI: Unknown Write: %08x = %08x%08x & %08x%08x\n", machine().describe_context(), 0x1f080000 + offset*8 + , (uint32_t)(data >> 32), (uint32_t)data, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + return; + } +} + +READ64_MEMBER(mace_device::vin1_r) +{ + uint64_t ret = 0ULL; + switch (offset) + { + default: + LOGMASKED(LOG_READ_VIN1, "%s: MACE: VIN1: Unknown Read: [%08x] & %08x%08x\n", machine().describe_context() + , 0x1f100000 + offset*8, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + break; + } + return ret; +} + +WRITE64_MEMBER(mace_device::vin1_w) +{ + switch (offset) + { + default: + LOGMASKED(LOG_WRITE_VIN1, "%s: MACE: VIN1: Unknown Write: %08x = %08x%08x & %08x%08x\n", machine().describe_context(), 0x1f100000 + offset*8 + , (uint32_t)(data >> 32), (uint32_t)data, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + return; + } +} + +READ64_MEMBER(mace_device::vin2_r) +{ + uint64_t ret = 0ULL; + switch (offset) + { + default: + LOGMASKED(LOG_READ_VIN2, "%s: MACE: VIN2: Unknown Read: [%08x] & %08x%08x\n", machine().describe_context() + , 0x1f180000 + offset*8, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + break; + } + return ret; +} + +WRITE64_MEMBER(mace_device::vin2_w) +{ + switch (offset) + { + default: + LOGMASKED(LOG_WRITE_VIN2, "%s: MACE: VIN2: Unknown Write: %08x = %08x%08x & %08x%08x\n", machine().describe_context(), 0x1f180000 + offset*8 + , (uint32_t)(data >> 32), (uint32_t)data, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + return; + } +} + +READ64_MEMBER(mace_device::vout_r) +{ + uint64_t ret = 0ULL; + switch (offset) + { + default: + LOGMASKED(LOG_READ_VOUT, "%s: MACE: VOUT: Unknown Read: [%08x] & %08x%08x\n", machine().describe_context() + , 0x1f200000 + offset*8, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + break; + } + return ret; +} + +WRITE64_MEMBER(mace_device::vout_w) +{ + switch (offset) + { + default: + LOGMASKED(LOG_WRITE_VOUT, "%s: MACE: VOUT: Unknown Write: %08x = %08x%08x & %08x%08x\n", machine().describe_context(), 0x1f200000 + offset*8 + , (uint32_t)(data >> 32), (uint32_t)data, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + return; + } +} + +READ64_MEMBER(mace_device::enet_r) +{ + uint64_t ret = 0ULL; + switch (offset) + { + default: + LOGMASKED(LOG_READ_ENET, "%s: MACE: ENET: Unknown Read: [%08x] & %08x%08x\n", machine().describe_context() + , 0x1f280000 + offset*8, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + break; + } + return ret; +} + +WRITE64_MEMBER(mace_device::enet_w) +{ + switch (offset) + { + default: + LOGMASKED(LOG_WRITE_ENET, "%s: MACE: ENET: Unknown Write: %08x = %08x%08x & %08x%08x\n", machine().describe_context(), 0x1f280000 + offset*8 + , (uint32_t)(data >> 32), (uint32_t)data, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + return; + } +} + +READ64_MEMBER(mace_device::audio_r) +{ + uint64_t ret = 0ULL; + switch (offset) + { + default: + LOGMASKED(LOG_READ_AUDIO, "%s: MACE: AUDIO: Unknown Read: [%08x] & %08x%08x\n", machine().describe_context() + , 0x1f300000 + offset*8, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + break; + } + return ret; +} + +WRITE64_MEMBER(mace_device::audio_w) +{ + switch (offset) + { + default: + LOGMASKED(LOG_WRITE_AUDIO, "%s: MACE: AUDIO: Unknown Write: %08x = %08x%08x & %08x%08x\n", machine().describe_context(), 0x1f300000 + offset*8 + , (uint32_t)(data >> 32), (uint32_t)data, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + return; + } +} + +READ64_MEMBER(mace_device::isa_r) +{ + uint64_t ret = 0ULL; + switch (offset) + { + case 0x0000/8: + ret = m_isa.m_ringbase_reset; + LOGMASKED(LOG_READ_ISA, "%s: MACE: ISA: Ringbase Address Read: %08x%08x & %08x%08x\n", machine().describe_context() + , (uint32_t)(ret >> 32), (uint32_t)ret, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + break; + case 0x0008/8: + ret = m_isa.m_flash_nic_ctrl; + LOGMASKED(LOG_HIFREQ, "%s: MACE: ISA: Flash/LED/DPRAM/NIC Control Read: %08x%08x & %08x%08x\n", machine().describe_context() + , (uint32_t)(ret >> 32), (uint32_t)ret, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + break; + case 0x0010/8: + ret = m_isa.m_int_status; + LOGMASKED(LOG_READ_ISA, "%s: MACE: ISA: Interrupt Status Read: %08x%08x & %08x%08x\n", machine().describe_context() + , (uint32_t)(ret >> 32), (uint32_t)ret, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + break; + case 0x0018/8: + ret = m_isa.m_int_mask; + LOGMASKED(LOG_READ_ISA, "%s: MACE: ISA: Interrupt Mask Read: %08x%08x & %08x%08x\n", machine().describe_context() + , (uint32_t)(ret >> 32), (uint32_t)ret, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + break; + default: + LOGMASKED(LOG_READ_ISA, "%s: MACE: ISA: Unknown Read: [%08x] & %08x%08x\n", machine().describe_context() + , 0x1f310000 + offset*8, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + break; + } + return ret; +} + +WRITE64_MEMBER(mace_device::isa_w) +{ + switch (offset) + { + case 0x0000/8: + LOGMASKED(LOG_WRITE_ISA, "%s: MACE: ISA: Ringbase Address/Reset Write: %08x%08x & %08x%08x\n", machine().describe_context() + , (uint32_t)(data >> 32), (uint32_t)data, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + m_isa.m_ringbase_reset = data; + break; + case 0x0008/8: + LOGMASKED(LOG_HIFREQ, "%s: MACE: ISA: Flash/LED/DPRAM/NIC Control Write: %08x%08x & %08x%08x\n", machine().describe_context() + , (uint32_t)(data >> 32), (uint32_t)data, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + LOGMASKED(LOG_HIFREQ, " Enable Flash Writes: %d\n", BIT(data, 0)); + LOGMASKED(LOG_HIFREQ, " NIC Deassert: %d\n", BIT(data, 2)); + LOGMASKED(LOG_HIFREQ, " NIC Data: %d\n", BIT(data, 3)); + LOGMASKED(LOG_HIFREQ, " Red LED: %d\n", BIT(data, 4)); + LOGMASKED(LOG_HIFREQ, " Green LED: %d\n", BIT(data, 5)); + LOGMASKED(LOG_HIFREQ, " DP-RAM Enable: %d\n", BIT(data, 6)); + m_isa.m_flash_nic_ctrl = data; + break; + case 0x0010/8: + LOGMASKED(LOG_WRITE_ISA, "%s: MACE: ISA: Interrupt Status Write (Ignored): %08x%08x & %08x%08x\n", machine().describe_context() + , (uint32_t)(data >> 32), (uint32_t)data, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + break; + case 0x0018/8: + LOGMASKED(LOG_WRITE_ISA, "%s: MACE: ISA: Interrupt Mask Write: %08x%08x & %08x%08x\n", machine().describe_context() + , (uint32_t)(data >> 32), (uint32_t)data, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + m_isa.m_int_mask = data; + break; + default: + LOGMASKED(LOG_WRITE_ISA, "%s: MACE: ISA: Unknown Write: %08x = %08x%08x & %08x%08x\n", machine().describe_context(), 0x1f310000 + offset*8 + , (uint32_t)(data >> 32), (uint32_t)data, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + return; + } +} + +READ64_MEMBER(mace_device::kbdms_r) +{ + uint64_t ret = 0ULL; + switch (offset) + { + default: + LOGMASKED(LOG_READ_KBDMS, "%s: MACE: KBDMS: Unknown Read: [%08x] & %08x%08x\n", machine().describe_context() + , 0x1f320000 + offset*8, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + break; + } + return ret; +} + +WRITE64_MEMBER(mace_device::kbdms_w) +{ + switch (offset) + { + default: + LOGMASKED(LOG_WRITE_KBDMS, "%s: MACE: KBDMS: Unknown Write: %08x = %08x%08x & %08x%08x\n", machine().describe_context(), 0x1f320000 + offset*8 + , (uint32_t)(data >> 32), (uint32_t)data, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + return; + } +} + +READ64_MEMBER(mace_device::i2c_r) +{ + uint64_t ret = 0ULL; + switch (offset) + { + default: + LOGMASKED(LOG_READ_I2C, "%s: MACE: I2C: Unknown Read: [%08x] & %08x%08x\n", machine().describe_context() + , 0x1f330000 + offset*8, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + break; + } + return ret; +} + +WRITE64_MEMBER(mace_device::i2c_w) +{ + switch (offset) + { + default: + LOGMASKED(LOG_WRITE_I2C, "%s: MACE: I2C: Unknown Write: %08x = %08x%08x & %08x%08x\n", machine().describe_context(), 0x1f330000 + offset*8 + , (uint32_t)(data >> 32), (uint32_t)data, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + return; + } +} + +READ64_MEMBER(mace_device::isa_ext_r) +{ + uint64_t ret = 0ULL; + switch (offset) + { + default: + LOGMASKED(LOG_READ_ISA_EXT, "%s: MACE: ISA_EXT: Unknown Read: [%08x] & %08x%08x\n", machine().describe_context() + , 0x1f380000 + offset*8, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + break; + } + return ret; +} + +WRITE64_MEMBER(mace_device::isa_ext_w) +{ + switch (offset) + { + default: + LOGMASKED(LOG_WRITE_ISA_EXT, "%s: MACE: ISA_EXT: Unknown Write: %08x = %08x%08x & %08x%08x\n", machine().describe_context(), 0x1f380000 + offset*8 + , (uint32_t)(data >> 32), (uint32_t)data, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + return; + } +} + +//************************************************************************** +// RTC +//************************************************************************** + +READ64_MEMBER(mace_device::rtc_r) +{ + uint64_t ret = 0ULL; + switch (offset) + { + case 0x3f00/8: + ret = m_rtc.m_unknown; + LOGMASKED(LOG_READ_RTC, "%s: MACE: RTC: Unknown Read: %08x = %08x%08x & %08x%08x\n", machine().describe_context(), 0x1f3a0000 + offset*8 + , (uint32_t)(ret >> 32), (uint32_t)ret, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + break; + default: + LOGMASKED(LOG_READ_RTC, "%s: MACE: RTC: Unknown Read: %08x = %08x%08x & %08x%08x\n", machine().describe_context() + , 0x1f3a0000 + offset*8, (uint32_t)(ret >> 32), (uint32_t)ret, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + break; + } + return ret; +} + +WRITE64_MEMBER(mace_device::rtc_w) +{ + switch (offset) + { + case 0x3f00/8: + LOGMASKED(LOG_WRITE_RTC, "%s: MACE: RTC: Unknown Write: %08x = %08x%08x & %08x%08x\n", machine().describe_context(), 0x1f3a0000 + offset*8 + , (uint32_t)(data >> 32), (uint32_t)data, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + m_rtc.m_unknown = data; + break; + default: + LOGMASKED(LOG_WRITE_RTC, "%s: MACE: RTC: Unknown Write: %08x = %08x%08x & %08x%08x\n", machine().describe_context(), 0x1f3a0000 + offset*8 + , (uint32_t)(data >> 32), (uint32_t)data, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + return; + } +} + +//************************************************************************** +// TIMERS +//************************************************************************** + +void mace_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) +{ + if (id == TIMER_UST) + { + m_ust_msc.m_ust++; + m_ust_msc.m_ust_msc &= 0x00000000ffffffffULL; + m_ust_msc.m_ust_msc |= (uint64_t)m_ust_msc.m_ust << 32; + } + else if (id == TIMER_MSC) + { + m_ust_msc.m_msc++; + m_ust_msc.m_ust_msc &= 0xffffffff00000000ULL; + m_ust_msc.m_ust_msc |= m_ust_msc.m_msc; + } + check_ust_msc_compare(); +} + +void mace_device::check_ust_msc_compare() +{ + if (m_ust_msc.m_ust_msc == m_ust_msc.m_compare1) + m_isa.m_int_status |= ISA_INT_COMPARE1; + if (m_ust_msc.m_ust_msc == m_ust_msc.m_compare2) + m_isa.m_int_status |= ISA_INT_COMPARE2; + if (m_ust_msc.m_ust_msc == m_ust_msc.m_compare3) + m_isa.m_int_status |= ISA_INT_COMPARE3; +} + +READ64_MEMBER(mace_device::ust_msc_r) +{ + uint64_t ret = 0ULL; + switch (offset) + { + case 0x0000/8: + ret = ((uint64_t)m_ust_msc.m_ust << 32) | m_ust_msc.m_msc; + LOGMASKED(LOG_HIFREQ, "%s: MACE: UST_MSC: MSC/UST Counter Read: %08x%08x & %08x%08x\n", machine().describe_context() + , m_ust_msc.m_ust, m_ust_msc.m_msc, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + break; + case 0x0008/8: + ret = m_ust_msc.m_compare1; + LOGMASKED(LOG_READ_UST_MSC, "%s: MACE: UST_MSC: Compare1 Read: %08x%08x & %08x%08x\n", machine().describe_context() + , (uint32_t)(ret >> 32), (uint32_t)ret, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + break; + case 0x0010/8: + ret = m_ust_msc.m_compare2; + LOGMASKED(LOG_READ_UST_MSC, "%s: MACE: UST_MSC: Compare2 Read: %08x%08x & %08x%08x\n", machine().describe_context() + , (uint32_t)(ret >> 32), (uint32_t)ret, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + break; + case 0x0018/8: + ret = m_ust_msc.m_compare3; + LOGMASKED(LOG_READ_UST_MSC, "%s: MACE: UST_MSC: Compare3 Read: %08x%08x & %08x%08x\n", machine().describe_context() + , (uint32_t)(ret >> 32), (uint32_t)ret, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + break; + case 0x0020/8: + ret = m_ust_msc.m_ain_msc_ust; + LOGMASKED(LOG_READ_UST_MSC, "%s: MACE: UST_MSC: Audio In MSC/UST Read: %08x%08x & %08x%08x\n", machine().describe_context() + , (uint32_t)(ret >> 32), (uint32_t)ret, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + break; + case 0x0028/8: + ret = m_ust_msc.m_aout1_msc_ust; + LOGMASKED(LOG_READ_UST_MSC, "%s: MACE: UST_MSC: Audio Out 1 MSC/UST Read: %08x%08x & %08x%08x\n", machine().describe_context() + , (uint32_t)(ret >> 32), (uint32_t)ret, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + break; + case 0x0030/8: + ret = m_ust_msc.m_aout2_msc_ust; + LOGMASKED(LOG_READ_UST_MSC, "%s: MACE: UST_MSC: Audio Out 2 MSC/UST Read: %08x%08x & %08x%08x\n", machine().describe_context() + , (uint32_t)(ret >> 32), (uint32_t)ret, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + break; + case 0x0038/8: + ret = m_ust_msc.m_vin1_msc_ust; + LOGMASKED(LOG_READ_UST_MSC, "%s: MACE: UST_MSC: Video In 1 MSC/UST Read: %08x%08x & %08x%08x\n", machine().describe_context() + , (uint32_t)(ret >> 32), (uint32_t)ret, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + break; + case 0x0040/8: + ret = m_ust_msc.m_vin2_msc_ust; + LOGMASKED(LOG_READ_UST_MSC, "%s: MACE: UST_MSC: Video In 2 MSC/UST Read: %08x%08x & %08x%08x\n", machine().describe_context() + , (uint32_t)(ret >> 32), (uint32_t)ret, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + break; + case 0x0048/8: + ret = m_ust_msc.m_vout_msc_ust; + LOGMASKED(LOG_READ_UST_MSC, "%s: MACE: UST_MSC: Video Out MSC/UST Read: %08x%08x & %08x%08x\n", machine().describe_context() + , (uint32_t)(ret >> 32), (uint32_t)ret, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + break; + default: + LOGMASKED(LOG_READ_UST_MSC, "%s: MACE: UST_MSC: Unknown Read: [%08x] & %08x%08x\n", machine().describe_context() + , 0x1f340000 + offset*8, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + break; + } + return ret; +} + +WRITE64_MEMBER(mace_device::ust_msc_w) +{ + switch (offset) + { + case 0x0000/8: + LOGMASKED(LOG_WRITE_UST_MSC, "%s: MACE: UST_MSC: MSC/UST Counter Write (Ignored): %08x%08x & %08x%08x\n", machine().describe_context() + , (uint32_t)(data >> 32), (uint32_t)data, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + break; + case 0x0008/8: + LOGMASKED(LOG_WRITE_UST_MSC, "%s: MACE: UST_MSC: Compare1 Write: %08x%08x & %08x%08x\n", machine().describe_context() + , (uint32_t)(data >> 32), (uint32_t)data, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + m_ust_msc.m_compare1 = data; + break; + case 0x0010/8: + LOGMASKED(LOG_WRITE_UST_MSC, "%s: MACE: UST_MSC: Compare2 Write: %08x%08x & %08x%08x\n", machine().describe_context() + , (uint32_t)(data >> 32), (uint32_t)data, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + m_ust_msc.m_compare2 = data; + break; + case 0x0018/8: + LOGMASKED(LOG_WRITE_UST_MSC, "%s: MACE: UST_MSC: Compare3 Write: %08x%08x & %08x%08x\n", machine().describe_context() + , (uint32_t)(data >> 32), (uint32_t)data, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + m_ust_msc.m_compare3 = data; + break; + default: + LOGMASKED(LOG_WRITE_UST_MSC, "%s: MACE: UST_MSC: Unknown Write: %08x = %08x%08x & %08x%08x\n", machine().describe_context() + , 0x1f340000 + offset*8, (uint32_t)(data >> 32), (uint32_t)data, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + return; + } +} diff --git a/src/mame/machine/mace.h b/src/mame/machine/mace.h new file mode 100644 index 00000000000..9c18042d562 --- /dev/null +++ b/src/mame/machine/mace.h @@ -0,0 +1,118 @@ +// license:BSD-3-Clause +// copyright-holders:Ryan Holtz +/********************************************************************** + + SGI MACE skeleton device + +**********************************************************************/ + +#ifndef MAME_MACHINE_MACE_H +#define MAME_MACHINE_MACE_H + +#pragma once + +#include "cpu/mips/mips3.h" + +class mace_device : public device_t +{ +public: + template + mace_device(const machine_config &mconfig, const char *tag, device_t *owner, T &&cpu_tag) + : mace_device(mconfig, tag, owner, (uint32_t)0) + { + m_maincpu.set_tag(std::forward(cpu_tag)); + } + + mace_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + + void map(address_map &map); + +protected: + virtual void device_start() override; + virtual void device_reset() override; + virtual void device_add_mconfig(machine_config &config) override; + virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override; + + static const device_timer_id TIMER_MSC = 0; + static const device_timer_id TIMER_UST = 1; + + // UST/MSC Timer + void check_ust_msc_compare(); + + // Read/Write Handlers + DECLARE_READ64_MEMBER(pci_r); + DECLARE_WRITE64_MEMBER(pci_w); + DECLARE_READ64_MEMBER(vin1_r); + DECLARE_WRITE64_MEMBER(vin1_w); + DECLARE_READ64_MEMBER(vin2_r); + DECLARE_WRITE64_MEMBER(vin2_w); + DECLARE_READ64_MEMBER(vout_r); + DECLARE_WRITE64_MEMBER(vout_w); + DECLARE_READ64_MEMBER(enet_r); + DECLARE_WRITE64_MEMBER(enet_w); + DECLARE_READ64_MEMBER(audio_r); + DECLARE_WRITE64_MEMBER(audio_w); + DECLARE_READ64_MEMBER(isa_r); + DECLARE_WRITE64_MEMBER(isa_w); + DECLARE_READ64_MEMBER(kbdms_r); + DECLARE_WRITE64_MEMBER(kbdms_w); + DECLARE_READ64_MEMBER(i2c_r); + DECLARE_WRITE64_MEMBER(i2c_w); + DECLARE_READ64_MEMBER(ust_msc_r); + DECLARE_WRITE64_MEMBER(ust_msc_w); + DECLARE_READ64_MEMBER(isa_ext_r); + DECLARE_WRITE64_MEMBER(isa_ext_w); + DECLARE_READ64_MEMBER(rtc_r); + DECLARE_WRITE64_MEMBER(rtc_w); + + required_device m_maincpu; + + enum + { + ISA_INT_COMPARE1 = 0x2000, + ISA_INT_COMPARE2 = 0x4000, + ISA_INT_COMPARE3 = 0x8000, + }; + + struct isa_t + { + uint32_t m_ringbase_reset; + uint32_t m_flash_nic_ctrl; + uint32_t m_int_status; + uint32_t m_int_mask; + }; + + struct ust_msc_t + { + uint32_t m_msc; + uint32_t m_ust; + uint64_t m_ust_msc; + uint64_t m_compare1; + uint64_t m_compare2; + uint64_t m_compare3; + uint64_t m_ain_msc_ust; + uint64_t m_aout1_msc_ust; + uint64_t m_aout2_msc_ust; + uint64_t m_vin1_msc_ust; + uint64_t m_vin2_msc_ust; + uint64_t m_vout_msc_ust; + }; + + // DS17287 RTC; proper hookup is unknown + struct rtc_t + { + uint64_t m_unknown; + }; + + isa_t m_isa; + + ust_msc_t m_ust_msc; + emu_timer *m_timer_ust; + emu_timer *m_timer_msc; + + rtc_t m_rtc; +}; + +DECLARE_DEVICE_TYPE(SGI_MACE, mace_device) + +#endif // MAME_MACHINE_MACE_H diff --git a/src/mame/machine/sgi.cpp b/src/mame/machine/sgi.cpp index 2375c7979cb..942f734cbfe 100644 --- a/src/mame/machine/sgi.cpp +++ b/src/mame/machine/sgi.cpp @@ -22,7 +22,7 @@ #define LOG_EEPROM (1 << 7) #define LOG_DEFAULT (LOG_READS | LOG_WRITES | LOG_RPSS | LOG_WATCHDOG | LOG_UNKNOWN) -#define VERBOSE (LOG_UNKNOWN) +#define VERBOSE (0) #include "logmacro.h" DEFINE_DEVICE_TYPE(SGI_MC, sgi_mc_device, "sgi_mc", "SGI Memory Controller") diff --git a/src/mame/machine/sgi.h b/src/mame/machine/sgi.h index 634c286ba2d..45937d6c649 100644 --- a/src/mame/machine/sgi.h +++ b/src/mame/machine/sgi.h @@ -32,6 +32,7 @@ public: DECLARE_WRITE32_MEMBER(write); void set_cpu_buserr(uint32_t address); + uint32_t get_mem_config(int channel) const { return m_mem_config[channel]; } protected: // device-level overrides diff --git a/src/mame/video/crime.cpp b/src/mame/video/crime.cpp new file mode 100644 index 00000000000..05c76f7da73 --- /dev/null +++ b/src/mame/video/crime.cpp @@ -0,0 +1,112 @@ +// license:BSD-3-Clause +// copyright-holders:Ryan Holtz +/********************************************************************** + + SGI CRIME skeleton device + +**********************************************************************/ + +#include "emu.h" +#include "video/crime.h" + +#define LOG_UNKNOWN (1 << 0U) +#define LOG_READS (1 << 1U) +#define LOG_WRITES (1 << 2U) +#define LOG_ALL (LOG_UNKNOWN | LOG_READS | LOG_WRITES) + +#define VERBOSE (LOG_ALL) +#include "logmacro.h" + +DEFINE_DEVICE_TYPE(SGI_CRIME, crime_device, "sgicrime", "SGI CRIME") + +crime_device::crime_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) + : device_t(mconfig, SGI_CRIME, tag, owner, clock) + , m_maincpu(*this, finder_base::DUMMY_TAG) +{ +} + +void crime_device::device_start() +{ + save_item(NAME(m_mem_bank_ctrl)); +} + +void crime_device::device_reset() +{ + memset(m_mem_bank_ctrl, 0, sizeof(uint64_t) * 8); +} + +//************************************************************************** +// DEVICE HARDWARE +//************************************************************************** + +void crime_device::device_add_mconfig(machine_config &config) +{ +} + +void crime_device::map(address_map &map) +{ + map(0x00000000, 0x000003ff).rw(FUNC(crime_device::base_r), FUNC(crime_device::base_w)); +} + +//************************************************************************** +// REGISTER ACCESS +//************************************************************************** + +READ64_MEMBER(crime_device::base_r) +{ + uint64_t ret = 0ULL; + switch (offset) + { + case 0x000000/8: + ret = 1ULL; + LOGMASKED(LOG_READS, "%s: CRIME: ID Read: %08x%08x & %08x%08x\n", machine().describe_context() + , (uint32_t)(ret >> 32), (uint32_t)ret, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + break; + case 0x000208/8: + case 0x000210/8: + case 0x000218/8: + case 0x000220/8: + case 0x000228/8: + case 0x000230/8: + case 0x000238/8: + case 0x000240/8: + { + const uint32_t index = offset - 0x000208/8; + ret = m_mem_bank_ctrl[index]; + LOGMASKED(LOG_READS, "%s: CRIME: Memory Bank %d Control Read: %08x%08x & %08x%08x\n", machine().describe_context(), index + , (uint32_t)(ret >> 32), (uint32_t)ret, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + break; + } + default: + LOGMASKED(LOG_UNKNOWN | LOG_READS, "%s: CRIME: Unknown Read: [%08x] & %08x%08x\n", machine().describe_context() + , 0x14000000 + offset*8, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + break; + } + return ret; +} + +WRITE64_MEMBER(crime_device::base_w) +{ + switch (offset) + { + case 0x000208/8: + case 0x000210/8: + case 0x000218/8: + case 0x000220/8: + case 0x000228/8: + case 0x000230/8: + case 0x000238/8: + case 0x000240/8: + { + const uint32_t index = offset - 0x000208/8; + LOGMASKED(LOG_WRITES, "%s: CRIME: Memory Bank %d Control Write: %08x%08x & %08x%08x\n", machine().describe_context(), index + , (uint32_t)(data >> 32), (uint32_t)data, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + m_mem_bank_ctrl[index] = data; + break; + } + default: + LOGMASKED(LOG_UNKNOWN | LOG_WRITES, "%s: CRIME: Unknown Write: %08x = %08x%08x & %08x%08x\n", machine().describe_context(), 0x14000000 + offset*8 + , (uint32_t)(data >> 32), (uint32_t)data, (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + return; + } +} diff --git a/src/mame/video/crime.h b/src/mame/video/crime.h new file mode 100644 index 00000000000..9b90473c503 --- /dev/null +++ b/src/mame/video/crime.h @@ -0,0 +1,45 @@ +// license:BSD-3-Clause +// copyright-holders:Ryan Holtz +/********************************************************************** + + SGI CRIME skeleton device + +**********************************************************************/ + +#ifndef MAME_VIDEO_CRIME_H +#define MAME_VIDEO_CRIME_H + +#pragma once + +#include "cpu/mips/mips3.h" + +class crime_device : public device_t +{ +public: + template + crime_device(const machine_config &mconfig, const char *tag, device_t *owner, T &&cpu_tag) + : crime_device(mconfig, tag, owner, (uint32_t)0) + { + m_maincpu.set_tag(std::forward(cpu_tag)); + } + + crime_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + + void map(address_map &map); + +protected: + virtual void device_start() override; + virtual void device_reset() override; + virtual void device_add_mconfig(machine_config &config) override; + + DECLARE_READ64_MEMBER(base_r); + DECLARE_WRITE64_MEMBER(base_w); + + required_device m_maincpu; + + uint64_t m_mem_bank_ctrl[8]; +}; + +DECLARE_DEVICE_TYPE(SGI_CRIME, crime_device) + +#endif // MAME_VIDEO_CRIME_H diff --git a/src/mame/video/newport.cpp b/src/mame/video/newport.cpp index 3b12ccd003d..ca3013ac298 100644 --- a/src/mame/video/newport.cpp +++ b/src/mame/video/newport.cpp @@ -48,7 +48,7 @@ DEFINE_DEVICE_TYPE(NEWPORT_VIDEO, newport_video_device, "newport_video", "SGI Ne newport_video_device::newport_video_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : device_t(mconfig, NEWPORT_VIDEO, tag, owner, clock) , m_maincpu(*this, finder_base::DUMMY_TAG) - , m_ioc2(*this, finder_base::DUMMY_TAG) + , m_hpc3(*this, finder_base::DUMMY_TAG) { } @@ -715,7 +715,7 @@ WRITE_LINE_MEMBER(newport_video_device::vblank_w) { m_rex3.m_status |= 0x20; if (BIT(m_vc2.m_display_ctrl, 0)) - m_ioc2->raise_local1_irq(ioc2_device::INT3_LOCAL1_RETRACE); + m_hpc3->raise_local_irq(1, ioc2_device::INT3_LOCAL1_RETRACE); } } @@ -938,7 +938,7 @@ READ32_MEMBER(newport_video_device::rex3_r) LOGMASKED(LOG_REX3, "REX3 Status Read: %08x\n", m_rex3.m_status); uint32_t old_status = m_rex3.m_status; m_rex3.m_status = 0; - m_ioc2->lower_local1_irq(ioc2_device::INT3_LOCAL1_RETRACE); + m_hpc3->lower_local_irq(1, ioc2_device::INT3_LOCAL1_RETRACE); return old_status; } case 0x133c/4: diff --git a/src/mame/video/newport.h b/src/mame/video/newport.h index 1c362b80974..a5a3b4a0918 100644 --- a/src/mame/video/newport.h +++ b/src/mame/video/newport.h @@ -10,17 +10,17 @@ #pragma once #include "cpu/mips/mips3.h" -#include "machine/ioc2.h" +#include "machine/hpc3.h" class newport_video_device : public device_t { public: template - newport_video_device(const machine_config &mconfig, const char *tag, device_t *owner, T &&cpu_tag, U &&ioc2_tag) + newport_video_device(const machine_config &mconfig, const char *tag, device_t *owner, T &&cpu_tag, U &&hpc3_tag) : newport_video_device(mconfig, tag, owner, (uint32_t)0) // TODO: Use actual pixel clock { m_maincpu.set_tag(std::forward(cpu_tag)); - m_ioc2.set_tag(std::forward(ioc2_tag)); + m_hpc3.set_tag(std::forward(hpc3_tag)); } newport_video_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); @@ -184,7 +184,7 @@ private: void do_rex3_command(); required_device m_maincpu; - required_device m_ioc2; + required_device m_hpc3; vc2_t m_vc2; xmap_t m_xmap0; xmap_t m_xmap1;