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Clean-ups and version bump

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This commit is contained in:
Angelo Salese 2012-01-15 21:40:54 +00:00
parent 71bb1c0818
commit 7b631e4c5b
54 changed files with 476 additions and 476 deletions
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14
src/emu/cpu/arm7/arm7ops.c
View File

@ -1840,7 +1840,7 @@ const void arm7ops_0123(arm_state *cpustate, UINT32 insn)
HandleALU(cpustate, insn); HandleALU(cpustate, insn);
} }
} }
// break; // break;
} }
const void arm7ops_4567(arm_state *cpustate, UINT32 insn) /* Data Transfer - Single Data Access */ const void arm7ops_4567(arm_state *cpustate, UINT32 insn) /* Data Transfer - Single Data Access */
@ -1851,7 +1851,7 @@ const void arm7ops_4567(arm_state *cpustate, UINT32 insn) /* Data Transfer - Sin
//case 7: //case 7:
HandleMemSingle(cpustate, insn); HandleMemSingle(cpustate, insn);
R15 += 4; R15 += 4;
// break; // break;
} }
const void arm7ops_89(arm_state *cpustate, UINT32 insn) /* Block Data Transfer/Access */ const void arm7ops_89(arm_state *cpustate, UINT32 insn) /* Block Data Transfer/Access */
@ -1860,7 +1860,7 @@ const void arm7ops_89(arm_state *cpustate, UINT32 insn) /* Block Data Transfer/A
//case 9: //case 9:
HandleMemBlock(cpustate, insn); HandleMemBlock(cpustate, insn);
R15 += 4; R15 += 4;
// break; // break;
} }
const void arm7ops_ab(arm_state *cpustate, UINT32 insn) /* Branch or Branch & Link */ const void arm7ops_ab(arm_state *cpustate, UINT32 insn) /* Branch or Branch & Link */
@ -1868,7 +1868,7 @@ const void arm7ops_ab(arm_state *cpustate, UINT32 insn) /* Branch or Branch & Li
//case 0xa: //case 0xa:
//case 0xb: //case 0xb:
HandleBranch(cpustate, insn); HandleBranch(cpustate, insn);
// break; // break;
} }
const void arm7ops_cd(arm_state *cpustate, UINT32 insn) /* Co-Processor Data Transfer */ const void arm7ops_cd(arm_state *cpustate, UINT32 insn) /* Co-Processor Data Transfer */
@ -1877,7 +1877,7 @@ const void arm7ops_cd(arm_state *cpustate, UINT32 insn) /* Co-Processor Data Tra
//case 0xd: //case 0xd:
HandleCoProcDT(cpustate, insn); HandleCoProcDT(cpustate, insn);
R15 += 4; R15 += 4;
// break; // break;
} }
const void arm7ops_e(arm_state *cpustate, UINT32 insn) /* Co-Processor Data Operation or Register Transfer */ const void arm7ops_e(arm_state *cpustate, UINT32 insn) /* Co-Processor Data Operation or Register Transfer */
@ -1888,7 +1888,7 @@ const void arm7ops_e(arm_state *cpustate, UINT32 insn) /* Co-Processor Data Oper
else else
HandleCoProcDO(cpustate, insn); HandleCoProcDO(cpustate, insn);
R15 += 4; R15 += 4;
// break; // break;
} }
const void arm7ops_f(arm_state *cpustate, UINT32 insn) /* Software Interrupt */ const void arm7ops_f(arm_state *cpustate, UINT32 insn) /* Software Interrupt */
@ -1896,5 +1896,5 @@ const void arm7ops_f(arm_state *cpustate, UINT32 insn) /* Software Interrupt */
cpustate->pendingSwi = 1; cpustate->pendingSwi = 1;
ARM7_CHECKIRQ; ARM7_CHECKIRQ;
//couldn't find any cycle counts for SWI //couldn't find any cycle counts for SWI
// break; // break;
} }

62
src/emu/cpu/arm7/arm7thmb.c
View File

@ -587,9 +587,9 @@ const void tg04_00_0f(arm_state *cpustate, UINT32 pc, UINT32 insn) /* MVN Rd, Rs
const void tg04_01_00(arm_state *cpustate, UINT32 pc, UINT32 insn) const void tg04_01_00(arm_state *cpustate, UINT32 pc, UINT32 insn)
{ {
// UINT32 rs, rd; // UINT32 rs, rd;
// rs = (insn & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT; // rs = (insn & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
// rd = insn & THUMB_HIREG_RD; // rd = insn & THUMB_HIREG_RD;
fatalerror("%08x: G4-1-0 Undefined Thumb instruction: %04x %x\n", pc, insn, (insn & THUMB_HIREG_H) >> THUMB_HIREG_H_SHIFT); fatalerror("%08x: G4-1-0 Undefined Thumb instruction: %04x %x\n", pc, insn, (insn & THUMB_HIREG_H) >> THUMB_HIREG_H_SHIFT);
@ -826,8 +826,8 @@ const void tg04_01_31(arm_state *cpustate, UINT32 pc, UINT32 insn)
const void tg04_01_32(arm_state *cpustate, UINT32 pc, UINT32 insn) const void tg04_01_32(arm_state *cpustate, UINT32 pc, UINT32 insn)
{ {
// UINT32 addr; // UINT32 addr;
// UINT32 rd; // UINT32 rd;
fatalerror("%08x: G4-3 Undefined Thumb instruction: %04x\n", pc, insn); fatalerror("%08x: G4-3 Undefined Thumb instruction: %04x\n", pc, insn);
@ -837,8 +837,8 @@ const void tg04_01_32(arm_state *cpustate, UINT32 pc, UINT32 insn)
const void tg04_01_33(arm_state *cpustate, UINT32 pc, UINT32 insn) const void tg04_01_33(arm_state *cpustate, UINT32 pc, UINT32 insn)
{ {
// UINT32 addr; // UINT32 addr;
// UINT32 rd; // UINT32 rd;
fatalerror("%08x: G4-3 Undefined Thumb instruction: %04x\n", pc, insn); fatalerror("%08x: G4-3 Undefined Thumb instruction: %04x\n", pc, insn);
@ -1129,8 +1129,8 @@ const void tg0b_0(arm_state *cpustate, UINT32 pc, UINT32 insn) /* ADD SP, #imm *
const void tg0b_1(arm_state *cpustate, UINT32 pc, UINT32 insn) const void tg0b_1(arm_state *cpustate, UINT32 pc, UINT32 insn)
{ {
// UINT32 addr; // UINT32 addr;
// INT32 offs; // INT32 offs;
fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, insn); fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, insn);
R15 += 2; R15 += 2;
@ -1139,8 +1139,8 @@ const void tg0b_1(arm_state *cpustate, UINT32 pc, UINT32 insn)
const void tg0b_2(arm_state *cpustate, UINT32 pc, UINT32 insn) const void tg0b_2(arm_state *cpustate, UINT32 pc, UINT32 insn)
{ {
// UINT32 addr; // UINT32 addr;
// INT32 offs; // INT32 offs;
fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, insn); fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, insn);
R15 += 2; R15 += 2;
@ -1149,8 +1149,8 @@ const void tg0b_2(arm_state *cpustate, UINT32 pc, UINT32 insn)
const void tg0b_3(arm_state *cpustate, UINT32 pc, UINT32 insn) const void tg0b_3(arm_state *cpustate, UINT32 pc, UINT32 insn)
{ {
// UINT32 addr; // UINT32 addr;
// INT32 offs; // INT32 offs;
fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, insn); fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, insn);
R15 += 2; R15 += 2;
@ -1193,8 +1193,8 @@ const void tg0b_5(arm_state *cpustate, UINT32 pc, UINT32 insn) /* PUSH {Rlist}{L
const void tg0b_6(arm_state *cpustate, UINT32 pc, UINT32 insn) const void tg0b_6(arm_state *cpustate, UINT32 pc, UINT32 insn)
{ {
// UINT32 addr; // UINT32 addr;
// INT32 offs; // INT32 offs;
fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, insn); fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, insn);
R15 += 2; R15 += 2;
@ -1203,8 +1203,8 @@ const void tg0b_6(arm_state *cpustate, UINT32 pc, UINT32 insn)
const void tg0b_7(arm_state *cpustate, UINT32 pc, UINT32 insn) const void tg0b_7(arm_state *cpustate, UINT32 pc, UINT32 insn)
{ {
// UINT32 addr; // UINT32 addr;
// INT32 offs; // INT32 offs;
fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, insn); fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, insn);
R15 += 2; R15 += 2;
@ -1213,8 +1213,8 @@ const void tg0b_7(arm_state *cpustate, UINT32 pc, UINT32 insn)
const void tg0b_8(arm_state *cpustate, UINT32 pc, UINT32 insn) const void tg0b_8(arm_state *cpustate, UINT32 pc, UINT32 insn)
{ {
// UINT32 addr; // UINT32 addr;
// INT32 offs; // INT32 offs;
fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, insn); fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, insn);
R15 += 2; R15 += 2;
@ -1223,8 +1223,8 @@ const void tg0b_8(arm_state *cpustate, UINT32 pc, UINT32 insn)
const void tg0b_9(arm_state *cpustate, UINT32 pc, UINT32 insn) const void tg0b_9(arm_state *cpustate, UINT32 pc, UINT32 insn)
{ {
// UINT32 addr; // UINT32 addr;
// INT32 offs; // INT32 offs;
fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, insn); fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, insn);
R15 += 2; R15 += 2;
@ -1233,8 +1233,8 @@ const void tg0b_9(arm_state *cpustate, UINT32 pc, UINT32 insn)
const void tg0b_a(arm_state *cpustate, UINT32 pc, UINT32 insn) const void tg0b_a(arm_state *cpustate, UINT32 pc, UINT32 insn)
{ {
// UINT32 addr; // UINT32 addr;
// INT32 offs; // INT32 offs;
fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, insn); fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, insn);
R15 += 2; R15 += 2;
@ -1243,8 +1243,8 @@ const void tg0b_a(arm_state *cpustate, UINT32 pc, UINT32 insn)
const void tg0b_b(arm_state *cpustate, UINT32 pc, UINT32 insn) const void tg0b_b(arm_state *cpustate, UINT32 pc, UINT32 insn)
{ {
// UINT32 addr; // UINT32 addr;
// INT32 offs; // INT32 offs;
fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, insn); fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, insn);
R15 += 2; R15 += 2;
@ -1286,8 +1286,8 @@ const void tg0b_d(arm_state *cpustate, UINT32 pc, UINT32 insn) /* POP {Rlist}{PC
const void tg0b_e(arm_state *cpustate, UINT32 pc, UINT32 insn) const void tg0b_e(arm_state *cpustate, UINT32 pc, UINT32 insn)
{ {
// UINT32 addr; // UINT32 addr;
// INT32 offs; // INT32 offs;
fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, insn); fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, insn);
R15 += 2; R15 += 2;
@ -1296,8 +1296,8 @@ const void tg0b_e(arm_state *cpustate, UINT32 pc, UINT32 insn)
const void tg0b_f(arm_state *cpustate, UINT32 pc, UINT32 insn) const void tg0b_f(arm_state *cpustate, UINT32 pc, UINT32 insn)
{ {
// UINT32 addr; // UINT32 addr;
// INT32 offs; // INT32 offs;
fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, insn); fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, insn);
R15 += 2; R15 += 2;
@ -1610,7 +1610,7 @@ const void tg0d_d(arm_state *cpustate, UINT32 pc, UINT32 insn) // COND_LE:
const void tg0d_e(arm_state *cpustate, UINT32 pc, UINT32 insn) // COND_AL: const void tg0d_e(arm_state *cpustate, UINT32 pc, UINT32 insn) // COND_AL:
{ {
// INT32 offs; // INT32 offs;
// offs = (INT8)(insn & THUMB_INSN_IMM); // offs = (INT8)(insn & THUMB_INSN_IMM);
//case //case
@ -1621,7 +1621,7 @@ const void tg0d_e(arm_state *cpustate, UINT32 pc, UINT32 insn) // COND_AL:
const void tg0d_f(arm_state *cpustate, UINT32 pc, UINT32 insn) // COND_NV: // SWI (this is sort of a "hole" in the opcode encoding) const void tg0d_f(arm_state *cpustate, UINT32 pc, UINT32 insn) // COND_NV: // SWI (this is sort of a "hole" in the opcode encoding)
{ {
// INT32 offs; // INT32 offs;
// offs = (INT8)(insn & THUMB_INSN_IMM); // offs = (INT8)(insn & THUMB_INSN_IMM);

224
src/emu/cpu/i386/i386.c
View File

@ -2260,7 +2260,7 @@ static void i386_protected_mode_iret(i386_state* cpustate, int operand32)
{ {
if(newflags & 0x00020000) // if returning to virtual 8086 mode if(newflags & 0x00020000) // if returning to virtual 8086 mode
{ {
// UINT8 SSRPL,SSDPL; // UINT8 SSRPL,SSDPL;
memset(&desc, 0, sizeof(desc)); memset(&desc, 0, sizeof(desc));
desc.selector = newCS; desc.selector = newCS;
i386_load_protected_mode_segment(cpustate,&desc); i386_load_protected_mode_segment(cpustate,&desc);
@ -2275,118 +2275,118 @@ static void i386_protected_mode_iret(i386_state* cpustate, int operand32)
/* Return to v86 mode */ /* Return to v86 mode */
logerror("IRET (%08x): Returning to Virtual 8086 mode.\n",cpustate->pc); logerror("IRET (%08x): Returning to Virtual 8086 mode.\n",cpustate->pc);
// Should these be done at this point? The 386 programmers' reference is a bit confusing about this // Should these be done at this point? The 386 programmers' reference is a bit confusing about this
/* if(RPL != 3) /* if(RPL != 3)
{ {
logerror("IRET to V86 (%08x): Return CS RPL is not 3\n",cpustate->pc); logerror("IRET to V86 (%08x): Return CS RPL is not 3\n",cpustate->pc);
FAULT(FAULT_GP,newCS); FAULT(FAULT_GP,newCS);
} }
if(operand32 == 0) if(operand32 == 0)
{ {
if(REG16(SP)+36 > cpustate->sreg[SS].limit) if(REG16(SP)+36 > cpustate->sreg[SS].limit)
{ {
logerror("IRET to V86 (%08x): Stack does not have enough room left\n",cpustate->pc); logerror("IRET to V86 (%08x): Stack does not have enough room left\n",cpustate->pc);
FAULT(FAULT_SS,0); FAULT(FAULT_SS,0);
} }
} }
else else
{ {
if(REG32(ESP)+36 > cpustate->sreg[SS].limit) if(REG32(ESP)+36 > cpustate->sreg[SS].limit)
{ {
logerror("IRET to V86 (%08x): Stack does not have enough space left\n",cpustate->pc); logerror("IRET to V86 (%08x): Stack does not have enough space left\n",cpustate->pc);
FAULT(FAULT_SS,0); FAULT(FAULT_SS,0);
} }
} }
// code segment checks // code segment checks
if((newCS & ~0x07) == 0) if((newCS & ~0x07) == 0)
{ {
logerror("IRET to V86 (%08x): Return CS selector is null\n",cpustate->pc); logerror("IRET to V86 (%08x): Return CS selector is null\n",cpustate->pc);
FAULT(FAULT_GP,newCS); FAULT(FAULT_GP,newCS);
} }
if(desc.flags & 0x04) if(desc.flags & 0x04)
{ // LDT { // LDT
if(newCS > cpustate->ldtr.limit) if(newCS > cpustate->ldtr.limit)
{ {
logerror("IRET to V86 (%08x): Return CS selector is past LDT limit\n",cpustate->pc); logerror("IRET to V86 (%08x): Return CS selector is past LDT limit\n",cpustate->pc);
FAULT(FAULT_GP,newCS); FAULT(FAULT_GP,newCS);
} }
} }
else else
{ // GDT { // GDT
if(newCS > cpustate->gdtr.limit) if(newCS > cpustate->gdtr.limit)
{ {
logerror("IRET to V86 (%08x): Return CS selector is past GDT limit\n",cpustate->pc); logerror("IRET to V86 (%08x): Return CS selector is past GDT limit\n",cpustate->pc);
FAULT(FAULT_GP,newCS); FAULT(FAULT_GP,newCS);
} }
} }
if((desc.flags & 0x18) != 0x18) if((desc.flags & 0x18) != 0x18)
{ {
logerror("IRET to V86 (%08x): Return CS segment is not a code segment\n",cpustate->pc); logerror("IRET to V86 (%08x): Return CS segment is not a code segment\n",cpustate->pc);
FAULT(FAULT_GP,newCS); FAULT(FAULT_GP,newCS);
} }
if(DPL != 3) if(DPL != 3)
{ {
logerror("IRET to V86 (%08x): Return CS segment does not have a DPL of 3\n",cpustate->pc); logerror("IRET to V86 (%08x): Return CS segment does not have a DPL of 3\n",cpustate->pc);
FAULT(FAULT_GP,newCS); FAULT(FAULT_GP,newCS);
} }
if(!(desc.flags & 0x0080)) if(!(desc.flags & 0x0080))
{ {
logerror("IRET to V86 (%08x): Return CS segment is not present\n",cpustate->pc); logerror("IRET to V86 (%08x): Return CS segment is not present\n",cpustate->pc);
FAULT(FAULT_NP,newCS); FAULT(FAULT_NP,newCS);
} }
// Stack segment checks // Stack segment checks
if((newSS & ~0x07) == 0) if((newSS & ~0x07) == 0)
{ {
logerror("IRET to V86 (%08x): Return SS segment is null\n",cpustate->pc); logerror("IRET to V86 (%08x): Return SS segment is null\n",cpustate->pc);
FAULT(FAULT_GP,newSS); FAULT(FAULT_GP,newSS);
} }
if(desc.flags & 0x04) if(desc.flags & 0x04)
{ // LDT { // LDT
if(newSS > cpustate->ldtr.limit) if(newSS > cpustate->ldtr.limit)
{ {
logerror("IRET to V86 (%08x): Return SS selector is past LDT limit\n",cpustate->pc); logerror("IRET to V86 (%08x): Return SS selector is past LDT limit\n",cpustate->pc);
FAULT(FAULT_GP,newSS); FAULT(FAULT_GP,newSS);
} }
} }
else else
{ // GDT { // GDT
if(newSS > cpustate->gdtr.limit) if(newSS > cpustate->gdtr.limit)
{ {
logerror("IRET to V86 (%08x): Return SS selector is past GDT limit\n",cpustate->pc); logerror("IRET to V86 (%08x): Return SS selector is past GDT limit\n",cpustate->pc);
FAULT(FAULT_GP,newSS); FAULT(FAULT_GP,newSS);
} }
} }
if(SSRPL != RPL) if(SSRPL != RPL)
{ {
logerror("IRET to V86 (%08x): Return SS selector RPL is not equal to CS selector RPL\n",cpustate->pc); logerror("IRET to V86 (%08x): Return SS selector RPL is not equal to CS selector RPL\n",cpustate->pc);
FAULT(FAULT_GP,newSS); FAULT(FAULT_GP,newSS);
} }
if(((stack.flags & 0x0018) != 0x10) && (!(stack.flags & 0x02))) if(((stack.flags & 0x0018) != 0x10) && (!(stack.flags & 0x02)))
{ {
logerror("IRET to V86 (%08x): Return SS segment is not a writable data segment\n",cpustate->pc); logerror("IRET to V86 (%08x): Return SS segment is not a writable data segment\n",cpustate->pc);
FAULT(FAULT_GP,newSS); FAULT(FAULT_GP,newSS);
} }
if(SSDPL != RPL) if(SSDPL != RPL)
{ {
logerror("IRET to V86 (%08x): Return SS segment DPL is not equal to CS selector RPL\n",cpustate->pc); logerror("IRET to V86 (%08x): Return SS segment DPL is not equal to CS selector RPL\n",cpustate->pc);
FAULT(FAULT_GP,newSS); FAULT(FAULT_GP,newSS);
} }
if(!(stack.flags & 0x0080)) if(!(stack.flags & 0x0080))
{ {
logerror("IRET to V86 (%08x): Return SS segment is not present\n",cpustate->pc); logerror("IRET to V86 (%08x): Return SS segment is not present\n",cpustate->pc);
FAULT(FAULT_NP,newSS); FAULT(FAULT_NP,newSS);
} }
if(newEIP > desc.limit) if(newEIP > desc.limit)
{ {
logerror("IRET to V86 (%08x): New EIP is past CS segment limit\n",cpustate->pc); logerror("IRET to V86 (%08x): New EIP is past CS segment limit\n",cpustate->pc);
FAULT(FAULT_GP,0); FAULT(FAULT_GP,0);
} }
*/ */
set_flags(cpustate,newflags); set_flags(cpustate,newflags);
cpustate->eip = POP32(cpustate) & 0xffff; // high 16 bits are ignored cpustate->eip = POP32(cpustate) & 0xffff; // high 16 bits are ignored
cpustate->sreg[CS].selector = POP32(cpustate) & 0xffff; cpustate->sreg[CS].selector = POP32(cpustate) & 0xffff;
POP32(cpustate); // already set flags POP32(cpustate); // already set flags
// if(RPL > CPL) // if(RPL > CPL)
{ {
newESP = POP32(cpustate); newESP = POP32(cpustate);
newSS = POP32(cpustate) & 0xffff; newSS = POP32(cpustate) & 0xffff;
@ -2649,10 +2649,10 @@ static void i386_protected_mode_iret(i386_state* cpustate, int operand32)
FAULT(FAULT_GP,0) FAULT(FAULT_GP,0)
} }
// if(operand32 == 0) // if(operand32 == 0)
// REG16(SP) += 10; // REG16(SP) += 10;
// else // else
// REG32(ESP) += 20; // REG32(ESP) += 20;
if(operand32 == 0) if(operand32 == 0)
{ {

2
src/emu/imagedev/cartslot.h
View File

@ -40,7 +40,7 @@ public:
virtual bool call_load(); virtual bool call_load();
virtual void call_unload(); virtual void call_unload();
virtual void call_display_info() { if (m_device_displayinfo) m_device_displayinfo(*this); } virtual void call_display_info() { if (m_device_displayinfo) m_device_displayinfo(*this); }
virtual bool call_softlist_load(char *swlist, char *swname, rom_entry *start_entry) { load_software_part_region( this, swlist, swname, start_entry ); return TRUE; } virtual bool call_softlist_load(char *swlist, char *swname, rom_entry *start_entry) { load_software_part_region( this, swlist, swname, start_entry ); return TRUE; }
virtual device_image_partialhash_func get_partial_hash() const { return m_device_partialhash; } virtual device_image_partialhash_func get_partial_hash() const { return m_device_partialhash; }
virtual iodevice_t image_type() const { return IO_CARTSLOT; } virtual iodevice_t image_type() const { return IO_CARTSLOT; }

4
src/emu/machine/laserdsc.c
View File

@ -292,7 +292,7 @@ void laserdisc_device::static_set_overlay(device_t &device, UINT32 width, UINT32
//------------------------------------------------- //-------------------------------------------------
// static_set_overlay - set the overlay visible // static_set_overlay - set the overlay visible
// subregion // subregion
//------------------------------------------------- //-------------------------------------------------
void laserdisc_device::static_set_overlay_clip(device_t &device, INT32 minx, INT32 maxx, INT32 miny, INT32 maxy) void laserdisc_device::static_set_overlay_clip(device_t &device, INT32 minx, INT32 maxx, INT32 miny, INT32 maxy)
@ -316,7 +316,7 @@ void laserdisc_device::static_set_overlay_position(device_t &device, float posx,
//------------------------------------------------- //-------------------------------------------------
// static_set_overlay_scale - set the overlay // static_set_overlay_scale - set the overlay
// scale parameters // scale parameters
//------------------------------------------------- //-------------------------------------------------
void laserdisc_device::static_set_overlay_scale(device_t &device, float scalex, float scaley) void laserdisc_device::static_set_overlay_scale(device_t &device, float scalex, float scaley)

2
src/emu/machine/laserdsc.h
View File

@ -165,7 +165,7 @@ struct laserdisc_overlay_config
// ======================> laserdisc_device // ======================> laserdisc_device
// base laserdisc class // base laserdisc class
class laserdisc_device : public device_t, class laserdisc_device : public device_t,
public device_sound_interface, public device_sound_interface,
public laserdisc_overlay_config public laserdisc_overlay_config
{ {

2
src/emu/machine/ldpr8210.c
View File

@ -639,7 +639,7 @@ READ8_MEMBER( pioneer_pr8210_device::i8049_bus_r )
$04 = (in) SIZE 8/12 $04 = (in) SIZE 8/12
$02 = (in) FG via op-amp (spindle motor stop detector) $02 = (in) FG via op-amp (spindle motor stop detector)
$01 = (in) SLOW TIMER OUT $01 = (in) SLOW TIMER OUT
*/ */
UINT8 result = 0x00; UINT8 result = 0x00;

6
src/emu/screen.h
View File

@ -406,9 +406,9 @@ extern const device_type SCREEN;
//------------------------------------------------- //-------------------------------------------------
// screen_update_delegate_smart - collection of // screen_update_delegate_smart - collection of
// inline helpers which create the appropriate // inline helpers which create the appropriate
// screen_update_delegate based on the input // screen_update_delegate based on the input
// function type // function type
//------------------------------------------------- //-------------------------------------------------
inline screen_update_ind16_delegate screen_update_delegate_smart(UINT32 (*callback)(device_t *, screen_device &, bitmap_ind16 &, const rectangle &), const char *name) inline screen_update_ind16_delegate screen_update_delegate_smart(UINT32 (*callback)(device_t *, screen_device &, bitmap_ind16 &, const rectangle &), const char *name)

2
src/emu/video/pc_vga.c
View File

@ -181,7 +181,7 @@ static VIDEO_RESET( vga );
void pc_video_start(running_machine &machine) void pc_video_start(running_machine &machine)
{ {
// pc_choosevideomode = choosevideomode; // pc_choosevideomode = choosevideomode;
pc_current_height = -1; pc_current_height = -1;
pc_current_width = -1; pc_current_width = -1;
} }

4
src/lib/formats/ap_dsk35.c
View File

@ -1397,8 +1397,8 @@ bool dc42_format::save(io_generic *io, floppy_image *image)
UINT8 tr = gcr6bw_tb[h[0]] | (v2 & 1 ? 0x40 : 0x00); UINT8 tr = gcr6bw_tb[h[0]] | (v2 & 1 ? 0x40 : 0x00);
UINT8 se = gcr6bw_tb[h[1]]; UINT8 se = gcr6bw_tb[h[1]];
UINT8 si = v2 & 0x20 ? 1 : 0; UINT8 si = v2 & 0x20 ? 1 : 0;
// UINT8 ds = v3 & 0x20 ? 1 : 0; // UINT8 ds = v3 & 0x20 ? 1 : 0;
// UINT8 fmt = v3 & 0x1f; // UINT8 fmt = v3 & 0x1f;
UINT8 c1 = (tr^se^v2^v3) & 0x3f; UINT8 c1 = (tr^se^v2^v3) & 0x3f;
UINT8 chk = gcr6bw_tb[h[4]]; UINT8 chk = gcr6bw_tb[h[4]];
if(chk == c1 && tr == track && si == head && se < nsect) { if(chk == c1 && tr == track && si == head && se < nsect) {

8
src/mame/drivers/dlair.c
View File

@ -968,15 +968,15 @@ ROM_END
static DRIVER_INIT( fixed ) static DRIVER_INIT( fixed )
{ {
// dlair_state *state = machine.driver_data<dlair_state>(); // dlair_state *state = machine.driver_data<dlair_state>();
// state->m_laserdisc_type = LASERDISC_TYPE_FIXED; // state->m_laserdisc_type = LASERDISC_TYPE_FIXED;
} }
static DRIVER_INIT( variable ) static DRIVER_INIT( variable )
{ {
// dlair_state *state = machine.driver_data<dlair_state>(); // dlair_state *state = machine.driver_data<dlair_state>();
// state->m_laserdisc_type = LASERDISC_TYPE_VARIABLE; // state->m_laserdisc_type = LASERDISC_TYPE_VARIABLE;
} }

2
src/mame/drivers/pgm.c
View File

@ -4432,7 +4432,7 @@ static DRIVER_INIT( kov )
static DRIVER_INIT( kovboot ) static DRIVER_INIT( kovboot )
{ {
pgm_basic_init(machine); pgm_basic_init(machine);
// pgm_kov_decrypt(machine); // pgm_kov_decrypt(machine);
kovsh_latch_init(machine); kovsh_latch_init(machine);
install_protection_asic_sim_kov(machine); install_protection_asic_sim_kov(machine);
} }

2
src/mame/drivers/pgm2.c
View File

@ -116,7 +116,7 @@ static MACHINE_CONFIG_START( pgm2, pgm2_state )
/* basic machine hardware */ /* basic machine hardware */
MCFG_CPU_ADD("maincpu", ARM7, 20000000) // ?? unknown CPU, has internal ROM. MCFG_CPU_ADD("maincpu", ARM7, 20000000) // ?? unknown CPU, has internal ROM.
MCFG_CPU_PROGRAM_MAP(pgm2_map) MCFG_CPU_PROGRAM_MAP(pgm2_map)
// MCFG_DEVICE_DISABLE() // MCFG_DEVICE_DISABLE()
MCFG_MACHINE_START( pgm2 ) MCFG_MACHINE_START( pgm2 )
MCFG_MACHINE_RESET( pgm2 ) MCFG_MACHINE_RESET( pgm2 )

2
src/mame/drivers/savquest.c
View File

@ -77,7 +77,7 @@ protected:
// driver_device overrides // driver_device overrides
// virtual void video_start(); // virtual void video_start();
}; };
// Intel 82439TX System Controller (MXTC) // Intel 82439TX System Controller (MXTC)

4
src/mame/drivers/thayers.c
View File

@ -760,8 +760,8 @@ static MACHINE_RESET( thayers )
state->m_cart_present = 0; state->m_cart_present = 0;
state->m_pr7820_enter = 0; state->m_pr7820_enter = 0;
// newtype = (input_port_read(machine, "DSWB") & 0x18) ? LASERDISC_TYPE_PIONEER_LDV1000 : LASERDISC_TYPE_PIONEER_PR7820; // newtype = (input_port_read(machine, "DSWB") & 0x18) ? LASERDISC_TYPE_PIONEER_LDV1000 : LASERDISC_TYPE_PIONEER_PR7820;
// laserdisc_set_type(state->m_laserdisc, newtype); // laserdisc_set_type(state->m_laserdisc, newtype);
} }
/* COP400 Interface */ /* COP400 Interface */

8
src/mame/machine/megadriv.c
View File

@ -9412,7 +9412,7 @@ SCREEN_VBLANK(megadriv)
megadrive_sprite_collision=0;//? when to reset this .. megadrive_sprite_collision=0;//? when to reset this ..
megadrive_imode = MEGADRIVE_REG0C_INTERLEAVE; // can't change mid-frame.. megadrive_imode = MEGADRIVE_REG0C_INTERLEAVE; // can't change mid-frame..
megadrive_imode_odd_frame^=1; megadrive_imode_odd_frame^=1;
// cputag_set_input_line(machine, "genesis_snd_z80", 0, CLEAR_LINE); // if the z80 interrupt hasn't happened by now, clear it.. // cputag_set_input_line(machine, "genesis_snd_z80", 0, CLEAR_LINE); // if the z80 interrupt hasn't happened by now, clear it..
if (input_port_read_safe(screen.machine(), "RESET", 0x00) & 0x01) if (input_port_read_safe(screen.machine(), "RESET", 0x00) & 0x01)
cputag_set_input_line(screen.machine(), "maincpu", INPUT_LINE_RESET, PULSE_LINE); cputag_set_input_line(screen.machine(), "maincpu", INPUT_LINE_RESET, PULSE_LINE);
@ -9481,7 +9481,7 @@ int megadrive_z80irq_hpos = 320;
case 2:scr_width = 320;break;// configure_screen(0, 320-1, megadrive_visible_scanlines-1,(double)megadriv_framerate); break; /* technically invalid, but used in rare cases */ case 2:scr_width = 320;break;// configure_screen(0, 320-1, megadrive_visible_scanlines-1,(double)megadriv_framerate); break; /* technically invalid, but used in rare cases */
case 3:scr_width = 320;break;// configure_screen(0, 320-1, megadrive_visible_scanlines-1,(double)megadriv_framerate); break; case 3:scr_width = 320;break;// configure_screen(0, 320-1, megadrive_visible_scanlines-1,(double)megadriv_framerate); break;
} }
// mame_printf_debug("my mode %02x", megadrive_vdp_register[0x0c]); // mame_printf_debug("my mode %02x", megadrive_vdp_register[0x0c]);
visarea.min_x = 0; visarea.min_x = 0;
visarea.max_x = scr_width-1; visarea.max_x = scr_width-1;
@ -9493,10 +9493,10 @@ int megadrive_z80irq_hpos = 320;
if (0) if (0)
{ {
//int xxx; //int xxx;
// UINT64 frametime; // UINT64 frametime;
// /* reference */ // /* reference */
// frametime = ATTOSECONDS_PER_SECOND/megadriv_framerate; // frametime = ATTOSECONDS_PER_SECOND/megadriv_framerate;
//time_elapsed_since_crap = frame_timer->time_elapsed(); //time_elapsed_since_crap = frame_timer->time_elapsed();
//xxx = screen.machine().device<cpudevice>("maincpu")->attotime_to_cycles(time_elapsed_since_crap); //xxx = screen.machine().device<cpudevice>("maincpu")->attotime_to_cycles(time_elapsed_since_crap);

14
src/mame/machine/n64.c
View File

@ -378,7 +378,7 @@ WRITE32_MEMBER( n64_periphs::open_w )
// RDRAM Interface (RI) // RDRAM Interface (RI)
#define RDRAM_CONFIG (0) #define RDRAM_CONFIG (0)
#define RDRAM_DEVICE_ID (1) #define RDRAM_DEVICE_ID (1)
#define RDRAM_DELAY (2) #define RDRAM_DELAY (2)
#define RDRAM_MODE (3) #define RDRAM_MODE (3)
@ -1336,9 +1336,9 @@ WRITE32_MEMBER( n64_periphs::pi_reg_w )
pi_dma_dir = 0; pi_dma_dir = 0;
pi_status |= 1; pi_status |= 1;
attotime dma_period = attotime::from_hz(93750000) * (pi_rd_len + 1) * 3; attotime dma_period = attotime::from_hz(93750000) * (pi_rd_len + 1) * 3;
//printf("want read dma in %d\n", (pi_rd_len + 1)); //printf("want read dma in %d\n", (pi_rd_len + 1));
pi_dma_timer->adjust(dma_period); pi_dma_timer->adjust(dma_period);
break; break;
} }
@ -1348,9 +1348,9 @@ WRITE32_MEMBER( n64_periphs::pi_reg_w )
pi_dma_dir = 1; pi_dma_dir = 1;
pi_status |= 1; pi_status |= 1;
attotime dma_period = attotime::from_hz(93750000) * (pi_wr_len + 1) * 3; attotime dma_period = attotime::from_hz(93750000) * (pi_wr_len + 1) * 3;
//printf("want write dma in %d\n", (pi_wr_len + 1)); //printf("want write dma in %d\n", (pi_wr_len + 1));
pi_dma_timer->adjust(dma_period); pi_dma_timer->adjust(dma_period);
break; break;
} }

4
src/mame/machine/pgmprot.c
View File

@ -1163,7 +1163,7 @@ WRITE16_HANDLER( kov_asic_sim_w )
kov_value ^= kov_key; kov_value ^= kov_key;
// bprintf (PRINT_NORMAL, _T("ASIC27 command: %2.2x data: %4.4x\n"), (data ^ kov_key) & 0xff, kov_value); // bprintf (PRINT_NORMAL, _T("ASIC27 command: %2.2x data: %4.4x\n"), (data ^ kov_key) & 0xff, kov_value);
switch ((data ^ kov_key) & 0xff) switch ((data ^ kov_key) & 0xff)
{ {
@ -1282,7 +1282,7 @@ WRITE16_HANDLER( kov_asic_sim_w )
default: default:
kov_response = 0x880000; kov_response = 0x880000;
// bprintf (PRINT_NORMAL, _T("Unknown ASIC27 command: %2.2x data: %4.4x\n"), (data ^ kov_key) & 0xff, kov_value); // bprintf (PRINT_NORMAL, _T("Unknown ASIC27 command: %2.2x data: %4.4x\n"), (data ^ kov_key) & 0xff, kov_value);
break; break;
} }

2
src/mame/mame.lst
View File

@ -4813,7 +4813,7 @@ mvsc2 // 2000.03 Marvel Vs. Capcom 2 New Age of Heroes (Rev A)
smarinef // 2000.03 Sega Marine Fishing smarinef // 2000.03 Sega Marine Fishing
wldkicks // 2000.03 World Kicks wldkicks // 2000.03 World Kicks
pstone2 // 2000.04 Power Stone 2 pstone2 // 2000.04 Power Stone 2
toukon4 // 2000.04 Shin Nihon Prowrestling Toukon Retsuden 4 Arcade Edition toukon4 // 2000.04 Shin Nihon Prowrestling Toukon Retsuden 4 Arcade Edition
qmegamis // 2000.05 Quiz Ah Megamisama qmegamis // 2000.05 Quiz Ah Megamisama
derbyo2k // 2000.06 Derby Owners Club 2000 Ver.2 (Rev A) derbyo2k // 2000.06 Derby Owners Club 2000 Ver.2 (Rev A)
vonot // 2000.06 Virtual-on Oratorio Tangram M.S.B.S. ver.5.66 2000 Edition vonot // 2000.06 Virtual-on Oratorio Tangram M.S.B.S. ver.5.66 2000 Edition

8
src/mame/video/deco_mlc.c
View File

@ -501,10 +501,10 @@ SCREEN_VBLANK( mlc )
{ {
deco_mlc_state *state = screen.machine().driver_data<deco_mlc_state>(); deco_mlc_state *state = screen.machine().driver_data<deco_mlc_state>();
/* Spriteram is definitely double buffered, as the vram lookup tables /* Spriteram is definitely double buffered, as the vram lookup tables
are often updated a frame after spriteram is setup to point to a new are often updated a frame after spriteram is setup to point to a new
lookup table. Without buffering incorrect one frame glitches are seen lookup table. Without buffering incorrect one frame glitches are seen
in several places, especially in Hoops. in several places, especially in Hoops.
*/ */
memcpy(state->m_mlc_buffered_spriteram, state->m_spriteram, 0x3000); memcpy(state->m_mlc_buffered_spriteram, state->m_spriteram, 0x3000);
} }
} }

4
src/mame/video/lastduel.c
View File

@ -314,8 +314,8 @@ SCREEN_VBLANK( lastduel )
address_space *space = screen.machine().device("maincpu")->memory().space(AS_PROGRAM); address_space *space = screen.machine().device("maincpu")->memory().space(AS_PROGRAM);
/* Spriteram is always 1 frame ahead, suggesting buffering. I can't find /* Spriteram is always 1 frame ahead, suggesting buffering. I can't find
a register to control this so I assume it happens automatically a register to control this so I assume it happens automatically
every frame at the end of vblank */ every frame at the end of vblank */
buffer_spriteram16_w(space, 0, 0, 0xffff); buffer_spriteram16_w(space, 0, 0, 0xffff);
} }
} }

8
src/mame/video/nmk16.c
View File

@ -798,10 +798,10 @@ SCREEN_VBLANK( nmk )
{ {
nmk16_state *state = screen.machine().driver_data<nmk16_state>(); nmk16_state *state = screen.machine().driver_data<nmk16_state>();
/* sprites are DMA'd from Main RAM to a private buffer automatically /* sprites are DMA'd from Main RAM to a private buffer automatically
(or at least this is how I interpret the datasheet) */ (or at least this is how I interpret the datasheet) */
/* -- I actually see little evidence to support this, sprite lag /* -- I actually see little evidence to support this, sprite lag
in some games should be checked on real boards */ in some games should be checked on real boards */
// memcpy(state->m_spriteram_old2,state->m_spriteram_old,0x1000); // memcpy(state->m_spriteram_old2,state->m_spriteram_old,0x1000);
memcpy(state->m_spriteram_old2,state->m_mainram+0x8000/2,0x1000); memcpy(state->m_spriteram_old2,state->m_mainram+0x8000/2,0x1000);
@ -815,10 +815,10 @@ SCREEN_VBLANK( strahl )
{ {
nmk16_state *state = screen.machine().driver_data<nmk16_state>(); nmk16_state *state = screen.machine().driver_data<nmk16_state>();
/* sprites are DMA'd from Main RAM to a private buffer automatically /* sprites are DMA'd from Main RAM to a private buffer automatically
(or at least this is how I interpret the datasheet) */ (or at least this is how I interpret the datasheet) */
/* -- I actually see little evidence to support this, sprite lag /* -- I actually see little evidence to support this, sprite lag
in some games should be checked on real boards */ in some games should be checked on real boards */
/* strahl sprites are allocated in memory range FF000-FFFFF */ /* strahl sprites are allocated in memory range FF000-FFFFF */

4
src/mame/video/pgm.c
View File

@ -184,8 +184,8 @@ static void draw_sprite_new_zoomed( pgm_state *state, running_machine &machine,
/* precalculate where drawing will end, for flipped zoomed cases. */ /* precalculate where drawing will end, for flipped zoomed cases. */
/* if we're to avoid pre-decoding the data for each sprite each time we draw then we have to draw the sprite data /* if we're to avoid pre-decoding the data for each sprite each time we draw then we have to draw the sprite data
in the order it is in ROM due to the nature of the compresson scheme. This means drawing upwards from the end point in the order it is in ROM due to the nature of the compresson scheme. This means drawing upwards from the end point
in the case of flipped sprites */ in the case of flipped sprites */
ycnt = 0; ycnt = 0;
ycntdraw = 0; ycntdraw = 0;
int realysize = 0; int realysize = 0;

12
src/mame/video/sprint2.c
View File

@ -156,12 +156,12 @@ SCREEN_VBLANK( sprint2 )
const rectangle &visarea = screen.machine().primary_screen->visible_area(); const rectangle &visarea = screen.machine().primary_screen->visible_area();
/* /*
* Collisions are detected for both player cars: * Collisions are detected for both player cars:
* *
* D7 => state->m_collision w/ white playfield * D7 => state->m_collision w/ white playfield
* D6 => state->m_collision w/ black playfield or another car * D6 => state->m_collision w/ black playfield or another car
* *
*/ */
for (i = 0; i < 2; i++) for (i = 0; i < 2; i++)
{ {

2
src/mame/video/taito_f2.c
View File

@ -971,7 +971,7 @@ SCREEN_VBLANK( taitof2_partial_buffer_delayed_qzchikyu )
if (vblank_on) if (vblank_on)
{ {
/* spriteram[2] and [3] are 1 frame behind... /* spriteram[2] and [3] are 1 frame behind...
probably thundfox_eof_callback would work fine */ probably thundfox_eof_callback would work fine */
taitof2_state *state = screen.machine().driver_data<taitof2_state>(); taitof2_state *state = screen.machine().driver_data<taitof2_state>();
UINT16 *spriteram = state->m_spriteram; UINT16 *spriteram = state->m_spriteram;

4
src/mame/video/twin16.c
View File

@ -550,8 +550,8 @@ SCREEN_VBLANK( twin16 )
state->m_need_process_spriteram = 1; state->m_need_process_spriteram = 1;
/* if the sprite preprocessor is used, sprite ram is copied to an external buffer first, /* if the sprite preprocessor is used, sprite ram is copied to an external buffer first,
as evidenced by 1-frame sprite lag in gradius2 and devilw otherwise, though there's probably as evidenced by 1-frame sprite lag in gradius2 and devilw otherwise, though there's probably
more to it than that */ more to it than that */
memcpy(&screen.machine().generic.buffered_spriteram.u16[0x1800],state->m_sprite_buffer,0x800*sizeof(UINT16)); memcpy(&screen.machine().generic.buffered_spriteram.u16[0x1800],state->m_sprite_buffer,0x800*sizeof(UINT16));
memcpy(state->m_sprite_buffer,&screen.machine().generic.spriteram.u16[0x1800],0x800*sizeof(UINT16)); memcpy(state->m_sprite_buffer,&screen.machine().generic.spriteram.u16[0x1800],0x800*sizeof(UINT16));
} }

4
src/mame/video/twincobr.c
View File

@ -524,8 +524,8 @@ SCREEN_VBLANK( toaplan0 )
address_space *space = screen.machine().device("maincpu")->memory().space(AS_PROGRAM); address_space *space = screen.machine().device("maincpu")->memory().space(AS_PROGRAM);
/* Spriteram is always 1 frame ahead, suggesting spriteram buffering. /* Spriteram is always 1 frame ahead, suggesting spriteram buffering.
There are no CPU output registers that control this so we There are no CPU output registers that control this so we
assume it happens automatically every frame, at the end of vblank */ assume it happens automatically every frame, at the end of vblank */
buffer_spriteram16_w(space,0,0,0xffff); buffer_spriteram16_w(space,0,0,0xffff);
} }
} }

14
src/mame/video/xmen.c
View File

@ -172,9 +172,9 @@ SCREEN_VBLANK( xmen6p )
memcpy(state->m_k053247_ram, state->m_xmen6p_spriteramright, 0x1000); memcpy(state->m_k053247_ram, state->m_xmen6p_spriteramright, 0x1000);
/* we write the entire content of the tileram to the chip to ensure /* we write the entire content of the tileram to the chip to ensure
everything gets marked as dirty and the desired tilemap is rendered everything gets marked as dirty and the desired tilemap is rendered
this is not very efficient! this is not very efficient!
*/ */
for (offset = 0; offset < (0xc000 / 2); offset++) for (offset = 0; offset < (0xc000 / 2); offset++)
{ {
// K052109_lsb_w // K052109_lsb_w
@ -190,10 +190,10 @@ SCREEN_VBLANK( xmen6p )
memcpy(state->m_k053247_ram, state->m_xmen6p_spriteramleft, 0x1000); memcpy(state->m_k053247_ram, state->m_xmen6p_spriteramleft, 0x1000);
/* we write the entire content of the tileram to the chip to ensure /* we write the entire content of the tileram to the chip to ensure
everything gets marked as dirty and the desired tilemap is rendered everything gets marked as dirty and the desired tilemap is rendered
this is not very efficient! this is not very efficient!
*/ */
for (offset = 0; offset < (0xc000 / 2); offset++) for (offset = 0; offset < (0xc000 / 2); offset++)
{ {
// K052109_lsb_w // K052109_lsb_w
@ -230,7 +230,7 @@ SCREEN_VBLANK( xmen6p )
k052109_tilemap_draw(state->m_k052109, *renderbitmap, cliprect, layer[2], 0, 4); k052109_tilemap_draw(state->m_k052109, *renderbitmap, cliprect, layer[2], 0, 4);
/* this isn't supported anymore and it is unsure if still needed; keeping here for reference /* this isn't supported anymore and it is unsure if still needed; keeping here for reference
pdrawgfx_shadow_lowpri = 1; fix shadows of boulders in front of feet */ pdrawgfx_shadow_lowpri = 1; fix shadows of boulders in front of feet */
k053247_sprites_draw(state->m_k053246, *renderbitmap, cliprect); k053247_sprites_draw(state->m_k053246, *renderbitmap, cliprect);
} }
} }