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Pet peeving with extreme prejudice (nw)

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This commit is contained in:
Olivier Galibert 2017-11-30 10:54:32 +01:00
parent 29825789a8
commit 7c8a1fa409
115 changed files with 533 additions and 559 deletions
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2
src/devices/bus/cbus/pc9801_118.cpp
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@ -137,7 +137,7 @@ void pc9801_118_device::device_validity_check(validity_checker &valid) const
void pc9801_118_device::install_device(offs_t start, offs_t end, read8_delegate rhandler, write8_delegate whandler)
{
int buswidth = machine().firstcpu->space_config(AS_IO)->m_databus_width;
int buswidth = machine().firstcpu->space_config(AS_IO)->m_data_width;
switch(buswidth)
{
case 8:

2
src/devices/bus/cbus/pc9801_26.cpp
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@ -130,7 +130,7 @@ void pc9801_26_device::device_validity_check(validity_checker &valid) const
void pc9801_26_device::install_device(offs_t start, offs_t end, read8_delegate rhandler, write8_delegate whandler)
{
int buswidth = machine().firstcpu->space_config(AS_IO)->m_databus_width;
int buswidth = machine().firstcpu->space_config(AS_IO)->m_data_width;
switch(buswidth)
{
case 8:

2
src/devices/bus/cbus/pc9801_86.cpp
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@ -148,7 +148,7 @@ void pc9801_86_device::device_validity_check(validity_checker &valid) const
void pc9801_86_device::install_device(offs_t start, offs_t end, read8_delegate rhandler, write8_delegate whandler)
{
int buswidth = machine().firstcpu->space_config(AS_IO)->m_databus_width;
int buswidth = machine().firstcpu->space_config(AS_IO)->m_data_width;
switch(buswidth)
{
case 8:

2
src/devices/bus/cbus/pc9801_amd98.cpp
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@ -125,7 +125,7 @@ void pc9801_amd98_device::device_validity_check(validity_checker &valid) const
void pc9801_amd98_device::install_device(offs_t start, offs_t end, read8_delegate rhandler, write8_delegate whandler)
{
int buswidth = machine().firstcpu->space_config(AS_IO)->m_databus_width;
int buswidth = machine().firstcpu->space_config(AS_IO)->m_data_width;
switch(buswidth)
{
case 8:

2
src/devices/bus/hp_dio/hp_dio.cpp
View File

@ -147,7 +147,7 @@ void dio16_device::device_start()
m_maincpu = subdevice<cpu_device>(m_cputag);
m_prgspace = &m_maincpu->space(AS_PROGRAM);
m_prgwidth = m_maincpu->space_config(AS_PROGRAM)->m_databus_width;
m_prgwidth = m_maincpu->space_config(AS_PROGRAM)->m_data_width;
}
//-------------------------------------------------

4
src/devices/bus/isa/isa.cpp
View File

@ -232,9 +232,9 @@ void isa8_device::device_start()
else // use host CPU's program and I/O spaces directly
{
m_iospace = &m_maincpu->space(AS_IO);
m_iowidth = m_maincpu->space_config(AS_IO)->m_databus_width;
m_iowidth = m_maincpu->space_config(AS_IO)->m_data_width;
m_memspace = &m_maincpu->space(AS_PROGRAM);
m_memwidth = m_maincpu->space_config(AS_PROGRAM)->m_databus_width;
m_memwidth = m_maincpu->space_config(AS_PROGRAM)->m_data_width;
}
}

10
src/devices/bus/nubus/nubus.cpp
View File

@ -125,7 +125,7 @@ void nubus_device::add_nubus_card(device_nubus_card_interface *card)
void nubus_device::install_device(offs_t start, offs_t end, read8_delegate rhandler, write8_delegate whandler, uint32_t mask)
{
m_maincpu = machine().device<cpu_device>(m_cputag);
int buswidth = m_maincpu->space_config(AS_PROGRAM)->m_databus_width;
int buswidth = m_maincpu->space_config(AS_PROGRAM)->m_data_width;
switch(buswidth)
{
case 32:
@ -142,7 +142,7 @@ void nubus_device::install_device(offs_t start, offs_t end, read8_delegate rhand
void nubus_device::install_device(offs_t start, offs_t end, read16_delegate rhandler, write16_delegate whandler, uint32_t mask)
{
m_maincpu = machine().device<cpu_device>(m_cputag);
int buswidth = m_maincpu->space_config(AS_PROGRAM)->m_databus_width;
int buswidth = m_maincpu->space_config(AS_PROGRAM)->m_data_width;
switch(buswidth)
{
case 32:
@ -159,7 +159,7 @@ void nubus_device::install_device(offs_t start, offs_t end, read16_delegate rhan
void nubus_device::install_device(offs_t start, offs_t end, read32_delegate rhandler, write32_delegate whandler, uint32_t mask)
{
m_maincpu = machine().device<cpu_device>(m_cputag);
int buswidth = m_maincpu->space_config(AS_PROGRAM)->m_databus_width;
int buswidth = m_maincpu->space_config(AS_PROGRAM)->m_data_width;
switch(buswidth)
{
case 32:
@ -176,7 +176,7 @@ void nubus_device::install_device(offs_t start, offs_t end, read32_delegate rhan
void nubus_device::install_readonly_device(offs_t start, offs_t end, read32_delegate rhandler, uint32_t mask)
{
m_maincpu = machine().device<cpu_device>(m_cputag);
int buswidth = m_maincpu->space_config(AS_PROGRAM)->m_databus_width;
int buswidth = m_maincpu->space_config(AS_PROGRAM)->m_data_width;
switch(buswidth)
{
case 32:
@ -193,7 +193,7 @@ void nubus_device::install_readonly_device(offs_t start, offs_t end, read32_dele
void nubus_device::install_writeonly_device(offs_t start, offs_t end, write32_delegate whandler, uint32_t mask)
{
m_maincpu = machine().device<cpu_device>(m_cputag);
int buswidth = m_maincpu->space_config(AS_PROGRAM)->m_databus_width;
int buswidth = m_maincpu->space_config(AS_PROGRAM)->m_data_width;
switch(buswidth)
{
case 32:

2
src/devices/bus/vme/vme.cpp
View File

@ -266,7 +266,7 @@ void vme_device::device_start()
LOG(" - using owner memory spaces for %s\n", m_cputag);
m_maincpu = owner()->subdevice<cpu_device>(m_cputag);
m_prgspace = &m_maincpu->space(AS_PROGRAM);
m_prgwidth = m_maincpu->space_config(AS_PROGRAM)->m_databus_width;
m_prgwidth = m_maincpu->space_config(AS_PROGRAM)->m_data_width;
LOG(" - Done at %d width\n", m_prgwidth);
}
}

6
src/devices/cpu/i8089/i8089.cpp
View File

@ -40,7 +40,7 @@ i8089_device::i8089_device(const machine_config &mconfig, const char *tag, devic
m_ch1(*this, "1"),
m_ch2(*this, "2"),
m_write_sintr1(*this),
m_write_sintr2(*this), m_databus_width(0), m_mem(nullptr), m_io(nullptr),
m_write_sintr2(*this), m_data_width(0), m_mem(nullptr), m_io(nullptr),
m_sysbus(0),
m_scb(0),
m_soc(0), m_initialized(false),
@ -117,8 +117,8 @@ void i8089_device::device_start()
void i8089_device::device_config_complete()
{
m_program_config = address_space_config("program", ENDIANNESS_LITTLE, m_databus_width, 20);
m_io_config = address_space_config("io", ENDIANNESS_LITTLE, m_databus_width, 16);
m_program_config = address_space_config("program", ENDIANNESS_LITTLE, m_data_width, 20);
m_io_config = address_space_config("io", ENDIANNESS_LITTLE, m_data_width, 16);
}
//-------------------------------------------------

8
src/devices/cpu/i8089/i8089.h
View File

@ -22,8 +22,8 @@
// INTERFACE CONFIGURATION MACROS
//**************************************************************************
#define MCFG_I8089_DATABUS_WIDTH(_databus_width) \
i8089_device::set_databus_width(*device, _databus_width);
#define MCFG_I8089_DATA_WIDTH(_data_width) \
i8089_device::set_data_width(*device, _data_width);
#define MCFG_I8089_SINTR1(_sintr1) \
devcb = &downcast<i8089_device *>(device)->set_sintr1_callback(DEVCB_##_sintr1);
@ -54,7 +54,7 @@ public:
template <class Object> devcb_base &set_sintr2_callback(Object &&sintr2) { return m_write_sintr2.set_callback(std::forward<Object>(sintr2)); }
// static configuration helpers
static void set_databus_width(device_t &device, uint8_t databus_width) { downcast<i8089_device &>(device).m_databus_width = databus_width; }
static void set_data_width(device_t &device, uint8_t data_width) { downcast<i8089_device &>(device).m_data_width = data_width; }
// input lines
DECLARE_WRITE_LINE_MEMBER( ca_w );
@ -112,7 +112,7 @@ private:
void initialize();
uint8_t m_databus_width;
uint8_t m_data_width;
address_space *m_mem;
address_space *m_io;

4
src/devices/cpu/m6502/m4510.cpp
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@ -19,10 +19,10 @@ m4510_device::m4510_device(const machine_config &mconfig, const char *tag, devic
map_enable(0),
nomap(false)
{
program_config.m_addrbus_width = 20;
program_config.m_addr_width = 20;
program_config.m_logaddr_width = 16;
program_config.m_page_shift = 13;
sprogram_config.m_addrbus_width = 20;
sprogram_config.m_addr_width = 20;
sprogram_config.m_logaddr_width = 16;
sprogram_config.m_page_shift = 13;
}

4
src/devices/cpu/m6502/m6504.cpp
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@ -16,8 +16,8 @@ DEFINE_DEVICE_TYPE(M6504, m6504_device, "m6504", "M6504")
m6504_device::m6504_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
m6502_device(mconfig, M6504, tag, owner, clock)
{
program_config.m_addrbus_width = 13;
sprogram_config.m_addrbus_width = 13;
program_config.m_addr_width = 13;
sprogram_config.m_addr_width = 13;
}
void m6504_device::device_start()

4
src/devices/cpu/m6502/m6507.cpp
View File

@ -16,8 +16,8 @@ DEFINE_DEVICE_TYPE(M6507, m6507_device, "m6507", "M6507")
m6507_device::m6507_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
m6502_device(mconfig, M6507, tag, owner, clock)
{
program_config.m_addrbus_width = 13;
sprogram_config.m_addrbus_width = 13;
program_config.m_addr_width = 13;
sprogram_config.m_addr_width = 13;
}
void m6507_device::device_start()

4
src/devices/cpu/m6502/m6509.cpp
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@ -17,9 +17,9 @@ DEFINE_DEVICE_TYPE(M6509, m6509_device, "m6509", "M6509")
m6509_device::m6509_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
m6502_device(mconfig, M6509, tag, owner, clock), XPC(0), bank_i(0), bank_y(0)
{
program_config.m_addrbus_width = 20;
program_config.m_addr_width = 20;
program_config.m_logaddr_width = 20;
sprogram_config.m_addrbus_width = 20;
sprogram_config.m_addr_width = 20;
sprogram_config.m_logaddr_width = 20;
}

2
src/devices/cpu/powerpc/ppcdrc.cpp
View File

@ -996,7 +996,7 @@ void ppc_device::static_generate_memory_accessor(int mode, int size, int iswrite
/* on entry, address is in I0; data for writes is in I1; masks are in I2 */
/* on exit, read result is in I0 */
/* routine trashes I0-I3 */
int fastxor = BYTE8_XOR_BE(0) >> (int)(space_config(AS_PROGRAM)->m_databus_width < 64);
int fastxor = BYTE8_XOR_BE(0) >> (int)(space_config(AS_PROGRAM)->m_data_width < 64);
drcuml_block *block;
int translate_type;
int tlbreturn = 0;

4
src/devices/cpu/tms9900/tms9900.cpp
View File

@ -176,9 +176,9 @@ enum
twice their number. Accordingly, the TMS9900 has a CRU bitmask 0x0fff.
****************************************************************************/
tms99xx_device::tms99xx_device(const machine_config &mconfig, device_type type, const char *tag, int databus_width, int prg_addr_bits, int cru_addr_bits, device_t *owner, uint32_t clock)
tms99xx_device::tms99xx_device(const machine_config &mconfig, device_type type, const char *tag, int data_width, int prg_addr_bits, int cru_addr_bits, device_t *owner, uint32_t clock)
: cpu_device(mconfig, type, tag, owner, clock),
m_program_config("program", ENDIANNESS_BIG, databus_width, prg_addr_bits),
m_program_config("program", ENDIANNESS_BIG, data_width, prg_addr_bits),
m_io_config("cru", ENDIANNESS_BIG, 8, cru_addr_bits),
m_prgspace(nullptr),
m_cru(nullptr),

2
src/devices/cpu/tms9900/tms9900.h
View File

@ -64,7 +64,7 @@ public:
protected:
tms99xx_device(const machine_config &mconfig, device_type type,
const char *tag, int databus_width, int prg_addr_bits, int cru_addr_bits,
const char *tag, int data_width, int prg_addr_bits, int cru_addr_bits,
device_t *owner, uint32_t clock);
// device-level overrides

6
src/devices/machine/bankdev.cpp
View File

@ -10,8 +10,8 @@ address_map_bank_device::address_map_bank_device( const machine_config &mconfig,
: device_t(mconfig, ADDRESS_MAP_BANK, tag, owner, clock),
device_memory_interface(mconfig, *this),
m_endianness(ENDIANNESS_NATIVE),
m_databus_width(0),
m_addrbus_width(32),
m_data_width(0),
m_addr_width(32),
m_stride(1),
m_program(nullptr),
m_offset(0)
@ -83,7 +83,7 @@ READ64_MEMBER(address_map_bank_device::read64)
void address_map_bank_device::device_config_complete()
{
m_program_config = address_space_config( "program", m_endianness, m_databus_width, m_addrbus_width );
m_program_config = address_space_config( "program", m_endianness, m_data_width, m_addr_width );
}
void address_map_bank_device::device_start()

16
src/devices/machine/bankdev.h
View File

@ -9,11 +9,11 @@
#define MCFG_ADDRESS_MAP_BANK_ENDIANNESS(_endianness) \
address_map_bank_device::set_endianness(*device, _endianness);
#define MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(_databus_width) \
address_map_bank_device::set_databus_width(*device, _databus_width);
#define MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(_data_width) \
address_map_bank_device::set_data_width(*device, _data_width);
#define MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(_addrbus_width) \
address_map_bank_device::set_addrbus_width(*device, _addrbus_width);
#define MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(_addr_width) \
address_map_bank_device::set_addr_width(*device, _addr_width);
#define MCFG_ADDRESS_MAP_BANK_STRIDE(_stride) \
address_map_bank_device::set_stride(*device, _stride);
@ -28,8 +28,8 @@ public:
// static configuration helpers
static void set_endianness(device_t &device, endianness_t endianness) { downcast<address_map_bank_device &>(device).m_endianness = endianness; }
static void set_databus_width(device_t &device, uint8_t databus_width) { downcast<address_map_bank_device &>(device).m_databus_width = databus_width; }
static void set_addrbus_width(device_t &device, uint8_t addrbus_width) { downcast<address_map_bank_device &>(device).m_addrbus_width = addrbus_width; }
static void set_data_width(device_t &device, uint8_t data_width) { downcast<address_map_bank_device &>(device).m_data_width = data_width; }
static void set_addr_width(device_t &device, uint8_t addr_width) { downcast<address_map_bank_device &>(device).m_addr_width = addr_width; }
static void set_stride(device_t &device, uint32_t stride) { downcast<address_map_bank_device &>(device).m_stride = stride; }
DECLARE_ADDRESS_MAP(amap8, 8);
@ -59,8 +59,8 @@ protected:
private:
// internal state
endianness_t m_endianness;
uint8_t m_databus_width;
uint8_t m_addrbus_width;
uint8_t m_data_width;
uint8_t m_addr_width;
uint32_t m_stride;
address_space_config m_program_config;
address_space *m_program;

4
src/emu/addrmap.cpp
View File

@ -605,7 +605,7 @@ void address_map::map_validity_check(validity_checker &valid, int spacenum) cons
{
// it's safe to assume here that the device has a memory interface and a config for this space
const address_space_config &spaceconfig = *m_device->memory().space_config(spacenum);
int datawidth = spaceconfig.m_databus_width;
int datawidth = spaceconfig.m_data_width;
int alignunit = spaceconfig.alignment();
bool detected_overlap = DETECT_OVERLAPPING_MEMORY ? false : true;
@ -620,7 +620,7 @@ void address_map::map_validity_check(validity_checker &valid, int spacenum) cons
if (m_databits != datawidth)
osd_printf_error("Wrong memory handlers provided for %s space! (width = %d, memory = %08x)\n", spaceconfig.m_name, datawidth, m_databits);
offs_t globalmask = 0xffffffffUL >> (32 - spaceconfig.m_addrbus_width);
offs_t globalmask = 0xffffffffUL >> (32 - spaceconfig.m_addr_width);
if (m_globalmask != 0)
globalmask = m_globalmask;

2
src/emu/debug/debugbuf.cpp
View File

@ -176,7 +176,7 @@ void debug_disasm_buffer::debug_data_buffer::data_get(offs_t pc, offs_t size, st
void debug_disasm_buffer::debug_data_buffer::setup_methods()
{
address_space *space = m_space ? m_space : m_back->get_underlying_space();
int shift = space->addrbus_shift();
int shift = space->addr_shift();
int alignment = m_intf->opcode_alignment();
endianness_t endian = space->endianness();

16
src/emu/debug/debugcmd.cpp
View File

@ -1669,7 +1669,7 @@ void debugger_commands::execute_save(int ref, const std::vector<std::string> &pa
/* now write the data out */
auto dis = space->machine().disable_side_effect();
switch (space->addrbus_shift())
switch (space->addr_shift())
{
case -3:
for (offs_t i = offset; i != endoffset; i++)
@ -1748,10 +1748,10 @@ void debugger_commands::execute_load(int ref, const std::vector<std::string> &pa
f.seekg(0, std::ios::end);
length = f.tellg();
f.seekg(0);
if (space->addrbus_shift() < 0)
length >>= -space->addrbus_shift();
else if (space->addrbus_shift() > 0)
length <<= space->addrbus_shift();
if (space->addr_shift() < 0)
length >>= -space->addr_shift();
else if (space->addr_shift() > 0)
length <<= space->addr_shift();
}
// determine the addresses to read
@ -1759,7 +1759,7 @@ void debugger_commands::execute_load(int ref, const std::vector<std::string> &pa
offset = offset & space->addrmask();
offs_t i = 0;
// now read the data in, ignore endoffset and load entire file if length has been set to zero (offset-1)
switch (space->addrbus_shift())
switch (space->addr_shift())
{
case -3:
for (i = offset; f.good() && (i <= endoffset || endoffset == offset - 1); i++)
@ -1850,7 +1850,7 @@ void debugger_commands::execute_dump(int ref, const std::vector<std::string> &pa
if (!validate_cpu_space_parameter((params.size() > 6) ? params[6].c_str() : nullptr, ref, space))
return;
int shift = space->addrbus_shift();
int shift = space->addr_shift();
u64 granularity = shift > 0 ? 2 : 1 << -shift;
/* further validation */
@ -2453,7 +2453,7 @@ void debugger_commands::execute_find(int ref, const std::vector<std::string> &pa
/* further validation */
endoffset = (offset + length - 1) & space->addrmask();
offset = offset & space->addrmask();
cur_data_size = space->addrbus_shift() > 0 ? 2 : 1 << -space->addrbus_shift();
cur_data_size = space->addr_shift() > 0 ? 2 : 1 << -space->addr_shift();
if (cur_data_size == 0)
cur_data_size = 1;

2
src/emu/debug/dvdisasm.cpp
View File

@ -231,7 +231,7 @@ bool debug_view_disasm::generate_with_pc(debug_disasm_buffer &buffer, offs_t pc)
{
// Consider that instructions are 64 bytes max
const debug_view_disasm_source &source = downcast<const debug_view_disasm_source &>(*m_source);
int shift = source.m_space.addrbus_shift();
int shift = source.m_space.addr_shift();
offs_t backwards_offset;
if(shift < 0)

30
src/emu/dimemory.cpp
View File

@ -30,9 +30,9 @@
address_space_config::address_space_config()
: m_name("unknown"),
m_endianness(ENDIANNESS_NATIVE),
m_databus_width(0),
m_addrbus_width(0),
m_addrbus_shift(0),
m_data_width(0),
m_addr_width(0),
m_addr_shift(0),
m_logaddr_width(0),
m_page_shift(0),
m_is_octal(false),
@ -53,9 +53,9 @@ address_space_config::address_space_config()
address_space_config::address_space_config(const char *name, endianness_t endian, u8 datawidth, u8 addrwidth, s8 addrshift, address_map_constructor internal, address_map_constructor defmap)
: m_name(name),
m_endianness(endian),
m_databus_width(datawidth),
m_addrbus_width(addrwidth),
m_addrbus_shift(addrshift),
m_data_width(datawidth),
m_addr_width(addrwidth),
m_addr_shift(addrshift),
m_logaddr_width(addrwidth),
m_page_shift(0),
m_is_octal(false),
@ -67,9 +67,9 @@ address_space_config::address_space_config(const char *name, endianness_t endian
address_space_config::address_space_config(const char *name, endianness_t endian, u8 datawidth, u8 addrwidth, s8 addrshift, u8 logwidth, u8 pageshift, address_map_constructor internal, address_map_constructor defmap)
: m_name(name),
m_endianness(endian),
m_databus_width(datawidth),
m_addrbus_width(addrwidth),
m_addrbus_shift(addrshift),
m_data_width(datawidth),
m_addr_width(addrwidth),
m_addr_shift(addrshift),
m_logaddr_width(logwidth),
m_page_shift(pageshift),
m_is_octal(false),
@ -81,9 +81,9 @@ address_space_config::address_space_config(const char *name, endianness_t endian
address_space_config::address_space_config(const char *name, endianness_t endian, u8 datawidth, u8 addrwidth, s8 addrshift, address_map_delegate internal, address_map_delegate defmap)
: m_name(name),
m_endianness(endian),
m_databus_width(datawidth),
m_addrbus_width(addrwidth),
m_addrbus_shift(addrshift),
m_data_width(datawidth),
m_addr_width(addrwidth),
m_addr_shift(addrshift),
m_logaddr_width(addrwidth),
m_page_shift(0),
m_is_octal(false),
@ -97,9 +97,9 @@ address_space_config::address_space_config(const char *name, endianness_t endian
address_space_config::address_space_config(const char *name, endianness_t endian, u8 datawidth, u8 addrwidth, s8 addrshift, u8 logwidth, u8 pageshift, address_map_delegate internal, address_map_delegate defmap)
: m_name(name),
m_endianness(endian),
m_databus_width(datawidth),
m_addrbus_width(addrwidth),
m_addrbus_shift(addrshift),
m_data_width(datawidth),
m_addr_width(addrwidth),
m_addr_shift(addrshift),
m_logaddr_width(logwidth),
m_page_shift(pageshift),
m_is_octal(false),

322
src/emu/emumem.cpp
View File

@ -414,8 +414,8 @@ private:
u64 read_stub_64(address_space &space, offs_t offset, u64 mask);
// stubs for reading I/O ports
template<typename _UintType>
_UintType read_stub_ioport(address_space &space, offs_t offset, _UintType mask) { return m_ioport->read(); }
template<typename UintType>
UintType read_stub_ioport(address_space &space, offs_t offset, UintType mask) { return m_ioport->read(); }
// internal helper
virtual void remove_subunit(int entry) override;
@ -477,8 +477,8 @@ private:
void write_stub_64(address_space &space, offs_t offset, u64 data, u64 mask);
// stubs for writing I/O ports
template<typename _UintType>
void write_stub_ioport(address_space &space, offs_t offset, _UintType data, _UintType mask) { m_ioport->write(data, mask); }
template<typename UintType>
void write_stub_ioport(address_space &space, offs_t offset, UintType data, UintType mask) { m_ioport->write(data, mask); }
// internal helper
virtual void remove_subunit(int entry) override;
@ -521,15 +521,15 @@ private:
// A proxy class that contains an handler_entry_read or _write and forwards the setter calls
template<typename _HandlerEntry>
template<typename HandlerEntry>
class handler_entry_proxy
{
public:
handler_entry_proxy(std::list<_HandlerEntry *> _handlers, u64 _mask) : handlers(std::move(_handlers)), mask(_mask) {}
handler_entry_proxy(const handler_entry_proxy<_HandlerEntry> &hep) : handlers(hep.handlers), mask(hep.mask) {}
handler_entry_proxy(std::list<HandlerEntry *> _handlers, u64 _mask) : handlers(std::move(_handlers)), mask(_mask) {}
handler_entry_proxy(const handler_entry_proxy<HandlerEntry> &hep) : handlers(hep.handlers), mask(hep.mask) {}
// forward delegate callbacks configuration
template<typename _delegate> void set_delegate(_delegate delegate) const {
template<typename Delegate> void set_delegate(Delegate delegate) const {
for (const auto & elem : handlers)
(elem)->set_delegate(delegate, mask);
}
@ -541,7 +541,7 @@ public:
}
private:
std::list<_HandlerEntry *> handlers;
std::list<HandlerEntry *> handlers;
u64 mask;
};
@ -714,8 +714,8 @@ public:
private:
// internal unmapped handler
template<typename _UintType>
_UintType unmap_r(address_space &space, offs_t offset, _UintType mask)
template<typename UintType>
UintType unmap_r(address_space &space, offs_t offset, UintType mask)
{
if (m_space.log_unmap() && !m_space.machine().side_effect_disabled())
{
@ -724,32 +724,32 @@ private:
? "%s: unmapped %s memory read from %0*o & %0*o\n"
: "%s: unmapped %s memory read from %0*X & %0*X\n",
m_space.machine().describe_context(), m_space.name(),
m_space.addrchars(), m_space.byte_to_address(offset * sizeof(_UintType)),
2 * sizeof(_UintType), mask);
m_space.addrchars(), m_space.byte_to_address(offset * sizeof(UintType)),
2 * sizeof(UintType), mask);
}
return m_space.unmap();
}
// internal no-op handler
template<typename _UintType>
_UintType nop_r(address_space &space, offs_t offset, _UintType mask)
template<typename UintType>
UintType nop_r(address_space &space, offs_t offset, UintType mask)
{
return m_space.unmap();
}
// internal watchpoint handler
template<typename _UintType>
_UintType watchpoint_r(address_space &space, offs_t offset, _UintType mask)
template<typename UintType>
UintType watchpoint_r(address_space &space, offs_t offset, UintType mask)
{
m_space.device().debug()->memory_read_hook(m_space, offset * sizeof(_UintType), mask);
m_space.device().debug()->memory_read_hook(m_space, offset * sizeof(UintType), mask);
u16 *oldtable = m_live_lookup;
m_live_lookup = &m_table[0];
_UintType result;
if (sizeof(_UintType) == 1) result = m_space.read_byte(offset);
if (sizeof(_UintType) == 2) result = m_space.read_word(offset << 1, mask);
if (sizeof(_UintType) == 4) result = m_space.read_dword(offset << 2, mask);
if (sizeof(_UintType) == 8) result = m_space.read_qword(offset << 3, mask);
UintType result;
if (sizeof(UintType) == 1) result = m_space.read_byte(offset);
if (sizeof(UintType) == 2) result = m_space.read_word(offset << 1, mask);
if (sizeof(UintType) == 4) result = m_space.read_dword(offset << 2, mask);
if (sizeof(UintType) == 8) result = m_space.read_qword(offset << 3, mask);
m_live_lookup = oldtable;
return result;
}
@ -785,8 +785,8 @@ public:
private:
// internal handlers
template<typename _UintType>
void unmap_w(address_space &space, offs_t offset, _UintType data, _UintType mask)
template<typename UintType>
void unmap_w(address_space &space, offs_t offset, UintType data, UintType mask)
{
if (m_space.log_unmap() && !m_space.machine().side_effect_disabled())
{
@ -795,28 +795,28 @@ private:
? "%s: unmapped %s memory write to %0*o = %0*o & %0*o\n"
: "%s: unmapped %s memory write to %0*X = %0*X & %0*X\n",
m_space.machine().describe_context(), m_space.name(),
m_space.addrchars(), m_space.byte_to_address(offset * sizeof(_UintType)),
2 * sizeof(_UintType), data,
2 * sizeof(_UintType), mask);
m_space.addrchars(), m_space.byte_to_address(offset * sizeof(UintType)),
2 * sizeof(UintType), data,
2 * sizeof(UintType), mask);
}
}
template<typename _UintType>
void nop_w(address_space &space, offs_t offset, _UintType data, _UintType mask)
template<typename UintType>
void nop_w(address_space &space, offs_t offset, UintType data, UintType mask)
{
}
template<typename _UintType>
void watchpoint_w(address_space &space, offs_t offset, _UintType data, _UintType mask)
template<typename UintType>
void watchpoint_w(address_space &space, offs_t offset, UintType data, UintType mask)
{
m_space.device().debug()->memory_write_hook(m_space, offset * sizeof(_UintType), data, mask);
m_space.device().debug()->memory_write_hook(m_space, offset * sizeof(UintType), data, mask);
u16 *oldtable = m_live_lookup;
m_live_lookup = &m_table[0];
if (sizeof(_UintType) == 1) m_space.write_byte(offset, data);
if (sizeof(_UintType) == 2) m_space.write_word(offset << 1, data, mask);
if (sizeof(_UintType) == 4) m_space.write_dword(offset << 2, data, mask);
if (sizeof(_UintType) == 8) m_space.write_qword(offset << 3, data, mask);
if (sizeof(UintType) == 1) m_space.write_byte(offset, data);
if (sizeof(UintType) == 2) m_space.write_word(offset << 1, data, mask);
if (sizeof(UintType) == 4) m_space.write_dword(offset << 2, data, mask);
if (sizeof(UintType) == 8) m_space.write_qword(offset << 3, data, mask);
m_live_lookup = oldtable;
}
@ -878,31 +878,31 @@ private:
// ======================> address_space_specific
// this is a derived class of address_space with specific width, endianness, and table size
template<typename _NativeType, endianness_t _Endian, int _Shift, bool _Large>
template<typename NativeType, endianness_t Endian, int AddrShift, bool Large>
class address_space_specific : public address_space
{
typedef address_space_specific<_NativeType, _Endian, _Shift, _Large> this_type;
typedef address_space_specific<NativeType, Endian, AddrShift, Large> this_type;
// constants describing the native size
static const u32 NATIVE_BYTES = sizeof(_NativeType);
static const u32 NATIVE_STEP = _Shift >= 0 ? NATIVE_BYTES << iabs(_Shift) : NATIVE_BYTES >> iabs(_Shift);
static const u32 NATIVE_MASK = NATIVE_STEP - 1;
static const u32 NATIVE_BITS = 8 * NATIVE_BYTES;
static constexpr u32 NATIVE_BYTES = sizeof(NativeType);
static constexpr u32 NATIVE_STEP = AddrShift >= 0 ? NATIVE_BYTES << iabs(AddrShift) : NATIVE_BYTES >> iabs(AddrShift);
static constexpr u32 NATIVE_MASK = NATIVE_STEP - 1;
static constexpr u32 NATIVE_BITS = 8 * NATIVE_BYTES;
// helpers to simplify core code
u32 read_lookup(offs_t address) const { return _Large ? m_read.lookup_live_large(address) : m_read.lookup_live_small(address); }
u32 write_lookup(offs_t address) const { return _Large ? m_write.lookup_live_large(address) : m_write.lookup_live_small(address); }
u32 setoffset_lookup(offs_t address) const { return _Large ? m_setoffset.lookup_live_large(address) : m_setoffset.lookup_live_small(address); }
u32 read_lookup(offs_t address) const { return Large ? m_read.lookup_live_large(address) : m_read.lookup_live_small(address); }
u32 write_lookup(offs_t address) const { return Large ? m_write.lookup_live_large(address) : m_write.lookup_live_small(address); }
u32 setoffset_lookup(offs_t address) const { return Large ? m_setoffset.lookup_live_large(address) : m_setoffset.lookup_live_small(address); }
static inline offs_t offset_to_byte(offs_t offset) { return _Shift < 0 ? offset << iabs(_Shift) : offset >> iabs(_Shift); }
static inline constexpr offs_t offset_to_byte(offs_t offset) { return AddrShift < 0 ? offset << iabs(AddrShift) : offset >> iabs(AddrShift); }
public:
// construction/destruction
address_space_specific(memory_manager &manager, device_memory_interface &memory, int spacenum)
: address_space(manager, memory, spacenum, _Large),
m_read(*this, _Large),
m_write(*this, _Large),
m_setoffset(*this, _Large)
: address_space(manager, memory, spacenum, Large),
m_read(*this, Large),
m_write(*this, Large),
m_setoffset(*this, Large)
{
#if (TEST_HANDLER)
// test code to verify the read/write handlers are touching the correct bits
@ -911,25 +911,25 @@ public:
// install some dummy RAM for the first 16 bytes with well-known values
u8 buffer[16];
for (int index = 0; index < 16; index++)
buffer[index ^ ((_Endian == ENDIANNESS_NATIVE) ? 0 : (data_width()/8 - 1))] = index * 0x11;
buffer[index ^ ((Endian == ENDIANNESS_NATIVE) ? 0 : (data_width()/8 - 1))] = index * 0x11;
install_ram_generic(0x00, 0x0f, 0x0f, 0, read_or_write::READWRITE, buffer);
printf("\n\naddress_space(%d, %s, %s)\n", NATIVE_BITS, (_Endian == ENDIANNESS_LITTLE) ? "little" : "big", _Large ? "large" : "small");
printf("\n\naddress_space(%d, %s, %s)\n", NATIVE_BITS, (Endian == ENDIANNESS_LITTLE) ? "little" : "big", Large ? "large" : "small");
// walk through the first 8 addresses
for (int address = 0; address < 8; address++)
{
// determine expected values
u64 expected64 = (u64((address + ((_Endian == ENDIANNESS_LITTLE) ? 7 : 0)) * 0x11) << 56) |
(u64((address + ((_Endian == ENDIANNESS_LITTLE) ? 6 : 1)) * 0x11) << 48) |
(u64((address + ((_Endian == ENDIANNESS_LITTLE) ? 5 : 2)) * 0x11) << 40) |
(u64((address + ((_Endian == ENDIANNESS_LITTLE) ? 4 : 3)) * 0x11) << 32) |
(u64((address + ((_Endian == ENDIANNESS_LITTLE) ? 3 : 4)) * 0x11) << 24) |
(u64((address + ((_Endian == ENDIANNESS_LITTLE) ? 2 : 5)) * 0x11) << 16) |
(u64((address + ((_Endian == ENDIANNESS_LITTLE) ? 1 : 6)) * 0x11) << 8) |
(u64((address + ((_Endian == ENDIANNESS_LITTLE) ? 0 : 7)) * 0x11) << 0);
u32 expected32 = (_Endian == ENDIANNESS_LITTLE) ? expected64 : (expected64 >> 32);
u16 expected16 = (_Endian == ENDIANNESS_LITTLE) ? expected32 : (expected32 >> 16);
u8 expected8 = (_Endian == ENDIANNESS_LITTLE) ? expected16 : (expected16 >> 8);
u64 expected64 = (u64((address + ((Endian == ENDIANNESS_LITTLE) ? 7 : 0)) * 0x11) << 56) |
(u64((address + ((Endian == ENDIANNESS_LITTLE) ? 6 : 1)) * 0x11) << 48) |
(u64((address + ((Endian == ENDIANNESS_LITTLE) ? 5 : 2)) * 0x11) << 40) |
(u64((address + ((Endian == ENDIANNESS_LITTLE) ? 4 : 3)) * 0x11) << 32) |
(u64((address + ((Endian == ENDIANNESS_LITTLE) ? 3 : 4)) * 0x11) << 24) |
(u64((address + ((Endian == ENDIANNESS_LITTLE) ? 2 : 5)) * 0x11) << 16) |
(u64((address + ((Endian == ENDIANNESS_LITTLE) ? 1 : 6)) * 0x11) << 8) |
(u64((address + ((Endian == ENDIANNESS_LITTLE) ? 0 : 7)) * 0x11) << 0);
u32 expected32 = (Endian == ENDIANNESS_LITTLE) ? expected64 : (expected64 >> 32);
u16 expected16 = (Endian == ENDIANNESS_LITTLE) ? expected32 : (expected32 >> 16);
u8 expected8 = (Endian == ENDIANNESS_LITTLE) ? expected16 : (expected16 >> 8);
u64 result64;
u32 result32;
@ -1098,11 +1098,11 @@ public:
}
// native read
_NativeType read_native(offs_t offset, _NativeType mask)
NativeType read_native(offs_t offset, NativeType mask)
{
g_profiler.start(PROFILER_MEMREAD);
if (TEST_HANDLER) printf("[r%X,%s]", offset, core_i64_hex_format(mask, sizeof(_NativeType) * 2));
if (TEST_HANDLER) printf("[r%X,%s]", offset, core_i64_hex_format(mask, sizeof(NativeType) * 2));
// look up the handler
offs_t address = offset & m_addrmask;
@ -1111,19 +1111,19 @@ public:
// either read directly from RAM, or call the delegate
offset = offset_to_byte(handler.offset(address));
_NativeType result;
if (entry <= STATIC_BANKMAX) result = *reinterpret_cast<_NativeType *>(handler.ramptr(offset));
else if (sizeof(_NativeType) == 1) result = handler.read8(*this, offset, mask);
else if (sizeof(_NativeType) == 2) result = handler.read16(*this, offset >> 1, mask);
else if (sizeof(_NativeType) == 4) result = handler.read32(*this, offset >> 2, mask);
else if (sizeof(_NativeType) == 8) result = handler.read64(*this, offset >> 3, mask);
NativeType result;
if (entry <= STATIC_BANKMAX) result = *reinterpret_cast<NativeType *>(handler.ramptr(offset));
else if (sizeof(NativeType) == 1) result = handler.read8(*this, offset, mask);
else if (sizeof(NativeType) == 2) result = handler.read16(*this, offset >> 1, mask);
else if (sizeof(NativeType) == 4) result = handler.read32(*this, offset >> 2, mask);
else if (sizeof(NativeType) == 8) result = handler.read64(*this, offset >> 3, mask);
g_profiler.stop();
return result;
}
// mask-less native read
_NativeType read_native(offs_t offset)
NativeType read_native(offs_t offset)
{
g_profiler.start(PROFILER_MEMREAD);
@ -1136,19 +1136,19 @@ public:
// either read directly from RAM, or call the delegate
offset = offset_to_byte(handler.offset(address));
_NativeType result;
if (entry <= STATIC_BANKMAX) result = *reinterpret_cast<_NativeType *>(handler.ramptr(offset));
else if (sizeof(_NativeType) == 1) result = handler.read8(*this, offset, 0xff);
else if (sizeof(_NativeType) == 2) result = handler.read16(*this, offset >> 1, 0xffff);
else if (sizeof(_NativeType) == 4) result = handler.read32(*this, offset >> 2, 0xffffffff);
else if (sizeof(_NativeType) == 8) result = handler.read64(*this, offset >> 3, 0xffffffffffffffffU);
NativeType result;
if (entry <= STATIC_BANKMAX) result = *reinterpret_cast<NativeType *>(handler.ramptr(offset));
else if (sizeof(NativeType) == 1) result = handler.read8(*this, offset, 0xff);
else if (sizeof(NativeType) == 2) result = handler.read16(*this, offset >> 1, 0xffff);
else if (sizeof(NativeType) == 4) result = handler.read32(*this, offset >> 2, 0xffffffff);
else if (sizeof(NativeType) == 8) result = handler.read64(*this, offset >> 3, 0xffffffffffffffffU);
g_profiler.stop();
return result;
}
// native write
void write_native(offs_t offset, _NativeType data, _NativeType mask)
void write_native(offs_t offset, NativeType data, NativeType mask)
{
g_profiler.start(PROFILER_MEMWRITE);
@ -1161,19 +1161,19 @@ public:
offset = offset_to_byte(handler.offset(address));
if (entry <= STATIC_BANKMAX)
{
_NativeType *dest = reinterpret_cast<_NativeType *>(handler.ramptr(offset));
NativeType *dest = reinterpret_cast<NativeType *>(handler.ramptr(offset));
*dest = (*dest & ~mask) | (data & mask);
}
else if (sizeof(_NativeType) == 1) handler.write8(*this, offset, data, mask);
else if (sizeof(_NativeType) == 2) handler.write16(*this, offset >> 1, data, mask);
else if (sizeof(_NativeType) == 4) handler.write32(*this, offset >> 2, data, mask);
else if (sizeof(_NativeType) == 8) handler.write64(*this, offset >> 3, data, mask);
else if (sizeof(NativeType) == 1) handler.write8(*this, offset, data, mask);
else if (sizeof(NativeType) == 2) handler.write16(*this, offset >> 1, data, mask);
else if (sizeof(NativeType) == 4) handler.write32(*this, offset >> 2, data, mask);
else if (sizeof(NativeType) == 8) handler.write64(*this, offset >> 3, data, mask);
g_profiler.stop();
}
// mask-less native write
void write_native(offs_t offset, _NativeType data)
void write_native(offs_t offset, NativeType data)
{
g_profiler.start(PROFILER_MEMWRITE);
@ -1184,34 +1184,34 @@ public:
// either write directly to RAM, or call the delegate
offset = offset_to_byte(handler.offset(address));
if (entry <= STATIC_BANKMAX) *reinterpret_cast<_NativeType *>(handler.ramptr(offset)) = data;
else if (sizeof(_NativeType) == 1) handler.write8(*this, offset, data, 0xff);
else if (sizeof(_NativeType) == 2) handler.write16(*this, offset >> 1, data, 0xffff);
else if (sizeof(_NativeType) == 4) handler.write32(*this, offset >> 2, data, 0xffffffff);
else if (sizeof(_NativeType) == 8) handler.write64(*this, offset >> 3, data, 0xffffffffffffffffU);
if (entry <= STATIC_BANKMAX) *reinterpret_cast<NativeType *>(handler.ramptr(offset)) = data;
else if (sizeof(NativeType) == 1) handler.write8(*this, offset, data, 0xff);
else if (sizeof(NativeType) == 2) handler.write16(*this, offset >> 1, data, 0xffff);
else if (sizeof(NativeType) == 4) handler.write32(*this, offset >> 2, data, 0xffffffff);
else if (sizeof(NativeType) == 8) handler.write64(*this, offset >> 3, data, 0xffffffffffffffffU);
g_profiler.stop();
}
// generic direct read
template<typename _TargetType, bool _Aligned>
_TargetType read_direct(offs_t address, _TargetType mask)
template<typename TargetType, bool Aligned>
TargetType read_direct(offs_t address, TargetType mask)
{
const u32 TARGET_BYTES = sizeof(_TargetType);
const u32 TARGET_BYTES = sizeof(TargetType);
const u32 TARGET_BITS = 8 * TARGET_BYTES;
// equal to native size and aligned; simple pass-through to the native reader
if (NATIVE_BYTES == TARGET_BYTES && (_Aligned || (address & NATIVE_MASK) == 0))
if (NATIVE_BYTES == TARGET_BYTES && (Aligned || (address & NATIVE_MASK) == 0))
return read_native(address & ~NATIVE_MASK, mask);
// if native size is larger, see if we can do a single masked read (guaranteed if we're aligned)
if (NATIVE_BYTES > TARGET_BYTES)
{
u32 offsbits = 8 * (offset_to_byte(address) & (NATIVE_BYTES - (_Aligned ? TARGET_BYTES : 1)));
if (_Aligned || (offsbits + TARGET_BITS <= NATIVE_BITS))
u32 offsbits = 8 * (offset_to_byte(address) & (NATIVE_BYTES - (Aligned ? TARGET_BYTES : 1)));
if (Aligned || (offsbits + TARGET_BITS <= NATIVE_BITS))
{
if (_Endian != ENDIANNESS_LITTLE) offsbits = NATIVE_BITS - TARGET_BITS - offsbits;
return read_native(address & ~NATIVE_MASK, (_NativeType)mask << offsbits) >> offsbits;
if (Endian != ENDIANNESS_LITTLE) offsbits = NATIVE_BITS - TARGET_BITS - offsbits;
return read_native(address & ~NATIVE_MASK, (NativeType)mask << offsbits) >> offsbits;
}
}
@ -1223,11 +1223,11 @@ public:
if (NATIVE_BYTES >= TARGET_BYTES)
{
// little-endian case
if (_Endian == ENDIANNESS_LITTLE)
if (Endian == ENDIANNESS_LITTLE)
{
// read lower bits from lower address
_TargetType result = 0;
_NativeType curmask = (_NativeType)mask << offsbits;
TargetType result = 0;
NativeType curmask = (NativeType)mask << offsbits;
if (curmask != 0) result = read_native(address, curmask) >> offsbits;
// read upper bits from upper address
@ -1242,9 +1242,9 @@ public:
{
// left-justify the mask to the target type
const u32 LEFT_JUSTIFY_TARGET_TO_NATIVE_SHIFT = ((NATIVE_BITS >= TARGET_BITS) ? (NATIVE_BITS - TARGET_BITS) : 0);
_NativeType result = 0;
_NativeType ljmask = (_NativeType)mask << LEFT_JUSTIFY_TARGET_TO_NATIVE_SHIFT;
_NativeType curmask = ljmask >> offsbits;
NativeType result = 0;
NativeType ljmask = (NativeType)mask << LEFT_JUSTIFY_TARGET_TO_NATIVE_SHIFT;
NativeType curmask = ljmask >> offsbits;
// read upper bits from lower address
if (curmask != 0) result = read_native(address, curmask) << offsbits;
@ -1265,13 +1265,13 @@ public:
// compute the maximum number of loops; we do it this way so that there are
// a fixed number of loops for the compiler to unroll if it desires
const u32 MAX_SPLITS_MINUS_ONE = TARGET_BYTES / NATIVE_BYTES - 1;
_TargetType result = 0;
TargetType result = 0;
// little-endian case
if (_Endian == ENDIANNESS_LITTLE)
if (Endian == ENDIANNESS_LITTLE)
{
// read lowest bits from first address
_NativeType curmask = mask << offsbits;
NativeType curmask = mask << offsbits;
if (curmask != 0) result = read_native(address, curmask) >> offsbits;
// read middle bits from subsequent addresses
@ -1280,15 +1280,15 @@ public:
{
address += NATIVE_STEP;
curmask = mask >> offsbits;
if (curmask != 0) result |= (_TargetType)read_native(address, curmask) << offsbits;
if (curmask != 0) result |= (TargetType)read_native(address, curmask) << offsbits;
offsbits += NATIVE_BITS;
}
// if we're not aligned and we still have bits left, read uppermost bits from last address
if (!_Aligned && offsbits < TARGET_BITS)
if (!Aligned && offsbits < TARGET_BITS)
{
curmask = mask >> offsbits;
if (curmask != 0) result |= (_TargetType)read_native(address + NATIVE_STEP, curmask) << offsbits;
if (curmask != 0) result |= (TargetType)read_native(address + NATIVE_STEP, curmask) << offsbits;
}
}
@ -1297,8 +1297,8 @@ public:
{
// read highest bits from first address
offsbits = TARGET_BITS - (NATIVE_BITS - offsbits);
_NativeType curmask = mask >> offsbits;
if (curmask != 0) result = (_TargetType)read_native(address, curmask) << offsbits;
NativeType curmask = mask >> offsbits;
if (curmask != 0) result = (TargetType)read_native(address, curmask) << offsbits;
// read middle bits from subsequent addresses
for (u32 index = 0; index < MAX_SPLITS_MINUS_ONE; index++)
@ -1306,11 +1306,11 @@ public:
offsbits -= NATIVE_BITS;
address += NATIVE_STEP;
curmask = mask >> offsbits;
if (curmask != 0) result |= (_TargetType)read_native(address, curmask) << offsbits;
if (curmask != 0) result |= (TargetType)read_native(address, curmask) << offsbits;
}
// if we're not aligned and we still have bits left, read lowermost bits from the last address
if (!_Aligned && offsbits != 0)
if (!Aligned && offsbits != 0)
{
offsbits = NATIVE_BITS - offsbits;
curmask = mask << offsbits;
@ -1322,24 +1322,24 @@ public:
}
// generic direct write
template<typename _TargetType, bool _Aligned>
void write_direct(offs_t address, _TargetType data, _TargetType mask)
template<typename TargetType, bool Aligned>
void write_direct(offs_t address, TargetType data, TargetType mask)
{
const u32 TARGET_BYTES = sizeof(_TargetType);
const u32 TARGET_BYTES = sizeof(TargetType);
const u32 TARGET_BITS = 8 * TARGET_BYTES;
// equal to native size and aligned; simple pass-through to the native writer
if (NATIVE_BYTES == TARGET_BYTES && (_Aligned || (address & NATIVE_MASK) == 0))
if (NATIVE_BYTES == TARGET_BYTES && (Aligned || (address & NATIVE_MASK) == 0))
return write_native(address & ~NATIVE_MASK, data, mask);
// if native size is larger, see if we can do a single masked write (guaranteed if we're aligned)
if (NATIVE_BYTES > TARGET_BYTES)
{
u32 offsbits = 8 * (offset_to_byte(address) & (NATIVE_BYTES - (_Aligned ? TARGET_BYTES : 1)));
if (_Aligned || (offsbits + TARGET_BITS <= NATIVE_BITS))
u32 offsbits = 8 * (offset_to_byte(address) & (NATIVE_BYTES - (Aligned ? TARGET_BYTES : 1)));
if (Aligned || (offsbits + TARGET_BITS <= NATIVE_BITS))
{
if (_Endian != ENDIANNESS_LITTLE) offsbits = NATIVE_BITS - TARGET_BITS - offsbits;
return write_native(address & ~NATIVE_MASK, (_NativeType)data << offsbits, (_NativeType)mask << offsbits);
if (Endian != ENDIANNESS_LITTLE) offsbits = NATIVE_BITS - TARGET_BITS - offsbits;
return write_native(address & ~NATIVE_MASK, (NativeType)data << offsbits, (NativeType)mask << offsbits);
}
}
@ -1351,11 +1351,11 @@ public:
if (NATIVE_BYTES >= TARGET_BYTES)
{
// little-endian case
if (_Endian == ENDIANNESS_LITTLE)
if (Endian == ENDIANNESS_LITTLE)
{
// write lower bits to lower address
_NativeType curmask = (_NativeType)mask << offsbits;
if (curmask != 0) write_native(address, (_NativeType)data << offsbits, curmask);
NativeType curmask = (NativeType)mask << offsbits;
if (curmask != 0) write_native(address, (NativeType)data << offsbits, curmask);
// write upper bits to upper address
offsbits = NATIVE_BITS - offsbits;
@ -1368,11 +1368,11 @@ public:
{
// left-justify the mask and data to the target type
const u32 LEFT_JUSTIFY_TARGET_TO_NATIVE_SHIFT = ((NATIVE_BITS >= TARGET_BITS) ? (NATIVE_BITS - TARGET_BITS) : 0);
_NativeType ljdata = (_NativeType)data << LEFT_JUSTIFY_TARGET_TO_NATIVE_SHIFT;
_NativeType ljmask = (_NativeType)mask << LEFT_JUSTIFY_TARGET_TO_NATIVE_SHIFT;
NativeType ljdata = (NativeType)data << LEFT_JUSTIFY_TARGET_TO_NATIVE_SHIFT;
NativeType ljmask = (NativeType)mask << LEFT_JUSTIFY_TARGET_TO_NATIVE_SHIFT;
// write upper bits to lower address
_NativeType curmask = ljmask >> offsbits;
NativeType curmask = ljmask >> offsbits;
if (curmask != 0) write_native(address, ljdata >> offsbits, curmask);
// write lower bits to upper address
@ -1390,10 +1390,10 @@ public:
const u32 MAX_SPLITS_MINUS_ONE = TARGET_BYTES / NATIVE_BYTES - 1;
// little-endian case
if (_Endian == ENDIANNESS_LITTLE)
if (Endian == ENDIANNESS_LITTLE)
{
// write lowest bits to first address
_NativeType curmask = mask << offsbits;
NativeType curmask = mask << offsbits;
if (curmask != 0) write_native(address, data << offsbits, curmask);
// write middle bits to subsequent addresses
@ -1407,7 +1407,7 @@ public:
}
// if we're not aligned and we still have bits left, write uppermost bits to last address
if (!_Aligned && offsbits < TARGET_BITS)
if (!Aligned && offsbits < TARGET_BITS)
{
curmask = mask >> offsbits;
if (curmask != 0) write_native(address + NATIVE_STEP, data >> offsbits, curmask);
@ -1419,7 +1419,7 @@ public:
{
// write highest bits to first address
offsbits = TARGET_BITS - (NATIVE_BITS - offsbits);
_NativeType curmask = mask >> offsbits;
NativeType curmask = mask >> offsbits;
if (curmask != 0) write_native(address, data >> offsbits, curmask);
// write middle bits to subsequent addresses
@ -1432,7 +1432,7 @@ public:
}
// if we're not aligned and we still have bits left, write lowermost bits to the last address
if (!_Aligned && offsbits != 0)
if (!Aligned && offsbits != 0)
{
offsbits = NATIVE_BITS - offsbits;
curmask = mask << offsbits;
@ -1452,7 +1452,7 @@ public:
const handler_entry_setoffset &handler = m_setoffset.handler_setoffset(entry);
offs_t offset = handler.offset(address);
handler.setoffset(*this, offset / sizeof(_NativeType));
handler.setoffset(*this, offset / sizeof(NativeType));
}
// virtual access to these functions
@ -1601,7 +1601,7 @@ void memory_manager::allocate(device_memory_interface &memory)
if (spaceconfig)
{
// allocate one of the appropriate type
bool const large(spaceconfig->addr2byte_end(0xffffffffUL >> (32 - spaceconfig->m_addrbus_width)) >= (1 << 18));
bool const large(spaceconfig->addr2byte_end(0xffffffffUL >> (32 - spaceconfig->m_addr_width)) >= (1 << 18));
switch (spaceconfig->data_width())
{
@ -1623,7 +1623,7 @@ void memory_manager::allocate(device_memory_interface &memory)
break;
case 16:
switch (spaceconfig->addrbus_shift())
switch (spaceconfig->addr_shift())
{
case 3:
if (spaceconfig->endianness() == ENDIANNESS_LITTLE)
@ -1679,7 +1679,7 @@ void memory_manager::allocate(device_memory_interface &memory)
break;
case 32:
switch (spaceconfig->addrbus_shift())
switch (spaceconfig->addr_shift())
{
case 0:
if (spaceconfig->endianness() == ENDIANNESS_LITTLE)
@ -1735,7 +1735,7 @@ void memory_manager::allocate(device_memory_interface &memory)
break;
case 64:
switch (spaceconfig->addrbus_shift())
switch (spaceconfig->addr_shift())
{
case 0:
if (spaceconfig->endianness() == ENDIANNESS_LITTLE)
@ -1954,24 +1954,24 @@ void memory_manager::bank_reattach()
address_space::address_space(memory_manager &manager, device_memory_interface &memory, int spacenum, bool large)
: m_config(*memory.space_config(spacenum)),
m_device(memory.device()),
m_addrmask(0xffffffffUL >> (32 - m_config.m_addrbus_width)),
m_addrmask(0xffffffffUL >> (32 - m_config.m_addr_width)),
m_logaddrmask(0xffffffffUL >> (32 - m_config.m_logaddr_width)),
m_unmap(0),
m_spacenum(spacenum),
m_log_unmap(true),
m_name(memory.space_config(spacenum)->name()),
m_addrchars((m_config.m_addrbus_width + 3) / 4),
m_addrchars((m_config.m_addr_width + 3) / 4),
m_logaddrchars((m_config.m_logaddr_width + 3) / 4),
m_manager(manager),
m_machine(memory.device().machine())
{
switch(m_config.addrbus_shift()) {
switch(m_config.addr_shift()) {
case 3: m_direct = static_cast<void *>(new direct_read_data< 3>(*this)); break;
case 0: m_direct = static_cast<void *>(new direct_read_data< 0>(*this)); break;
case -1: m_direct = static_cast<void *>(new direct_read_data<-1>(*this)); break;
case -2: m_direct = static_cast<void *>(new direct_read_data<-2>(*this)); break;
case -3: m_direct = static_cast<void *>(new direct_read_data<-3>(*this)); break;
default: fatalerror("Unsupported address shift %d\n", m_config.addrbus_shift());
default: fatalerror("Unsupported address shift %d\n", m_config.addr_shift());
}
}
@ -1982,7 +1982,7 @@ address_space::address_space(memory_manager &manager, device_memory_interface &m
address_space::~address_space()
{
switch(m_config.addrbus_shift()) {
switch(m_config.addr_shift()) {
case 3: delete static_cast<direct_read_data< 3> *>(m_direct); break;
case 0: delete static_cast<direct_read_data< 0> *>(m_direct); break;
case -1: delete static_cast<direct_read_data<-1> *>(m_direct); break;
@ -2014,7 +2014,7 @@ void address_space::check_optimize_all(const char *function, offs_t addrstart, o
if (addrend & ~m_addrmask)
fatalerror("%s: In range %x-%x mask %x mirror %x select %x, end address is outside of the global address mask %x, did you mean %x ?\n", function, addrstart, addrend, addrmask, addrmirror, addrselect, m_addrmask, addrend & m_addrmask);
offs_t lowbits_mask = (m_config.data_width() >> (3 - m_config.m_addrbus_shift)) - 1;
offs_t lowbits_mask = (m_config.data_width() >> (3 - m_config.m_addr_shift)) - 1;
if (addrstart & lowbits_mask)
fatalerror("%s: In range %x-%x mask %x mirror %x select %x, start address has low bits set, did you mean %x ?\n", function, addrstart, addrend, addrmask, addrmirror, addrselect, addrstart & ~lowbits_mask);
if ((~addrend) & lowbits_mask)
@ -2075,7 +2075,7 @@ void address_space::check_optimize_mirror(const char *function, offs_t addrstart
if (addrend & ~m_addrmask)
fatalerror("%s: In range %x-%x mirror %x, end address is outside of the global address mask %x, did you mean %x ?\n", function, addrstart, addrend, addrmirror, m_addrmask, addrend & m_addrmask);
offs_t lowbits_mask = (m_config.data_width() >> (3 - m_config.m_addrbus_shift)) - 1;
offs_t lowbits_mask = (m_config.data_width() >> (3 - m_config.m_addr_shift)) - 1;
if (addrstart & lowbits_mask)
fatalerror("%s: In range %x-%x mirror %x, start address has low bits set, did you mean %x ?\n", function, addrstart, addrend, addrmirror, addrstart & ~lowbits_mask);
if ((~addrend) & lowbits_mask)
@ -2125,7 +2125,7 @@ void address_space::check_address(const char *function, offs_t addrstart, offs_t
if (addrend & ~m_addrmask)
fatalerror("%s: In range %x-%x, end address is outside of the global address mask %x, did you mean %x ?\n", function, addrstart, addrend, m_addrmask, addrend & m_addrmask);
offs_t lowbits_mask = (m_config.data_width() >> (3 - m_config.m_addrbus_shift)) - 1;
offs_t lowbits_mask = (m_config.data_width() >> (3 - m_config.m_addr_shift)) - 1;
if (addrstart & lowbits_mask)
fatalerror("%s: In range %x-%x, start address has low bits set, did you mean %x ?\n", function, addrstart, addrend, addrstart & ~lowbits_mask);
if ((~addrend) & lowbits_mask)
@ -2509,8 +2509,8 @@ void address_space::dump_map(FILE *file, read_or_write readorwrite)
const address_table &table = (readorwrite == read_or_write::READ) ? static_cast<address_table &>(read()) : static_cast<address_table &>(write());
// dump generic information
fprintf(file, " Address bits = %d\n", m_config.m_addrbus_width);
fprintf(file, " Data bits = %d\n", m_config.m_databus_width);
fprintf(file, " Address bits = %d\n", m_config.m_addr_width);
fprintf(file, " Data bits = %d\n", m_config.m_data_width);
fprintf(file, " Address mask = %X\n", m_addrmask);
fprintf(file, "\n");
@ -3048,7 +3048,7 @@ memory_bank *address_space::bank_find_anonymous(offs_t addrstart, offs_t addrend
void address_space::invalidate_read_caches()
{
switch(m_config.addrbus_shift()) {
switch(m_config.addr_shift()) {
case 3: static_cast<direct_read_data< 3> *>(m_direct)->force_update(); break;
case 0: static_cast<direct_read_data< 0> *>(m_direct)->force_update(); break;
case -1: static_cast<direct_read_data<-1> *>(m_direct)->force_update(); break;
@ -3059,7 +3059,7 @@ void address_space::invalidate_read_caches()
void address_space::invalidate_read_caches(u16 entry)
{
switch(m_config.addrbus_shift()) {
switch(m_config.addr_shift()) {
case 3: static_cast<direct_read_data< 3> *>(m_direct)->force_update(entry); break;
case 0: static_cast<direct_read_data< 0> *>(m_direct)->force_update(entry); break;
case -1: static_cast<direct_read_data<-1> *>(m_direct)->force_update(entry); break;
@ -3070,7 +3070,7 @@ void address_space::invalidate_read_caches(u16 entry)
void address_space::invalidate_read_caches(offs_t start, offs_t end)
{
switch(m_config.addrbus_shift()) {
switch(m_config.addr_shift()) {
case 3: static_cast<direct_read_data< 3> *>(m_direct)->remove_intersecting_ranges(start, end); break;
case 0: static_cast<direct_read_data< 0> *>(m_direct)->remove_intersecting_ranges(start, end); break;
case -1: static_cast<direct_read_data<-1> *>(m_direct)->remove_intersecting_ranges(start, end); break;
@ -4049,7 +4049,7 @@ handler_entry &address_table_write::handler(u32 index) const
// direct_read_data - constructor
//-------------------------------------------------
template<int addr_shift> direct_read_data<addr_shift>::direct_read_data(address_space &space)
template<int AddrShift> direct_read_data<AddrShift>::direct_read_data(address_space &space)
: m_space(space),
m_ptr(nullptr),
m_addrmask(space.addrmask()),
@ -4064,7 +4064,7 @@ template<int addr_shift> direct_read_data<addr_shift>::direct_read_data(address_
// ~direct_read_data - destructor
//-------------------------------------------------
template<int addr_shift> direct_read_data<addr_shift>::~direct_read_data()
template<int AddrShift> direct_read_data<AddrShift>::~direct_read_data()
{
}
@ -4074,7 +4074,7 @@ template<int addr_shift> direct_read_data<addr_shift>::~direct_read_data()
// update the opcode base for the given address
//-------------------------------------------------
template<int addr_shift> bool direct_read_data<addr_shift>::set_direct_region(offs_t address)
template<int AddrShift> bool direct_read_data<AddrShift>::set_direct_region(offs_t address)
{
// find or allocate a matching range
direct_range *range = find_range(address, m_entry);
@ -4095,10 +4095,10 @@ template<int addr_shift> bool direct_read_data<addr_shift>::set_direct_region(of
const handler_entry_read &handler = m_space.read().handler_read(m_entry);
m_addrmask = handler.addrmask();
u32 delta = handler.addrstart() & m_addrmask;
if(addr_shift < 0)
delta = delta << iabs(addr_shift);
else if(addr_shift > 0)
delta = delta >> iabs(addr_shift);
if(AddrShift < 0)
delta = delta << iabs(AddrShift);
else if(AddrShift > 0)
delta = delta >> iabs(AddrShift);
m_ptr = base - delta;
m_addrstart = maskedbits | range->m_addrstart;
@ -4111,7 +4111,7 @@ template<int addr_shift> bool direct_read_data<addr_shift>::set_direct_region(of
// find_range - find a byte address in a range
//-------------------------------------------------
template<int addr_shift> typename direct_read_data<addr_shift>::direct_range *direct_read_data<addr_shift>::find_range(offs_t address, u16 &entry)
template<int AddrShift> typename direct_read_data<AddrShift>::direct_range *direct_read_data<AddrShift>::find_range(offs_t address, u16 &entry)
{
// determine which entry
address &= m_space.m_addrmask;
@ -4136,7 +4136,7 @@ template<int addr_shift> typename direct_read_data<addr_shift>::direct_range *di
// ranges that intersect the given address range
//-------------------------------------------------
template<int addr_shift> void direct_read_data<addr_shift>::remove_intersecting_ranges(offs_t addrstart, offs_t addrend)
template<int AddrShift> void direct_read_data<AddrShift>::remove_intersecting_ranges(offs_t addrstart, offs_t addrend)
{
// loop over all entries
for (auto & elem : m_rangelist)

110
src/emu/emumem.h
View File

@ -114,12 +114,12 @@ typedef device_delegate<void (address_space &, offs_t)> setoffset_delegate;
// ======================> direct_read_data
// direct_read_data contains state data for direct read access
template<int addr_shift> class direct_read_data
template<int AddrShift> class direct_read_data
{
friend class address_table;
public:
using direct_update_delegate = delegate<offs_t (direct_read_data<addr_shift> &, offs_t)>;
using direct_update_delegate = delegate<offs_t (direct_read_data<AddrShift> &, offs_t)>;
// direct_range is an internal class that is part of a list of start/end ranges
class direct_range
@ -162,6 +162,8 @@ public:
void remove_intersecting_ranges(offs_t start, offs_t end);
static inline constexpr offs_t offset_to_byte(offs_t offset) { return AddrShift < 0 ? offset << iabs(AddrShift) : offset >> iabs(AddrShift); }
private:
// internal helpers
bool set_direct_region(offs_t address);
@ -194,27 +196,27 @@ public:
// getters
const char *name() const { return m_name; }
endianness_t endianness() const { return m_endianness; }
int data_width() const { return m_databus_width; }
int addr_width() const { return m_addrbus_width; }
int addrbus_shift() const { return m_addrbus_shift; }
int data_width() const { return m_data_width; }
int addr_width() const { return m_addr_width; }
int addr_shift() const { return m_addr_shift; }
// Actual alignment of the bus addresses
int alignment() const { int bytes = m_databus_width / 8; return m_addrbus_shift < 0 ? bytes >> -m_addrbus_shift : bytes << m_addrbus_shift; }
int alignment() const { int bytes = m_data_width / 8; return m_addr_shift < 0 ? bytes >> -m_addr_shift : bytes << m_addr_shift; }
// Address delta to byte delta helpers
inline offs_t addr2byte(offs_t address) const { return (m_addrbus_shift < 0) ? (address << -m_addrbus_shift) : (address >> m_addrbus_shift); }
inline offs_t byte2addr(offs_t address) const { return (m_addrbus_shift > 0) ? (address << m_addrbus_shift) : (address >> -m_addrbus_shift); }
inline offs_t addr2byte(offs_t address) const { return (m_addr_shift < 0) ? (address << -m_addr_shift) : (address >> m_addr_shift); }
inline offs_t byte2addr(offs_t address) const { return (m_addr_shift > 0) ? (address << m_addr_shift) : (address >> -m_addr_shift); }
// address-to-byte conversion helpers
inline offs_t addr2byte_end(offs_t address) const { return (m_addrbus_shift < 0) ? ((address << -m_addrbus_shift) | ((1 << -m_addrbus_shift) - 1)) : (address >> m_addrbus_shift); }
inline offs_t byte2addr_end(offs_t address) const { return (m_addrbus_shift > 0) ? ((address << m_addrbus_shift) | ((1 << m_addrbus_shift) - 1)) : (address >> -m_addrbus_shift); }
inline offs_t addr2byte_end(offs_t address) const { return (m_addr_shift < 0) ? ((address << -m_addr_shift) | ((1 << -m_addr_shift) - 1)) : (address >> m_addr_shift); }
inline offs_t byte2addr_end(offs_t address) const { return (m_addr_shift > 0) ? ((address << m_addr_shift) | ((1 << m_addr_shift) - 1)) : (address >> -m_addr_shift); }
// state
const char * m_name;
endianness_t m_endianness;
u8 m_databus_width;
u8 m_addrbus_width;
s8 m_addrbus_shift;
u8 m_data_width;
u8 m_addr_width;
s8 m_addr_shift;
u8 m_logaddr_width;
u8 m_page_shift;
bool m_is_octal; // to determine if messages/debugger will show octal or hex
@ -256,18 +258,18 @@ public:
int spacenum() const { return m_spacenum; }
address_map *map() const { return m_map.get(); }
template<int addr_shift> direct_read_data<addr_shift> *direct() const {
static_assert(addr_shift == 3 || addr_shift == 0 || addr_shift == -1 || addr_shift == -2 || addr_shift == -3, "Unsupported addr_shift in direct()");
if(addr_shift != m_config.addrbus_shift())
fatalerror("Requesing direct() with address shift %d while the config says %d\n", addr_shift, m_config.addrbus_shift());
return static_cast<direct_read_data<addr_shift> *>(m_direct);
template<int AddrShift> direct_read_data<AddrShift> *direct() const {
static_assert(AddrShift == 3 || AddrShift == 0 || AddrShift == -1 || AddrShift == -2 || AddrShift == -3, "Unsupported AddrShift in direct()");
if(AddrShift != m_config.addr_shift())
fatalerror("Requesing direct() with address shift %d while the config says %d\n", AddrShift, m_config.addr_shift());
return static_cast<direct_read_data<AddrShift> *>(m_direct);
}
int data_width() const { return m_config.data_width(); }
int addr_width() const { return m_config.addr_width(); }
int alignment() const { return m_config.alignment(); }
endianness_t endianness() const { return m_config.endianness(); }
int addrbus_shift() const { return m_config.addrbus_shift(); }
int addr_shift() const { return m_config.addr_shift(); }
u64 unmap() const { return m_unmap; }
bool is_octal() const { return m_config.m_is_octal; }
@ -819,16 +821,10 @@ private:
// backing that address
//-------------------------------------------------
template<int addr_shift> inline void *direct_read_data<addr_shift>::read_ptr(offs_t address, offs_t directxor)
template<int AddrShift> inline void *direct_read_data<AddrShift>::read_ptr(offs_t address, offs_t directxor)
{
if (address_is_valid(address)) {
if(addr_shift < 0)
return &m_ptr[((address ^ directxor) & m_addrmask) << iabs(addr_shift)];
else if(addr_shift == 0)
return &m_ptr[(address ^ directxor) & m_addrmask];
else
return &m_ptr[((address ^ directxor) & m_addrmask) >> iabs(addr_shift)];
}
if (address_is_valid(address))
return &m_ptr[offset_to_byte(((address ^ directxor) & m_addrmask))];
return nullptr;
}
@ -838,16 +834,12 @@ template<int addr_shift> inline void *direct_read_data<addr_shift>::read_ptr(off
// direct_read_data class
//-------------------------------------------------
template<int addr_shift> inline u8 direct_read_data<addr_shift>::read_byte(offs_t address, offs_t directxor)
template<int AddrShift> inline u8 direct_read_data<AddrShift>::read_byte(offs_t address, offs_t directxor)
{
if(addr_shift <= -1)
fatalerror("Can't direct_read_data::read_byte on a memory space with address shift %d", addr_shift);
if (address_is_valid(address)) {
if(addr_shift == 0)
return m_ptr[(address ^ directxor) & m_addrmask];
else
return m_ptr[((address ^ directxor) & m_addrmask) >> iabs(addr_shift)];
}
if(AddrShift <= -1)
fatalerror("Can't direct_read_data::read_byte on a memory space with address shift %d", AddrShift);
if (address_is_valid(address))
return m_ptr[offset_to_byte((address ^ directxor) & m_addrmask)];
return m_space.read_byte(address);
}
@ -857,18 +849,12 @@ template<int addr_shift> inline u8 direct_read_data<addr_shift>::read_byte(offs_
// direct_read_data class
//-------------------------------------------------
template<int addr_shift> inline u16 direct_read_data<addr_shift>::read_word(offs_t address, offs_t directxor)
template<int AddrShift> inline u16 direct_read_data<AddrShift>::read_word(offs_t address, offs_t directxor)
{
if(addr_shift <= -2)
fatalerror("Can't direct_read_data::read_word on a memory space with address shift %d", addr_shift);
if (address_is_valid(address)) {
if(addr_shift < 0)
return *reinterpret_cast<u16 *>(&m_ptr[((address ^ directxor) & m_addrmask) << iabs(addr_shift)]);
else if(addr_shift == 0)
return *reinterpret_cast<u16 *>(&m_ptr[(address ^ directxor) & m_addrmask]);
else
return *reinterpret_cast<u16 *>(&m_ptr[((address ^ directxor) & m_addrmask) >> iabs(addr_shift)]);
}
if(AddrShift <= -2)
fatalerror("Can't direct_read_data::read_word on a memory space with address shift %d", AddrShift);
if (address_is_valid(address))
return *reinterpret_cast<u16 *>(&m_ptr[offset_to_byte((address ^ directxor) & m_addrmask)]);
return m_space.read_word(address);
}
@ -878,18 +864,12 @@ template<int addr_shift> inline u16 direct_read_data<addr_shift>::read_word(offs
// direct_read_data class
//-------------------------------------------------
template<int addr_shift> inline u32 direct_read_data<addr_shift>::read_dword(offs_t address, offs_t directxor)
template<int AddrShift> inline u32 direct_read_data<AddrShift>::read_dword(offs_t address, offs_t directxor)
{
if(addr_shift <= -3)
fatalerror("Can't direct_read_data::read_dword on a memory space with address shift %d", addr_shift);
if (address_is_valid(address)) {
if(addr_shift < 0)
return *reinterpret_cast<u32 *>(&m_ptr[((address ^ directxor) & m_addrmask) << iabs(addr_shift)]);
else if(addr_shift == 0)
return *reinterpret_cast<u32 *>(&m_ptr[(address ^ directxor) & m_addrmask]);
else
return *reinterpret_cast<u32 *>(&m_ptr[((address ^ directxor) & m_addrmask) >> iabs(addr_shift)]);
}
if(AddrShift <= -3)
fatalerror("Can't direct_read_data::read_dword on a memory space with address shift %d", AddrShift);
if (address_is_valid(address))
return *reinterpret_cast<u32 *>(&m_ptr[offset_to_byte((address ^ directxor) & m_addrmask)]);
return m_space.read_dword(address);
}
@ -899,16 +879,10 @@ template<int addr_shift> inline u32 direct_read_data<addr_shift>::read_dword(off
// direct_read_data class
//-------------------------------------------------
template<int addr_shift> inline u64 direct_read_data<addr_shift>::read_qword(offs_t address, offs_t directxor)
template<int AddrShift> inline u64 direct_read_data<AddrShift>::read_qword(offs_t address, offs_t directxor)
{
if (address_is_valid(address)) {
if(addr_shift < 0)
return *reinterpret_cast<u64 *>(&m_ptr[((address ^ directxor) & m_addrmask) << iabs(addr_shift)]);
else if(addr_shift == 0)
return *reinterpret_cast<u64 *>(&m_ptr[(address ^ directxor) & m_addrmask]);
else
return *reinterpret_cast<u64 *>(&m_ptr[((address ^ directxor) & m_addrmask) >> iabs(addr_shift)]);
}
if (address_is_valid(address))
return *reinterpret_cast<u64 *>(&m_ptr[offset_to_byte((address ^ directxor) & m_addrmask)]);
return m_space.read_qword(address);
}

2
src/emu/romload.cpp
View File

@ -1275,7 +1275,7 @@ void rom_load_manager::normalize_flags_for_device(running_machine &machine, cons
endian = ENDIANNESS_BIG;
/* set the width */
buswidth = spaceconfig->m_databus_width;
buswidth = spaceconfig->m_data_width;
if (buswidth <= 8)
width = 1;
else if (buswidth <= 16)

8
src/mame/audio/dcs.cpp
View File

@ -2628,8 +2628,8 @@ MACHINE_CONFIG_MEMBER( dcs2_audio_dsio_device::device_add_mconfig )
MCFG_DEVICE_ADD("data_map_bank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(dsio_rambank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(14)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(14)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
MCFG_TIMER_DEVICE_ADD("dcs_reg_timer", DEVICE_SELF, dcs_audio_device, dcs_irq)
@ -2669,8 +2669,8 @@ MACHINE_CONFIG_MEMBER( dcs2_audio_denver_device::device_add_mconfig )
MCFG_DEVICE_ADD("data_map_bank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(denver_rambank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(14)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(14)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
MCFG_TIMER_DEVICE_ADD("dcs_reg_timer", DEVICE_SELF, dcs_audio_device, dcs_irq)

4
src/mame/drivers/a7150.cpp
View File

@ -471,8 +471,8 @@ static MACHINE_CONFIG_START( a7150 )
MCFG_DEVICE_ADD("video_bankdev", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(k7070_cpu_banked)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(18)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(18)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x10000)
MCFG_DEVICE_ADD(Z80CTC_TAG, Z80CTC, XTAL_16MHz/3)

2
src/mame/drivers/agat.cpp
View File

@ -1026,7 +1026,7 @@ static MACHINE_CONFIG_START( agat7 )
MCFG_DEVICE_ADD(A7_UPPERBANK_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(inhbank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x3000)
/* keyboard controller -- XXX must be replaced */

4
src/mame/drivers/alg.cpp
View File

@ -298,8 +298,8 @@ static MACHINE_CONFIG_START( alg_r1 )
MCFG_DEVICE_ADD("overlay", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(overlay_512kb_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x200000)
MCFG_NVRAM_ADD_0FILL("nvram")

4
src/mame/drivers/aliens.cpp
View File

@ -204,8 +204,8 @@ static MACHINE_CONFIG_START( aliens )
MCFG_DEVICE_ADD("bank0000", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank0000_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(11)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(11)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x400)
MCFG_WATCHDOG_ADD("watchdog")

4
src/mame/drivers/alphatpx.cpp
View File

@ -523,8 +523,8 @@ static MACHINE_CONFIG_START( alphatp3 )
MCFG_DEVICE_ADD("bankdev", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(alphatp3_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(18)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(18)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x10000)
// video hardware

6
src/mame/drivers/alphatro.cpp
View File

@ -759,21 +759,21 @@ static MACHINE_CONFIG_START( alphatro )
MCFG_DEVICE_ADD("lowbank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(rombank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x6000)
/* A000 banking */
MCFG_DEVICE_ADD("cartbank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(cartbank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
/* F000 banking */
MCFG_DEVICE_ADD("monbank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(monbank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000)
MACHINE_CONFIG_END

2
src/mame/drivers/altos8600.cpp
View File

@ -691,7 +691,7 @@ static MACHINE_CONFIG_START(altos8600)
MCFG_CPU_ADD("dmac", I8089, XTAL_5MHz)
MCFG_CPU_PROGRAM_MAP(dmac_mem)
MCFG_CPU_IO_MAP(dmac_io)
MCFG_I8089_DATABUS_WIDTH(16)
MCFG_I8089_DATA_WIDTH(16)
MCFG_I8089_SINTR1(WRITELINE(altos8600_state, sintr1_w))
MCFG_I8089_SINTR2(DEVWRITELINE("pic8259_2", pic8259_device, ir4_w))

44
src/mame/drivers/amiga.cpp
View File

@ -1393,15 +1393,15 @@ static MACHINE_CONFIG_DERIVED( a1000, amiga_base )
MCFG_DEVICE_ADD("overlay", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(a1000_overlay_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x200000)
MCFG_DEVICE_ADD("bootrom", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(a1000_bootrom_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(19)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(19)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x40000)
MCFG_SOFTWARE_LIST_ADD("a1000_list", "amiga_a1000")
@ -1430,8 +1430,8 @@ static MACHINE_CONFIG_DERIVED( a2000, amiga_base )
MCFG_DEVICE_ADD("overlay", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(overlay_512kb_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x200000)
// real-time clock
@ -1475,8 +1475,8 @@ static MACHINE_CONFIG_DERIVED( a500, amiga_base )
//MCFG_DEVICE_PROGRAM_MAP(overlay_512kb_map)
MCFG_DEVICE_PROGRAM_MAP(overlay_1mb_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x200000)
// cpu slot
@ -1519,8 +1519,8 @@ static MACHINE_CONFIG_DERIVED( cdtv, amiga_base )
MCFG_DEVICE_ADD("overlay", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(overlay_1mb_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x200000)
// standard sram
@ -1582,8 +1582,8 @@ static MACHINE_CONFIG_DERIVED( a3000, amiga_base )
MCFG_DEVICE_ADD("overlay", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(overlay_1mb_map32)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x200000)
// real-time clock
@ -1615,8 +1615,8 @@ static MACHINE_CONFIG_DERIVED( a500p, amiga_base )
MCFG_DEVICE_ADD("overlay", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(overlay_1mb_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x200000)
// real-time clock
@ -1652,8 +1652,8 @@ static MACHINE_CONFIG_DERIVED( a600, amiga_base )
MCFG_DEVICE_ADD("overlay", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(overlay_2mb_map16)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x200000)
MCFG_GAYLE_ADD("gayle", amiga_state::CLK_28M_PAL / 2, a600_state::GAYLE_ID)
@ -1697,8 +1697,8 @@ static MACHINE_CONFIG_DERIVED( a1200, amiga_base )
MCFG_DEVICE_ADD("overlay", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(overlay_2mb_map32)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x200000)
MCFG_DEVICE_MODIFY("screen")
@ -1760,8 +1760,8 @@ static MACHINE_CONFIG_DERIVED( a4000, amiga_base )
MCFG_DEVICE_ADD("overlay", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(overlay_2mb_map32)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x200000)
MCFG_DEVICE_MODIFY("screen")
@ -1835,8 +1835,8 @@ static MACHINE_CONFIG_DERIVED( cd32, amiga_base )
MCFG_DEVICE_ADD("overlay", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(overlay_2mb_map32)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x200000)
MCFG_I2CMEM_ADD("i2cmem")

2
src/mame/drivers/apple2.cpp
View File

@ -1379,7 +1379,7 @@ static MACHINE_CONFIG_START( apple2_common )
MCFG_DEVICE_ADD(A2_UPPERBANK_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(inhbank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x3000)
/* soft switches */

24
src/mame/drivers/apple2e.cpp
View File

@ -3868,84 +3868,84 @@ static MACHINE_CONFIG_START( apple2e )
MCFG_DEVICE_ADD(A2_0000_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(r0000bank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x200)
/* 0200 banking */
MCFG_DEVICE_ADD(A2_0200_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(r0200bank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x200)
/* 0400 banking */
MCFG_DEVICE_ADD(A2_0400_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(r0400bank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x400)
/* 0800 banking */
MCFG_DEVICE_ADD(A2_0800_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(r0800bank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
/* 2000 banking */
MCFG_DEVICE_ADD(A2_2000_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(r2000bank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
/* 4000 banking */
MCFG_DEVICE_ADD(A2_4000_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(r4000bank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x8000)
/* C100 banking */
MCFG_DEVICE_ADD(A2_C100_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(c100bank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x200)
/* C300 banking */
MCFG_DEVICE_ADD(A2_C300_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(c300bank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x100)
/* C400 banking */
MCFG_DEVICE_ADD(A2_C400_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(c400bank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x400)
/* C800 banking */
MCFG_DEVICE_ADD(A2_C800_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(c800bank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x800)
/* built-in language card emulation */
MCFG_DEVICE_ADD(A2_LCBANK_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(lcbank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x3000)
/* /INH banking */
MCFG_DEVICE_ADD(A2_UPPERBANK_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(inhbank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x3000)
/* keyboard controller */

2
src/mame/drivers/apricot.cpp
View File

@ -360,7 +360,7 @@ static MACHINE_CONFIG_START( apricot )
MCFG_CPU_ADD("ic71", I8089, XTAL_15MHz / 3)
MCFG_CPU_PROGRAM_MAP(apricot_mem)
MCFG_CPU_IO_MAP(apricot_io)
MCFG_I8089_DATABUS_WIDTH(16)
MCFG_I8089_DATA_WIDTH(16)
MCFG_I8089_SINTR1(DEVWRITELINE("ic31", pic8259_device, ir0_w))
MCFG_I8089_SINTR2(DEVWRITELINE("ic31", pic8259_device, ir1_w))

4
src/mame/drivers/arsystems.cpp
View File

@ -297,8 +297,8 @@ static MACHINE_CONFIG_START( arcadia )
MCFG_DEVICE_ADD("overlay", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(overlay_512kb_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x200000)
MCFG_NVRAM_ADD_0FILL("nvram")

6
src/mame/drivers/astrocde.cpp
View File

@ -1270,8 +1270,8 @@ static MACHINE_CONFIG_DERIVED( astrocade_16color_base, astrocade_base )
MCFG_DEVICE_ADD("bank4000", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank4000_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
MCFG_NVRAM_ADD_0FILL("nvram")
@ -1432,7 +1432,7 @@ static MACHINE_CONFIG_DERIVED( profpac, astrocade_16color_base )
MCFG_DEVICE_MODIFY("bank4000")
MCFG_DEVICE_PROGRAM_MAP(profpac_bank4000_map)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(20)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(20)
MACHINE_CONFIG_END

4
src/mame/drivers/avigo.cpp
View File

@ -802,13 +802,13 @@ static MACHINE_CONFIG_START( avigo )
MCFG_DEVICE_ADD("bank0", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(avigo_banked_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
MCFG_DEVICE_ADD("bank1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(avigo_banked_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
MCFG_NVRAM_ADD_CUSTOM_DRIVER("nvram", avigo_state, nvram_init)

4
src/mame/drivers/beezer.cpp
View File

@ -467,8 +467,8 @@ static MACHINE_CONFIG_START( beezer )
MCFG_DEVICE_ADD("sysbank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(banked_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(15)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(15)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000)
MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", beezer_state, scanline_cb, "screen", 0, 1)

4
src/mame/drivers/blockhl.cpp
View File

@ -279,8 +279,8 @@ static MACHINE_CONFIG_START( blockhl )
MCFG_DEVICE_ADD("bank5800", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank5800_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(12)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(12)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x0800)
MCFG_CPU_ADD("audiocpu", Z80, XTAL_3_579545MHz)

4
src/mame/drivers/bwing.cpp
View File

@ -377,8 +377,8 @@ static MACHINE_CONFIG_START( bwing )
MCFG_DEVICE_ADD("vrambank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(15)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(15)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
// video hardware

12
src/mame/drivers/cedar_magnet.cpp
View File

@ -765,22 +765,22 @@ static MACHINE_CONFIG_START( cedar_magnet )
MCFG_DEVICE_ADD("bank0", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(cedar_bank0)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(18)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(18)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x10000)
MCFG_DEVICE_ADD("mb_sub_ram", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(cedar_magnet_mainboard_sub_ram_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(18)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(18)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x10000)
MCFG_DEVICE_ADD("mb_sub_pal", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(cedar_magnet_mainboard_sub_pal_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(8+6)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(8+6)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x100)
MCFG_DEVICE_ADD("z80pio_ic48", Z80PIO, 4000000/2)

4
src/mame/drivers/chqflag.cpp
View File

@ -332,8 +332,8 @@ static MACHINE_CONFIG_START( chqflag )
MCFG_DEVICE_ADD("bank1000", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank1000_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(13)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(13)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000)
MCFG_QUANTUM_TIME(attotime::from_hz(600))

8
src/mame/drivers/clcd.cpp
View File

@ -771,25 +771,25 @@ static MACHINE_CONFIG_START(clcd)
MCFG_DEVICE_ADD("bank1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(clcd_banked_mem)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x400)
MCFG_DEVICE_ADD("bank2", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(clcd_banked_mem)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x400)
MCFG_DEVICE_ADD("bank3", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(clcd_banked_mem)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x400)
MCFG_DEVICE_ADD("bank4", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(clcd_banked_mem)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x400)
MCFG_DEVICE_ADD("rtc", MSM58321, XTAL_32_768kHz)

4
src/mame/drivers/coco12.cpp
View File

@ -407,8 +407,8 @@ MACHINE_CONFIG_START( coco_floating )
MCFG_DEVICE_ADD(FLOATING_TAG, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(coco_floating_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(16)
MACHINE_CONFIG_END

4
src/mame/drivers/crgolf.cpp
View File

@ -536,8 +536,8 @@ static MACHINE_CONFIG_START( crgolf )
MCFG_DEVICE_ADD("vrambank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vrambank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x8000) /* technically 0x6000, but powers of 2 makes the memory map / address masking cleaner. */
MCFG_PALETTE_ADD("palette", 0x20)

4
src/mame/drivers/crimfght.cpp
View File

@ -311,8 +311,8 @@ static MACHINE_CONFIG_START( crimfght )
MCFG_DEVICE_ADD("bank0000", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank0000_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(11)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(11)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x400)
MCFG_WATCHDOG_ADD("watchdog")

4
src/mame/drivers/cubo.cpp
View File

@ -1033,8 +1033,8 @@ static MACHINE_CONFIG_START( cubo )
MCFG_DEVICE_ADD("overlay", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(overlay_2mb_map32)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x200000)
MCFG_I2CMEM_ADD("i2cmem")

4
src/mame/drivers/cultures.cpp
View File

@ -405,8 +405,8 @@ static MACHINE_CONFIG_START( cultures )
MCFG_DEVICE_ADD("vrambank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vrambank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(15)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(15)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)

4
src/mame/drivers/ddenlovr.cpp
View File

@ -4273,8 +4273,8 @@ static MACHINE_CONFIG_START( htengoku )
MCFG_DEVICE_ADD("bankdev", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(htengoku_banked_map)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(20)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(20)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x8000)
MCFG_MACHINE_START_OVERRIDE(ddenlovr_state,dynax)

8
src/mame/drivers/dec0.cpp
View File

@ -1969,15 +1969,15 @@ static MACHINE_CONFIG_DERIVED( slyspy, dec1 )
MCFG_DEVICE_ADD("pfprotect", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(slyspy_protection_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(18)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(18)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x10000)
MCFG_DEVICE_ADD("sndprotect", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(slyspy_sound_protection_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(21)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(21)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000)

4
src/mame/drivers/discoboy.cpp
View File

@ -457,8 +457,8 @@ static MACHINE_CONFIG_START( discoboy )
MCFG_DEVICE_ADD("rambank1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(rambank1_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(13)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(13)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x800)
/* video hardware */

18
src/mame/drivers/dynax.cpp
View File

@ -4300,8 +4300,8 @@ static MACHINE_CONFIG_START( hnoridur )
MCFG_DEVICE_ADD("bankdev", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(hnoridur_banked_map)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(20)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(20)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x8000)
MCFG_NVRAM_ADD_0FILL("nvram")
@ -4363,8 +4363,8 @@ static MACHINE_CONFIG_START( hjingi )
MCFG_DEVICE_ADD("bankdev", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(hjingi_banked_map)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(20)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(20)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x8000)
MCFG_NVRAM_ADD_0FILL("nvram")
@ -4569,7 +4569,7 @@ MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( mjangels, yarunara )
MCFG_DEVICE_MODIFY("bankdev")
MCFG_DEVICE_PROGRAM_MAP(mjangels_banked_map)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(21)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(21)
MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( quiztvqq, mjangels )
@ -4805,8 +4805,8 @@ static MACHINE_CONFIG_START( tenkai )
MCFG_DEVICE_ADD("bankdev", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(tenkai_banked_map)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(20)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(20)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x8000)
MCFG_MACHINE_START_OVERRIDE(dynax_state,dynax)
@ -4877,8 +4877,8 @@ static MACHINE_CONFIG_START( gekisha )
MCFG_DEVICE_ADD("bankdev", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(gekisha_banked_map)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(17)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(17)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x8000)
MCFG_MACHINE_START_OVERRIDE(dynax_state,dynax)

4
src/mame/drivers/elwro800.cpp
View File

@ -620,12 +620,12 @@ static MACHINE_CONFIG_START( elwro800 )
MCFG_DEVICE_ADD("bank1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(elwro800_bank1)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
MCFG_DEVICE_ADD("bank2", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(elwro800_bank2)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
MACHINE_CONFIG_END

4
src/mame/drivers/fidel6502.cpp
View File

@ -1708,8 +1708,8 @@ static MACHINE_CONFIG_START( sc12 )
MCFG_DEVICE_ADD("sc12_map", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(sc12_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(16)
MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", fidelbase_state, display_decay_tick, attotime::from_msec(1))
MCFG_DEFAULT_LAYOUT(layout_fidel_sc12)

2
src/mame/drivers/fm7.cpp
View File

@ -2051,7 +2051,7 @@ SLOT_INTERFACE_END
MCFG_DEVICE_ADD(tag, ADDRESS_MAP_BANK, 0) \
MCFG_DEVICE_PROGRAM_MAP(fm7_banked_mem) \
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE) \
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8) \
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8) \
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000)

4
src/mame/drivers/funkball.cpp
View File

@ -782,8 +782,8 @@ static MACHINE_CONFIG_START( funkball )
MCFG_DEVICE_ADD("flashbank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(flashbank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x10000)
/* video hardware */

2
src/mame/drivers/gimix.cpp
View File

@ -542,7 +542,7 @@ SLOT_INTERFACE_END
MCFG_DEVICE_ADD(tag, ADDRESS_MAP_BANK, 0) \
MCFG_DEVICE_PROGRAM_MAP(gimix_banked_mem) \
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE) \
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8) \
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8) \
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000)
static MACHINE_CONFIG_START( gimix )

4
src/mame/drivers/goldnpkr.cpp
View File

@ -4656,8 +4656,8 @@ static MACHINE_CONFIG_START( megadpkr )
MCFG_DEVICE_ADD("bankdev", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(megadpkr_banked_map)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
MCFG_CPU_ADD("mcu", M68705P5, CPU_CLOCK) /* unknown */

4
src/mame/drivers/hp80.cpp
View File

@ -1331,8 +1331,8 @@ static MACHINE_CONFIG_START(hp85)
MCFG_DEVICE_ADD("rombank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(rombank_mem_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(21)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(21)
MCFG_ADDRESS_MAP_BANK_STRIDE(HP80_OPTROM_SIZE)
MCFG_SCREEN_ADD("screen" , RASTER)

4
src/mame/drivers/hp_ipc.cpp
View File

@ -716,8 +716,8 @@ static MACHINE_CONFIG_START(hp_ipc)
MCFG_DEVICE_ADD("bankdev", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(hp_ipc_mem_inner)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(25)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(25)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000000)
// horizontal time = 60 us (min)

6
src/mame/drivers/hunter2.cpp
View File

@ -413,19 +413,19 @@ static MACHINE_CONFIG_START( hunter2 )
MCFG_DEVICE_ADD("bank1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(hunter2_banked_mem)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
MCFG_DEVICE_ADD("bank2", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(hunter2_banked_mem)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
MCFG_DEVICE_ADD("bank3", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(hunter2_banked_mem)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
MACHINE_CONFIG_END

8
src/mame/drivers/intellec4.cpp
View File

@ -311,15 +311,15 @@ MACHINE_CONFIG_START(intellec4)
MCFG_DEVICE_ADD("prgbank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(intellec4_program_banks)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(14)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(14)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000)
MCFG_DEVICE_ADD("rpbank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(intellec4_rom_port_banks)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(14)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(14)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000)
MCFG_DEVICE_ADD("promprg", INTEL_IMM6_76, 0)

4
src/mame/drivers/itt3030.cpp
View File

@ -688,8 +688,8 @@ static MACHINE_CONFIG_START( itt3030 )
MCFG_DEVICE_ADD("lowerbank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(lower48_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(20)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(20)
MCFG_ADDRESS_MAP_BANK_STRIDE(0xc000)
MCFG_DEVICE_ADD("crt5027", CRT5027, XTAL_6MHz)

2
src/mame/drivers/ksys573.cpp
View File

@ -2040,7 +2040,7 @@ static MACHINE_CONFIG_START( konami573 )
MCFG_DEVICE_ADD( "flashbank", ADDRESS_MAP_BANK, 0 )
MCFG_DEVICE_PROGRAM_MAP( flashbank_map )
MCFG_ADDRESS_MAP_BANK_ENDIANNESS( ENDIANNESS_LITTLE )
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH( 16 )
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH( 16 )
MCFG_ADDRESS_MAP_BANK_STRIDE( 0x400000 )
/* video hardware */

8
src/mame/drivers/laser3k.cpp
View File

@ -980,22 +980,22 @@ static MACHINE_CONFIG_START( laser3k )
MCFG_DEVICE_ADD("bank0", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(banks_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
MCFG_DEVICE_ADD("bank1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(banks_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
MCFG_DEVICE_ADD("bank2", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(banks_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
MCFG_DEVICE_ADD("bank3", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(banks_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
MCFG_RAM_ADD("mainram")

4
src/mame/drivers/lethal.cpp
View File

@ -499,8 +499,8 @@ static MACHINE_CONFIG_START( lethalen )
MCFG_DEVICE_ADD("bank4000", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank4000_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
MCFG_EEPROM_SERIAL_ER5911_8BIT_ADD("eeprom")

8
src/mame/drivers/majorpkr.cpp
View File

@ -995,15 +995,15 @@ static MACHINE_CONFIG_START( majorpkr )
MCFG_DEVICE_ADD("palette_bank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(palettebanks)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(13)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(13)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x0800)
MCFG_DEVICE_ADD("vram_bank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vrambanks)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(13)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(13)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x0800)
MCFG_NVRAM_ADD_0FILL("nvram")

2
src/mame/drivers/miniframe.cpp
View File

@ -230,7 +230,7 @@ static MACHINE_CONFIG_START( miniframe )
MCFG_DEVICE_ADD("ramrombank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(ramrombank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x400000)
// floppy

4
src/mame/drivers/mquake.cpp
View File

@ -311,8 +311,8 @@ static MACHINE_CONFIG_START( mquake )
MCFG_DEVICE_ADD("overlay", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(overlay_512kb_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(22)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x200000)
MCFG_NVRAM_ADD_0FILL("nvram")

4
src/mame/drivers/mstation.cpp
View File

@ -470,13 +470,13 @@ static MACHINE_CONFIG_START( mstation )
MCFG_DEVICE_ADD("bank0", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(mstation_banked_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
MCFG_DEVICE_ADD("bank1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(mstation_banked_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
/* internal ram */

2
src/mame/drivers/mtouchxl.cpp
View File

@ -242,7 +242,7 @@ static MACHINE_CONFIG_START( at486 )
MCFG_DEVICE_ADD("dbank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(dbank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x10000)
/* Flash ROM */

8
src/mame/drivers/mz700.cpp
View File

@ -376,8 +376,8 @@ static MACHINE_CONFIG_START( mz700 )
MCFG_DEVICE_ADD("banke", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(mz700_banke)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
MCFG_MACHINE_RESET_OVERRIDE(mz_state, mz700)
@ -442,8 +442,8 @@ static MACHINE_CONFIG_DERIVED( mz800, mz700 )
MCFG_DEVICE_ADD("bankf", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(mz800_bankf)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
MCFG_MACHINE_RESET_OVERRIDE(mz_state, mz800)

4
src/mame/drivers/nds.cpp
View File

@ -978,13 +978,13 @@ static MACHINE_CONFIG_START( nds )
MCFG_DEVICE_ADD("nds7wram", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(nds7_wram_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x8000)
MCFG_DEVICE_ADD("nds9wram", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(nds9_wram_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x8000)
MACHINE_CONFIG_END

4
src/mame/drivers/nes_vt.cpp
View File

@ -840,8 +840,8 @@ static MACHINE_CONFIG_START( nes_vt )
MCFG_DEVICE_ADD("prg", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(prg_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(15)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(15)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x8000)
MCFG_NES_CONTROL_PORT_ADD("ctrl1", nes_control_port1_devices, "joypad")

2
src/mame/drivers/octopus.cpp
View File

@ -1002,7 +1002,7 @@ static MACHINE_CONFIG_START( octopus )
MCFG_DEVICE_ADD("z80_bank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(octopus_mem)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x10000)
MCFG_RAM_ADD("ram")

8
src/mame/drivers/parodius.cpp
View File

@ -238,15 +238,15 @@ static MACHINE_CONFIG_START( parodius )
MCFG_DEVICE_ADD("bank0000", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank0000_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(13)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(13)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x0800)
MCFG_DEVICE_ADD("bank2000", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank2000_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(12)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(12)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x0800)
MCFG_WATCHDOG_ADD("watchdog")

2
src/mame/drivers/pasogo.cpp
View File

@ -544,7 +544,7 @@ static MACHINE_CONFIG_START( pasogo )
MCFG_DEVICE_ADD("ems", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(emsbank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
MCFG_IBM5160_MOTHERBOARD_ADD("mb", "maincpu")

4
src/mame/drivers/pc9801.cpp
View File

@ -2396,8 +2396,8 @@ static MACHINE_CONFIG_START( pc9801rs )
MCFG_DEVICE_ADD("ipl_bank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(ipl_bank)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(18)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(18)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x18000)
MCFG_MACHINE_START_OVERRIDE(pc9801_state,pc9801rs)

4
src/mame/drivers/pcxt.cpp
View File

@ -496,8 +496,8 @@ static MACHINE_CONFIG_START( filetto )
MCFG_DEVICE_ADD("bank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(18)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(18)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x10000)
MACHINE_CONFIG_END

16
src/mame/drivers/pengadvb.cpp
View File

@ -214,29 +214,29 @@ static MACHINE_CONFIG_START( pengadvb )
MCFG_DEVICE_ADD("page0", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank_mem)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(18)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(18)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x10000)
MCFG_DEVICE_ADD("page1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank_mem)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(18)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(18)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x10000)
MCFG_DEVICE_ADD("page2", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank_mem)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(18)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(18)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x10000)
MCFG_DEVICE_ADD("page3", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank_mem)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(18)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(18)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x10000)
MCFG_DEVICE_ADD("ppi8255", I8255, 0)

8
src/mame/drivers/psychic5.cpp
View File

@ -722,8 +722,8 @@ static MACHINE_CONFIG_START( psychic5 )
MCFG_DEVICE_ADD("vrambank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(psychic5_vrambank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(14)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(14)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
MCFG_CPU_ADD("audiocpu", Z80, XTAL_5MHz)
@ -776,8 +776,8 @@ static MACHINE_CONFIG_START( bombsa )
MCFG_DEVICE_ADD("vrambank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bombsa_vrambank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(14)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(14)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
MCFG_CPU_ADD("audiocpu", Z80, XTAL_5MHz )

4
src/mame/drivers/pwrview.cpp
View File

@ -380,8 +380,8 @@ static MACHINE_CONFIG_START( pwrview )
MCFG_DEVICE_ADD("bios_bank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bios_bank)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(17)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(17)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x8000)
MACHINE_CONFIG_END

8
src/mame/drivers/rex6000.cpp
View File

@ -898,13 +898,13 @@ static MACHINE_CONFIG_START( rex6000 )
MCFG_DEVICE_ADD("bank0", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(rex6000_banked_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
MCFG_DEVICE_ADD("bank1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(rex6000_banked_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
MCFG_DEVICE_ADD( "ns16550", NS16550, XTAL_1_8432MHz )
@ -987,13 +987,13 @@ static MACHINE_CONFIG_START( oz750 )
MCFG_DEVICE_ADD("bank0", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(oz750_banked_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
MCFG_DEVICE_ADD("bank1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(oz750_banked_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
/* quickload */

8
src/mame/drivers/simpsons.cpp
View File

@ -331,15 +331,15 @@ static MACHINE_CONFIG_START( simpsons )
MCFG_DEVICE_ADD("bank0000", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank0000_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(13)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(13)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000)
MCFG_DEVICE_ADD("bank2000", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank2000_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(14)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(14)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
MCFG_EEPROM_SERIAL_ER5911_8BIT_ADD("eeprom")

4
src/mame/drivers/sitcom.cpp
View File

@ -340,8 +340,8 @@ MACHINE_CONFIG_START( sitcom )
MCFG_DEVICE_ADD("bank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(sitcom_bank)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x8000)
MCFG_CLOCK_ADD("100hz", 100)

2
src/mame/drivers/sm7238.cpp
View File

@ -362,7 +362,7 @@ static MACHINE_CONFIG_START( sm7238 )
MCFG_DEVICE_ADD("videobank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(videobank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
MCFG_NVRAM_ADD_0FILL("nvram")

14
src/mame/drivers/socrates.cpp
View File

@ -1454,19 +1454,19 @@ static MACHINE_CONFIG_START( socrates )
MCFG_DEVICE_ADD("rombank1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(socrates_rombank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
MCFG_DEVICE_ADD("rambank1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(socrates_rambank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
MCFG_DEVICE_ADD("rambank2", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(socrates_rambank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
/* video hardware */
@ -1520,25 +1520,25 @@ static MACHINE_CONFIG_START( iqunlimz )
MCFG_DEVICE_ADD("rombank1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(iqunlimz_rombank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
MCFG_DEVICE_ADD("rombank2", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(iqunlimz_rombank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
MCFG_DEVICE_ADD("rambank1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(iqunlimz_rambank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
MCFG_DEVICE_ADD("rambank2", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(iqunlimz_rambank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
/* video hardware */

16
src/mame/drivers/sun2.cpp
View File

@ -601,28 +601,28 @@ static MACHINE_CONFIG_START( sun2vme )
MCFG_DEVICE_ADD("type0", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype0space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000000)
// MMU Type 1 device space
MCFG_DEVICE_ADD("type1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype1space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000000)
// MMU Type 2 device space
MCFG_DEVICE_ADD("type2", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype2space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000000)
// MMU Type 3 device space
MCFG_DEVICE_ADD("type3", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype3space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000000)
MCFG_SCREEN_ADD("bwtwo", RASTER)
@ -673,28 +673,28 @@ static MACHINE_CONFIG_START( sun2mbus )
MCFG_DEVICE_ADD("type0", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(mbustype0space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000000)
// MMU Type 1 device space
MCFG_DEVICE_ADD("type1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(mbustype1space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000000)
// MMU Type 2 device space
MCFG_DEVICE_ADD("type2", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(mbustype2space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000000)
// MMU Type 3 device space
MCFG_DEVICE_ADD("type3", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(mbustype3space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000000)
MCFG_SCREEN_ADD("bwtwo", RASTER)

16
src/mame/drivers/sun3.cpp
View File

@ -973,28 +973,28 @@ static MACHINE_CONFIG_START( sun3 )
MCFG_DEVICE_ADD("type0", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype0space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
// MMU Type 1 device space
MCFG_DEVICE_ADD("type1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype1space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
// MMU Type 2 device space
MCFG_DEVICE_ADD("type2", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype2space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
// MMU Type 3 device space
MCFG_DEVICE_ADD("type3", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype3space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
MCFG_TIMER_DRIVER_ADD_PERIODIC("timer", sun3_state, sun3_timer, attotime::from_hz(100))
@ -1077,28 +1077,28 @@ static MACHINE_CONFIG_START( sun3_50 )
MCFG_DEVICE_ADD("type0", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype0space_novram_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
// MMU Type 1 device space
MCFG_DEVICE_ADD("type1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype1space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
// MMU Type 2 device space
MCFG_DEVICE_ADD("type2", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype2space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
// MMU Type 3 device space
MCFG_DEVICE_ADD("type3", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype3space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
MCFG_SCC8530_ADD(SCC1_TAG, XTAL_4_9152MHz, 0, 0, 0, 0)

8
src/mame/drivers/sun4.cpp
View File

@ -1909,14 +1909,14 @@ static MACHINE_CONFIG_START( sun4 )
MCFG_DEVICE_ADD("type0", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(type0space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
// MMU Type 1 device space
MCFG_DEVICE_ADD("type1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(type1space_s4_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
// Keyboard/mouse
@ -1974,14 +1974,14 @@ static MACHINE_CONFIG_START( sun4c )
MCFG_DEVICE_ADD("type0", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(type0space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
// MMU Type 1 device space
MCFG_DEVICE_ADD("type1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(type1space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
// Keyboard/mouse

4
src/mame/drivers/surpratk.cpp
View File

@ -177,8 +177,8 @@ static MACHINE_CONFIG_START( surpratk )
MCFG_DEVICE_ADD("bank0000", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(bank0000_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(13)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(13)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x800)
MCFG_WATCHDOG_ADD("watchdog")

4
src/mame/drivers/svi318.cpp
View File

@ -529,8 +529,8 @@ static MACHINE_CONFIG_START( svi318 )
MCFG_DEVICE_ADD("io", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(svi3x8_io_bank)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(9)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(9)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x100)
MCFG_DEVICE_ADD("ppi", I8255, 0)

2
src/mame/drivers/taitogn.cpp
View File

@ -730,7 +730,7 @@ static MACHINE_CONFIG_START( coh3002t )
MCFG_DEVICE_ADD("flashbank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(flashbank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x8000000)
// 5MHz NEC uPD78081 MCU:

4
src/mame/drivers/tandy1t.cpp
View File

@ -702,8 +702,8 @@ static MACHINE_CONFIG_START( t1000rl )
MCFG_DEVICE_ADD("biosbank", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(biosbank_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(20)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(20)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x10000)
MCFG_MACHINE_RESET_OVERRIDE(tandy1000_state,tandy1000rl)

6
src/mame/drivers/thunderx.cpp
View File

@ -643,8 +643,8 @@ static MACHINE_CONFIG_START( scontra )
MCFG_DEVICE_ADD("bank5800", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(scontra_bank5800_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(12)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(12)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x0800)
MCFG_WATCHDOG_ADD("watchdog")
@ -705,7 +705,7 @@ static MACHINE_CONFIG_DERIVED( thunderx, scontra )
MCFG_DEVICE_MODIFY("bank5800")
MCFG_DEVICE_PROGRAM_MAP(thunderx_bank5800_map)
MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(13)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(13)
MCFG_DEVICE_REMOVE("k007232")
MACHINE_CONFIG_END

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