From 7d4f1b05f96ed660dafb65d258453eddf65942ad Mon Sep 17 00:00:00 2001 From: AJR Date: Thu, 20 Jun 2019 22:08:01 -0400 Subject: [PATCH] riscii: Add the register space (nw) --- src/devices/cpu/rii/riscii.cpp | 33 ++++++++++++++++++++++++++------- src/devices/cpu/rii/riscii.h | 11 +++++++++++ 2 files changed, 37 insertions(+), 7 deletions(-) diff --git a/src/devices/cpu/rii/riscii.cpp b/src/devices/cpu/rii/riscii.cpp index 6c3334b58dd..cf2101295a3 100644 --- a/src/devices/cpu/rii/riscii.cpp +++ b/src/devices/cpu/rii/riscii.cpp @@ -20,15 +20,27 @@ DEFINE_DEVICE_TYPE(RISCII, riscii_series_device, "riscii", "Elan RISC II") +void riscii_series_device::regs_map(address_map &map) +{ + map(0x0000, 0x007f).mirror(m_bankmask << 8).ram(); // TODO: special function registers + for (unsigned b = 0; b <= m_maxbank; b++) + map(0x0080 | (b << 8), 0x00ff | (b << 8)).ram(); +} + std::unique_ptr riscii_series_device::create_disassembler() { return std::make_unique(); } -riscii_series_device::riscii_series_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) - : cpu_device(mconfig, RISCII, tag, owner, clock) - , m_program_config("program", ENDIANNESS_LITTLE, 16, 18, -1) +riscii_series_device::riscii_series_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, unsigned prgbits, unsigned bankbits, uint8_t maxbank) + : cpu_device(mconfig, type, tag, owner, clock) + , m_program_config("program", ENDIANNESS_LITTLE, 16, prgbits, -1) + , m_regs_config("register", ENDIANNESS_LITTLE, 8, 8 + bankbits, 0, address_map_constructor(FUNC(riscii_series_device::regs_map), this)) , m_program(nullptr) + , m_regs(nullptr) + , m_prgbits(prgbits) + , m_bankmask((1 << bankbits) - 1) + , m_maxbank(maxbank) , m_pc(0) , m_acc(0) , m_fsr0(0) @@ -43,28 +55,35 @@ riscii_series_device::riscii_series_device(const machine_config &mconfig, const m_prod.w = 0; } +riscii_series_device::riscii_series_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) + : riscii_series_device(mconfig, RISCII, tag, owner, clock, 18, 5, 0x1f) +{ +} + device_memory_interface::space_config_vector riscii_series_device::memory_space_config() const { return space_config_vector { std::make_pair(AS_PROGRAM, &m_program_config), + std::make_pair(AS_DATA, &m_regs_config) }; } void riscii_series_device::device_start() { m_program = &space(AS_PROGRAM); + m_regs = &space(AS_DATA); set_icountptr(m_icount); - state_add(RII_PC, "PC", m_pc).mask(0x3ffff); + state_add(RII_PC, "PC", m_pc).mask((1 << m_prgbits) - 1); state_add(STATE_GENPC, "GENPC", m_pc).callimport().noshow(); state_add(STATE_GENPCBASE, "CURPC", m_pc).callimport().noshow(); state_add(RII_ACC, "ACC", m_acc); - state_add(RII_BSR, "BSR", m_bsr).mask(0x1f); + state_add(RII_BSR, "BSR", m_bsr).mask(m_bankmask); state_add(RII_FSR0, "FSR0", m_fsr0); - state_add(RII_BSR1, "BSR1", m_fsr1.b.h).mask(0x1f); + state_add(RII_BSR1, "BSR1", m_fsr1.b.h).mask(m_bankmask); state_add(RII_FSR1, "FSR1", m_fsr1.b.l); // TODO: high bit forced to 1 - state_add(RII_TABPTR, "TABPTR", m_tabptr).mask(0xffffff); + state_add(RII_TABPTR, "TABPTR", m_tabptr).mask(0x800000 + (1 << (m_prgbits + 1)) - 1); state_add(RII_STKPTR, "STKPTR", m_stkptr); state_add(RII_CPUCON, "CPUCON", m_cpucon).mask(0x9f); state_add(RII_STATUS, "STATUS", m_status); diff --git a/src/devices/cpu/rii/riscii.h b/src/devices/cpu/rii/riscii.h index 7550bd2458b..869a3f551ce 100644 --- a/src/devices/cpu/rii/riscii.h +++ b/src/devices/cpu/rii/riscii.h @@ -35,6 +35,8 @@ public: riscii_series_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); protected: + riscii_series_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, unsigned prgbits, unsigned bankbits, uint8_t maxbank); + // device-level overrides virtual void device_start() override; virtual void device_reset() override; @@ -50,9 +52,18 @@ protected: virtual space_config_vector memory_space_config() const override; private: + void regs_map(address_map &map); + // address spaces address_space_config m_program_config; + address_space_config m_regs_config; address_space *m_program; + address_space *m_regs; + + // model-specific parameters + const unsigned m_prgbits; + const uint8_t m_bankmask; + const uint8_t m_maxbank; // internal state u32 m_pc;