mirror of
https://github.com/holub/mame
synced 2025-04-23 00:39:36 +03:00
hd63450_device: converted to devcb2 (nw)
This commit is contained in:
Ivan Vangelista
parent
fdc538eb29
commit
7e12918ace
@ -10,7 +10,17 @@ const device_type HD63450 = &device_creator<hd63450_device>;
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hd63450_device::hd63450_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: device_t(mconfig, HD63450, "Hitachi HD63450", tag, owner, clock, "hd63450", __FILE__),
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m_cpu(NULL)
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m_dma_end(*this),
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m_dma_error(*this),
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m_dma_read_0(*this),
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m_dma_read_1(*this),
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m_dma_read_2(*this),
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m_dma_read_3(*this),
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m_dma_write_0(*this),
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m_dma_write_1(*this),
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m_dma_write_2(*this),
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m_dma_write_3(*this),
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m_cpu(NULL)
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{
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for (int i = 0; i < 4; i++)
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{
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@ -52,6 +62,18 @@ void hd63450_device::device_start()
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m_cpu = machine().device<cpu_device>(m_cpu_tag);
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assert(m_cpu != NULL);
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// resolve callbacks
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m_dma_end.resolve();
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m_dma_error.resolve_safe();
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m_dma_read_0.resolve();
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m_dma_read_1.resolve();
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m_dma_read_2.resolve();
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m_dma_read_3.resolve();
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m_dma_write_0.resolve();
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m_dma_write_1.resolve();
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m_dma_write_2.resolve();
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m_dma_write_3.resolve();
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// Initialise timers and registers
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for (int x = 0; x < 4 ; x++)
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{
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@ -147,7 +169,7 @@ WRITE16_MEMBER(hd63450_device::write)
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if(ACCESSING_BITS_0_7)
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{
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m_reg[channel].ccr = data & 0x00ff;
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if((data & 0x0080))// && !dma_read[channel] && !dma_write[channel])
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if((data & 0x0080))// && !m_dma_read[channel] && !m_dma_write[channel])
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dma_transfer_start(channel,0);
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if(data & 0x0010) // software abort
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dma_transfer_abort(channel);
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@ -300,9 +322,33 @@ void hd63450_device::single_transfer(int x)
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{
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if(m_reg[x].ocr & 0x80) // direction: 1 = device -> memory
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{
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if(dma_read[x])
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if((x == 0) && !m_dma_read_0.isnull())
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{
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data = dma_read[x](machine(),m_reg[x].mar);
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data = m_dma_read_0(m_reg[x].mar);
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if(data == -1)
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return; // not ready to receive data
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space.write_byte(m_reg[x].mar,data);
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datasize = 1;
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}
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else if((x == 1) && !m_dma_read_1.isnull())
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{
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data = m_dma_read_1(m_reg[x].mar);
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if(data == -1)
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return; // not ready to receive data
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space.write_byte(m_reg[x].mar,data);
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datasize = 1;
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}
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else if((x == 2) && !m_dma_read_2.isnull())
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{
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data = m_dma_read_2(m_reg[x].mar);
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if(data == -1)
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return; // not ready to receive data
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space.write_byte(m_reg[x].mar,data);
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datasize = 1;
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}
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else if((x == 3) && !m_dma_read_3.isnull())
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{
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data = m_dma_read_3(m_reg[x].mar);
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if(data == -1)
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return; // not ready to receive data
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space.write_byte(m_reg[x].mar,data);
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@ -340,10 +386,28 @@ void hd63450_device::single_transfer(int x)
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}
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else // memory -> device
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{
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if(dma_write[x])
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if((x == 0) && !m_dma_write_0.isnull())
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{
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data = space.read_byte(m_reg[x].mar);
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dma_write[x](machine(), m_reg[x].mar,data);
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m_dma_write_0((offs_t)m_reg[x].mar,data);
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datasize = 1;
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}
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else if((x == 1) && !m_dma_write_1.isnull())
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{
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data = space.read_byte(m_reg[x].mar);
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m_dma_write_1((offs_t)m_reg[x].mar,data);
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datasize = 1;
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}
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else if((x == 2) && !m_dma_write_2.isnull())
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{
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data = space.read_byte(m_reg[x].mar);
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m_dma_write_2((offs_t)m_reg[x].mar,data);
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datasize = 1;
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}
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else if((x == 3) && !m_dma_write_3.isnull())
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{
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data = space.read_byte(m_reg[x].mar);
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m_dma_write_3((offs_t)m_reg[x].mar,data);
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datasize = 1;
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}
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else
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@ -417,8 +481,8 @@ void hd63450_device::single_transfer(int x)
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m_cpu->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
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}
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if(dma_end)
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dma_end(machine(),x,m_reg[x].ccr & 0x08);
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if(!m_dma_end.isnull())
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m_dma_end((offs_t)x, m_reg[x].ccr & 0x08);
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}
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}
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}
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@ -5,6 +5,37 @@
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#include "emu.h"
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#define MCFG_HD63450_DMA_END_CB(_devcb) \
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devcb = &hd63450_device::set_dma_end_callback(*device, DEVCB2_##_devcb);
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#define MCFG_HD63450_DMA_ERROR_CB(_devcb) \
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devcb = &hd63450_device::set_dma_error_callback(*device, DEVCB2_##_devcb);
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#define MCFG_HD63450_DMA_READ_0_CB(_devcb) \
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devcb = &hd63450_device::set_dma_read_0_callback(*device, DEVCB2_##_devcb);
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#define MCFG_HD63450_DMA_READ_1_CB(_devcb) \
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devcb = &hd63450_device::set_dma_read_1_callback(*device, DEVCB2_##_devcb);
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#define MCFG_HD63450_DMA_READ_2_CB(_devcb) \
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devcb = &hd63450_device::set_dma_read_2_callback(*device, DEVCB2_##_devcb);
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#define MCFG_HD63450_DMA_READ_3_CB(_devcb) \
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devcb = &hd63450_device::set_dma_read_3_callback(*device, DEVCB2_##_devcb);
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#define MCFG_HD63450_DMA_WRITE_0_CB(_devcb) \
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devcb = &hd63450_device::set_dma_write_0_callback(*device, DEVCB2_##_devcb);
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#define MCFG_HD63450_DMA_WRITE_1_CB(_devcb) \
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devcb = &hd63450_device::set_dma_write_1_callback(*device, DEVCB2_##_devcb);
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#define MCFG_HD63450_DMA_WRITE_2_CB(_devcb) \
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devcb = &hd63450_device::set_dma_write_2_callback(*device, DEVCB2_##_devcb);
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#define MCFG_HD63450_DMA_WRITE_3_CB(_devcb) \
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devcb = &hd63450_device::set_dma_write_3_callback(*device, DEVCB2_##_devcb);
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struct hd63450_regs
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{ // offsets in bytes
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unsigned char csr; // [00] Channel status register (R/W)
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@ -32,10 +63,6 @@ struct hd63450_interface
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const char *m_cpu_tag;
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attotime m_our_clock[4];
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attotime m_burst_clock[4];
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void (*dma_end)(running_machine &machine,int channel,int irq); // called when the DMA transfer ends
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void (*dma_error)(running_machine &machine,int channel, int irq); // called when a DMA transfer error occurs
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int (*dma_read[4])(running_machine &machine,int addr); // special read / write handlers for each channel
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void (*dma_write[4])(running_machine &machine,int addr,int data);
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};
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class hd63450_device : public device_t,
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@ -45,6 +72,17 @@ public:
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hd63450_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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~hd63450_device() {}
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template<class _Object> static devcb2_base &set_dma_end_callback(device_t &device, _Object object) { return downcast<hd63450_device &>(device).m_dma_end.set_callback(object); }
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template<class _Object> static devcb2_base &set_dma_error_callback(device_t &device, _Object object) { return downcast<hd63450_device &>(device).m_dma_error.set_callback(object); }
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template<class _Object> static devcb2_base &set_dma_read_0_callback(device_t &device, _Object object) { return downcast<hd63450_device &>(device).m_dma_read_0.set_callback(object); }
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template<class _Object> static devcb2_base &set_dma_read_1_callback(device_t &device, _Object object) { return downcast<hd63450_device &>(device).m_dma_read_1.set_callback(object); }
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template<class _Object> static devcb2_base &set_dma_read_2_callback(device_t &device, _Object object) { return downcast<hd63450_device &>(device).m_dma_read_2.set_callback(object); }
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template<class _Object> static devcb2_base &set_dma_read_3_callback(device_t &device, _Object object) { return downcast<hd63450_device &>(device).m_dma_read_3.set_callback(object); }
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template<class _Object> static devcb2_base &set_dma_write_0_callback(device_t &device, _Object object) { return downcast<hd63450_device &>(device).m_dma_write_0.set_callback(object); }
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template<class _Object> static devcb2_base &set_dma_write_1_callback(device_t &device, _Object object) { return downcast<hd63450_device &>(device).m_dma_write_1.set_callback(object); }
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template<class _Object> static devcb2_base &set_dma_write_2_callback(device_t &device, _Object object) { return downcast<hd63450_device &>(device).m_dma_write_2.set_callback(object); }
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template<class _Object> static devcb2_base &set_dma_write_3_callback(device_t &device, _Object object) { return downcast<hd63450_device &>(device).m_dma_write_3.set_callback(object); }
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DECLARE_READ16_MEMBER( read );
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DECLARE_WRITE16_MEMBER( write );
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@ -59,6 +97,17 @@ protected:
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virtual void device_start();
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private:
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devcb2_write8 m_dma_end;
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devcb2_write8 m_dma_error;
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devcb2_read8 m_dma_read_0;
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devcb2_read8 m_dma_read_1;
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devcb2_read8 m_dma_read_2;
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devcb2_read8 m_dma_read_3;
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devcb2_write8 m_dma_write_0;
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devcb2_write8 m_dma_write_1;
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devcb2_write8 m_dma_write_2;
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devcb2_write8 m_dma_write_3;
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// internal state
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hd63450_regs m_reg[4];
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emu_timer* m_timer[4]; // for timing data reading/writing each channel
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@ -75,8 +124,3 @@ private:
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};
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extern const device_type HD63450;
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#define MCFG_HD63450_ADD(_tag, _config) \
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MCFG_DEVICE_ADD(_tag, HD63450, 0) \
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MCFG_DEVICE_CONFIG(_config)
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@ -222,6 +222,12 @@ public:
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DECLARE_INPUT_CHANGED_MEMBER(key_stroke);
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IRQ_CALLBACK_MEMBER(maincpu_irq_acknowledge_callback);
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DECLARE_WRITE_LINE_MEMBER(esq5505_otis_irq);
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//dmac
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DECLARE_WRITE8_MEMBER(dma_end);
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DECLARE_WRITE8_MEMBER(dma_error);
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DECLARE_READ8_MEMBER(fdc_read_byte);
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DECLARE_WRITE8_MEMBER(fdc_write_byte);
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};
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FLOPPY_FORMATS_MEMBER( esq5505_state::floppy_formats )
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@ -505,53 +511,46 @@ WRITE_LINE_MEMBER(esq5505_state::duart_tx_b)
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m_panel->rx_w(state);
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}
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static void esq_dma_end(running_machine &machine, int channel, int irq)
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WRITE8_MEMBER(esq5505_state::dma_end)
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{
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esq5505_state *state = machine.driver_data<esq5505_state>();
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if (irq != 0)
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if (data != 0)
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{
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printf("DMAC IRQ, vector = %x\n", state->m_dmac->get_vector(channel));
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state->dmac_irq_state = 1;
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state->dmac_irq_vector = state->m_dmac->get_vector(channel);
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printf("DMAC IRQ, vector = %x\n", m_dmac->get_vector(offset));
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dmac_irq_state = 1;
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dmac_irq_vector = m_dmac->get_vector(offset);
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}
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else
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{
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state->dmac_irq_state = 0;
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dmac_irq_state = 0;
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}
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state->update_irq_to_maincpu();
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update_irq_to_maincpu();
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}
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static void esq_dma_error(running_machine &machine, int channel, int irq)
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WRITE8_MEMBER(esq5505_state::dma_error)
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{
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esq5505_state *state = machine.driver_data<esq5505_state>();
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if(irq != 0)
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if(data != 0)
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{
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printf("DMAC error, vector = %x\n", state->m_dmac->get_error_vector(channel));
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state->dmac_irq_state = 1;
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state->dmac_irq_vector = state->m_dmac->get_vector(channel);
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printf("DMAC error, vector = %x\n", m_dmac->get_error_vector(offset));
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dmac_irq_state = 1;
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dmac_irq_vector = m_dmac->get_vector(offset);
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}
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else
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{
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state->dmac_irq_state = 0;
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dmac_irq_state = 0;
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}
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state->update_irq_to_maincpu();
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update_irq_to_maincpu();
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}
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static int esq_fdc_read_byte(running_machine &machine, int addr)
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READ8_MEMBER(esq5505_state::fdc_read_byte)
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{
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esq5505_state *state = machine.driver_data<esq5505_state>();
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return state->m_fdc->data_r();
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return m_fdc->data_r();
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}
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static void esq_fdc_write_byte(running_machine &machine, int addr, int data)
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WRITE8_MEMBER(esq5505_state::fdc_write_byte)
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{
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esq5505_state *state = machine.driver_data<esq5505_state>();
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state->m_fdc->data_w(data & 0xff);
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m_fdc->data_w(data & 0xff);
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}
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#if KEYBOARD_HACK
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@ -607,10 +606,6 @@ static const hd63450_interface dmac_interface =
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"maincpu", // CPU - 68000
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{attotime::from_usec(32),attotime::from_nsec(450),attotime::from_usec(4),attotime::from_hz(15625/2)}, // Cycle steal mode timing (guesstimate)
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{attotime::from_usec(32),attotime::from_nsec(450),attotime::from_nsec(50),attotime::from_nsec(50)}, // Burst mode timing (guesstimate)
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esq_dma_end,
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esq_dma_error,
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{ esq_fdc_read_byte, 0, 0, 0 }, // ch 0 = fdc, ch 1 = 340001 (ADC?)
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{ esq_fdc_write_byte, 0, 0, 0 }
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};
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static const es5505_interface es5505_config =
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@ -675,7 +670,12 @@ static MACHINE_CONFIG_DERIVED(eps, vfx)
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MCFG_WD1772x_ADD("wd1772", 8000000)
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MCFG_FLOPPY_DRIVE_ADD("wd1772:0", ensoniq_floppies, "35dd", esq5505_state::floppy_formats)
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MCFG_HD63450_ADD( "mc68450", dmac_interface ) // MC68450 compatible
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MCFG_DEVICE_ADD("mc68450", HD63450, 0) // MC68450 compatible
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MCFG_DEVICE_CONFIG(dmac_interface)
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MCFG_HD63450_DMA_END_CB(WRITE8(esq5505_state, dma_end))
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MCFG_HD63450_DMA_ERROR_CB(WRITE8(esq5505_state, dma_error))
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MCFG_HD63450_DMA_READ_0_CB(READ8(esq5505_state, fdc_read_byte)) // ch 0 = fdc, ch 1 = 340001 (ADC?)
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MCFG_HD63450_DMA_WRITE_0_CB(WRITE8(esq5505_state, fdc_write_byte))
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MACHINE_CONFIG_END
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static MACHINE_CONFIG_DERIVED(vfxsd, vfx)
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@ -726,16 +726,14 @@ WRITE_LINE_MEMBER( x68k_state::fdc_irq )
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}
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}
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static int x68k_fdc_read_byte(running_machine &machine,int addr)
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READ8_MEMBER(x68k_state::fdc_read_byte)
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{
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x68k_state *state = machine.driver_data<x68k_state>();
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return state->m_fdc.fdc->dma_r();
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return m_fdc.fdc->dma_r();
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}
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static void x68k_fdc_write_byte(running_machine &machine,int addr, int data)
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WRITE8_MEMBER(x68k_state::fdc_write_byte)
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{
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x68k_state *state = machine.driver_data<x68k_state>();
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return state->m_fdc.fdc->dma_w(data);
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return m_fdc.fdc->dma_w(data);
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}
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WRITE_LINE_MEMBER( x68k_state::fdc_drq )
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@ -1157,36 +1155,33 @@ WRITE16_MEMBER(x68k_state::x68k_exp_w)
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}
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}
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static void x68k_dma_irq(running_machine &machine, int channel)
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void x68k_state::dma_irq(int channel)
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{
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x68k_state *state = machine.driver_data<x68k_state>();
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state->m_current_vector[3] = state->m_hd63450->get_vector(channel);
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state->m_current_irq_line = 3;
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logerror("DMA#%i: DMA End (vector 0x%02x)\n",channel,state->m_current_vector[3]);
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state->m_maincpu->set_input_line_and_vector(3,ASSERT_LINE,state->m_current_vector[3]);
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m_current_vector[3] = m_hd63450->get_vector(channel);
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m_current_irq_line = 3;
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logerror("DMA#%i: DMA End (vector 0x%02x)\n",channel,m_current_vector[3]);
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m_maincpu->set_input_line_and_vector(3,ASSERT_LINE,m_current_vector[3]);
|
||||
}
|
||||
|
||||
static void x68k_dma_end(running_machine &machine, int channel,int irq)
|
||||
WRITE8_MEMBER(x68k_state::dma_end)
|
||||
{
|
||||
if(irq != 0)
|
||||
if(data != 0)
|
||||
{
|
||||
x68k_dma_irq(machine, channel);
|
||||
dma_irq(offset);
|
||||
}
|
||||
if(channel == 0)
|
||||
if(offset == 0)
|
||||
{
|
||||
x68k_state *state = machine.driver_data<x68k_state>();
|
||||
state->m_fdc_tc->adjust(attotime::from_usec(1), 0, attotime::never);
|
||||
m_fdc_tc->adjust(attotime::from_usec(1), 0, attotime::never);
|
||||
}
|
||||
}
|
||||
|
||||
static void x68k_dma_error(running_machine &machine, int channel, int irq)
|
||||
WRITE8_MEMBER(x68k_state::dma_error)
|
||||
{
|
||||
x68k_state *state = machine.driver_data<x68k_state>();
|
||||
if(irq != 0)
|
||||
if(data != 0)
|
||||
{
|
||||
state->m_current_vector[3] = state->m_hd63450->get_error_vector(channel);
|
||||
state->m_current_irq_line = 3;
|
||||
state->m_maincpu->set_input_line_and_vector(3,ASSERT_LINE,state->m_current_vector[3]);
|
||||
m_current_vector[3] = m_hd63450->get_error_vector(offset);
|
||||
m_current_irq_line = 3;
|
||||
m_maincpu->set_input_line_and_vector(3,ASSERT_LINE,m_current_vector[3]);
|
||||
}
|
||||
}
|
||||
|
||||
@ -1411,12 +1406,6 @@ static const hd63450_interface dmac_interface =
|
||||
"maincpu", // CPU - 68000
|
||||
{attotime::from_usec(32),attotime::from_nsec(450),attotime::from_usec(4),attotime::from_hz(15625/2)}, // Cycle steal mode timing (guesstimate)
|
||||
{attotime::from_usec(32),attotime::from_nsec(450),attotime::from_nsec(50),attotime::from_nsec(50)}, // Burst mode timing (guesstimate)
|
||||
x68k_dma_end,
|
||||
x68k_dma_error,
|
||||
{ x68k_fdc_read_byte, 0, 0, 0 },
|
||||
{ x68k_fdc_write_byte, 0, 0, 0 }
|
||||
// { 0, 0, 0, 0 },
|
||||
// { 0, 0, 0, 0 }
|
||||
};
|
||||
|
||||
static const okim6258_interface x68k_okim6258_interface =
|
||||
@ -1897,7 +1886,12 @@ static MACHINE_CONFIG_FRAGMENT( x68000_base )
|
||||
|
||||
MCFG_I8255A_ADD( "ppi8255", ppi_interface )
|
||||
|
||||
MCFG_HD63450_ADD( "hd63450", dmac_interface )
|
||||
MCFG_DEVICE_ADD( "hd63450", HD63450, 0 )
|
||||
MCFG_DEVICE_CONFIG(dmac_interface)
|
||||
MCFG_HD63450_DMA_END_CB(WRITE8(x68k_state, dma_end))
|
||||
MCFG_HD63450_DMA_ERROR_CB(WRITE8(x68k_state, dma_error))
|
||||
MCFG_HD63450_DMA_READ_0_CB(READ8(x68k_state, fdc_read_byte))
|
||||
MCFG_HD63450_DMA_WRITE_0_CB(WRITE8(x68k_state, fdc_write_byte))
|
||||
|
||||
MCFG_DEVICE_ADD( "scc", SCC8530, 5000000 )
|
||||
|
||||
|
||||
@ -247,6 +247,13 @@ public:
|
||||
DECLARE_WRITE_LINE_MEMBER(mfp_irq_callback);
|
||||
DECLARE_WRITE_LINE_MEMBER(x68k_scsi_irq);
|
||||
DECLARE_WRITE_LINE_MEMBER(x68k_scsi_drq);
|
||||
|
||||
//dmac
|
||||
void dma_irq(int channel);
|
||||
DECLARE_WRITE8_MEMBER(dma_end);
|
||||
DECLARE_WRITE8_MEMBER(dma_error);
|
||||
DECLARE_READ8_MEMBER(fdc_read_byte);
|
||||
DECLARE_WRITE8_MEMBER(fdc_write_byte);
|
||||
|
||||
int x68k_read_mouse();
|
||||
void x68k_set_adpcm();
|
||||
|
||||
Loading…
Reference in New Issue
Block a user