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arm: Eliminate big-endian bus variant not actually implemented until ARM6 (which is also not emulated here)

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AJR 2022-09-25 19:54:31 -04:00
parent 32ba5268e8
commit 7e61dc3a3d
3 changed files with 12 additions and 42 deletions
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35
src/devices/cpu/arm/arm.cpp
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@ -1,7 +1,7 @@
// license:BSD-3-Clause
// copyright-holders:Bryan McPhail, Phil Stroffolino
/*
ARM 2/3/6 Emulation (26 bit address bus)
ARM 2/3 Emulation (26 bit address bus, no separate PSRs)
Todo:
- Timing - Currently very approximated, nothing relies on proper timing so far.
@ -220,8 +220,7 @@ enum
/***************************************************************************/
DEFINE_DEVICE_TYPE(ARM, arm_cpu_device, "arm_le", "ARM (little)")
DEFINE_DEVICE_TYPE(ARM_BE, arm_be_cpu_device, "arm_be", "ARM (big)")
DEFINE_DEVICE_TYPE(ARM, arm_cpu_device, "arm_cpu", "ARM")
device_memory_interface::space_config_vector arm_cpu_device::memory_space_config() const
@ -232,27 +231,20 @@ device_memory_interface::space_config_vector arm_cpu_device::memory_space_config
}
arm_cpu_device::arm_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: arm_cpu_device(mconfig, ARM, tag, owner, clock, ENDIANNESS_LITTLE)
: arm_cpu_device(mconfig, ARM, tag, owner, clock)
{
}
arm_cpu_device::arm_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, endianness_t endianness)
arm_cpu_device::arm_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
: cpu_device(mconfig, type, tag, owner, clock)
, m_program_config("program", endianness, 32, 26, 0)
, m_endian(endianness)
, m_program_config("program", ENDIANNESS_LITTLE, 32, 26, 0)
, m_copro_type(copro_type::UNKNOWN_CP15)
{
std::fill(std::begin(m_sArmRegister), std::end(m_sArmRegister), 0);
}
arm_be_cpu_device::arm_be_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: arm_cpu_device(mconfig, ARM_BE, tag, owner, clock, ENDIANNESS_BIG)
{
}
void arm_cpu_device::cpu_write32( int addr, uint32_t data )
{
@ -342,7 +334,7 @@ void arm_cpu_device::execute_run()
/* load instruction */
uint32_t pc = R15;
uint32_t insn = m_pr32( pc & ADDRESS_MASK );
uint32_t insn = m_cache.read_dword( pc & ADDRESS_MASK );
switch (insn >> INSN_COND_SHIFT)
{
@ -447,10 +439,10 @@ void arm_cpu_device::arm_check_irq_state()
{
uint32_t pc = R15+4; /* save old pc (already incremented in pipeline) */;
/* Exception priorities (from ARM6, not specifically ARM2/3):
/* Exception priorities for ARM2/3:
Reset
Data abort
Data abort or address exception
FIRQ
IRQ
Prefetch abort
@ -496,16 +488,7 @@ void arm_cpu_device::device_start()
{
m_program = &space(AS_PROGRAM);
if(m_program->endianness() == ENDIANNESS_LITTLE)
{
m_program->cache(m_cachele);
m_pr32 = [this](offs_t address) -> u32 { return m_cachele.read_dword(address); };
}
else
{
m_program->cache(m_cachebe);
m_pr32 = [this](offs_t address) -> u32 { return m_cachebe.read_dword(address); };
}
m_program->cache(m_cache);
save_item(NAME(m_sArmRegister));
save_item(NAME(m_coproRegister));

18
src/devices/cpu/arm/arm.h
View File

@ -41,7 +41,7 @@ protected:
ARM32_IR13, ARM32_IR14, ARM32_SR13, ARM32_SR14
};
arm_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, endianness_t endianness);
arm_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
// device-level overrides
virtual void device_start() override;
@ -64,8 +64,7 @@ protected:
virtual std::unique_ptr<util::disasm_interface> create_disassembler() override;
address_space_config m_program_config;
memory_access<26, 2, 0, ENDIANNESS_LITTLE>::cache m_cachele;
memory_access<26, 2, 0, ENDIANNESS_BIG>::cache m_cachebe;
memory_access<26, 2, 0, ENDIANNESS_LITTLE>::cache m_cache;
int m_icount;
uint32_t m_sArmRegister[27];
@ -73,8 +72,6 @@ protected:
uint8_t m_pendingIrq;
uint8_t m_pendingFiq;
address_space *m_program;
std::function<u32 (offs_t)> m_pr32;
endianness_t m_endian;
copro_type m_copro_type;
void cpu_write32( int addr, uint32_t data );
@ -103,15 +100,6 @@ protected:
};
class arm_be_cpu_device : public arm_cpu_device
{
public:
// construction/destruction
arm_be_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
};
DECLARE_DEVICE_TYPE(ARM, arm_cpu_device)
DECLARE_DEVICE_TYPE(ARM_BE, arm_be_cpu_device)
DECLARE_DEVICE_TYPE(ARM, arm_cpu_device)
#endif // MAME_CPU_ARM_ARM_H

1
src/tools/unidasm.cpp
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@ -387,7 +387,6 @@ static const dasm_table_entry dasm_table[] =
{ "arc", be, 0, []() -> util::disasm_interface * { return new arc_disassembler; } },
{ "arcompact", le, 0, []() -> util::disasm_interface * { return new arcompact_disassembler; } },
{ "arm", le, 0, []() -> util::disasm_interface * { return new arm_disassembler; } },
{ "arm_be", be, 0, []() -> util::disasm_interface * { return new arm_disassembler; } },
{ "arm7", le, 0, []() -> util::disasm_interface * { arm7_unidasm.t_flag = false; return new arm7_disassembler(&arm7_unidasm); } },
{ "arm7_be", be, 0, []() -> util::disasm_interface * { arm7_unidasm.t_flag = false; return new arm7_disassembler(&arm7_unidasm); } },
{ "arm7thumb", le, 0, []() -> util::disasm_interface * { arm7_unidasm.t_flag = true; return new arm7_disassembler(&arm7_unidasm); } },