From 7ee8bf47074822afda37ff893d965f39dc4ea16a Mon Sep 17 00:00:00 2001 From: smf- Date: Mon, 11 Dec 2017 18:36:09 +0000 Subject: [PATCH] only define LSL, LSR, ROL & ROR when building the cpu core (nw) --- src/devices/cpu/arm7/arm7core.h | 5 ----- src/devices/cpu/arm7/arm7help.h | 5 +++++ 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/devices/cpu/arm7/arm7core.h b/src/devices/cpu/arm7/arm7core.h index 9ae499ae109..c33bdee9dd2 100644 --- a/src/devices/cpu/arm7/arm7core.h +++ b/src/devices/cpu/arm7/arm7core.h @@ -470,11 +470,6 @@ enum COND_NV /* 0 never */ }; -#define LSL(v, s) ((v) << (s)) -#define LSR(v, s) ((v) >> (s)) -#define ROL(v, s) (LSL((v), (s)) | (LSR((v), 32u - (s)))) -#define ROR(v, s) (LSR((v), (s)) | (LSL((v), 32u - (s)))) - /* Convenience Macros */ #define R15 m_r[eR15] #define SPSR 17 // SPSR is always the 18th register in our 0 based array sRegisterTable[][18] diff --git a/src/devices/cpu/arm7/arm7help.h b/src/devices/cpu/arm7/arm7help.h index 4b0b4f21c8a..c006bfbf1af 100644 --- a/src/devices/cpu/arm7/arm7help.h +++ b/src/devices/cpu/arm7/arm7help.h @@ -166,3 +166,8 @@ #define WRITE32(addr,data) arm7_cpu_write32(addr,data) #define PTR_READ32 &arm7_cpu_read32 #define PTR_WRITE32 &arm7_cpu_write32 + +#define LSL(v, s) ((v) << (s)) +#define LSR(v, s) ((v) >> (s)) +#define ROL(v, s) (LSL((v), (s)) | (LSR((v), 32u - (s)))) +#define ROR(v, s) (LSR((v), (s)) | (LSL((v), 32u - (s))))