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upd765: Simplify read/write handlers (nw)

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This commit is contained in:
AJR 2019-03-10 16:20:26 -04:00
parent 3e1d84b7fa
commit 7f50bbafaa
36 changed files with 133 additions and 175 deletions
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6
src/devices/bus/a2bus/corvfdc02.cpp
View File

@ -132,10 +132,10 @@ uint8_t a2bus_corvfdc02_device::read_c0nx(uint8_t offset)
switch (offset)
{
case 0: // 765 FIFO
return m_fdc->read_fifo();
return m_fdc->fifo_r();
case 1: // 765 MSR
return m_fdc->read_msr();
return m_fdc->msr_r();
case 2: // buffer address
return (m_bufptr>>1) & 0xff;
@ -170,7 +170,7 @@ void a2bus_corvfdc02_device::write_c0nx(uint8_t offset, uint8_t data)
switch (offset)
{
case 0: // FDC FIFO write
m_fdc->write_fifo(data);
m_fdc->fifo_w(data);
break;
case 1: // FDC ???

6
src/devices/bus/bbc/fdc/opus.cpp
View File

@ -227,14 +227,14 @@ READ8_MEMBER(bbc_opus8272_device::read)
if (m_floppy0->get_device()) m_floppy0->get_device()->mon_w(1);
if (m_floppy1->get_device()) m_floppy1->get_device()->mon_w(1);
case 0x04:
data = m_fdc->msr_r(space, 0);
data = m_fdc->msr_r();
break;
case 0x05:
if (m_floppy0->get_device()) m_floppy0->get_device()->mon_w(0);
if (m_floppy1->get_device()) m_floppy1->get_device()->mon_w(0);
case 0x07:
data = m_fdc->fifo_r(space, 0);
data = m_fdc->fifo_r();
break;
}
return data;
@ -259,7 +259,7 @@ WRITE8_MEMBER(bbc_opus8272_device::write)
if (m_floppy0->get_device()) m_floppy0->get_device()->mon_w(0);
if (m_floppy1->get_device()) m_floppy1->get_device()->mon_w(0);
case 0x07:
m_fdc->fifo_w(space, 0, data);
m_fdc->fifo_w(data);
break;
}
}

6
src/devices/bus/cpc/ddi1.cpp
View File

@ -116,7 +116,7 @@ WRITE8_MEMBER(cpc_ddi1_device::fdc_w)
switch(offset)
{
case 0x01:
m_fdc->fifo_w(space, 0,data);
m_fdc->fifo_w(data);
break;
}
}
@ -128,10 +128,10 @@ READ8_MEMBER(cpc_ddi1_device::fdc_r)
switch(offset)
{
case 0x00:
data = m_fdc->msr_r(space, 0);
data = m_fdc->msr_r();
break;
case 0x01:
data = m_fdc->fifo_r(space, 0);
data = m_fdc->fifo_r();
break;
}
return data;

6
src/devices/bus/hexbus/hx5102.cpp
View File

@ -373,12 +373,12 @@ READ8_MEMBER(hx5102_device::fdc_read)
{
case 0:
// Main status register
val = m_floppy_ctrl->read_msr();
val = m_floppy_ctrl->msr_r();
LOGMASKED(LOG_STATUS, "i8272A.msr -> %02x\n", val);
break;
case 4:
// FIFO read
val = m_floppy_ctrl->read_fifo();
val = m_floppy_ctrl->fifo_r();
LOGMASKED(LOG_FIFO, "i8272A.fifo -> %02x\n", val);
break;
}
@ -397,7 +397,7 @@ WRITE8_MEMBER(hx5102_device::fdc_write)
case 0x08:
// Command register (FIFO write)
LOGMASKED(LOG_STATUS, "i8272A.fifo <- %02x\n", data);
m_floppy_ctrl->write_fifo(data);
m_floppy_ctrl->fifo_w(data);
break;
case 0x0c:
// DMA lock

11
src/devices/bus/iq151/disc2.cpp
View File

@ -95,7 +95,7 @@ const tiny_rom_entry *iq151_disc2_device::device_rom_region() const
void iq151_disc2_device::read(offs_t offset, uint8_t &data)
{
// interal ROM is mapped at 0xe000-0xe7ff
// internal ROM is mapped at 0xe000-0xe7ff
if (offset >= 0xe000 && offset < 0xe800 && m_rom_enabled)
data = m_rom[offset & 0x7ff];
}
@ -107,12 +107,10 @@ void iq151_disc2_device::read(offs_t offset, uint8_t &data)
void iq151_disc2_device::io_read(offs_t offset, uint8_t &data)
{
/* This is gross */
address_space *space = nullptr;
if (offset == 0xaa)
data = m_fdc->msr_r(*space, 0, 0xff);
data = m_fdc->msr_r();
else if (offset == 0xab)
data = m_fdc->fifo_r(*space, 0, 0xff);
data = m_fdc->fifo_r();
}
//-------------------------------------------------
@ -121,9 +119,8 @@ void iq151_disc2_device::io_read(offs_t offset, uint8_t &data)
void iq151_disc2_device::io_write(offs_t offset, uint8_t data)
{
address_space *space = nullptr;
if (offset == 0xab)
m_fdc->fifo_w(*space, 0, data, 0xff);
m_fdc->fifo_w(data);
else if (offset == 0xac)
m_rom_enabled = (data == 0x01);
}

6
src/devices/bus/isbx/compis_fdc.cpp
View File

@ -112,8 +112,8 @@ uint8_t compis_fdc_device::mcs0_r(offs_t offset)
switch (BIT(offset, 0))
{
case 0: data = m_fdc->msr_r(machine().dummy_space(), 0); break;
case 1: data = m_fdc->fifo_r(machine().dummy_space(), 0); break;
case 0: data = m_fdc->msr_r(); break;
case 1: data = m_fdc->fifo_r(); break;
}
return data;
@ -128,7 +128,7 @@ void compis_fdc_device::mcs0_w(offs_t offset, uint8_t data)
{
switch (BIT(offset, 0))
{
case 1: m_fdc->fifo_w(machine().dummy_space(), 0, data); break;
case 1: m_fdc->fifo_w(data); break;
}
}

6
src/devices/bus/isbx/isbc_218a.cpp
View File

@ -117,8 +117,8 @@ uint8_t isbc_218a_device::mcs0_r(offs_t offset)
switch (BIT(offset, 0))
{
case 0: data = m_fdc->msr_r(machine().dummy_space(), 0); break;
case 1: data = m_fdc->fifo_r(machine().dummy_space(), 0); break;
case 0: data = m_fdc->msr_r(); break;
case 1: data = m_fdc->fifo_r(); break;
}
return data;
@ -133,7 +133,7 @@ void isbc_218a_device::mcs0_w(offs_t offset, uint8_t data)
{
switch (BIT(offset, 0))
{
case 1: m_fdc->fifo_w(machine().dummy_space(), 0, data); break;
case 1: m_fdc->fifo_w(data); break;
}
}

4
src/devices/bus/kc/d004.cpp
View File

@ -33,7 +33,7 @@ void kc_d004_device::kc_d004_io(address_map &map)
map.unmap_value_high();
map.global_mask(0xff);
map(0xf0, 0xf1).m(UPD765_TAG, FUNC(upd765a_device::map));
map(0xf2, 0xf3).rw(UPD765_TAG, FUNC(upd765a_device::mdma_r), FUNC(upd765a_device::mdma_w));
map(0xf2, 0xf3).rw(UPD765_TAG, FUNC(upd765a_device::dma_r), FUNC(upd765a_device::dma_w));
map(0xf4, 0xf4).r(FUNC(kc_d004_device::hw_input_gate_r));
map(0xf6, 0xf7).w(FUNC(kc_d004_device::fdd_select_w));
map(0xf8, 0xf9).w(FUNC(kc_d004_device::hw_terminal_count_w));
@ -45,7 +45,7 @@ void kc_d004_gide_device::kc_d004_gide_io(address_map &map)
map.unmap_value_high();
map(0x0000, 0xffff).rw(FUNC(kc_d004_gide_device::gide_r), FUNC(kc_d004_gide_device::gide_w));
map(0x00f0, 0x00f1).mirror(0xff00).m(UPD765_TAG, FUNC(upd765a_device::map));
map(0x00f2, 0x00f3).mirror(0xff00).rw(UPD765_TAG, FUNC(upd765a_device::mdma_r), FUNC(upd765a_device::mdma_w));
map(0x00f2, 0x00f3).mirror(0xff00).rw(UPD765_TAG, FUNC(upd765a_device::dma_r), FUNC(upd765a_device::dma_w));
map(0x00f4, 0x00f4).mirror(0xff00).r(FUNC(kc_d004_gide_device::hw_input_gate_r));
map(0x00f6, 0x00f7).mirror(0xff00).w(FUNC(kc_d004_gide_device::fdd_select_w));
map(0x00f8, 0x00f9).mirror(0xff00).w(FUNC(kc_d004_gide_device::hw_terminal_count_w));

14
src/devices/bus/msx_cart/disk.cpp
View File

@ -566,17 +566,15 @@ void msx_cart_fsfd1a_device::device_reset()
uint8_t msx_cart_fsfd1a_device::read_cart(offs_t offset)
{
address_space &space = machine().dummy_space();
switch (offset)
{
case 0x7ffa:
case 0xbffa:
return m_fdc->msr_r(space, 4);
return m_fdc->msr_r();
case 0x7ffb:
case 0xbffb:
return m_fdc->fifo_r(space, 5);
return m_fdc->fifo_r();
}
if (offset >= 0x4000 && offset < 0x8000)
@ -589,23 +587,21 @@ uint8_t msx_cart_fsfd1a_device::read_cart(offs_t offset)
void msx_cart_fsfd1a_device::write_cart(offs_t offset, uint8_t data)
{
address_space &space = machine().dummy_space();
switch (offset)
{
case 0x7ff8:
case 0xbff8:
m_fdc->dor_w(space, 2, data);
m_fdc->dor_w(data);
break;
case 0x7ff9:
case 0xbff9:
m_fdc->cr1_w(space, 3, data);
m_fdc->cr1_w(data);
break;
case 0x7ffb:
case 0xbffb:
m_fdc->fifo_w(space, 5, data);
m_fdc->fifo_w(data);
break;
default:

28
src/devices/bus/msx_slot/disk.cpp
View File

@ -429,20 +429,18 @@ msx_slot_disk3_device::msx_slot_disk3_device(const machine_config &mconfig, cons
void msx_slot_disk3_device::write(offs_t offset, uint8_t data)
{
address_space &space = machine().dummy_space();
switch (offset)
{
case 0x7ff8: // CR0 : 0 - 0 - MEN1 - MEN0 - 0 - -FRST - 0 - DSA
m_fdc->dor_w(space, 2, data);
m_fdc->dor_w(data);
break;
case 0x7ff9: // CR1 : 0 - 0 - C4E - C4 - SBME - SBM - TCE - FDCTC
m_fdc->cr1_w(space, 3, data);
m_fdc->cr1_w(data);
break;
case 0x7ffb: // Data Register
m_fdc->fifo_w(space, 5, data);
m_fdc->fifo_w(data);
break;
default:
@ -454,14 +452,12 @@ void msx_slot_disk3_device::write(offs_t offset, uint8_t data)
uint8_t msx_slot_disk3_device::read(offs_t offset)
{
address_space &space = machine().dummy_space();
switch (offset)
{
case 0x7ffa: // Status Register
return m_fdc->msr_r(space, 4);
return m_fdc->msr_r();
case 0x7ffb: // Data Register
return m_fdc->fifo_r(space, 5);
return m_fdc->fifo_r();
}
return msx_slot_rom_device::read(offset);
@ -479,23 +475,21 @@ msx_slot_disk4_device::msx_slot_disk4_device(const machine_config &mconfig, cons
void msx_slot_disk4_device::write(offs_t offset, uint8_t data)
{
address_space &space = machine().dummy_space();
switch (offset)
{
case 0x7ff1: // FDD : x - x - MC1 - MC0 - x - x - x - x
break;
case 0x7ff2: // CR0 : 0 - 0 - MEN1 - MEN0 - 0 - -FRST - 0 - DSA
m_fdc->dor_w(space, 2, data);
m_fdc->dor_w(data);
break;
case 0x7ff3: // CR1 : 0 - 0 - C4E - C4 - SBME - SBM - TCE - FDCTC
m_fdc->cr1_w(space, 3, data);
m_fdc->cr1_w(data);
break;
case 0x7ff5: // Data Register
m_fdc->fifo_w(space, 5, data);
m_fdc->fifo_w(data);
break;
default:
@ -507,8 +501,6 @@ void msx_slot_disk4_device::write(offs_t offset, uint8_t data)
uint8_t msx_slot_disk4_device::read(offs_t offset)
{
address_space &space = machine().dummy_space();
switch (offset)
{
case 0x7ff1: // FDD : x - x - MC1 - MC0 - x - x - x - x
@ -516,9 +508,9 @@ uint8_t msx_slot_disk4_device::read(offs_t offset)
break;
case 0x7ff4: // Status Register
return m_fdc->msr_r(space, 4);
return m_fdc->msr_r();
case 0x7ff5: // Data Register
return m_fdc->fifo_r(space, 5);
return m_fdc->fifo_r();
}
return msx_slot_rom_device::read(offset);

2
src/devices/machine/pc_fdc.cpp
View File

@ -157,7 +157,7 @@ uint8_t pc_fdc_family_device::do_dir_r()
WRITE8_MEMBER( pc_fdc_xt_device::dor_fifo_w)
{
fdc->fifo_w(space, 0, data, mem_mask);
fdc->fifo_w(data);
dor_w(space, 0, data, mem_mask);
}

56
src/devices/machine/upd765.cpp
View File

@ -355,7 +355,7 @@ void upd765_family_device::set_floppy(floppy_image_device *flop)
idx_cb(0);
}
READ8_MEMBER(upd765_family_device::sra_r)
uint8_t upd765_family_device::sra_r()
{
uint8_t sra = 0;
int fid = dor & 3;
@ -378,17 +378,17 @@ READ8_MEMBER(upd765_family_device::sra_r)
return sra;
}
READ8_MEMBER(upd765_family_device::srb_r)
uint8_t upd765_family_device::srb_r()
{
return 0;
}
READ8_MEMBER(upd765_family_device::dor_r)
uint8_t upd765_family_device::dor_r()
{
return dor;
}
WRITE8_MEMBER(upd765_family_device::dor_w)
void upd765_family_device::dor_w(uint8_t data)
{
LOGREGS("dor = %02x\n", data);
uint8_t diff = dor ^ data;
@ -404,21 +404,16 @@ WRITE8_MEMBER(upd765_family_device::dor_w)
check_irq();
}
READ8_MEMBER(upd765_family_device::tdr_r)
uint8_t upd765_family_device::tdr_r()
{
return 0;
}
WRITE8_MEMBER(upd765_family_device::tdr_w)
void upd765_family_device::tdr_w(uint8_t data)
{
}
READ8_MEMBER(upd765_family_device::msr_r)
{
return read_msr();
}
uint8_t upd765_family_device::read_msr()
uint8_t upd765_family_device::msr_r()
{
uint32_t msr = 0;
switch(main_phase) {
@ -457,7 +452,7 @@ uint8_t upd765_family_device::read_msr()
return msr;
}
WRITE8_MEMBER(upd765_family_device::dsr_w)
void upd765_family_device::dsr_w(uint8_t data)
{
LOGREGS("dsr_w %02x (%s)\n", data, machine().describe_context());
if(data & 0x80)
@ -471,14 +466,14 @@ void upd765_family_device::set_rate(int rate)
cur_rate = rate;
}
uint8_t upd765_family_device::read_fifo()
uint8_t upd765_family_device::fifo_r()
{
uint8_t r = 0xff;
switch(main_phase) {
case PHASE_EXEC:
if(internal_drq)
return fifo_pop(false);
LOGFIFO("read_fifo in phase %d\n", main_phase);
LOGFIFO("fifo_r in phase %d\n", main_phase);
break;
case PHASE_RESULT:
@ -496,14 +491,14 @@ uint8_t upd765_family_device::read_fifo()
}
break;
default:
LOGFIFO("read_fifo in phase %d\n", main_phase);
LOGFIFO("fifo_r in phase %d\n", main_phase);
break;
}
return r;
}
void upd765_family_device::write_fifo(uint8_t data)
void upd765_family_device::fifo_w(uint8_t data)
{
switch(main_phase) {
case PHASE_CMD: {
@ -529,11 +524,11 @@ void upd765_family_device::write_fifo(uint8_t data)
fifo_push(data, false);
return;
}
LOGFIFO("write_fifo in phase %d\n", main_phase);
LOGFIFO("fifo_w in phase %d\n", main_phase);
break;
default:
LOGFIFO("write_fifo in phase %d\n", main_phase);
LOGFIFO("fifo_w in phase %d\n", main_phase);
break;
}
}
@ -546,12 +541,7 @@ uint8_t upd765_family_device::do_dir_r()
return 0x00;
}
READ8_MEMBER(upd765_family_device::dir_r)
{
return do_dir_r();
}
WRITE8_MEMBER(upd765_family_device::ccr_w)
void upd765_family_device::ccr_w(uint8_t data)
{
dsr = (dsr & 0xfc) | (data & 3);
cur_rate = rates[data & 3];
@ -653,16 +643,6 @@ void upd765_family_device::fifo_expect(int size, bool write)
enable_transfer();
}
READ8_MEMBER(upd765_family_device::mdma_r)
{
return dma_r();
}
WRITE8_MEMBER(upd765_family_device::mdma_w)
{
dma_w(data);
}
uint8_t upd765_family_device::dma_r()
{
return fifo_pop(false);
@ -2977,7 +2957,7 @@ void mcs3201_device::device_start()
m_input_handler.resolve_safe(0);
}
READ8_MEMBER( mcs3201_device::input_r )
uint8_t mcs3201_device::input_r()
{
return m_input_handler();
}
@ -2997,7 +2977,7 @@ void tc8566af_device::device_start()
save_item(NAME(m_cr1));
}
WRITE8_MEMBER(tc8566af_device::cr1_w)
void tc8566af_device::cr1_w(uint8_t data)
{
m_cr1 = data;
@ -3007,7 +2987,7 @@ WRITE8_MEMBER(tc8566af_device::cr1_w)
}
}
WRITE8_MEMBER(upd72065_device::auxcmd_w)
void upd72065_device::auxcmd_w(uint8_t data)
{
switch(data) {
case 0x36: // reset

37
src/devices/machine/upd765.h
View File

@ -50,31 +50,24 @@ public:
virtual void map(address_map &map) override = 0;
DECLARE_READ8_MEMBER (sra_r);
DECLARE_READ8_MEMBER (srb_r);
DECLARE_READ8_MEMBER (dor_r);
DECLARE_WRITE8_MEMBER(dor_w);
DECLARE_READ8_MEMBER (tdr_r);
DECLARE_WRITE8_MEMBER(tdr_w);
uint8_t read_msr();
DECLARE_READ8_MEMBER (msr_r);
DECLARE_WRITE8_MEMBER(dsr_w);
uint8_t read_fifo();
void write_fifo(uint8_t data);
DECLARE_READ8_MEMBER (fifo_r) { return read_fifo(); }
DECLARE_WRITE8_MEMBER(fifo_w) { write_fifo(data); }
DECLARE_READ8_MEMBER (dir_r);
DECLARE_WRITE8_MEMBER(ccr_w);
uint8_t sra_r();
uint8_t srb_r();
uint8_t dor_r();
void dor_w(uint8_t data);
uint8_t tdr_r();
void tdr_w(uint8_t data);
uint8_t msr_r();
void dsr_w(uint8_t data);
uint8_t fifo_r();
void fifo_w(uint8_t data);
uint8_t dir_r() { return do_dir_r(); }
void ccr_w(uint8_t data);
virtual uint8_t do_dir_r() override;
uint8_t dma_r() override;
void dma_w(uint8_t data) override;
// Same as the previous ones, but as memory-mappable members
DECLARE_READ8_MEMBER(mdma_r);
DECLARE_WRITE8_MEMBER(mdma_w);
bool get_irq() const;
bool get_drq() const;
void tc_w(bool val) override;
@ -477,7 +470,7 @@ public:
upd72065_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
virtual void map(address_map &map) override;
DECLARE_WRITE8_MEMBER(auxcmd_w);
void auxcmd_w(uint8_t data);
};
class n82077aa_device : public upd765_family_device {
@ -528,7 +521,7 @@ public:
auto input_handler() { return m_input_handler.bind(); }
virtual void map(address_map &map) override;
DECLARE_READ8_MEMBER( input_r );
uint8_t input_r();
protected:
virtual void device_start() override;
@ -543,7 +536,7 @@ public:
virtual void map(address_map &map) override;
DECLARE_WRITE8_MEMBER(cr1_w);
void cr1_w(uint8_t data);
protected:
virtual void device_start() override;

6
src/mame/drivers/alphatro.cpp
View File

@ -763,9 +763,9 @@ MACHINE_CONFIG_START(alphatro_state::alphatro)
m_dmac->out_hrq_cb().set(FUNC(alphatro_state::hrq_w));
m_dmac->in_memr_cb().set(FUNC(alphatro_state::ram0000_r));
m_dmac->out_memw_cb().set(FUNC(alphatro_state::ram0000_w));
m_dmac->in_ior_cb<2>().set("fdc", FUNC(upd765a_device::mdma_r));
m_dmac->out_iow_cb<2>().set("fdc", FUNC(upd765a_device::mdma_w));
m_dmac->out_tc_cb().set("fdc", FUNC(upd765a_device::tc_line_w));
m_dmac->in_ior_cb<2>().set(m_fdc, FUNC(upd765a_device::dma_r));
m_dmac->out_iow_cb<2>().set(m_fdc, FUNC(upd765a_device::dma_w));
m_dmac->out_tc_cb().set(m_fdc, FUNC(upd765a_device::tc_line_w));
HD6845(config, m_crtc, 16_MHz_XTAL / 8);
m_crtc->set_screen(m_screen);

4
src/mame/drivers/dmv.cpp
View File

@ -817,8 +817,8 @@ void dmv_state::dmv(machine_config &config)
m_dmac->out_iow_callback<1>().set_log("Write DMA CH2");
m_dmac->in_ior_callback<2>().set(m_hgdc, FUNC(upd7220_device::dack_r));
m_dmac->out_iow_callback<2>().set(m_hgdc, FUNC(upd7220_device::dack_w));
m_dmac->in_ior_callback<3>().set(m_fdc, FUNC(i8272a_device::mdma_r));
m_dmac->out_iow_callback<3>().set(m_fdc, FUNC(i8272a_device::mdma_w));
m_dmac->in_ior_callback<3>().set(m_fdc, FUNC(i8272a_device::dma_r));
m_dmac->out_iow_callback<3>().set(m_fdc, FUNC(i8272a_device::dma_w));
m_dmac->out_dack_callback<3>().set(FUNC(dmv_state::dmac_dack3));
I8272A(config, m_fdc, 8'000'000, true);

4
src/mame/drivers/dps1.cpp
View File

@ -158,11 +158,11 @@ WRITE_LINE_MEMBER( dps1_state::fdc_drq_w )
address_space& mem = m_maincpu->space(AS_PROGRAM);
if (m_dma_dir)
{ // disk to mem
mem.write_byte(m_dma_adr, m_fdc->mdma_r(mem, 0));
mem.write_byte(m_dma_adr, m_fdc->dma_r());
}
else
{ // mem to disk
m_fdc->mdma_w(mem, 0, mem.read_byte(m_dma_adr));
m_fdc->dma_w(mem.read_byte(m_dma_adr));
}
m_dma_adr++;
}

4
src/mame/drivers/duet16.cpp
View File

@ -375,8 +375,8 @@ MACHINE_CONFIG_START(duet16_state::duet16)
m_dmac->out_hreq_callback().set(FUNC(duet16_state::hrq_w));
m_dmac->in_memr_callback().set(FUNC(duet16_state::dma_mem_r));
m_dmac->out_memw_callback().set(FUNC(duet16_state::dma_mem_w));
m_dmac->in_ior_callback<0>().set(m_fdc, FUNC(upd765a_device::mdma_r));
m_dmac->out_iow_callback<0>().set(m_fdc, FUNC(upd765a_device::mdma_w));
m_dmac->in_ior_callback<0>().set(m_fdc, FUNC(upd765a_device::dma_r));
m_dmac->out_iow_callback<0>().set(m_fdc, FUNC(upd765a_device::dma_w));
m_dmac->out_eop_callback().set(m_fdc, FUNC(upd765a_device::tc_line_w));
pit8253_device &bgpit(PIT8253(config, "bgpit", 0));

6
src/mame/drivers/elwro800.cpp
View File

@ -284,11 +284,11 @@ READ8_MEMBER(elwro800_state::elwro800jr_io_r)
// CSFDC
if (offset & 1)
{
return m_upd765->fifo_r(space, 0, 0xff);
return m_upd765->fifo_r();
}
else
{
return m_upd765->msr_r(space, 0, 0xff);
return m_upd765->msr_r();
}
}
else if (!BIT(cs,4))
@ -332,7 +332,7 @@ WRITE8_MEMBER(elwro800_state::elwro800jr_io_w)
// CSFDC
if (offset & 1)
{
m_upd765->fifo_w(space, 0, data, 0xff);
m_upd765->fifo_w(data);
}
}
else if (!BIT(cs,4))

2
src/mame/drivers/hec2hrp.cpp
View File

@ -110,7 +110,7 @@ void hec2hrp_state::hecdisc2_io(address_map &map)
map(0x050, 0x05f).rw(FUNC(hec2hrp_state::disc2_io50_port_r), FUNC(hec2hrp_state::disc2_io50_port_w));
// uPD765 link
map(0x060, 0x061).m(m_upd_fdc, FUNC(upd765a_device::map));
map(0x070, 0x07f).rw(m_upd_fdc, FUNC(upd765a_device::mdma_r), FUNC(upd765a_device::mdma_w));
map(0x070, 0x070).mirror(0x00f).rw(m_upd_fdc, FUNC(upd765a_device::dma_r), FUNC(upd765a_device::dma_w));
}
void hec2hrp_state::hec2hrp_mem(address_map &map)

10
src/mame/drivers/ibm6580.cpp
View File

@ -617,7 +617,7 @@ WRITE8_MEMBER(ibm6580_state::floppy_w)
break;
case 5: // 815A
m_fdc->fifo_w(space, offset, data);
m_fdc->fifo_w(data);
if (m_floppy_idle)
m_floppy_idle = false;
break;
@ -646,11 +646,11 @@ READ8_MEMBER(ibm6580_state::floppy_r)
break;
case 4: // 8158
data = m_fdc->msr_r(space, offset);
data = m_fdc->msr_r();
break;
case 5: // 815a
data = m_fdc->fifo_r(space, offset);
data = m_fdc->fifo_r();
break;
case 6: // 815c
@ -919,8 +919,8 @@ void ibm6580_state::ibm6580(machine_config &config)
m_dma8257->out_tc_cb().set(m_fdc, FUNC(upd765a_device::tc_line_w));
m_dma8257->in_memr_cb().set(FUNC(ibm6580_state::memory_read_byte));
m_dma8257->out_memw_cb().set(FUNC(ibm6580_state::memory_write_byte));
m_dma8257->in_ior_cb<0>().set(m_fdc, FUNC(upd765a_device::mdma_r));
m_dma8257->out_iow_cb<0>().set(m_fdc, FUNC(upd765a_device::mdma_w));
m_dma8257->in_ior_cb<0>().set(m_fdc, FUNC(upd765a_device::dma_r));
m_dma8257->out_iow_cb<0>().set(m_fdc, FUNC(upd765a_device::dma_w));
UPD765A(config, m_fdc, 24_MHz_XTAL / 3, false, false);
m_fdc->intrq_wr_callback().set(FUNC(ibm6580_state::floppy_intrq));

4
src/mame/drivers/interpro.cpp
View File

@ -780,8 +780,8 @@ void interpro_state::ioga(machine_config &config)
//m_ioga->dma_r_callback<0>().set(unknown); // plotter
m_ioga->dma_r_callback<1>().set(INTERPRO_SCSI_DEVICE_TAG, FUNC(ncr53c90a_device::dma_r));
m_ioga->dma_w_callback<1>().set(INTERPRO_SCSI_DEVICE_TAG, FUNC(ncr53c90a_device::dma_w));
m_ioga->dma_r_callback<2>().set(m_fdc, FUNC(upd765_family_device::mdma_r));
m_ioga->dma_w_callback<2>().set(m_fdc, FUNC(upd765_family_device::mdma_w));
m_ioga->dma_r_callback<2>().set(m_fdc, FUNC(upd765_family_device::dma_r));
m_ioga->dma_w_callback<2>().set(m_fdc, FUNC(upd765_family_device::dma_w));
m_ioga->serial_dma_r_callback<0>().set(m_scc2, FUNC(z80scc_device::db_r));
m_ioga->serial_dma_w_callback<0>().set(m_scc2, FUNC(z80scc_device::db_w));
m_ioga->serial_dma_r_callback<1>().set(m_scc1, FUNC(z80scc_device::da_r));

2
src/mame/drivers/kdt6.cpp
View File

@ -187,7 +187,7 @@ void kdt6_state::psi98_io(address_map &map)
map(0x19, 0x19).rw(m_crtc, FUNC(mc6845_device::register_r), FUNC(mc6845_device::register_w));
map(0x1c, 0x1c).w(FUNC(kdt6_state::status0_w));
map(0x1d, 0x1d).r(m_keyboard, FUNC(psi_keyboard_bus_device::key_data_r));
map(0x1e, 0x1e).rw(m_fdc, FUNC(upd765a_device::mdma_r), FUNC(upd765a_device::mdma_w));
map(0x1e, 0x1e).rw(m_fdc, FUNC(upd765a_device::dma_r), FUNC(upd765a_device::dma_w));
map(0x1f, 0x1f).w(FUNC(kdt6_state::fdc_tc_w));
map(0x20, 0x2f).rw(FUNC(kdt6_state::mapper_r), FUNC(kdt6_state::mapper_w));
map(0x30, 0x30).rw(FUNC(kdt6_state::video_data_r), FUNC(kdt6_state::video_data_w));

10
src/mame/drivers/mikromik.cpp
View File

@ -114,11 +114,11 @@ READ8_MEMBER( mm1_state::read )
case 5:
if (BIT(offset, 0))
{
data = m_fdc->fifo_r(space, 0, 0xff);
data = m_fdc->fifo_r();
}
else
{
data = m_fdc->msr_r(space, 0, 0xff);
data = m_fdc->msr_r();
}
break;
@ -183,7 +183,7 @@ WRITE8_MEMBER( mm1_state::write )
case 5:
if (BIT(offset, 0))
{
m_fdc->fifo_w(space, 0, data, 0xff);
m_fdc->fifo_w(data);
}
break;
@ -480,10 +480,10 @@ void mm1_state::mm1(machine_config &config)
m_dmac->in_memr_callback().set(FUNC(mm1_state::read));
m_dmac->out_memw_callback().set(FUNC(mm1_state::write));
m_dmac->in_ior_callback<2>().set(FUNC(mm1_state::mpsc_dack_r));
m_dmac->in_ior_callback<3>().set(m_fdc, FUNC(upd765_family_device::mdma_r));
m_dmac->in_ior_callback<3>().set(m_fdc, FUNC(upd765_family_device::dma_r));
m_dmac->out_iow_callback<0>().set(m_crtc, FUNC(i8275_device::dack_w));
m_dmac->out_iow_callback<1>().set(FUNC(mm1_state::mpsc_dack_w));
m_dmac->out_iow_callback<3>().set(m_fdc, FUNC(upd765_family_device::mdma_w));
m_dmac->out_iow_callback<3>().set(m_fdc, FUNC(upd765_family_device::dma_w));
m_dmac->out_dack_callback<3>().set(FUNC(mm1_state::dack3_w));
PIT8253(config, m_pit, 0);

6
src/mame/drivers/pasopia7.cpp
View File

@ -572,8 +572,8 @@ READ8_MEMBER( pasopia7_state::pasopia7_fdc_r )
{
switch(offset)
{
case 4: return m_fdc->msr_r(space, 0, 0xff);
case 5: return m_fdc->fifo_r(space, 0, 0xff);
case 4: return m_fdc->msr_r();
case 5: return m_fdc->fifo_r();
//case 6: bit 7 interrupt bit
}
@ -586,7 +586,7 @@ WRITE8_MEMBER( pasopia7_state::pasopia7_fdc_w )
{
case 0: m_fdc->tc_w(false); break;
case 2: m_fdc->tc_w(true); break;
case 5: m_fdc->fifo_w(space, 0, data, 0xff); break;
case 5: m_fdc->fifo_w(data); break;
case 6:
if(data & 0x80)
m_fdc->reset();

4
src/mame/drivers/pc1512.cpp
View File

@ -566,8 +566,8 @@ READ8_MEMBER( pc1640_state::io_r )
else if (addr >= 0x078 && addr <= 0x07f) { data = mouse_r(space, offset & 0x07); decoded = true; }
else if (addr >= 0x378 && addr <= 0x37b) { data = printer_r(space, offset & 0x03); decoded = true; }
else if (addr >= 0x3b0 && addr <= 0x3df) { decoded = true; }
else if (addr >= 0x3f4 && addr <= 0x3f4) { data = m_fdc->fdc->msr_r(space, offset & 0x01); decoded = true; }
else if (addr >= 0x3f5 && addr <= 0x3f5) { data = m_fdc->fdc->fifo_r(space, offset & 0x01); decoded = true; }
else if (addr >= 0x3f4 && addr <= 0x3f4) { data = m_fdc->fdc->msr_r(); decoded = true; }
else if (addr >= 0x3f5 && addr <= 0x3f5) { data = m_fdc->fdc->fifo_r(); decoded = true; }
else if (addr >= 0x3f8 && addr <= 0x3ff) { data = m_uart->ins8250_r(space, offset & 0x07); decoded = true; }
if (decoded)

8
src/mame/drivers/pc9801.cpp
View File

@ -2317,8 +2317,8 @@ void pc9801_state::pc9801_common(machine_config &config)
m_dmac->out_eop_callback().set(FUNC(pc9801_state::tc_w));
m_dmac->in_memr_callback().set(FUNC(pc9801_state::dma_read_byte));
m_dmac->out_memw_callback().set(FUNC(pc9801_state::dma_write_byte));
m_dmac->in_ior_callback<2>().set(m_fdc_2hd, FUNC(upd765a_device::mdma_r));
m_dmac->out_iow_callback<2>().set(m_fdc_2hd, FUNC(upd765a_device::mdma_w));
m_dmac->in_ior_callback<2>().set(m_fdc_2hd, FUNC(upd765a_device::dma_r));
m_dmac->out_iow_callback<2>().set(m_fdc_2hd, FUNC(upd765a_device::dma_w));
m_dmac->out_dack_callback<0>().set(FUNC(pc9801_state::dack0_w));
m_dmac->out_dack_callback<1>().set(FUNC(pc9801_state::dack1_w));
m_dmac->out_dack_callback<2>().set(FUNC(pc9801_state::dack2_w));
@ -2408,8 +2408,8 @@ void pc9801_state::pc9801(machine_config &config)
pc9801_sasi(config);
UPD1990A(config, m_rtc);
m_dmac->in_ior_callback<3>().set(m_fdc_2dd, FUNC(upd765a_device::mdma_r));
m_dmac->out_iow_callback<3>().set(m_fdc_2dd, FUNC(upd765a_device::mdma_w));
m_dmac->in_ior_callback<3>().set(m_fdc_2dd, FUNC(upd765a_device::dma_r));
m_dmac->out_iow_callback<3>().set(m_fdc_2dd, FUNC(upd765a_device::dma_w));
PALETTE(config, m_palette, FUNC(pc9801_state::pc9801_palette), 16);
}

4
src/mame/drivers/peoplepc.cpp
View File

@ -288,8 +288,8 @@ void peoplepc_state::olypeopl(machine_config &config)
m_dmac->out_tc_cb().set(FUNC(peoplepc_state::tc_w));
m_dmac->in_memr_cb().set(FUNC(peoplepc_state::memory_read_byte));
m_dmac->out_memw_cb().set(FUNC(peoplepc_state::memory_write_byte));
m_dmac->in_ior_cb<0>().set("upd765", FUNC(upd765a_device::mdma_r));
m_dmac->out_iow_cb<0>().set("upd765", FUNC(upd765a_device::mdma_w));
m_dmac->in_ior_cb<0>().set("upd765", FUNC(upd765a_device::dma_r));
m_dmac->out_iow_cb<0>().set("upd765", FUNC(upd765a_device::dma_w));
UPD765A(config, m_fdc, 8'000'000, true, true);
m_fdc->intrq_wr_callback().set("pic8259_0", FUNC(pic8259_device::ir2_w));

2
src/mame/drivers/prof180x.cpp
View File

@ -196,7 +196,7 @@ void prof180x_state::prof180x_io(address_map &map)
{
map(0x08, 0x08).mirror(0xff00).w(FUNC(prof180x_state::flr_w));
map(0x09, 0x09).select(0xff00).r(FUNC(prof180x_state::status_r));
map(0x0a, 0x0a).mirror(0xff00).rw(FDC9268_TAG, FUNC(upd765a_device::mdma_r), FUNC(upd765a_device::mdma_w));
map(0x0a, 0x0a).mirror(0xff00).rw(FDC9268_TAG, FUNC(upd765a_device::dma_r), FUNC(upd765a_device::dma_w));
map(0x0b, 0x0b).mirror(0xff00).w("cent_data_out", FUNC(output_latch_device::bus_w));
map(0x0c, 0x0d).mirror(0xff00).m(FDC9268_TAG, FUNC(upd765a_device::map));
}

4
src/mame/drivers/rc702.cpp
View File

@ -359,8 +359,8 @@ void rc702_state::rc702(machine_config &config)
m_dma->out_eop_callback().set(FUNC(rc702_state::eop_w)).invert(); // real line is active low, mame has it backwards
m_dma->in_memr_callback().set(FUNC(rc702_state::memory_read_byte));
m_dma->out_memw_callback().set(FUNC(rc702_state::memory_write_byte));
m_dma->in_ior_callback<1>().set(m_fdc, FUNC(upd765a_device::mdma_r));
m_dma->out_iow_callback<1>().set(m_fdc, FUNC(upd765a_device::mdma_w));
m_dma->in_ior_callback<1>().set(m_fdc, FUNC(upd765a_device::dma_r));
m_dma->out_iow_callback<1>().set(m_fdc, FUNC(upd765a_device::dma_w));
m_dma->out_iow_callback<2>().set("crtc", FUNC(i8275_device::dack_w));
m_dma->out_iow_callback<3>().set("crtc", FUNC(i8275_device::dack_w));
m_dma->out_dack_callback<1>().set(FUNC(rc702_state::dack1_w));

2
src/mame/drivers/rt1715.cpp
View File

@ -413,7 +413,7 @@ void rt1715_state::rt1715w_io(address_map &map)
// map(0x3c, 0x3f) // RST (RST2) -- Ru:cksetzen von Flip-Flops in V.24 (Pru:ftechnik)
// used via DMA only
map(0x40, 0x40).r(m_fdc, FUNC(i8272a_device::msr_r));
map(0x41, 0x41).rw(m_fdc, FUNC(i8272a_device::mdma_r), FUNC(i8272a_device::mdma_w));
map(0x41, 0x41).rw(m_fdc, FUNC(i8272a_device::dma_r), FUNC(i8272a_device::dma_w));
}
void rt1715_state::k7658_mem(address_map &map)

6
src/mame/drivers/specpls3.cpp
View File

@ -175,7 +175,7 @@ static const int spectrum_plus3_memory_selections[]=
WRITE8_MEMBER( spectrum_state::spectrum_plus3_port_3ffd_w )
{
if (m_floppy==1)
m_upd765->fifo_w(space, 0, data, 0xff);
m_upd765->fifo_w(data);
}
READ8_MEMBER( spectrum_state::spectrum_plus3_port_3ffd_r )
@ -183,7 +183,7 @@ READ8_MEMBER( spectrum_state::spectrum_plus3_port_3ffd_r )
if (m_floppy==0)
return 0xff;
else
return m_upd765->fifo_r(space, 0, 0xff);
return m_upd765->fifo_r();
}
@ -192,7 +192,7 @@ READ8_MEMBER( spectrum_state::spectrum_plus3_port_2ffd_r )
if (m_floppy==0)
return 0xff;
else
return m_upd765->msr_r(space, 0, 0xff);
return m_upd765->msr_r();
}

16
src/mame/drivers/sun4.cpp
View File

@ -1356,20 +1356,20 @@ READ8_MEMBER( sun4_state::fdc_r )
switch(offset)
{
case 0: // Main Status (R, 82072)
return m_fdc->msr_r(space, 0, 0xff);
return m_fdc->msr_r();
case 1: // FIFO Data Port (R, 82072)
case 5: // FIFO Data Port (R, 82077)
return m_fdc->fifo_r(space, 0, 0xff);
return m_fdc->fifo_r();
case 2: // Digital Output Register (R, 82077)
return m_fdc->dor_r(space, 0, 0xff);
return m_fdc->dor_r();
case 4: // Main Status Register (R, 82077)
return m_fdc->msr_r(space, 0, 0xff);
return m_fdc->msr_r();
case 7:// Digital Input Register (R, 82077)
return m_fdc->dir_r(space, 0, 0xff);
return m_fdc->dir_r();
default:
break;
@ -1384,16 +1384,16 @@ WRITE8_MEMBER( sun4_state::fdc_w )
{
case 0: // Data Rate Select Register (W, 82072)
case 4: // Data Rate Select Register (W, 82077)
m_fdc->dsr_w(space, 0, data, 0xff);
m_fdc->dsr_w(data);
break;
case 1: // FIFO Data Port (W, 82072)
case 5: // FIFO Data Port (W, 82077)
m_fdc->fifo_w(space, 0, data, 0xff);
m_fdc->fifo_w(data);
break;
case 7: // Configuration Control REgister (W, 82077)
m_fdc->ccr_w(space, 0, data, 0xff);
m_fdc->ccr_w(data);
break;
default:

2
src/mame/drivers/tandy2k.cpp
View File

@ -380,7 +380,7 @@ void tandy2k_state::tandy2k_io(address_map &map)
map(0x00052, 0x00052).mirror(0x8).r(FUNC(tandy2k_state::kbint_clr_r));
map(0x00060, 0x00063).mirror(0xc).rw(m_pic0, FUNC(pic8259_device::read), FUNC(pic8259_device::write)).umask16(0x00ff);
map(0x00070, 0x00073).mirror(0xc).rw(m_pic1, FUNC(pic8259_device::read), FUNC(pic8259_device::write)).umask16(0x00ff);
map(0x00080, 0x00080).mirror(0xe).rw(m_fdc, FUNC(i8272a_device::mdma_r), FUNC(i8272a_device::mdma_w));
map(0x00080, 0x00080).mirror(0xe).rw(m_fdc, FUNC(i8272a_device::dma_r), FUNC(i8272a_device::dma_w));
map(0x00100, 0x0017f).rw(m_vpac, FUNC(crt9007_device::read), FUNC(crt9007_device::write)).umask16(0x00ff);
map(0x00100, 0x0017f).w(FUNC(tandy2k_state::addr_ctrl_w)).umask16(0xff00);
map(0x00180, 0x00180).r(FUNC(tandy2k_state::hires_status_r)).umask16(0x00ff);

4
src/mame/drivers/x68k.cpp
View File

@ -1578,8 +1578,8 @@ void x68k_state::x68000_base(machine_config &config)
m_hd63450->set_burst_clocks(attotime::from_usec(2), attotime::from_nsec(450), attotime::from_nsec(50), attotime::from_nsec(50));
m_hd63450->dma_end().set(FUNC(x68k_state::dma_end));
m_hd63450->dma_error().set(FUNC(x68k_state::dma_error));
m_hd63450->dma_read<0>().set("upd72065", FUNC(upd72065_device::mdma_r));
m_hd63450->dma_write<0>().set("upd72065", FUNC(upd72065_device::mdma_w));
m_hd63450->dma_read<0>().set("upd72065", FUNC(upd72065_device::dma_r));
m_hd63450->dma_write<0>().set("upd72065", FUNC(upd72065_device::dma_w));
SCC8530(config, m_scc, 40_MHz_XTAL / 8);

6
src/mame/machine/amstrad.cpp
View File

@ -1939,10 +1939,10 @@ The exception is the case where none of b7-b0 are reset (i.e. port &FBFF), which
switch (b8b0)
{
case 0x02:
data = m_fdc->msr_r(space, 0);
data = m_fdc->msr_r();
break;
case 0x03:
data = m_fdc->fifo_r(space, 0);
data = m_fdc->fifo_r();
break;
default:
break;
@ -2158,7 +2158,7 @@ The exception is the case where none of b7-b0 are reset (i.e. port &FBFF), which
break;
case 0x03: /* Write Data register of FDC */
m_fdc->fifo_w(space, 0,data);
m_fdc->fifo_w(data);
break;
default:

4
src/mame/machine/isbc_208.cpp
View File

@ -38,8 +38,8 @@ void isbc_208_device::device_add_mconfig(machine_config &config)
m_dmac->out_eop_callback().set(FUNC(isbc_208_device::out_eop_w));
m_dmac->in_memr_callback().set(FUNC(isbc_208_device::dma_read_byte));
m_dmac->out_memw_callback().set(FUNC(isbc_208_device::dma_write_byte));
m_dmac->in_ior_callback<0>().set(m_fdc, FUNC(i8272a_device::mdma_r));
m_dmac->out_iow_callback<0>().set(m_fdc, FUNC(i8272a_device::mdma_w));
m_dmac->in_ior_callback<0>().set(m_fdc, FUNC(i8272a_device::dma_r));
m_dmac->out_iow_callback<0>().set(m_fdc, FUNC(i8272a_device::dma_w));
I8272A(config, m_fdc, 8_MHz_XTAL, true);
m_fdc->intrq_wr_callback().set(FUNC(isbc_208_device::irq_w));