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https://github.com/holub/mame
synced 2025-04-23 00:39:36 +03:00
r9751: Fix offset switching and enable write mask logging
This commit is contained in:
Brandon Munger
parent
b222e62574
commit
7f6b42536e
@ -156,32 +156,31 @@ void r9751_state::machine_reset()
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READ32_MEMBER( r9751_state::r9751_mmio_5ff_r )
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{
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UINT32 data;
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UINT32 address = offset * 4 + 0x5FF00000;
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switch(address)
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switch(offset << 2)
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{
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/* PDC HDD region (0x24, device 9) */
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case 0x5FF00824: /* HDD Command result code */
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case 0x0824: /* HDD Command result code */
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return 0x10;
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case 0x5FF03024: /* HDD SCSI command completed successfully */
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case 0x3024: /* HDD SCSI command completed successfully */
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data = 0x1;
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if(TRACE_HDC) logerror("SCSI HDD command completion status - Read: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
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if(TRACE_HDC) logerror("SCSI HDD command completion status - Read: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000);
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return data;
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/* SMIOC region (0x98, device 26) */
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case 0x5FF00898: /* Serial status or DMA status */
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case 0x0898: /* Serial status or DMA status */
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return 0x40;
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/* PDC FDD region (0xB0, device 44 */
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case 0x5FF008B0: /* FDD Command result code */
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case 0x08B0: /* FDD Command result code */
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return 0x10;
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case 0x5FF010B0: /* Clear 5FF030B0 ?? */
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case 0x10B0: /* Clear 5FF030B0 ?? */
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if(TRACE_FDC) logerror("--- FDD 0x5FF010B0 READ (0)\n");
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return 0;
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case 0x5FF030B0: /* FDD command completion status */
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case 0x30B0: /* FDD command completion status */
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data = (m_pdc->reg_p5 << 8) + m_pdc->reg_p4;
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if(TRACE_FDC) logerror("--- SCSI FDD command completion status - Read: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
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if(TRACE_FDC) logerror("--- SCSI FDD command completion status - Read: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000);
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return data;
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default:
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if(TRACE_FDC || TRACE_HDC || TRACE_SMIOC) logerror("Instruction: %08x READ MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), address, 0, mem_mask);
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if(TRACE_FDC || TRACE_HDC || TRACE_SMIOC) logerror("Instruction: %08x READ MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000, 0, mem_mask);
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return 0;
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}
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}
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@ -189,22 +188,24 @@ READ32_MEMBER( r9751_state::r9751_mmio_5ff_r )
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WRITE32_MEMBER( r9751_state::r9751_mmio_5ff_w )
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{
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UINT8 data_b0, data_b1;
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UINT32 address = offset * 4 + 0x5FF00000;
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/* Unknown mask */
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if (mem_mask != 0xFFFFFFFF)
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logerror("Mask found: %08X Register: %08X PC: %08X\n", mem_mask, offset << 2 | 0x5FF00000, space.machine().firstcpu->pc());
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switch(address)
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switch(offset << 2)
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{
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/* PDC HDD region (0x24, device 9 */
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case 0x5FF00224: /* HDD SCSI read command */
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if(TRACE_HDC) logerror("@@@ HDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
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case 0x0224: /* HDD SCSI read command */
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if(TRACE_HDC) logerror("@@@ HDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000);
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break;
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case 0x5FF08024: /* HDD SCSI read command */
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if(TRACE_HDC) logerror("@@@ HDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
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case 0x8024: /* HDD SCSI read command */
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if(TRACE_HDC) logerror("@@@ HDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000);
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break;
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case 0x5FF0C024: /* HDD SCSI read command */
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if(TRACE_HDC) logerror("@@@ HDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
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case 0xC024: /* HDD SCSI read command */
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if(TRACE_HDC) logerror("@@@ HDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000);
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break;
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/* SMIOC region (0x98, device 26) */
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case 0x5FF04098: /* Serial DMA Command */
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case 0x4098: /* Serial DMA Command */
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switch(data)
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{
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case 0x4100: /* Send byte to serial */
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@ -215,27 +216,27 @@ WRITE32_MEMBER( r9751_state::r9751_mmio_5ff_w )
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if(TRACE_SMIOC) logerror("Uknown serial DMA command: %X\n", data);
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}
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break;
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case 0x5FF0C098: /* Serial DMA output address */
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case 0xC098: /* Serial DMA output address */
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//smioc_out_addr = data * 2;
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smioc_out_addr = (smioc_dma_bank & 0x7FFFF800) | ((data&0x3FF)<<1);
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if(TRACE_SMIOC) logerror("Serial output address: %08X PC: %08X\n", smioc_out_addr, space.machine().firstcpu->pc());
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break;
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/* PDC FDD region (0xB0, device 44 */
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case 0x5FF001B0: /* FDD SCSI read command */
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if(TRACE_FDC) logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
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case 0x01B0: /* FDD SCSI read command */
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if(TRACE_FDC) logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000);
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break;
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case 0x5FF002B0: /* FDD SCSI read command */
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if(TRACE_FDC) logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
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case 0x02B0: /* FDD SCSI read command */
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if(TRACE_FDC) logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000);
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break;
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case 0x5FF004B0: /* FDD RESET PDC */
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case 0x04B0: /* FDD RESET PDC */
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if(TRACE_FDC) logerror("PDC RESET, PC: %08X\n", space.machine().firstcpu->pc());
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m_pdc->reset();
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break;
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case 0x5FF008B0: /* FDD SCSI read command */
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if(TRACE_FDC) logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
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case 0x08B0: /* FDD SCSI read command */
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if(TRACE_FDC) logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000);
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break;
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case 0x5FF041B0: /* Unknown - Probably old style commands */
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if(TRACE_FDC) logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
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case 0x41B0: /* Unknown - Probably old style commands */
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if(TRACE_FDC) logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000);
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/* Clear FDD Command completion status 0x5FF030B0 (PDC 0x4, 0x5) */
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m_pdc->reg_p4 = 0;
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@ -248,7 +249,7 @@ WRITE32_MEMBER( r9751_state::r9751_mmio_5ff_w )
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m_pdc->reg_p38 |= 0x2; /* Set bit 1 on port 38 register, PDC polls this port looking for a command */
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if(TRACE_FDC) logerror("--- FDD Old Command: %02X and %02X\n", data_b0, data_b1);
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break;
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case 0x5FF080B0: /* fdd_dest_address register */
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case 0x80B0: /* fdd_dest_address register */
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fdd_dest_address = data << 1;
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if(TRACE_FDC) logerror("--- FDD destination address: %08X\n", fdd_dest_address);
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data_b0 = data & 0xFF;
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@ -256,8 +257,8 @@ WRITE32_MEMBER( r9751_state::r9751_mmio_5ff_w )
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m_pdc->reg_p6 = data_b0;
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m_pdc->reg_p7 = data_b1;
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break;
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case 0x5FF0C0B0:
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case 0x5FF0C1B0: /* FDD command address register */
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case 0xC0B0:
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case 0xC1B0: /* FDD command address register */
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UINT32 fdd_scsi_command;
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UINT32 fdd_scsi_command2;
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unsigned char c_fdd_scsi_command[8]; // Array for SCSI command
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@ -296,7 +297,7 @@ WRITE32_MEMBER( r9751_state::r9751_mmio_5ff_w )
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break;
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default:
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if(TRACE_FDC || TRACE_HDC || TRACE_SMIOC) logerror("Instruction: %08x WRITE MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), address, data, mem_mask);
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if(TRACE_FDC || TRACE_HDC || TRACE_SMIOC) logerror("Instruction: %08x WRITE MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000, data, mem_mask);
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}
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}
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@ -306,9 +307,8 @@ WRITE32_MEMBER( r9751_state::r9751_mmio_5ff_w )
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READ32_MEMBER( r9751_state::r9751_mmio_ff01_r )
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{
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//UINT32 data;
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UINT32 address = offset * 4 + 0xFF010000;
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switch(address)
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switch(offset << 2)
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{
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default:
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//return data;
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@ -318,14 +318,16 @@ READ32_MEMBER( r9751_state::r9751_mmio_ff01_r )
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WRITE32_MEMBER( r9751_state::r9751_mmio_ff01_w )
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{
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UINT32 address = offset * 4 + 0xFF010000;
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/* Unknown mask */
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if (mem_mask != 0xFFFFFFFF)
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logerror("Mask found: %08X Register: %08X PC: %08X\n", mem_mask, offset << 2 | 0xFF010000, space.machine().firstcpu->pc());
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switch(address)
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switch(offset << 2)
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{
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case 0xFF01000C: /* FDD DMA Offset */
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case 0x000C: /* FDD DMA Offset */
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fdd_dma_bank = data;
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return;
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case 0xFF010010: /* SMIOC DMA Offset */
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case 0x0010: /* SMIOC DMA Offset */
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smioc_dma_bank = data;
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return;
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default:
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@ -336,76 +338,78 @@ WRITE32_MEMBER( r9751_state::r9751_mmio_ff01_w )
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READ32_MEMBER( r9751_state::r9751_mmio_ff05_r )
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{
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UINT32 data;
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UINT32 address = offset * 4 + 0xFF050000;
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switch(address)
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switch(offset << 2)
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{
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case 0xFF050004:
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case 0x0004:
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return reg_ff050004;
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case 0xFF050300:
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case 0x0300:
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return 0x1B | (1<<0x14);
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case 0xFF050320: /* Some type of counter */
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case 0x0320: /* Some type of counter */
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return (machine().time() - timer_32khz_last).as_ticks(32768) & 0xFFFF;
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case 0xFF050584:
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case 0x0584:
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return 0;
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case 0xFF050610:
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case 0x0610:
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return 0xabacabac;
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case 0xFF060014:
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case 0x0014:
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return 0x80;
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default:
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data = 0;
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if(TRACE_CPU_REG) logerror("Instruction: %08x READ MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), address, data, mem_mask);
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if(TRACE_CPU_REG) logerror("Instruction: %08x READ MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), offset << 2 | 0xFF050000, data, mem_mask);
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return data;
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}
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}
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WRITE32_MEMBER( r9751_state::r9751_mmio_ff05_w )
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{
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UINT32 address = offset * 4 + 0xFF050000;
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/* Unknown mask */
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if (mem_mask != 0xFFFFFFFF)
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logerror("Mask found: %08X Register: %08X PC: %08X\n", mem_mask, offset << 2 | 0xFF050000, space.machine().firstcpu->pc());
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switch(address)
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switch(offset << 2)
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{
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case 0xFF050004:
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case 0x0004:
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reg_ff050004 = data;
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return;
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case 0xFF05000C: /* CPU LED hex display indicator */
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case 0x000C: /* CPU LED hex display indicator */
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if(TRACE_LED) logerror("\n*** LED: %02x, Instruction: %08x ***\n\n", data, space.machine().firstcpu->pc());
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return;
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case 0xFF050320:
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case 0x0320:
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timer_32khz_last = machine().time();
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default:
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if(TRACE_CPU_REG) logerror("Instruction: %08x WRITE MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), address, data, mem_mask);
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if(TRACE_CPU_REG) logerror("Instruction: %08x WRITE MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), offset << 2 | 0xFF050000, data, mem_mask);
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return;
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}
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}
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READ32_MEMBER( r9751_state::r9751_mmio_fff8_r )
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{
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UINT32 data;
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UINT32 address = offset * 4 + 0xFFF80000;
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UINT32 data;
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switch(address)
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switch(offset << 2)
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{
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case 0xFFF80040:
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case 0x0040:
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return reg_fff80040;
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default:
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data = 0;
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if(TRACE_CPU_REG) logerror("Instruction: %08x READ MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), address, data, mem_mask);
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if(TRACE_CPU_REG) logerror("Instruction: %08x READ MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), offset << 2 | 0xFFF80000, data, mem_mask);
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return data;
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}
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}
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WRITE32_MEMBER( r9751_state::r9751_mmio_fff8_w )
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{
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UINT32 address = offset * 4 + 0xFFF80000;
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/* Unknown mask */
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if (mem_mask != 0xFFFFFFFF)
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logerror("Mask found: %08X Register: %08X PC: %08X\n", mem_mask, offset << 2 | 0xFFF80000, space.machine().firstcpu->pc());
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switch(address)
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switch(offset << 2)
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{
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case 0xFFF80040:
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case 0x0040:
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reg_fff80040 = data;
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return;
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default:
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if(TRACE_CPU_REG) logerror("Instruction: %08x WRITE MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), address, data, mem_mask);
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if(TRACE_CPU_REG) logerror("Instruction: %08x WRITE MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), offset << 2 | 0xFFF80000, data, mem_mask);
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}
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}
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