From 7fbd73c60c15cb5940b94036c1e1c39318216397 Mon Sep 17 00:00:00 2001 From: Aaron Giles Date: Sat, 22 Nov 2008 22:45:11 +0000 Subject: [PATCH] A few more conversions. --- src/emu/cpu/mb86233/mb86233.c | 12 +- src/emu/cpu/mb88xx/mb88xx.c | 17 +- src/emu/cpu/mc68hc11/mc68hc11.c | 47 +- src/emu/cpu/minx/minx.c | 7 +- src/emu/cpu/mips/mips3.c | 3 +- src/emu/cpu/mips/mips3com.c | 3 +- src/emu/cpu/mips/mips3com.h | 1 + src/emu/cpu/mips/r3000.c | 763 +++++++++++++++----------------- 8 files changed, 425 insertions(+), 428 deletions(-) diff --git a/src/emu/cpu/mb86233/mb86233.c b/src/emu/cpu/mb86233/mb86233.c index 4c7508577ac..a860f0860f6 100644 --- a/src/emu/cpu/mb86233/mb86233.c +++ b/src/emu/cpu/mb86233/mb86233.c @@ -13,6 +13,7 @@ ***************************************************************************/ +#define NO_LEGACY_MEMORY_HANDLERS 1 #include "mb86233.h" #include "debugger.h" @@ -45,6 +46,9 @@ typedef struct UINT32 gpr[16]; UINT32 extport[0x30]; + + const device_config *device; + const address_space *program; /* FIFO */ int fifo_wait; @@ -87,9 +91,9 @@ static int mb86233_icount; #define ALU(a) mb86233_alu(a) #define GETREPCNT() mb86233.repcnt -#define ROPCODE(a) program_decrypted_read_dword(a<<2) -#define RDMEM(a) program_read_dword_32le((a<<2)) -#define WRMEM(a,v) program_write_dword_32le((a<<2),v) +#define ROPCODE(a) memory_decrypted_read_dword(mb86233.program, a<<2) +#define RDMEM(a) memory_read_dword_32le(mb86233.program, (a<<2)) +#define WRMEM(a,v) memory_write_dword_32le(mb86233.program, (a<<2), v) /*************************************************************************** Context Switching @@ -122,6 +126,8 @@ static CPU_INIT( mb86233 ) (void)irqcallback; memset(&mb86233, 0, sizeof( MB86233_REGS ) ); + mb86233.device = device; + mb86233.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM); if ( _config ) { diff --git a/src/emu/cpu/mb88xx/mb88xx.c b/src/emu/cpu/mb88xx/mb88xx.c index 26e325745d6..6b5228192e3 100644 --- a/src/emu/cpu/mb88xx/mb88xx.c +++ b/src/emu/cpu/mb88xx/mb88xx.c @@ -13,6 +13,7 @@ ***************************************************************************/ +#define NO_LEGACY_MEMORY_HANDLERS 1 #include "debugger.h" #include "mb88xx.h" @@ -53,6 +54,9 @@ typedef struct int pending_interrupt; cpu_irq_callback irqcallback; const device_config *device; + const address_space *program; + const address_space *data; + const address_space *io; } mb88Regs; /*************************************************************************** @@ -66,13 +70,13 @@ static int mb88_icount; MACROS ***************************************************************************/ -#define READOP(a) (program_decrypted_read_byte(a)) +#define READOP(a) (memory_decrypted_read_byte(mb88.program, a)) -#define RDMEM(a) (data_read_byte_8be(a)) -#define WRMEM(a,v) (data_write_byte_8be((a), (v))) +#define RDMEM(a) (memory_read_byte_8be(mb88.data, a)) +#define WRMEM(a,v) (memory_write_byte_8be(mb88.data, (a), (v))) -#define READPORT(a) (io_read_byte_8be(a)) -#define WRITEPORT(a,v) (io_write_byte_8be((a), (v))) +#define READPORT(a) (memory_read_byte_8be(mb88.io, a)) +#define WRITEPORT(a,v) (memory_write_byte_8be(mb88.io, (a), (v))) #define TEST_ST() (mb88.st & 1) #define TEST_ZF() (mb88.zf & 1) @@ -128,6 +132,9 @@ static CPU_INIT( mb88 ) mb88.irqcallback = irqcallback; mb88.device = device; + mb88.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM); + mb88.data = memory_find_address_space(device, ADDRESS_SPACE_DATA); + mb88.io = memory_find_address_space(device, ADDRESS_SPACE_IO); state_save_register_item("mb88", device->tag, 0, mb88.PC); state_save_register_item("mb88", device->tag, 0, mb88.PA); diff --git a/src/emu/cpu/mc68hc11/mc68hc11.c b/src/emu/cpu/mc68hc11/mc68hc11.c index 8d5095b000f..924e1f73181 100644 --- a/src/emu/cpu/mc68hc11/mc68hc11.c +++ b/src/emu/cpu/mc68hc11/mc68hc11.c @@ -4,6 +4,7 @@ Written by Ville Linde */ +#define NO_LEGACY_MEMORY_HANDLERS 1 #include "debugger.h" #include "mc68hc11.h" @@ -53,6 +54,8 @@ typedef struct cpu_irq_callback irq_callback; const device_config *device; + const address_space *program; + const address_space *io; int icount; int ram_position; int reg_position; @@ -74,7 +77,7 @@ static UINT8 hc11_regs_r(UINT32 address) switch(reg) { case 0x00: /* PORTA */ - return io_read_byte(MC68HC11_IO_PORTA); + return memory_read_byte(hc11.io, MC68HC11_IO_PORTA); case 0x01: /* DDRA */ return 0; case 0x09: /* DDRD */ @@ -87,44 +90,44 @@ static UINT8 hc11_regs_r(UINT32 address) { if (hc11.adctl & 0x10) { - return io_read_byte((hc11.adctl & 0x4) + MC68HC11_IO_AD0); + return memory_read_byte(hc11.io, (hc11.adctl & 0x4) + MC68HC11_IO_AD0); } else { - return io_read_byte((hc11.adctl & 0x7) + MC68HC11_IO_AD0); + return memory_read_byte(hc11.io, (hc11.adctl & 0x7) + MC68HC11_IO_AD0); } } case 0x32: /* ADR2 */ { if (hc11.adctl & 0x10) { - return io_read_byte((hc11.adctl & 0x4) + MC68HC11_IO_AD1); + return memory_read_byte(hc11.io, (hc11.adctl & 0x4) + MC68HC11_IO_AD1); } else { - return io_read_byte((hc11.adctl & 0x7) + MC68HC11_IO_AD0); + return memory_read_byte(hc11.io, (hc11.adctl & 0x7) + MC68HC11_IO_AD0); } } case 0x33: /* ADR3 */ { if (hc11.adctl & 0x10) { - return io_read_byte((hc11.adctl & 0x4) + MC68HC11_IO_AD2); + return memory_read_byte(hc11.io, (hc11.adctl & 0x4) + MC68HC11_IO_AD2); } else { - return io_read_byte((hc11.adctl & 0x7) + MC68HC11_IO_AD0); + return memory_read_byte(hc11.io, (hc11.adctl & 0x7) + MC68HC11_IO_AD0); } } case 0x34: /* ADR4 */ { if (hc11.adctl & 0x10) { - return io_read_byte((hc11.adctl & 0x4) + MC68HC11_IO_AD3); + return memory_read_byte(hc11.io, (hc11.adctl & 0x4) + MC68HC11_IO_AD3); } else { - return io_read_byte((hc11.adctl & 0x7) + MC68HC11_IO_AD0); + return memory_read_byte(hc11.io, (hc11.adctl & 0x7) + MC68HC11_IO_AD0); } } case 0x38: /* OPT2 */ @@ -140,9 +143,9 @@ static UINT8 hc11_regs_r(UINT32 address) case 0x74: /* SCSR1 */ return 0x40; case 0x7c: /* PORTH */ - return io_read_byte(MC68HC11_IO_PORTH); + return memory_read_byte(hc11.io, MC68HC11_IO_PORTH); case 0x7e: /* PORTG */ - return io_read_byte(MC68HC11_IO_PORTG); + return memory_read_byte(hc11.io, MC68HC11_IO_PORTG); case 0x7f: /* DDRG */ return 0; @@ -151,7 +154,7 @@ static UINT8 hc11_regs_r(UINT32 address) case 0x89: /* SPSR2 */ return 0x80; case 0x8a: /* SPDR2 */ - return io_read_byte(MC68HC11_IO_SPI2_DATA); + return memory_read_byte(hc11.io, MC68HC11_IO_SPI2_DATA); case 0x8b: /* OPT4 */ return 0; @@ -168,13 +171,13 @@ static void hc11_regs_w(UINT32 address, UINT8 value) switch(reg) { case 0x00: /* PORTA */ - io_write_byte(MC68HC11_IO_PORTA, value); + memory_write_byte(hc11.io, MC68HC11_IO_PORTA, value); return; case 0x01: /* DDRA */ //mame_printf_debug("HC11: ddra = %02X\n", value); return; case 0x08: /* PORTD */ - io_write_byte(MC68HC11_IO_PORTD, value); + memory_write_byte(hc11.io, MC68HC11_IO_PORTD, value); return; case 0x09: /* DDRD */ //mame_printf_debug("HC11: ddrd = %02X\n", value); @@ -222,13 +225,13 @@ static void hc11_regs_w(UINT32 address, UINT8 value) case 0x77: /* SCDRL */ return; case 0x7c: /* PORTH */ - io_write_byte(MC68HC11_IO_PORTH, value); + memory_write_byte(hc11.io, MC68HC11_IO_PORTH, value); return; case 0x7d: /* DDRH */ //mame_printf_debug("HC11: ddrh = %02X at %04X\n", value, hc11.pc); return; case 0x7e: /* PORTG */ - io_write_byte(MC68HC11_IO_PORTG, value); + memory_write_byte(hc11.io, MC68HC11_IO_PORTG, value); return; case 0x7f: /* DDRG */ //mame_printf_debug("HC11: ddrg = %02X at %04X\n", value, hc11.pc); @@ -239,7 +242,7 @@ static void hc11_regs_w(UINT32 address, UINT8 value) case 0x89: /* SPSR2 */ return; case 0x8a: /* SPDR2 */ - io_write_byte(MC68HC11_IO_SPI2_DATA, value); + memory_write_byte(hc11.io, MC68HC11_IO_SPI2_DATA, value); return; case 0x8b: /* OPT4 */ @@ -253,13 +256,13 @@ static void hc11_regs_w(UINT32 address, UINT8 value) INLINE UINT8 FETCH(void) { - return program_decrypted_read_byte(hc11.pc++); + return memory_decrypted_read_byte(hc11.program, hc11.pc++); } INLINE UINT16 FETCH16(void) { UINT16 w; - w = (program_decrypted_read_byte(hc11.pc) << 8) | (program_decrypted_read_byte(hc11.pc+1)); + w = (memory_decrypted_read_byte(hc11.program, hc11.pc) << 8) | (memory_decrypted_read_byte(hc11.program, hc11.pc+1)); hc11.pc += 2; return w; } @@ -274,7 +277,7 @@ INLINE UINT8 READ8(UINT32 address) { return internal_ram[address-hc11.ram_position]; } - return program_read_byte(address); + return memory_read_byte(hc11.program, address); } INLINE void WRITE8(UINT32 address, UINT8 value) @@ -289,7 +292,7 @@ INLINE void WRITE8(UINT32 address, UINT8 value) internal_ram[address-hc11.ram_position] = value; return; } - program_write_byte(address, value); + memory_write_byte(hc11.program, address, value); } INLINE UINT16 READ16(UINT32 address) @@ -351,6 +354,8 @@ static CPU_INIT( hc11 ) hc11.ram_position = 0x100; hc11.irq_callback = irqcallback; hc11.device = device; + hc11.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM); + hc11.io = memory_find_address_space(device, ADDRESS_SPACE_IO); } static CPU_RESET( hc11 ) diff --git a/src/emu/cpu/minx/minx.c b/src/emu/cpu/minx/minx.c index 6678effd942..e160907ee47 100644 --- a/src/emu/cpu/minx/minx.c +++ b/src/emu/cpu/minx/minx.c @@ -42,6 +42,7 @@ TODO: */ +#define NO_LEGACY_MEMORY_HANDLERS 1 #include "minx.h" #include "debugger.h" #include "deprecat.h" @@ -85,13 +86,14 @@ typedef struct { UINT8 interrupt_pending; cpu_irq_callback irq_callback; const device_config *device; + const address_space *program; } minx_regs; static minx_regs regs; static int minx_icount; -#define RD(offset) program_read_byte_8be( offset ) -#define WR(offset,data) program_write_byte_8be( offset, data ) +#define RD(offset) memory_read_byte_8be( regs.program, offset ) +#define WR(offset,data) memory_write_byte_8be( regs.program, offset, data ) #define GET_MINX_PC ( ( regs.PC & 0x8000 ) ? ( regs.V << 15 ) | (regs.PC & 0x7FFF ) : regs.PC ) @@ -112,6 +114,7 @@ static CPU_INIT( minx ) { regs.irq_callback = irqcallback; regs.device = device; + regs.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM); if ( device->static_config != NULL ) { } diff --git a/src/emu/cpu/mips/mips3.c b/src/emu/cpu/mips/mips3.c index 0a312cae0ef..ce736b73732 100644 --- a/src/emu/cpu/mips/mips3.c +++ b/src/emu/cpu/mips/mips3.c @@ -9,6 +9,7 @@ ***************************************************************************/ +#define NO_LEGACY_MEMORY_HANDLERS 1 #include "debugger.h" #include "mips3com.h" @@ -150,7 +151,7 @@ static mips3_regs mips3; MEMORY ACCESSORS ***************************************************************************/ -#define ROPCODE(pc) program_decrypted_read_dword(pc) +#define ROPCODE(pc) memory_decrypted_read_dword(mips3.core.program, pc) diff --git a/src/emu/cpu/mips/mips3com.c b/src/emu/cpu/mips/mips3com.c index 396f97d5744..7ebe2c079ea 100644 --- a/src/emu/cpu/mips/mips3com.c +++ b/src/emu/cpu/mips/mips3com.c @@ -83,12 +83,13 @@ void mips3com_init(mips3_state *mips, mips3_flavor flavor, int bigendian, const mips->cpu_clock = clock; mips->irq_callback = irqcallback; mips->device = device; + mips->program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM); mips->icache_size = config->icache; mips->dcache_size = config->dcache; mips->system_clock = config->system_clock; /* set up the endianness */ - mips->memory = cpu_get_address_space(device, ADDRESS_SPACE_PROGRAM)->accessors; + mips->memory = mips->program->accessors; /* allocate the virtual TLB */ mips->vtlb = vtlb_alloc(device, ADDRESS_SPACE_PROGRAM, 2 * MIPS3_TLB_ENTRIES + 2, 0); diff --git a/src/emu/cpu/mips/mips3com.h b/src/emu/cpu/mips/mips3com.h index 0544e6f0b66..2e351e88b6e 100644 --- a/src/emu/cpu/mips/mips3com.h +++ b/src/emu/cpu/mips/mips3com.h @@ -196,6 +196,7 @@ struct _mips3_state mips3_flavor flavor; cpu_irq_callback irq_callback; const device_config *device; + const address_space *program; UINT32 system_clock; UINT32 cpu_clock; UINT64 count_zero_time; diff --git a/src/emu/cpu/mips/r3000.c b/src/emu/cpu/mips/r3000.c index 8a2fef78d99..94699333cb4 100644 --- a/src/emu/cpu/mips/r3000.c +++ b/src/emu/cpu/mips/r3000.c @@ -6,6 +6,7 @@ ***************************************************************************/ +#define NO_LEGACY_MEMORY_HANDLERS 1 #include "debugger.h" #include "r3000.h" @@ -80,33 +81,31 @@ #define RDREG ((op >> 11) & 31) #define SHIFT ((op >> 6) & 31) -#define RSVAL (r3000->r[RSREG]) -#define RTVAL (r3000->r[RTREG]) -#define RDVAL (r3000->r[RDREG]) +#define RSVAL r[RSREG] +#define RTVAL r[RTREG] +#define RDVAL r[RDREG] #define SIMMVAL ((INT16)op) #define UIMMVAL ((UINT16)op) #define LIMMVAL (op & 0x03ffffff) -#define ADDPC(x) r3000->nextpc = r3000->pc + ((x) << 2) -#define ADDPCL(x,l) { r3000->nextpc = r3000->pc + ((x) << 2); r3000->r[l] = r3000->pc + 4; } -#define ABSPC(x) r3000->nextpc = (r3000->pc & 0xf0000000) | ((x) << 2) -#define ABSPCL(x,l) { r3000->nextpc = (r3000->pc & 0xf0000000) | ((x) << 2); r3000->r[l] = r3000->pc + 4; } -#define SETPC(x) r3000->nextpc = (x) -#define SETPCL(x,l) { r3000->nextpc = (x); r3000->r[l] = r3000->pc + 4; } +#define ADDPC(R,x) do { (R)->nextpc = (R)->pc + ((x) << 2); } while (0) +#define ADDPCL(R,x,l) do { (R)->nextpc = (R)->pc + ((x) << 2); (R)->r[l] = (R)->pc + 4; } while (0) +#define ABSPC(R,x) do { (R)->nextpc = ((R)->pc & 0xf0000000) | ((x) << 2); } while (0) +#define ABSPCL(R,x,l) do { (R)->nextpc = ((R)->pc & 0xf0000000) | ((x) << 2); (R)->r[l] = (R)->pc + 4; } while (0) +#define SETPC(R,x) do { (R)->nextpc = (x); } while (0) +#define SETPCL(R,x,l) do { (R)->nextpc = (x); (R)->r[l] = (R)->pc + 4; } while (0) -#define RBYTE(x) (*r3000->cur.readbyte)(x) -#define RWORD(x) (*r3000->cur.readword)(x) -#define RLONG(x) (*r3000->cur.readlong)(x) +#define RBYTE(R,x) (*(R)->cur.read_byte)((R)->program, x) +#define RWORD(R,x) (*(R)->cur.read_word)((R)->program, x) +#define RLONG(R,x) (*(R)->cur.read_dword)((R)->program, x) -#define WBYTE(x,v) (*r3000->cur.writebyte)(x,v) -#define WWORD(x,v) (*r3000->cur.writeword)(x,v) -#define WLONG(x,v) (*r3000->cur.writelong)(x,v) +#define WBYTE(R,x,v) (*(R)->cur.write_byte)((R)->program, x, v) +#define WWORD(R,x,v) (*(R)->cur.write_word)((R)->program, x, v) +#define WLONG(R,x,v) (*(R)->cur.write_dword)((R)->program, x, v) -#define HIVAL r3000->hi -#define LOVAL r3000->lo -#define SR r3000->cpr[0][COP0_Status] -#define CAUSE r3000->cpr[0][COP0_Cause] +#define SR cpr[0][COP0_Status] +#define CAUSE cpr[0][COP0_Cause] @@ -114,17 +113,6 @@ STRUCTURES & TYPEDEFS ***************************************************************************/ -/* memory access function table */ -typedef struct -{ - UINT8 (*readbyte)(offs_t); - UINT16 (*readword)(offs_t); - UINT32 (*readlong)(offs_t); - void (*writebyte)(offs_t, UINT8); - void (*writeword)(offs_t, UINT16); - void (*writelong)(offs_t, UINT32); -} memory_accessors; - /* R3000 Registers */ typedef struct _r3000_state r3000_state; struct _r3000_state @@ -149,6 +137,7 @@ struct _r3000_state int hasfpu; cpu_irq_callback irq_callback; const device_config *device; + const address_space *program; /* endian-dependent load/store */ void (*lwl)(r3000_state *r3000, UINT32 op); @@ -158,9 +147,9 @@ struct _r3000_state /* memory accesses */ UINT8 bigendian; - memory_accessors cur; - const memory_accessors *memory_hand; - const memory_accessors *cache_hand; + data_accessors cur; + const data_accessors *memory_hand; + const data_accessors *cache_hand; /* cache memory */ UINT32 * cache; @@ -187,49 +176,36 @@ static void lwr_le(r3000_state *r3000, UINT32 op); static void swl_le(r3000_state *r3000, UINT32 op); static void swr_le(r3000_state *r3000, UINT32 op); -static UINT8 readcache_be(offs_t offset); -static UINT16 readcache_be_word(offs_t offset); -static UINT32 readcache_be_dword(offs_t offset); -static void writecache_be(offs_t offset, UINT8 data); -static void writecache_be_word(offs_t offset, UINT16 data); -static void writecache_be_dword(offs_t offset, UINT32 data); +static UINT8 readcache_be(const address_space *space, offs_t offset); +static UINT16 readcache_be_word(const address_space *space, offs_t offset); +static UINT32 readcache_be_dword(const address_space *space, offs_t offset); +static void writecache_be(const address_space *space, offs_t offset, UINT8 data); +static void writecache_be_word(const address_space *space, offs_t offset, UINT16 data); +static void writecache_be_dword(const address_space *space, offs_t offset, UINT32 data); + +static UINT8 readcache_le(const address_space *space, offs_t offset); +static UINT16 readcache_le_word(const address_space *space, offs_t offset); +static UINT32 readcache_le_dword(const address_space *space, offs_t offset); +static void writecache_le(const address_space *space, offs_t offset, UINT8 data); +static void writecache_le_word(const address_space *space, offs_t offset, UINT16 data); +static void writecache_le_dword(const address_space *space, offs_t offset, UINT32 data); -static UINT8 readcache_le(offs_t offset); -static UINT16 readcache_le_word(offs_t offset); -static UINT32 readcache_le_dword(offs_t offset); -static void writecache_le(offs_t offset, UINT8 data); -static void writecache_le_word(offs_t offset, UINT16 data); -static void writecache_le_dword(offs_t offset, UINT32 data); /*************************************************************************** PRIVATE GLOBAL VARIABLES ***************************************************************************/ -static void *token; - -static const memory_accessors be_memory = +static const data_accessors be_cache = { - program_read_byte_32be, program_read_word_32be, program_read_dword_32be, - program_write_byte_32be, program_write_word_32be, program_write_dword_32be + readcache_be, readcache_be_word, NULL, readcache_be_dword, NULL, NULL, NULL, + writecache_be, writecache_be_word, NULL, writecache_be_dword, NULL, NULL, NULL }; -static const memory_accessors le_memory = +static const data_accessors le_cache = { - program_read_byte_32le, program_read_word_32le, program_read_dword_32le, - program_write_byte_32le, program_write_word_32le, program_write_dword_32le -}; - -static const memory_accessors be_cache = -{ - readcache_be, readcache_be_word, readcache_be_dword, - writecache_be, writecache_be_word, writecache_be_dword -}; - -static const memory_accessors le_cache = -{ - readcache_le, readcache_le_word, readcache_le_dword, - writecache_le, writecache_le_word, writecache_le_dword + readcache_le, readcache_le_word, NULL, readcache_le_dword, NULL, NULL, NULL, + writecache_le, writecache_le_word, NULL, writecache_le_dword, NULL, NULL, NULL }; @@ -238,7 +214,7 @@ static const memory_accessors le_cache = MEMORY ACCESSORS ***************************************************************************/ -#define ROPCODE(pc) program_decrypted_read_dword(pc) +#define ROPCODE(R,pc) memory_decrypted_read_dword((R)->program, pc) @@ -252,21 +228,21 @@ INLINE void generate_exception(r3000_state *r3000, int exception) r3000->cpr[0][COP0_EPC] = r3000->pc; /* put the cause in the low 8 bits and clear the branch delay flag */ - CAUSE = (CAUSE & ~0x800000ff) | (exception << 2); + r3000->CAUSE = (r3000->CAUSE & ~0x800000ff) | (exception << 2); /* if we were in a branch delay slot, adjust */ if (r3000->nextpc != ~0) { r3000->nextpc = ~0; r3000->cpr[0][COP0_EPC] -= 4; - CAUSE |= 0x80000000; + r3000->CAUSE |= 0x80000000; } /* shift the exception bits */ - SR = (SR & 0xffffffc0) | ((SR << 2) & 0x3c); + r3000->SR = (r3000->SR & 0xffffffc0) | ((r3000->SR << 2) & 0x3c); /* based on the BEV bit, we either go to ROM or RAM */ - r3000->pc = (SR & SR_BEV) ? 0xbfc00000 : 0x80000000; + r3000->pc = (r3000->SR & SR_BEV) ? 0xbfc00000 : 0x80000000; /* most exceptions go to offset 0x180, except for TLB stuff */ if (exception >= EXCEPTION_TLBMOD && exception <= EXCEPTION_TLBSTORE) @@ -292,7 +268,7 @@ INLINE void invalid_instruction(r3000_state *r3000, UINT32 op) static void check_irqs(r3000_state *r3000) { - if ((CAUSE & SR & 0xff00) && (SR & SR_IEc)) + if ((r3000->CAUSE & r3000->SR & 0xff00) && (r3000->SR & SR_IEc)) generate_exception(r3000, EXCEPTION_INTERRUPT); } @@ -300,9 +276,9 @@ static void check_irqs(r3000_state *r3000) static void set_irq_line(r3000_state *r3000, int irqline, int state) { if (state != CLEAR_LINE) - CAUSE |= 0x400 << irqline; + r3000->CAUSE |= 0x400 << irqline; else - CAUSE &= ~(0x400 << irqline); + r3000->CAUSE &= ~(0x400 << irqline); check_irqs(r3000); } @@ -332,8 +308,6 @@ static CPU_INIT( r3000 ) const r3000_cpu_core *configdata = device->static_config; r3000_state *r3000 = device->token; - token = device->token; // temporary - /* allocate memory */ r3000->icache = auto_malloc(configdata->icache); r3000->dcache = auto_malloc(configdata->dcache); @@ -344,6 +318,7 @@ static CPU_INIT( r3000 ) r3000->irq_callback = irqcallback; r3000->device = device; + r3000->program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM); } @@ -353,7 +328,7 @@ static void r3000_reset(r3000_state *r3000, int bigendian) r3000->bigendian = bigendian; if (r3000->bigendian) { - r3000->memory_hand = &be_memory; + r3000->memory_hand = &r3000->program->accessors; r3000->cache_hand = &be_cache; r3000->lwl = lwl_be; r3000->lwr = lwr_be; @@ -362,7 +337,7 @@ static void r3000_reset(r3000_state *r3000, int bigendian) } else { - r3000->memory_hand = &le_memory; + r3000->memory_hand = &r3000->program->accessors; r3000->cache_hand = &le_cache; r3000->lwl = lwl_le; r3000->lwr = lwr_le; @@ -413,7 +388,7 @@ INLINE void set_cop0_reg(r3000_state *r3000, int idx, UINT32 val) { if (idx == COP0_Cause) { - CAUSE = (CAUSE & 0xfc00) | (val & ~0xfc00); + r3000->CAUSE = (r3000->CAUSE & 0xfc00) | (val & ~0xfc00); /* update interrupts -- software ints can occur this way */ check_irqs(r3000); @@ -461,20 +436,20 @@ INLINE void set_cop0_creg(r3000_state *r3000, int idx, UINT32 val) INLINE void handle_cop0(r3000_state *r3000, UINT32 op) { - if (!(SR & SR_COP0) && (SR & SR_KUc)) + if (!(r3000->SR & SR_COP0) && (r3000->SR & SR_KUc)) generate_exception(r3000, EXCEPTION_BADCOP); switch (RSREG) { - case 0x00: /* MFCz */ if (RTREG) RTVAL = get_cop0_reg(r3000, RDREG); break; - case 0x02: /* CFCz */ if (RTREG) RTVAL = get_cop0_creg(r3000, RDREG); break; - case 0x04: /* MTCz */ set_cop0_reg(r3000, RDREG, RTVAL); break; - case 0x06: /* CTCz */ set_cop0_creg(r3000, RDREG, RTVAL); break; + case 0x00: /* MFCz */ if (RTREG) r3000->RTVAL = get_cop0_reg(r3000, RDREG); break; + case 0x02: /* CFCz */ if (RTREG) r3000->RTVAL = get_cop0_creg(r3000, RDREG); break; + case 0x04: /* MTCz */ set_cop0_reg(r3000, RDREG, r3000->RTVAL); break; + case 0x06: /* CTCz */ set_cop0_creg(r3000, RDREG, r3000->RTVAL); break; case 0x08: /* BC */ switch (RTREG) { - case 0x00: /* BCzF */ if (!r3000->cf[0]) ADDPC(SIMMVAL); break; - case 0x01: /* BCzF */ if (r3000->cf[0]) ADDPC(SIMMVAL); break; + case 0x00: /* BCzF */ if (!r3000->cf[0]) ADDPC(r3000, SIMMVAL); break; + case 0x01: /* BCzF */ if (r3000->cf[0]) ADDPC(r3000, SIMMVAL); break; case 0x02: /* BCzFL */ invalid_instruction(r3000, op); break; case 0x03: /* BCzTL */ invalid_instruction(r3000, op); break; default: invalid_instruction(r3000, op); break; @@ -502,7 +477,7 @@ INLINE void handle_cop0(r3000_state *r3000, UINT32 op) case 0x02: /* TLBWI */ break; case 0x06: /* TLBWR */ break; case 0x08: /* TLBP */ break; - case 0x10: /* RFE */ SR = (SR & 0xfffffff0) | ((SR >> 2) & 0x0f); break; + case 0x10: /* RFE */ r3000->SR = (r3000->SR & 0xfffffff0) | ((r3000->SR >> 2) & 0x0f); break; case 0x18: /* ERET */ invalid_instruction(r3000, op); break; default: invalid_instruction(r3000, op); break; } @@ -539,22 +514,22 @@ INLINE void set_cop1_creg(r3000_state *r3000, int idx, UINT32 val) INLINE void handle_cop1(r3000_state *r3000, UINT32 op) { - if (!(SR & SR_COP1)) + if (!(r3000->SR & SR_COP1)) generate_exception(r3000, EXCEPTION_BADCOP); if (!r3000->hasfpu) return; switch (RSREG) { - case 0x00: /* MFCz */ if (RTREG) RTVAL = get_cop1_reg(r3000, RDREG); break; - case 0x02: /* CFCz */ if (RTREG) RTVAL = get_cop1_creg(r3000, RDREG); break; - case 0x04: /* MTCz */ set_cop1_reg(r3000, RDREG, RTVAL); break; - case 0x06: /* CTCz */ set_cop1_creg(r3000, RDREG, RTVAL); break; + case 0x00: /* MFCz */ if (RTREG) r3000->RTVAL = get_cop1_reg(r3000, RDREG); break; + case 0x02: /* CFCz */ if (RTREG) r3000->RTVAL = get_cop1_creg(r3000, RDREG); break; + case 0x04: /* MTCz */ set_cop1_reg(r3000, RDREG, r3000->RTVAL); break; + case 0x06: /* CTCz */ set_cop1_creg(r3000, RDREG, r3000->RTVAL); break; case 0x08: /* BC */ switch (RTREG) { - case 0x00: /* BCzF */ if (!r3000->cf[1]) ADDPC(SIMMVAL); break; - case 0x01: /* BCzF */ if (r3000->cf[1]) ADDPC(SIMMVAL); break; + case 0x00: /* BCzF */ if (!r3000->cf[1]) ADDPC(r3000, SIMMVAL); break; + case 0x01: /* BCzF */ if (r3000->cf[1]) ADDPC(r3000, SIMMVAL); break; case 0x02: /* BCzFL */ invalid_instruction(r3000, op); break; case 0x03: /* BCzTL */ invalid_instruction(r3000, op); break; default: invalid_instruction(r3000, op); break; @@ -608,20 +583,20 @@ INLINE void set_cop2_creg(r3000_state *r3000, int idx, UINT32 val) INLINE void handle_cop2(r3000_state *r3000, UINT32 op) { - if (!(SR & SR_COP2)) + if (!(r3000->SR & SR_COP2)) generate_exception(r3000, EXCEPTION_BADCOP); switch (RSREG) { - case 0x00: /* MFCz */ if (RTREG) RTVAL = get_cop2_reg(r3000, RDREG); break; - case 0x02: /* CFCz */ if (RTREG) RTVAL = get_cop2_creg(r3000, RDREG); break; - case 0x04: /* MTCz */ set_cop2_reg(r3000, RDREG, RTVAL); break; - case 0x06: /* CTCz */ set_cop2_creg(r3000, RDREG, RTVAL); break; + case 0x00: /* MFCz */ if (RTREG) r3000->RTVAL = get_cop2_reg(r3000, RDREG); break; + case 0x02: /* CFCz */ if (RTREG) r3000->RTVAL = get_cop2_creg(r3000, RDREG); break; + case 0x04: /* MTCz */ set_cop2_reg(r3000, RDREG, r3000->RTVAL); break; + case 0x06: /* CTCz */ set_cop2_creg(r3000, RDREG, r3000->RTVAL); break; case 0x08: /* BC */ switch (RTREG) { - case 0x00: /* BCzF */ if (!r3000->cf[2]) ADDPC(SIMMVAL); break; - case 0x01: /* BCzF */ if (r3000->cf[2]) ADDPC(SIMMVAL); break; + case 0x00: /* BCzF */ if (!r3000->cf[2]) ADDPC(r3000, SIMMVAL); break; + case 0x01: /* BCzF */ if (r3000->cf[2]) ADDPC(r3000, SIMMVAL); break; case 0x02: /* BCzFL */ invalid_instruction(r3000, op); break; case 0x03: /* BCzTL */ invalid_instruction(r3000, op); break; default: invalid_instruction(r3000, op); break; @@ -675,20 +650,20 @@ INLINE void set_cop3_creg(r3000_state *r3000, int idx, UINT32 val) INLINE void handle_cop3(r3000_state *r3000, UINT32 op) { - if (!(SR & SR_COP3)) + if (!(r3000->SR & SR_COP3)) generate_exception(r3000, EXCEPTION_BADCOP); switch (RSREG) { - case 0x00: /* MFCz */ if (RTREG) RTVAL = get_cop3_reg(r3000, RDREG); break; - case 0x02: /* CFCz */ if (RTREG) RTVAL = get_cop3_creg(r3000, RDREG); break; - case 0x04: /* MTCz */ set_cop3_reg(r3000, RDREG, RTVAL); break; - case 0x06: /* CTCz */ set_cop3_creg(r3000, RDREG, RTVAL); break; + case 0x00: /* MFCz */ if (RTREG) r3000->RTVAL = get_cop3_reg(r3000, RDREG); break; + case 0x02: /* CFCz */ if (RTREG) r3000->RTVAL = get_cop3_creg(r3000, RDREG); break; + case 0x04: /* MTCz */ set_cop3_reg(r3000, RDREG, r3000->RTVAL); break; + case 0x06: /* CTCz */ set_cop3_creg(r3000, RDREG, r3000->RTVAL); break; case 0x08: /* BC */ switch (RTREG) { - case 0x00: /* BCzF */ if (!r3000->cf[3]) ADDPC(SIMMVAL); break; - case 0x01: /* BCzF */ if (r3000->cf[3]) ADDPC(SIMMVAL); break; + case 0x00: /* BCzF */ if (!r3000->cf[3]) ADDPC(r3000, SIMMVAL); break; + case 0x01: /* BCzF */ if (r3000->cf[3]) ADDPC(r3000, SIMMVAL); break; case 0x02: /* BCzFL */ invalid_instruction(r3000, op); break; case 0x03: /* BCzTL */ invalid_instruction(r3000, op); break; default: invalid_instruction(r3000, op); break; @@ -724,8 +699,6 @@ static CPU_EXECUTE( r3000 ) { r3000_state *r3000 = device->token; - token = device->token; - /* count cycles and interrupt cycles */ r3000->icount = cycles; r3000->icount -= r3000->interrupt_cycles; @@ -747,7 +720,7 @@ static CPU_EXECUTE( r3000 ) debugger_instruction_hook(device, r3000->pc); /* instruction fetch */ - op = ROPCODE(r3000->pc); + op = ROPCODE(r3000, r3000->pc); /* adjust for next PC */ if (r3000->nextpc != ~0) @@ -765,151 +738,151 @@ static CPU_EXECUTE( r3000 ) case 0x00: /* SPECIAL */ switch (op & 63) { - case 0x00: /* SLL */ if (RDREG) RDVAL = RTVAL << SHIFT; break; - case 0x02: /* SRL */ if (RDREG) RDVAL = RTVAL >> SHIFT; break; - case 0x03: /* SRA */ if (RDREG) RDVAL = (INT32)RTVAL >> SHIFT; break; - case 0x04: /* SLLV */ if (RDREG) RDVAL = RTVAL << (RSVAL & 31); break; - case 0x06: /* SRLV */ if (RDREG) RDVAL = RTVAL >> (RSVAL & 31); break; - case 0x07: /* SRAV */ if (RDREG) RDVAL = (INT32)RTVAL >> (RSVAL & 31); break; - case 0x08: /* JR */ SETPC(RSVAL); break; - case 0x09: /* JALR */ SETPCL(RSVAL,RDREG); break; - case 0x0c: /* SYSCALL */ generate_exception(r3000, EXCEPTION_SYSCALL); break; - case 0x0d: /* BREAK */ generate_exception(r3000, EXCEPTION_BREAK); break; - case 0x0f: /* SYNC */ invalid_instruction(r3000, op); break; - case 0x10: /* MFHI */ if (RDREG) RDVAL = HIVAL; break; - case 0x11: /* MTHI */ HIVAL = RSVAL; break; - case 0x12: /* MFLO */ if (RDREG) RDVAL = LOVAL; break; - case 0x13: /* MTLO */ LOVAL = RSVAL; break; + case 0x00: /* SLL */ if (RDREG) r3000->RDVAL = r3000->RTVAL << SHIFT; break; + case 0x02: /* SRL */ if (RDREG) r3000->RDVAL = r3000->RTVAL >> SHIFT; break; + case 0x03: /* SRA */ if (RDREG) r3000->RDVAL = (INT32)r3000->RTVAL >> SHIFT; break; + case 0x04: /* SLLV */ if (RDREG) r3000->RDVAL = r3000->RTVAL << (r3000->RSVAL & 31); break; + case 0x06: /* SRLV */ if (RDREG) r3000->RDVAL = r3000->RTVAL >> (r3000->RSVAL & 31); break; + case 0x07: /* SRAV */ if (RDREG) r3000->RDVAL = (INT32)r3000->RTVAL >> (r3000->RSVAL & 31); break; + case 0x08: /* JR */ SETPC(r3000, r3000->RSVAL); break; + case 0x09: /* JALR */ SETPCL(r3000, r3000->RSVAL, RDREG); break; + case 0x0c: /* SYSCALL */ generate_exception(r3000, EXCEPTION_SYSCALL); break; + case 0x0d: /* BREAK */ generate_exception(r3000, EXCEPTION_BREAK); break; + case 0x0f: /* SYNC */ invalid_instruction(r3000, op); break; + case 0x10: /* MFHI */ if (RDREG) r3000->RDVAL = r3000->hi; break; + case 0x11: /* MTHI */ r3000->hi = r3000->RSVAL; break; + case 0x12: /* MFLO */ if (RDREG) r3000->RDVAL = r3000->lo; break; + case 0x13: /* MTLO */ r3000->lo = r3000->RSVAL; break; case 0x18: /* MULT */ - temp64 = (INT64)(INT32)RSVAL * (INT64)(INT32)RTVAL; - LOVAL = (UINT32)temp64; - HIVAL = (UINT32)(temp64 >> 32); + temp64 = (INT64)(INT32)r3000->RSVAL * (INT64)(INT32)r3000->RTVAL; + r3000->lo = (UINT32)temp64; + r3000->hi = (UINT32)(temp64 >> 32); r3000->icount -= 11; break; case 0x19: /* MULTU */ - temp64 = (UINT64)RSVAL * (UINT64)RTVAL; - LOVAL = (UINT32)temp64; - HIVAL = (UINT32)(temp64 >> 32); + temp64 = (UINT64)r3000->RSVAL * (UINT64)r3000->RTVAL; + r3000->lo = (UINT32)temp64; + r3000->hi = (UINT32)(temp64 >> 32); r3000->icount -= 11; break; case 0x1a: /* DIV */ - if (RTVAL) + if (r3000->RTVAL) { - LOVAL = (INT32)RSVAL / (INT32)RTVAL; - HIVAL = (INT32)RSVAL % (INT32)RTVAL; + r3000->lo = (INT32)r3000->RSVAL / (INT32)r3000->RTVAL; + r3000->hi = (INT32)r3000->RSVAL % (INT32)r3000->RTVAL; } r3000->icount -= 34; break; case 0x1b: /* DIVU */ - if (RTVAL) + if (r3000->RTVAL) { - LOVAL = RSVAL / RTVAL; - HIVAL = RSVAL % RTVAL; + r3000->lo = r3000->RSVAL / r3000->RTVAL; + r3000->hi = r3000->RSVAL % r3000->RTVAL; } r3000->icount -= 34; break; case 0x20: /* ADD */ - if (ENABLE_OVERFLOWS && RSVAL > ~RTVAL) generate_exception(r3000, EXCEPTION_OVERFLOW); - else RDVAL = RSVAL + RTVAL; + if (ENABLE_OVERFLOWS && r3000->RSVAL > ~r3000->RTVAL) generate_exception(r3000, EXCEPTION_OVERFLOW); + else r3000->RDVAL = r3000->RSVAL + r3000->RTVAL; break; - case 0x21: /* ADDU */ if (RDREG) RDVAL = RSVAL + RTVAL; break; + case 0x21: /* ADDU */ if (RDREG) r3000->RDVAL = r3000->RSVAL + r3000->RTVAL; break; case 0x22: /* SUB */ - if (ENABLE_OVERFLOWS && RSVAL < RTVAL) generate_exception(r3000, EXCEPTION_OVERFLOW); - else RDVAL = RSVAL - RTVAL; + if (ENABLE_OVERFLOWS && r3000->RSVAL < r3000->RTVAL) generate_exception(r3000, EXCEPTION_OVERFLOW); + else r3000->RDVAL = r3000->RSVAL - r3000->RTVAL; break; - case 0x23: /* SUBU */ if (RDREG) RDVAL = RSVAL - RTVAL; break; - case 0x24: /* AND */ if (RDREG) RDVAL = RSVAL & RTVAL; break; - case 0x25: /* OR */ if (RDREG) RDVAL = RSVAL | RTVAL; break; - case 0x26: /* XOR */ if (RDREG) RDVAL = RSVAL ^ RTVAL; break; - case 0x27: /* NOR */ if (RDREG) RDVAL = ~(RSVAL | RTVAL); break; - case 0x2a: /* SLT */ if (RDREG) RDVAL = (INT32)RSVAL < (INT32)RTVAL; break; - case 0x2b: /* SLTU */ if (RDREG) RDVAL = (UINT32)RSVAL < (UINT32)RTVAL; break; - case 0x30: /* TEQ */ invalid_instruction(r3000, op); break; - case 0x31: /* TGEU */ invalid_instruction(r3000, op); break; - case 0x32: /* TLT */ invalid_instruction(r3000, op); break; - case 0x33: /* TLTU */ invalid_instruction(r3000, op); break; - case 0x34: /* TGE */ invalid_instruction(r3000, op); break; - case 0x36: /* TNE */ invalid_instruction(r3000, op); break; - default: /* ??? */ invalid_instruction(r3000, op); break; + case 0x23: /* SUBU */ if (RDREG) r3000->RDVAL = r3000->RSVAL - r3000->RTVAL; break; + case 0x24: /* AND */ if (RDREG) r3000->RDVAL = r3000->RSVAL & r3000->RTVAL; break; + case 0x25: /* OR */ if (RDREG) r3000->RDVAL = r3000->RSVAL | r3000->RTVAL; break; + case 0x26: /* XOR */ if (RDREG) r3000->RDVAL = r3000->RSVAL ^ r3000->RTVAL; break; + case 0x27: /* NOR */ if (RDREG) r3000->RDVAL = ~(r3000->RSVAL | r3000->RTVAL); break; + case 0x2a: /* SLT */ if (RDREG) r3000->RDVAL = (INT32)r3000->RSVAL < (INT32)r3000->RTVAL; break; + case 0x2b: /* SLTU */ if (RDREG) r3000->RDVAL = (UINT32)r3000->RSVAL < (UINT32)r3000->RTVAL; break; + case 0x30: /* TEQ */ invalid_instruction(r3000, op); break; + case 0x31: /* TGEU */ invalid_instruction(r3000, op); break; + case 0x32: /* TLT */ invalid_instruction(r3000, op); break; + case 0x33: /* TLTU */ invalid_instruction(r3000, op); break; + case 0x34: /* TGE */ invalid_instruction(r3000, op); break; + case 0x36: /* TNE */ invalid_instruction(r3000, op); break; + default: /* ??? */ invalid_instruction(r3000, op); break; } break; case 0x01: /* REGIMM */ switch (RTREG) { - case 0x00: /* BLTZ */ if ((INT32)RSVAL < 0) ADDPC(SIMMVAL); break; - case 0x01: /* BGEZ */ if ((INT32)RSVAL >= 0) ADDPC(SIMMVAL); break; - case 0x02: /* BLTZL */ invalid_instruction(r3000, op); break; - case 0x03: /* BGEZL */ invalid_instruction(r3000, op); break; - case 0x08: /* TGEI */ invalid_instruction(r3000, op); break; - case 0x09: /* TGEIU */ invalid_instruction(r3000, op); break; - case 0x0a: /* TLTI */ invalid_instruction(r3000, op); break; - case 0x0b: /* TLTIU */ invalid_instruction(r3000, op); break; - case 0x0c: /* TEQI */ invalid_instruction(r3000, op); break; - case 0x0e: /* TNEI */ invalid_instruction(r3000, op); break; - case 0x10: /* BLTZAL */ if ((INT32)RSVAL < 0) ADDPCL(SIMMVAL,31); break; - case 0x11: /* BGEZAL */ if ((INT32)RSVAL >= 0) ADDPCL(SIMMVAL,31); break; - case 0x12: /* BLTZALL */ invalid_instruction(r3000, op); break; - case 0x13: /* BGEZALL */ invalid_instruction(r3000, op); break; - default: /* ??? */ invalid_instruction(r3000, op); break; + case 0x00: /* BLTZ */ if ((INT32)r3000->RSVAL < 0) ADDPC(r3000, SIMMVAL); break; + case 0x01: /* BGEZ */ if ((INT32)r3000->RSVAL >= 0) ADDPC(r3000, SIMMVAL); break; + case 0x02: /* BLTZL */ invalid_instruction(r3000, op); break; + case 0x03: /* BGEZL */ invalid_instruction(r3000, op); break; + case 0x08: /* TGEI */ invalid_instruction(r3000, op); break; + case 0x09: /* TGEIU */ invalid_instruction(r3000, op); break; + case 0x0a: /* TLTI */ invalid_instruction(r3000, op); break; + case 0x0b: /* TLTIU */ invalid_instruction(r3000, op); break; + case 0x0c: /* TEQI */ invalid_instruction(r3000, op); break; + case 0x0e: /* TNEI */ invalid_instruction(r3000, op); break; + case 0x10: /* BLTZAL */ if ((INT32)r3000->RSVAL < 0) ADDPCL(r3000,SIMMVAL,31); break; + case 0x11: /* BGEZAL */ if ((INT32)r3000->RSVAL >= 0) ADDPCL(r3000,SIMMVAL,31); break; + case 0x12: /* BLTZALL */ invalid_instruction(r3000, op); break; + case 0x13: /* BGEZALL */ invalid_instruction(r3000, op); break; + default: /* ??? */ invalid_instruction(r3000, op); break; } break; - case 0x02: /* J */ ABSPC(LIMMVAL); break; - case 0x03: /* JAL */ ABSPCL(LIMMVAL,31); break; - case 0x04: /* BEQ */ if (RSVAL == RTVAL) ADDPC(SIMMVAL); break; - case 0x05: /* BNE */ if (RSVAL != RTVAL) ADDPC(SIMMVAL); break; - case 0x06: /* BLEZ */ if ((INT32)RSVAL <= 0) ADDPC(SIMMVAL); break; - case 0x07: /* BGTZ */ if ((INT32)RSVAL > 0) ADDPC(SIMMVAL); break; + case 0x02: /* J */ ABSPC(r3000, LIMMVAL); break; + case 0x03: /* JAL */ ABSPCL(r3000, LIMMVAL,31); break; + case 0x04: /* BEQ */ if (r3000->RSVAL == r3000->RTVAL) ADDPC(r3000, SIMMVAL); break; + case 0x05: /* BNE */ if (r3000->RSVAL != r3000->RTVAL) ADDPC(r3000, SIMMVAL); break; + case 0x06: /* BLEZ */ if ((INT32)r3000->RSVAL <= 0) ADDPC(r3000, SIMMVAL); break; + case 0x07: /* BGTZ */ if ((INT32)r3000->RSVAL > 0) ADDPC(r3000, SIMMVAL); break; case 0x08: /* ADDI */ - if (ENABLE_OVERFLOWS && RSVAL > ~SIMMVAL) generate_exception(r3000, EXCEPTION_OVERFLOW); - else if (RTREG) RTVAL = RSVAL + SIMMVAL; + if (ENABLE_OVERFLOWS && r3000->RSVAL > ~SIMMVAL) generate_exception(r3000, EXCEPTION_OVERFLOW); + else if (RTREG) r3000->RTVAL = r3000->RSVAL + SIMMVAL; break; - case 0x09: /* ADDIU */ if (RTREG) RTVAL = RSVAL + SIMMVAL; break; - case 0x0a: /* SLTI */ if (RTREG) RTVAL = (INT32)RSVAL < (INT32)SIMMVAL; break; - case 0x0b: /* SLTIU */ if (RTREG) RTVAL = (UINT32)RSVAL < (UINT32)SIMMVAL; break; - case 0x0c: /* ANDI */ if (RTREG) RTVAL = RSVAL & UIMMVAL; break; - case 0x0d: /* ORI */ if (RTREG) RTVAL = RSVAL | UIMMVAL; break; - case 0x0e: /* XORI */ if (RTREG) RTVAL = RSVAL ^ UIMMVAL; break; - case 0x0f: /* LUI */ if (RTREG) RTVAL = UIMMVAL << 16; break; - case 0x10: /* COP0 */ handle_cop0(r3000, op); break; - case 0x11: /* COP1 */ handle_cop1(r3000, op); break; - case 0x12: /* COP2 */ handle_cop2(r3000, op); break; - case 0x13: /* COP3 */ handle_cop3(r3000, op); break; - case 0x14: /* BEQL */ invalid_instruction(r3000, op); break; - case 0x15: /* BNEL */ invalid_instruction(r3000, op); break; - case 0x16: /* BLEZL */ invalid_instruction(r3000, op); break; - case 0x17: /* BGTZL */ invalid_instruction(r3000, op); break; - case 0x20: /* LB */ temp = RBYTE(SIMMVAL+RSVAL); if (RTREG) RTVAL = (INT8)temp; break; - case 0x21: /* LH */ temp = RWORD(SIMMVAL+RSVAL); if (RTREG) RTVAL = (INT16)temp; break; - case 0x22: /* LWL */ (*r3000->lwl)(r3000, op); break; - case 0x23: /* LW */ temp = RLONG(SIMMVAL+RSVAL); if (RTREG) RTVAL = temp; break; - case 0x24: /* LBU */ temp = RBYTE(SIMMVAL+RSVAL); if (RTREG) RTVAL = (UINT8)temp; break; - case 0x25: /* LHU */ temp = RWORD(SIMMVAL+RSVAL); if (RTREG) RTVAL = (UINT16)temp; break; - case 0x26: /* LWR */ (*r3000->lwr)(r3000, op); break; - case 0x28: /* SB */ WBYTE(SIMMVAL+RSVAL, RTVAL); break; - case 0x29: /* SH */ WWORD(SIMMVAL+RSVAL, RTVAL); break; - case 0x2a: /* SWL */ (*r3000->swl)(r3000, op); break; - case 0x2b: /* SW */ WLONG(SIMMVAL+RSVAL, RTVAL); break; - case 0x2e: /* SWR */ (*r3000->swr)(r3000, op); break; - case 0x2f: /* CACHE */ invalid_instruction(r3000, op); break; - case 0x30: /* LL */ invalid_instruction(r3000, op); break; - case 0x31: /* LWC1 */ set_cop1_reg(r3000, RTREG, RLONG(SIMMVAL+RSVAL)); break; - case 0x32: /* LWC2 */ set_cop2_reg(r3000, RTREG, RLONG(SIMMVAL+RSVAL)); break; - case 0x33: /* LWC3 */ set_cop3_reg(r3000, RTREG, RLONG(SIMMVAL+RSVAL)); break; - case 0x34: /* LDC0 */ invalid_instruction(r3000, op); break; - case 0x35: /* LDC1 */ invalid_instruction(r3000, op); break; - case 0x36: /* LDC2 */ invalid_instruction(r3000, op); break; - case 0x37: /* LDC3 */ invalid_instruction(r3000, op); break; - case 0x38: /* SC */ invalid_instruction(r3000, op); break; - case 0x39: /* LWC1 */ WLONG(SIMMVAL+RSVAL, get_cop1_reg(r3000, RTREG)); break; - case 0x3a: /* LWC2 */ WLONG(SIMMVAL+RSVAL, get_cop2_reg(r3000, RTREG)); break; - case 0x3b: /* LWC3 */ WLONG(SIMMVAL+RSVAL, get_cop3_reg(r3000, RTREG)); break; - case 0x3c: /* SDC0 */ invalid_instruction(r3000, op); break; - case 0x3d: /* SDC1 */ invalid_instruction(r3000, op); break; - case 0x3e: /* SDC2 */ invalid_instruction(r3000, op); break; - case 0x3f: /* SDC3 */ invalid_instruction(r3000, op); break; - default: /* ??? */ invalid_instruction(r3000, op); break; + case 0x09: /* ADDIU */ if (RTREG) r3000->RTVAL = r3000->RSVAL + SIMMVAL; break; + case 0x0a: /* SLTI */ if (RTREG) r3000->RTVAL = (INT32)r3000->RSVAL < (INT32)SIMMVAL; break; + case 0x0b: /* SLTIU */ if (RTREG) r3000->RTVAL = (UINT32)r3000->RSVAL < (UINT32)SIMMVAL; break; + case 0x0c: /* ANDI */ if (RTREG) r3000->RTVAL = r3000->RSVAL & UIMMVAL; break; + case 0x0d: /* ORI */ if (RTREG) r3000->RTVAL = r3000->RSVAL | UIMMVAL; break; + case 0x0e: /* XORI */ if (RTREG) r3000->RTVAL = r3000->RSVAL ^ UIMMVAL; break; + case 0x0f: /* LUI */ if (RTREG) r3000->RTVAL = UIMMVAL << 16; break; + case 0x10: /* COP0 */ handle_cop0(r3000, op); break; + case 0x11: /* COP1 */ handle_cop1(r3000, op); break; + case 0x12: /* COP2 */ handle_cop2(r3000, op); break; + case 0x13: /* COP3 */ handle_cop3(r3000, op); break; + case 0x14: /* BEQL */ invalid_instruction(r3000, op); break; + case 0x15: /* BNEL */ invalid_instruction(r3000, op); break; + case 0x16: /* BLEZL */ invalid_instruction(r3000, op); break; + case 0x17: /* BGTZL */ invalid_instruction(r3000, op); break; + case 0x20: /* LB */ temp = RBYTE(r3000, SIMMVAL+r3000->RSVAL); if (RTREG) r3000->RTVAL = (INT8)temp; break; + case 0x21: /* LH */ temp = RWORD(r3000, SIMMVAL+r3000->RSVAL); if (RTREG) r3000->RTVAL = (INT16)temp; break; + case 0x22: /* LWL */ (*r3000->lwl)(r3000, op); break; + case 0x23: /* LW */ temp = RLONG(r3000, SIMMVAL+r3000->RSVAL); if (RTREG) r3000->RTVAL = temp; break; + case 0x24: /* LBU */ temp = RBYTE(r3000, SIMMVAL+r3000->RSVAL); if (RTREG) r3000->RTVAL = (UINT8)temp; break; + case 0x25: /* LHU */ temp = RWORD(r3000, SIMMVAL+r3000->RSVAL); if (RTREG) r3000->RTVAL = (UINT16)temp; break; + case 0x26: /* LWR */ (*r3000->lwr)(r3000, op); break; + case 0x28: /* SB */ WBYTE(r3000, SIMMVAL+r3000->RSVAL, r3000->RTVAL); break; + case 0x29: /* SH */ WWORD(r3000, SIMMVAL+r3000->RSVAL, r3000->RTVAL); break; + case 0x2a: /* SWL */ (*r3000->swl)(r3000, op); break; + case 0x2b: /* SW */ WLONG(r3000, SIMMVAL+r3000->RSVAL, r3000->RTVAL); break; + case 0x2e: /* SWR */ (*r3000->swr)(r3000, op); break; + case 0x2f: /* CACHE */ invalid_instruction(r3000, op); break; + case 0x30: /* LL */ invalid_instruction(r3000, op); break; + case 0x31: /* LWC1 */ set_cop1_reg(r3000, RTREG, RLONG(r3000, SIMMVAL+r3000->RSVAL)); break; + case 0x32: /* LWC2 */ set_cop2_reg(r3000, RTREG, RLONG(r3000, SIMMVAL+r3000->RSVAL)); break; + case 0x33: /* LWC3 */ set_cop3_reg(r3000, RTREG, RLONG(r3000, SIMMVAL+r3000->RSVAL)); break; + case 0x34: /* LDC0 */ invalid_instruction(r3000, op); break; + case 0x35: /* LDC1 */ invalid_instruction(r3000, op); break; + case 0x36: /* LDC2 */ invalid_instruction(r3000, op); break; + case 0x37: /* LDC3 */ invalid_instruction(r3000, op); break; + case 0x38: /* SC */ invalid_instruction(r3000, op); break; + case 0x39: /* LWC1 */ WLONG(r3000, SIMMVAL+r3000->RSVAL, get_cop1_reg(r3000, RTREG)); break; + case 0x3a: /* LWC2 */ WLONG(r3000, SIMMVAL+r3000->RSVAL, get_cop2_reg(r3000, RTREG)); break; + case 0x3b: /* LWC3 */ WLONG(r3000, SIMMVAL+r3000->RSVAL, get_cop3_reg(r3000, RTREG)); break; + case 0x3c: /* SDC0 */ invalid_instruction(r3000, op); break; + case 0x3d: /* SDC1 */ invalid_instruction(r3000, op); break; + case 0x3e: /* SDC2 */ invalid_instruction(r3000, op); break; + case 0x3f: /* SDC3 */ invalid_instruction(r3000, op); break; + default: /* ??? */ invalid_instruction(r3000, op); break; } r3000->icount--; @@ -949,86 +922,86 @@ static CPU_DISASSEMBLE( r3000le ) CACHE I/O ***************************************************************************/ -static UINT8 readcache_be(offs_t offset) +static UINT8 readcache_be(const address_space *space, offs_t offset) { - r3000_state *r3000 = token; /* fixme */ + r3000_state *r3000 = space->cpu->token; offset &= 0x1fffffff; return (offset * 4 < r3000->cache_size) ? r3000->cache[BYTE4_XOR_BE(offset)] : 0xff; } -static UINT16 readcache_be_word(offs_t offset) +static UINT16 readcache_be_word(const address_space *space, offs_t offset) { - r3000_state *r3000 = token; /* fixme */ + r3000_state *r3000 = space->cpu->token; offset &= 0x1fffffff; return (offset * 4 < r3000->cache_size) ? *(UINT16 *)&r3000->cache[WORD_XOR_BE(offset)] : 0xffff; } -static UINT32 readcache_be_dword(offs_t offset) +static UINT32 readcache_be_dword(const address_space *space, offs_t offset) { - r3000_state *r3000 = token; /* fixme */ + r3000_state *r3000 = space->cpu->token; offset &= 0x1fffffff; return (offset * 4 < r3000->cache_size) ? *(UINT32 *)&r3000->cache[offset] : 0xffffffff; } -static void writecache_be(offs_t offset, UINT8 data) +static void writecache_be(const address_space *space, offs_t offset, UINT8 data) { - r3000_state *r3000 = token; /* fixme */ + r3000_state *r3000 = space->cpu->token; offset &= 0x1fffffff; if (offset * 4 < r3000->cache_size) r3000->cache[BYTE4_XOR_BE(offset)] = data; } -static void writecache_be_word(offs_t offset, UINT16 data) +static void writecache_be_word(const address_space *space, offs_t offset, UINT16 data) { - r3000_state *r3000 = token; /* fixme */ + r3000_state *r3000 = space->cpu->token; offset &= 0x1fffffff; if (offset * 4 < r3000->cache_size) *(UINT16 *)&r3000->cache[WORD_XOR_BE(offset)] = data; } -static void writecache_be_dword(offs_t offset, UINT32 data) +static void writecache_be_dword(const address_space *space, offs_t offset, UINT32 data) { - r3000_state *r3000 = token; /* fixme */ + r3000_state *r3000 = space->cpu->token; offset &= 0x1fffffff; if (offset * 4 < r3000->cache_size) *(UINT32 *)&r3000->cache[offset] = data; } -static UINT8 readcache_le(offs_t offset) +static UINT8 readcache_le(const address_space *space, offs_t offset) { - r3000_state *r3000 = token; /* fixme */ + r3000_state *r3000 = space->cpu->token; offset &= 0x1fffffff; return (offset * 4 < r3000->cache_size) ? r3000->cache[BYTE4_XOR_LE(offset)] : 0xff; } -static UINT16 readcache_le_word(offs_t offset) +static UINT16 readcache_le_word(const address_space *space, offs_t offset) { - r3000_state *r3000 = token; /* fixme */ + r3000_state *r3000 = space->cpu->token; offset &= 0x1fffffff; return (offset * 4 < r3000->cache_size) ? *(UINT16 *)&r3000->cache[WORD_XOR_LE(offset)] : 0xffff; } -static UINT32 readcache_le_dword(offs_t offset) +static UINT32 readcache_le_dword(const address_space *space, offs_t offset) { - r3000_state *r3000 = token; /* fixme */ + r3000_state *r3000 = space->cpu->token; offset &= 0x1fffffff; return (offset * 4 < r3000->cache_size) ? *(UINT32 *)&r3000->cache[offset] : 0xffffffff; } -static void writecache_le(offs_t offset, UINT8 data) +static void writecache_le(const address_space *space, offs_t offset, UINT8 data) { - r3000_state *r3000 = token; /* fixme */ + r3000_state *r3000 = space->cpu->token; offset &= 0x1fffffff; if (offset * 4 < r3000->cache_size) r3000->cache[BYTE4_XOR_LE(offset)] = data; } -static void writecache_le_word(offs_t offset, UINT16 data) +static void writecache_le_word(const address_space *space, offs_t offset, UINT16 data) { - r3000_state *r3000 = token; /* fixme */ + r3000_state *r3000 = space->cpu->token; offset &= 0x1fffffff; if (offset * 4 < r3000->cache_size) *(UINT16 *)&r3000->cache[WORD_XOR_LE(offset)] = data; } -static void writecache_le_dword(offs_t offset, UINT32 data) +static void writecache_le_dword(const address_space *space, offs_t offset, UINT32 data) { - r3000_state *r3000 = token; /* fixme */ + r3000_state *r3000 = space->cpu->token; offset &= 0x1fffffff; if (offset * 4 < r3000->cache_size) *(UINT32 *)&r3000->cache[offset] = data; } @@ -1041,56 +1014,56 @@ static void writecache_le_dword(offs_t offset, UINT32 data) static void lwl_be(r3000_state *r3000, UINT32 op) { - offs_t offs = SIMMVAL + RSVAL; - UINT32 temp = RLONG(offs & ~3); + offs_t offs = SIMMVAL + r3000->RSVAL; + UINT32 temp = RLONG(r3000, offs & ~3); if (RTREG) { - if (!(offs & 3)) RTVAL = temp; + if (!(offs & 3)) r3000->RTVAL = temp; else { int shift = 8 * (offs & 3); - RTVAL = (RTVAL & (0x00ffffff >> (24 - shift))) | (temp << shift); + r3000->RTVAL = (r3000->RTVAL & (0x00ffffff >> (24 - shift))) | (temp << shift); } } } static void lwr_be(r3000_state *r3000, UINT32 op) { - offs_t offs = SIMMVAL + RSVAL; - UINT32 temp = RLONG(offs & ~3); + offs_t offs = SIMMVAL + r3000->RSVAL; + UINT32 temp = RLONG(r3000, offs & ~3); if (RTREG) { - if ((offs & 3) == 3) RTVAL = temp; + if ((offs & 3) == 3) r3000->RTVAL = temp; else { int shift = 8 * (offs & 3); - RTVAL = (RTVAL & (0xffffff00 << shift)) | (temp >> (24 - shift)); + r3000->RTVAL = (r3000->RTVAL & (0xffffff00 << shift)) | (temp >> (24 - shift)); } } } static void swl_be(r3000_state *r3000, UINT32 op) { - offs_t offs = SIMMVAL + RSVAL; - if (!(offs & 3)) WLONG(offs, RTVAL); + offs_t offs = SIMMVAL + r3000->RSVAL; + if (!(offs & 3)) WLONG(r3000, offs, r3000->RTVAL); else { - UINT32 temp = RLONG(offs & ~3); + UINT32 temp = RLONG(r3000, offs & ~3); int shift = 8 * (offs & 3); - WLONG(offs & ~3, (temp & (0xffffff00 << (24 - shift))) | (RTVAL >> shift)); + WLONG(r3000, offs & ~3, (temp & (0xffffff00 << (24 - shift))) | (r3000->RTVAL >> shift)); } } static void swr_be(r3000_state *r3000, UINT32 op) { - offs_t offs = SIMMVAL + RSVAL; - if ((offs & 3) == 3) WLONG(offs & ~3, RTVAL); + offs_t offs = SIMMVAL + r3000->RSVAL; + if ((offs & 3) == 3) WLONG(r3000, offs & ~3, r3000->RTVAL); else { - UINT32 temp = RLONG(offs & ~3); + UINT32 temp = RLONG(r3000, offs & ~3); int shift = 8 * (offs & 3); - WLONG(offs & ~3, (temp & (0x00ffffff >> shift)) | (RTVAL << (24 - shift))); + WLONG(r3000, offs & ~3, (temp & (0x00ffffff >> shift)) | (r3000->RTVAL << (24 - shift))); } } @@ -1098,55 +1071,55 @@ static void swr_be(r3000_state *r3000, UINT32 op) static void lwl_le(r3000_state *r3000, UINT32 op) { - offs_t offs = SIMMVAL + RSVAL; - UINT32 temp = RLONG(offs & ~3); + offs_t offs = SIMMVAL + r3000->RSVAL; + UINT32 temp = RLONG(r3000, offs & ~3); if (RTREG) { - if (!(offs & 3)) RTVAL = temp; + if (!(offs & 3)) r3000->RTVAL = temp; else { int shift = 8 * (offs & 3); - RTVAL = (RTVAL & (0xffffff00 << (24 - shift))) | (temp >> shift); + r3000->RTVAL = (r3000->RTVAL & (0xffffff00 << (24 - shift))) | (temp >> shift); } } } static void lwr_le(r3000_state *r3000, UINT32 op) { - offs_t offs = SIMMVAL + RSVAL; - UINT32 temp = RLONG(offs & ~3); + offs_t offs = SIMMVAL + r3000->RSVAL; + UINT32 temp = RLONG(r3000, offs & ~3); if (RTREG) { - if ((offs & 3) == 3) RTVAL = temp; + if ((offs & 3) == 3) r3000->RTVAL = temp; else { int shift = 8 * (offs & 3); - RTVAL = (RTVAL & (0x00ffffff >> shift)) | (temp << (24 - shift)); + r3000->RTVAL = (r3000->RTVAL & (0x00ffffff >> shift)) | (temp << (24 - shift)); } } } static void swl_le(r3000_state *r3000, UINT32 op) { - offs_t offs = SIMMVAL + RSVAL; - if (!(offs & 3)) WLONG(offs, RTVAL); + offs_t offs = SIMMVAL + r3000->RSVAL; + if (!(offs & 3)) WLONG(r3000, offs, r3000->RTVAL); else { - UINT32 temp = RLONG(offs & ~3); + UINT32 temp = RLONG(r3000, offs & ~3); int shift = 8 * (offs & 3); - WLONG(offs & ~3, (temp & (0x00ffffff >> (24 - shift))) | (RTVAL << shift)); + WLONG(r3000, offs & ~3, (temp & (0x00ffffff >> (24 - shift))) | (r3000->RTVAL << shift)); } } static void swr_le(r3000_state *r3000, UINT32 op) { - offs_t offs = SIMMVAL + RSVAL; - if ((offs & 3) == 3) WLONG(offs & ~3, RTVAL); + offs_t offs = SIMMVAL + r3000->RSVAL; + if ((offs & 3) == 3) WLONG(r3000, offs & ~3, r3000->RTVAL); else { - UINT32 temp = RLONG(offs & ~3); + UINT32 temp = RLONG(r3000, offs & ~3); int shift = 8 * (offs & 3); - WLONG(offs & ~3, (temp & (0xffffff00 << shift)) | (RTVAL >> (24 - shift))); + WLONG(r3000, offs & ~3, (temp & (0xffffff00 << shift)) | (r3000->RTVAL >> (24 - shift))); } } @@ -1171,7 +1144,7 @@ static CPU_SET_INFO( r3000 ) case CPUINFO_INT_PC: case CPUINFO_INT_REGISTER + R3000_PC: r3000->pc = info->i; break; - case CPUINFO_INT_REGISTER + R3000_SR: SR = info->i; break; + case CPUINFO_INT_REGISTER + R3000_SR: r3000->SR = info->i; break; case CPUINFO_INT_REGISTER + R3000_R0: r3000->r[0] = info->i; break; case CPUINFO_INT_REGISTER + R3000_R1: r3000->r[1] = info->i; break; @@ -1221,26 +1194,26 @@ static CPU_GET_INFO( r3000 ) switch (state) { /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(r3000_state); break; - case CPUINFO_INT_INPUT_LINES: info->i = 6; break; - case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break; - case CPUINFO_INT_ENDIANNESS: info->i = CPU_IS_LE; break; - case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; - case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; - case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 4; break; - case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 4; break; - case CPUINFO_INT_MIN_CYCLES: info->i = 1; break; - case CPUINFO_INT_MAX_CYCLES: info->i = 40; break; + case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(r3000_state); break; + case CPUINFO_INT_INPUT_LINES: info->i = 6; break; + case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break; + case CPUINFO_INT_ENDIANNESS: info->i = CPU_IS_LE; break; + case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; + case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; + case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 4; break; + case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 4; break; + case CPUINFO_INT_MIN_CYCLES: info->i = 1; break; + case CPUINFO_INT_MAX_CYCLES: info->i = 40; break; - case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 32; break; - case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 29; break; - case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_PROGRAM: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_DATA: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break; + case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 32; break; + case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 29; break; + case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_PROGRAM: info->i = 0; break; + case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 0; break; + case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 0; break; + case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_DATA: info->i = 0; break; + case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break; + case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break; + case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break; case CPUINFO_INT_INPUT_STATE + R3000_IRQ0: info->i = (r3000->cpr[0][COP0_Cause] & 0x400) ? ASSERT_LINE : CLEAR_LINE; break; case CPUINFO_INT_INPUT_STATE + R3000_IRQ1: info->i = (r3000->cpr[0][COP0_Cause] & 0x800) ? ASSERT_LINE : CLEAR_LINE; break; @@ -1249,102 +1222,102 @@ static CPU_GET_INFO( r3000 ) case CPUINFO_INT_INPUT_STATE + R3000_IRQ4: info->i = (r3000->cpr[0][COP0_Cause] & 0x4000) ? ASSERT_LINE : CLEAR_LINE; break; case CPUINFO_INT_INPUT_STATE + R3000_IRQ5: info->i = (r3000->cpr[0][COP0_Cause] & 0x8000) ? ASSERT_LINE : CLEAR_LINE; break; - case CPUINFO_INT_PREVIOUSPC: info->i = r3000->ppc; break; + case CPUINFO_INT_PREVIOUSPC: info->i = r3000->ppc; break; - case CPUINFO_INT_PC: info->i = r3000->pc & 0x1fffffff; break; - case CPUINFO_INT_REGISTER + R3000_PC: info->i = r3000->pc; break; - case CPUINFO_INT_REGISTER + R3000_SR: info->i = SR; break; + case CPUINFO_INT_PC: info->i = r3000->pc & 0x1fffffff; break; + case CPUINFO_INT_REGISTER + R3000_PC: info->i = r3000->pc; break; + case CPUINFO_INT_REGISTER + R3000_SR: info->i = r3000->SR; break; - case CPUINFO_INT_REGISTER + R3000_R0: info->i = r3000->r[0]; break; - case CPUINFO_INT_REGISTER + R3000_R1: info->i = r3000->r[1]; break; - case CPUINFO_INT_REGISTER + R3000_R2: info->i = r3000->r[2]; break; - case CPUINFO_INT_REGISTER + R3000_R3: info->i = r3000->r[3]; break; - case CPUINFO_INT_REGISTER + R3000_R4: info->i = r3000->r[4]; break; - case CPUINFO_INT_REGISTER + R3000_R5: info->i = r3000->r[5]; break; - case CPUINFO_INT_REGISTER + R3000_R6: info->i = r3000->r[6]; break; - case CPUINFO_INT_REGISTER + R3000_R7: info->i = r3000->r[7]; break; - case CPUINFO_INT_REGISTER + R3000_R8: info->i = r3000->r[8]; break; - case CPUINFO_INT_REGISTER + R3000_R9: info->i = r3000->r[9]; break; - case CPUINFO_INT_REGISTER + R3000_R10: info->i = r3000->r[10]; break; - case CPUINFO_INT_REGISTER + R3000_R11: info->i = r3000->r[11]; break; - case CPUINFO_INT_REGISTER + R3000_R12: info->i = r3000->r[12]; break; - case CPUINFO_INT_REGISTER + R3000_R13: info->i = r3000->r[13]; break; - case CPUINFO_INT_REGISTER + R3000_R14: info->i = r3000->r[14]; break; - case CPUINFO_INT_REGISTER + R3000_R15: info->i = r3000->r[15]; break; - case CPUINFO_INT_REGISTER + R3000_R16: info->i = r3000->r[16]; break; - case CPUINFO_INT_REGISTER + R3000_R17: info->i = r3000->r[17]; break; - case CPUINFO_INT_REGISTER + R3000_R18: info->i = r3000->r[18]; break; - case CPUINFO_INT_REGISTER + R3000_R19: info->i = r3000->r[19]; break; - case CPUINFO_INT_REGISTER + R3000_R20: info->i = r3000->r[20]; break; - case CPUINFO_INT_REGISTER + R3000_R21: info->i = r3000->r[21]; break; - case CPUINFO_INT_REGISTER + R3000_R22: info->i = r3000->r[22]; break; - case CPUINFO_INT_REGISTER + R3000_R23: info->i = r3000->r[23]; break; - case CPUINFO_INT_REGISTER + R3000_R24: info->i = r3000->r[24]; break; - case CPUINFO_INT_REGISTER + R3000_R25: info->i = r3000->r[25]; break; - case CPUINFO_INT_REGISTER + R3000_R26: info->i = r3000->r[26]; break; - case CPUINFO_INT_REGISTER + R3000_R27: info->i = r3000->r[27]; break; - case CPUINFO_INT_REGISTER + R3000_R28: info->i = r3000->r[28]; break; - case CPUINFO_INT_REGISTER + R3000_R29: info->i = r3000->r[29]; break; - case CPUINFO_INT_REGISTER + R3000_R30: info->i = r3000->r[30]; break; - case CPUINFO_INT_SP: info->i = r3000->r[31] & 0x1fffffff; break; - case CPUINFO_INT_REGISTER + R3000_R31: info->i = r3000->r[31]; break; + case CPUINFO_INT_REGISTER + R3000_R0: info->i = r3000->r[0]; break; + case CPUINFO_INT_REGISTER + R3000_R1: info->i = r3000->r[1]; break; + case CPUINFO_INT_REGISTER + R3000_R2: info->i = r3000->r[2]; break; + case CPUINFO_INT_REGISTER + R3000_R3: info->i = r3000->r[3]; break; + case CPUINFO_INT_REGISTER + R3000_R4: info->i = r3000->r[4]; break; + case CPUINFO_INT_REGISTER + R3000_R5: info->i = r3000->r[5]; break; + case CPUINFO_INT_REGISTER + R3000_R6: info->i = r3000->r[6]; break; + case CPUINFO_INT_REGISTER + R3000_R7: info->i = r3000->r[7]; break; + case CPUINFO_INT_REGISTER + R3000_R8: info->i = r3000->r[8]; break; + case CPUINFO_INT_REGISTER + R3000_R9: info->i = r3000->r[9]; break; + case CPUINFO_INT_REGISTER + R3000_R10: info->i = r3000->r[10]; break; + case CPUINFO_INT_REGISTER + R3000_R11: info->i = r3000->r[11]; break; + case CPUINFO_INT_REGISTER + R3000_R12: info->i = r3000->r[12]; break; + case CPUINFO_INT_REGISTER + R3000_R13: info->i = r3000->r[13]; break; + case CPUINFO_INT_REGISTER + R3000_R14: info->i = r3000->r[14]; break; + case CPUINFO_INT_REGISTER + R3000_R15: info->i = r3000->r[15]; break; + case CPUINFO_INT_REGISTER + R3000_R16: info->i = r3000->r[16]; break; + case CPUINFO_INT_REGISTER + R3000_R17: info->i = r3000->r[17]; break; + case CPUINFO_INT_REGISTER + R3000_R18: info->i = r3000->r[18]; break; + case CPUINFO_INT_REGISTER + R3000_R19: info->i = r3000->r[19]; break; + case CPUINFO_INT_REGISTER + R3000_R20: info->i = r3000->r[20]; break; + case CPUINFO_INT_REGISTER + R3000_R21: info->i = r3000->r[21]; break; + case CPUINFO_INT_REGISTER + R3000_R22: info->i = r3000->r[22]; break; + case CPUINFO_INT_REGISTER + R3000_R23: info->i = r3000->r[23]; break; + case CPUINFO_INT_REGISTER + R3000_R24: info->i = r3000->r[24]; break; + case CPUINFO_INT_REGISTER + R3000_R25: info->i = r3000->r[25]; break; + case CPUINFO_INT_REGISTER + R3000_R26: info->i = r3000->r[26]; break; + case CPUINFO_INT_REGISTER + R3000_R27: info->i = r3000->r[27]; break; + case CPUINFO_INT_REGISTER + R3000_R28: info->i = r3000->r[28]; break; + case CPUINFO_INT_REGISTER + R3000_R29: info->i = r3000->r[29]; break; + case CPUINFO_INT_REGISTER + R3000_R30: info->i = r3000->r[30]; break; + case CPUINFO_INT_SP: info->i = r3000->r[31] & 0x1fffffff; break; + case CPUINFO_INT_REGISTER + R3000_R31: info->i = r3000->r[31]; break; /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_PTR_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(r3000); break; + case CPUINFO_PTR_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(r3000); break; case CPUINFO_PTR_GET_CONTEXT: info->getcontext = CPU_GET_CONTEXT_NAME(r3000); break; case CPUINFO_PTR_SET_CONTEXT: info->setcontext = CPU_SET_CONTEXT_NAME(r3000); break; case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(r3000); break; - case CPUINFO_PTR_RESET: /* provided per-CPU */ break; + case CPUINFO_PTR_RESET: /* provided per-CPU */ break; case CPUINFO_PTR_EXIT: info->exit = CPU_EXIT_NAME(r3000); break; - case CPUINFO_PTR_EXECUTE: info->execute = CPU_EXECUTE_NAME(r3000); break; - case CPUINFO_PTR_BURN: info->burn = NULL; break; - case CPUINFO_PTR_DISASSEMBLE: /* provided per-CPU */ break; - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &r3000->icount; break; + case CPUINFO_PTR_EXECUTE: info->execute = CPU_EXECUTE_NAME(r3000); break; + case CPUINFO_PTR_BURN: info->burn = NULL; break; + case CPUINFO_PTR_DISASSEMBLE: /* provided per-CPU */ break; + case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &r3000->icount; break; /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "R3000"); break; - case CPUINFO_STR_CORE_FAMILY: strcpy(info->s, "MIPS II"); break; - case CPUINFO_STR_CORE_VERSION: strcpy(info->s, "1.0"); break; - case CPUINFO_STR_CORE_FILE: strcpy(info->s, __FILE__); break; - case CPUINFO_STR_CORE_CREDITS: strcpy(info->s, "Copyright Aaron Giles"); break; + case CPUINFO_STR_NAME: strcpy(info->s, "R3000"); break; + case CPUINFO_STR_CORE_FAMILY: strcpy(info->s, "MIPS II"); break; + case CPUINFO_STR_CORE_VERSION: strcpy(info->s, "1.0"); break; + case CPUINFO_STR_CORE_FILE: strcpy(info->s, __FILE__); break; + case CPUINFO_STR_CORE_CREDITS: strcpy(info->s, "Copyright Aaron Giles"); break; - case CPUINFO_STR_FLAGS: strcpy(info->s, " "); break; + case CPUINFO_STR_FLAGS: strcpy(info->s, " "); break; - case CPUINFO_STR_REGISTER + R3000_PC: sprintf(info->s, "PC: %08X", r3000->pc); break; - case CPUINFO_STR_REGISTER + R3000_SR: sprintf(info->s, "SR: %08X", r3000->cpr[0][COP0_Status]); break; + case CPUINFO_STR_REGISTER + R3000_PC: sprintf(info->s, "PC: %08X", r3000->pc); break; + case CPUINFO_STR_REGISTER + R3000_SR: sprintf(info->s, "SR: %08X", r3000->SR); break; - case CPUINFO_STR_REGISTER + R3000_R0: sprintf(info->s, "R0: %08X", r3000->r[0]); break; - case CPUINFO_STR_REGISTER + R3000_R1: sprintf(info->s, "R1: %08X", r3000->r[1]); break; - case CPUINFO_STR_REGISTER + R3000_R2: sprintf(info->s, "R2: %08X", r3000->r[2]); break; - case CPUINFO_STR_REGISTER + R3000_R3: sprintf(info->s, "R3: %08X", r3000->r[3]); break; - case CPUINFO_STR_REGISTER + R3000_R4: sprintf(info->s, "R4: %08X", r3000->r[4]); break; - case CPUINFO_STR_REGISTER + R3000_R5: sprintf(info->s, "R5: %08X", r3000->r[5]); break; - case CPUINFO_STR_REGISTER + R3000_R6: sprintf(info->s, "R6: %08X", r3000->r[6]); break; - case CPUINFO_STR_REGISTER + R3000_R7: sprintf(info->s, "R7: %08X", r3000->r[7]); break; - case CPUINFO_STR_REGISTER + R3000_R8: sprintf(info->s, "R8: %08X", r3000->r[8]); break; - case CPUINFO_STR_REGISTER + R3000_R9: sprintf(info->s, "R9: %08X", r3000->r[9]); break; - case CPUINFO_STR_REGISTER + R3000_R10: sprintf(info->s, "R10:%08X", r3000->r[10]); break; - case CPUINFO_STR_REGISTER + R3000_R11: sprintf(info->s, "R11:%08X", r3000->r[11]); break; - case CPUINFO_STR_REGISTER + R3000_R12: sprintf(info->s, "R12:%08X", r3000->r[12]); break; - case CPUINFO_STR_REGISTER + R3000_R13: sprintf(info->s, "R13:%08X", r3000->r[13]); break; - case CPUINFO_STR_REGISTER + R3000_R14: sprintf(info->s, "R14:%08X", r3000->r[14]); break; - case CPUINFO_STR_REGISTER + R3000_R15: sprintf(info->s, "R15:%08X", r3000->r[15]); break; - case CPUINFO_STR_REGISTER + R3000_R16: sprintf(info->s, "R16:%08X", r3000->r[16]); break; - case CPUINFO_STR_REGISTER + R3000_R17: sprintf(info->s, "R17:%08X", r3000->r[17]); break; - case CPUINFO_STR_REGISTER + R3000_R18: sprintf(info->s, "R18:%08X", r3000->r[18]); break; - case CPUINFO_STR_REGISTER + R3000_R19: sprintf(info->s, "R19:%08X", r3000->r[19]); break; - case CPUINFO_STR_REGISTER + R3000_R20: sprintf(info->s, "R20:%08X", r3000->r[20]); break; - case CPUINFO_STR_REGISTER + R3000_R21: sprintf(info->s, "R21:%08X", r3000->r[21]); break; - case CPUINFO_STR_REGISTER + R3000_R22: sprintf(info->s, "R22:%08X", r3000->r[22]); break; - case CPUINFO_STR_REGISTER + R3000_R23: sprintf(info->s, "R23:%08X", r3000->r[23]); break; - case CPUINFO_STR_REGISTER + R3000_R24: sprintf(info->s, "R24:%08X", r3000->r[24]); break; - case CPUINFO_STR_REGISTER + R3000_R25: sprintf(info->s, "R25:%08X", r3000->r[25]); break; - case CPUINFO_STR_REGISTER + R3000_R26: sprintf(info->s, "R26:%08X", r3000->r[26]); break; - case CPUINFO_STR_REGISTER + R3000_R27: sprintf(info->s, "R27:%08X", r3000->r[27]); break; - case CPUINFO_STR_REGISTER + R3000_R28: sprintf(info->s, "R28:%08X", r3000->r[28]); break; - case CPUINFO_STR_REGISTER + R3000_R29: sprintf(info->s, "R29:%08X", r3000->r[29]); break; - case CPUINFO_STR_REGISTER + R3000_R30: sprintf(info->s, "R30:%08X", r3000->r[30]); break; - case CPUINFO_STR_REGISTER + R3000_R31: sprintf(info->s, "R31:%08X", r3000->r[31]); break; + case CPUINFO_STR_REGISTER + R3000_R0: sprintf(info->s, "R0: %08X", r3000->r[0]); break; + case CPUINFO_STR_REGISTER + R3000_R1: sprintf(info->s, "R1: %08X", r3000->r[1]); break; + case CPUINFO_STR_REGISTER + R3000_R2: sprintf(info->s, "R2: %08X", r3000->r[2]); break; + case CPUINFO_STR_REGISTER + R3000_R3: sprintf(info->s, "R3: %08X", r3000->r[3]); break; + case CPUINFO_STR_REGISTER + R3000_R4: sprintf(info->s, "R4: %08X", r3000->r[4]); break; + case CPUINFO_STR_REGISTER + R3000_R5: sprintf(info->s, "R5: %08X", r3000->r[5]); break; + case CPUINFO_STR_REGISTER + R3000_R6: sprintf(info->s, "R6: %08X", r3000->r[6]); break; + case CPUINFO_STR_REGISTER + R3000_R7: sprintf(info->s, "R7: %08X", r3000->r[7]); break; + case CPUINFO_STR_REGISTER + R3000_R8: sprintf(info->s, "R8: %08X", r3000->r[8]); break; + case CPUINFO_STR_REGISTER + R3000_R9: sprintf(info->s, "R9: %08X", r3000->r[9]); break; + case CPUINFO_STR_REGISTER + R3000_R10: sprintf(info->s, "R10:%08X", r3000->r[10]); break; + case CPUINFO_STR_REGISTER + R3000_R11: sprintf(info->s, "R11:%08X", r3000->r[11]); break; + case CPUINFO_STR_REGISTER + R3000_R12: sprintf(info->s, "R12:%08X", r3000->r[12]); break; + case CPUINFO_STR_REGISTER + R3000_R13: sprintf(info->s, "R13:%08X", r3000->r[13]); break; + case CPUINFO_STR_REGISTER + R3000_R14: sprintf(info->s, "R14:%08X", r3000->r[14]); break; + case CPUINFO_STR_REGISTER + R3000_R15: sprintf(info->s, "R15:%08X", r3000->r[15]); break; + case CPUINFO_STR_REGISTER + R3000_R16: sprintf(info->s, "R16:%08X", r3000->r[16]); break; + case CPUINFO_STR_REGISTER + R3000_R17: sprintf(info->s, "R17:%08X", r3000->r[17]); break; + case CPUINFO_STR_REGISTER + R3000_R18: sprintf(info->s, "R18:%08X", r3000->r[18]); break; + case CPUINFO_STR_REGISTER + R3000_R19: sprintf(info->s, "R19:%08X", r3000->r[19]); break; + case CPUINFO_STR_REGISTER + R3000_R20: sprintf(info->s, "R20:%08X", r3000->r[20]); break; + case CPUINFO_STR_REGISTER + R3000_R21: sprintf(info->s, "R21:%08X", r3000->r[21]); break; + case CPUINFO_STR_REGISTER + R3000_R22: sprintf(info->s, "R22:%08X", r3000->r[22]); break; + case CPUINFO_STR_REGISTER + R3000_R23: sprintf(info->s, "R23:%08X", r3000->r[23]); break; + case CPUINFO_STR_REGISTER + R3000_R24: sprintf(info->s, "R24:%08X", r3000->r[24]); break; + case CPUINFO_STR_REGISTER + R3000_R25: sprintf(info->s, "R25:%08X", r3000->r[25]); break; + case CPUINFO_STR_REGISTER + R3000_R26: sprintf(info->s, "R26:%08X", r3000->r[26]); break; + case CPUINFO_STR_REGISTER + R3000_R27: sprintf(info->s, "R27:%08X", r3000->r[27]); break; + case CPUINFO_STR_REGISTER + R3000_R28: sprintf(info->s, "R28:%08X", r3000->r[28]); break; + case CPUINFO_STR_REGISTER + R3000_R29: sprintf(info->s, "R29:%08X", r3000->r[29]); break; + case CPUINFO_STR_REGISTER + R3000_R30: sprintf(info->s, "R30:%08X", r3000->r[30]); break; + case CPUINFO_STR_REGISTER + R3000_R31: sprintf(info->s, "R31:%08X", r3000->r[31]); break; } } @@ -1358,16 +1331,16 @@ CPU_GET_INFO( r3000be ) switch (state) { /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_ENDIANNESS: info->i = CPU_IS_BE; break; + case CPUINFO_INT_ENDIANNESS: info->i = CPU_IS_BE; break; /* --- the following bits of info are returned as pointers to data or functions --- */ case CPUINFO_PTR_RESET: info->reset = CPU_RESET_NAME(r3000be); break; case CPUINFO_PTR_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(r3000be); break; /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "R3000 (big)"); break; + case CPUINFO_STR_NAME: strcpy(info->s, "R3000 (big)"); break; - default: CPU_GET_INFO_CALL(r3000); break; + default: CPU_GET_INFO_CALL(r3000); break; } } @@ -1377,16 +1350,16 @@ CPU_GET_INFO( r3000le ) switch (state) { /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_ENDIANNESS: info->i = CPU_IS_LE; break; + case CPUINFO_INT_ENDIANNESS: info->i = CPU_IS_LE; break; /* --- the following bits of info are returned as pointers to data or functions --- */ case CPUINFO_PTR_RESET: info->reset = CPU_RESET_NAME(r3000le); break; case CPUINFO_PTR_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(r3000le); break; /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "R3000 (little)"); break; + case CPUINFO_STR_NAME: strcpy(info->s, "R3000 (little)"); break; - default: CPU_GET_INFO_CALL(r3000); break; + default: CPU_GET_INFO_CALL(r3000); break; } } @@ -1396,16 +1369,16 @@ CPU_GET_INFO( r3041be ) switch (state) { /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_ENDIANNESS: info->i = CPU_IS_BE; break; + case CPUINFO_INT_ENDIANNESS: info->i = CPU_IS_BE; break; /* --- the following bits of info are returned as pointers to data or functions --- */ case CPUINFO_PTR_RESET: info->reset = CPU_RESET_NAME(r3000be); break; case CPUINFO_PTR_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(r3000be); break; /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "R3041 (big)"); break; + case CPUINFO_STR_NAME: strcpy(info->s, "R3041 (big)"); break; - default: CPU_GET_INFO_CALL(r3000); break; + default: CPU_GET_INFO_CALL(r3000); break; } } @@ -1415,15 +1388,15 @@ CPU_GET_INFO( r3041le ) switch (state) { /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_ENDIANNESS: info->i = CPU_IS_LE; break; + case CPUINFO_INT_ENDIANNESS: info->i = CPU_IS_LE; break; /* --- the following bits of info are returned as pointers to data or functions --- */ case CPUINFO_PTR_RESET: info->reset = CPU_RESET_NAME(r3000le); break; case CPUINFO_PTR_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(r3000le); break; /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "R3041 (little)"); break; + case CPUINFO_STR_NAME: strcpy(info->s, "R3041 (little)"); break; - default: CPU_GET_INFO_CALL(r3000); break; + default: CPU_GET_INFO_CALL(r3000); break; } }