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sharc: Minor optimizations

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This commit is contained in:
Ville Linde 2012-09-08 19:10:58 +00:00
parent 7fde376357
commit 7fc6ec40ec
2 changed files with 35 additions and 45 deletions
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55
src/emu/cpu/sharc/sharc.c
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@ -66,6 +66,13 @@ typedef struct
UINT32 ext_count; UINT32 ext_count;
} DMA_REGS; } DMA_REGS;
typedef struct
{
UINT32 addr;
UINT32 code;
UINT32 loop_type;
} LADDR;
typedef struct _SHARC_REGS SHARC_REGS; typedef struct _SHARC_REGS SHARC_REGS;
struct _SHARC_REGS struct _SHARC_REGS
{ {
@ -84,7 +91,7 @@ struct _SHARC_REGS
UINT32 daddr; UINT32 daddr;
UINT32 pcstk; UINT32 pcstk;
UINT32 pcstkp; UINT32 pcstkp;
UINT32 laddr; LADDR laddr;
UINT32 curlcntr; UINT32 curlcntr;
UINT32 lcntr; UINT32 lcntr;
@ -131,8 +138,6 @@ struct _SHARC_REGS
void (*opcode_handler)(SHARC_REGS *cpustate); void (*opcode_handler)(SHARC_REGS *cpustate);
int icount; int icount;
UINT64 opcode; UINT64 opcode;
UINT64 fetch_opcode;
UINT64 decode_opcode;
UINT32 nfaddr; UINT32 nfaddr;
@ -197,11 +202,6 @@ INLINE void CHANGE_PC(SHARC_REGS *cpustate, UINT32 newpc)
cpustate->daddr = newpc; cpustate->daddr = newpc;
cpustate->faddr = newpc+1; cpustate->faddr = newpc+1;
cpustate->nfaddr = newpc+2; cpustate->nfaddr = newpc+2;
// next instruction to be executed
cpustate->decode_opcode = ROPCODE(cpustate->daddr);
// next instruction to be decoded
cpustate->fetch_opcode = ROPCODE(cpustate->faddr);
} }
INLINE void CHANGE_PC_DELAYED(SHARC_REGS *cpustate, UINT32 newpc) INLINE void CHANGE_PC_DELAYED(SHARC_REGS *cpustate, UINT32 newpc)
@ -449,7 +449,9 @@ static CPU_INIT( sharc )
device->save_item(NAME(cpustate->daddr)); device->save_item(NAME(cpustate->daddr));
device->save_item(NAME(cpustate->pcstk)); device->save_item(NAME(cpustate->pcstk));
device->save_item(NAME(cpustate->pcstkp)); device->save_item(NAME(cpustate->pcstkp));
device->save_item(NAME(cpustate->laddr)); device->save_item(NAME(cpustate->laddr.addr));
device->save_item(NAME(cpustate->laddr.code));
device->save_item(NAME(cpustate->laddr.loop_type));
device->save_item(NAME(cpustate->curlcntr)); device->save_item(NAME(cpustate->curlcntr));
device->save_item(NAME(cpustate->lcntr)); device->save_item(NAME(cpustate->lcntr));
@ -510,8 +512,6 @@ static CPU_INIT( sharc )
device->save_pointer(NAME(cpustate->internal_ram), 2 * 0x10000); device->save_pointer(NAME(cpustate->internal_ram), 2 * 0x10000);
device->save_item(NAME(cpustate->opcode)); device->save_item(NAME(cpustate->opcode));
device->save_item(NAME(cpustate->fetch_opcode));
device->save_item(NAME(cpustate->decode_opcode));
device->save_item(NAME(cpustate->nfaddr)); device->save_item(NAME(cpustate->nfaddr));
@ -600,10 +600,14 @@ static CPU_EXIT( sharc )
static void sharc_set_irq_line(SHARC_REGS *cpustate, int irqline, int state) static void sharc_set_irq_line(SHARC_REGS *cpustate, int irqline, int state)
{ {
if (state) if (state == ASSERT_LINE)
{ {
cpustate->irq_active |= 1 << (8-irqline); cpustate->irq_active |= 1 << (8-irqline);
} }
else
{
cpustate->irq_active &= ~(1 << (8-irqline));
}
} }
void sharc_set_flag_input(device_t *device, int flag_num, int state) void sharc_set_flag_input(device_t *device, int flag_num, int state)
@ -696,15 +700,6 @@ static CPU_EXECUTE( sharc )
cpustate->idle = 0; cpustate->idle = 0;
} }
// fill the initial pipeline
// next executed instruction
cpustate->opcode = ROPCODE(cpustate->daddr);
cpustate->opcode_handler = sharc_op[(cpustate->opcode >> 39) & 0x1ff];
// next decoded instruction
cpustate->fetch_opcode = ROPCODE(cpustate->faddr);
while (cpustate->icount > 0 && !cpustate->idle) while (cpustate->icount > 0 && !cpustate->idle)
{ {
cpustate->pc = cpustate->daddr; cpustate->pc = cpustate->daddr;
@ -716,21 +711,18 @@ static CPU_EXECUTE( sharc )
cpustate->astat_old_old = cpustate->astat_old; cpustate->astat_old_old = cpustate->astat_old;
cpustate->astat_old = cpustate->astat; cpustate->astat_old = cpustate->astat;
cpustate->decode_opcode = cpustate->fetch_opcode; cpustate->opcode = ROPCODE(cpustate->pc);
// fetch next instruction
cpustate->fetch_opcode = ROPCODE(cpustate->faddr);
debugger_instruction_hook(device, cpustate->pc); debugger_instruction_hook(device, cpustate->pc);
// handle looping // handle looping
if (cpustate->pc == (cpustate->laddr & 0xffffff)) if (cpustate->pc == cpustate->laddr.addr)
{ {
switch (cpustate->laddr >> 30) switch (cpustate->laddr.loop_type)
{ {
case 0: // arithmetic condition-based case 0: // arithmetic condition-based
{ {
int condition = (cpustate->laddr >> 24) & 0x1f; int condition = cpustate->laddr.code;
{ {
UINT32 looptop = TOP_PC(cpustate); UINT32 looptop = TOP_PC(cpustate);
@ -780,12 +772,7 @@ static CPU_EXECUTE( sharc )
} }
} }
// execute current instruction sharc_op[(cpustate->opcode >> 39) & 0x1ff](cpustate);
cpustate->opcode_handler(cpustate);
// decode next instruction
cpustate->opcode = cpustate->decode_opcode;
cpustate->opcode_handler = sharc_op[(cpustate->opcode >> 39) & 0x1ff];

23
src/emu/cpu/sharc/sharcops.c
View File

@ -1106,7 +1106,7 @@ INLINE UINT32 TOP_PC(SHARC_REGS *cpustate)
return cpustate->pcstack[cpustate->pcstkp]; return cpustate->pcstack[cpustate->pcstkp];
} }
INLINE void PUSH_LOOP(SHARC_REGS *cpustate, UINT32 pc, UINT32 count) INLINE void PUSH_LOOP(SHARC_REGS *cpustate, UINT32 addr, UINT32 code, UINT32 type, UINT32 count)
{ {
cpustate->lstkp++; cpustate->lstkp++;
if(cpustate->lstkp >= 6) if(cpustate->lstkp >= 6)
@ -1124,9 +1124,12 @@ INLINE void PUSH_LOOP(SHARC_REGS *cpustate, UINT32 pc, UINT32 count)
} }
cpustate->lcstack[cpustate->lstkp] = count; cpustate->lcstack[cpustate->lstkp] = count;
cpustate->lastack[cpustate->lstkp] = pc; cpustate->lastack[cpustate->lstkp] = (type << 30) | (code << 24) | addr;
cpustate->curlcntr = count; cpustate->curlcntr = count;
cpustate->laddr = pc;
cpustate->laddr.addr = addr;
cpustate->laddr.code = code;
cpustate->laddr.loop_type = type;
} }
INLINE void POP_LOOP(SHARC_REGS *cpustate) INLINE void POP_LOOP(SHARC_REGS *cpustate)
@ -1148,7 +1151,10 @@ INLINE void POP_LOOP(SHARC_REGS *cpustate)
} }
cpustate->curlcntr = cpustate->lcstack[cpustate->lstkp]; cpustate->curlcntr = cpustate->lcstack[cpustate->lstkp];
cpustate->laddr = cpustate->lastack[cpustate->lstkp];
cpustate->laddr.addr = cpustate->lastack[cpustate->lstkp] & 0xffffff;
cpustate->laddr.code = (cpustate->lastack[cpustate->lstkp] >> 24) & 0x1f;
cpustate->laddr.loop_type = (cpustate->lastack[cpustate->lstkp] >> 30) & 0x3;
} }
INLINE void PUSH_STATUS_STACK(SHARC_REGS *cpustate) INLINE void PUSH_STATUS_STACK(SHARC_REGS *cpustate)
@ -2391,7 +2397,7 @@ static void sharcop_do_until_counter_imm(SHARC_REGS *cpustate)
if (cpustate->lcntr > 0) if (cpustate->lcntr > 0)
{ {
PUSH_PC(cpustate, cpustate->pc+1); PUSH_PC(cpustate, cpustate->pc+1);
PUSH_LOOP(cpustate, address | (type << 30) | (cond << 24), cpustate->lcntr); PUSH_LOOP(cpustate, address, cond, type, cpustate->lcntr);
} }
} }
@ -2425,7 +2431,7 @@ static void sharcop_do_until_counter_ureg(SHARC_REGS *cpustate)
if (cpustate->lcntr > 0) if (cpustate->lcntr > 0)
{ {
PUSH_PC(cpustate, cpustate->pc+1); PUSH_PC(cpustate, cpustate->pc+1);
PUSH_LOOP(cpustate, address | (type << 30) | (cond << 24), cpustate->lcntr); PUSH_LOOP(cpustate, address, cond, type, cpustate->lcntr);
} }
} }
@ -2440,7 +2446,7 @@ static void sharcop_do_until(SHARC_REGS *cpustate)
UINT32 address = (cpustate->pc + offset); UINT32 address = (cpustate->pc + offset);
PUSH_PC(cpustate, cpustate->pc+1); PUSH_PC(cpustate, cpustate->pc+1);
PUSH_LOOP(cpustate, address | (cond << 24), 0); PUSH_LOOP(cpustate, address, cond, 0, 0);
} }
/*****************************************************************************/ /*****************************************************************************/
@ -2737,9 +2743,6 @@ static void sharcop_idle(SHARC_REGS *cpustate)
cpustate->faddr = cpustate->pc+1; cpustate->faddr = cpustate->pc+1;
cpustate->nfaddr = cpustate->pc+2; cpustate->nfaddr = cpustate->pc+2;
cpustate->decode_opcode = ROPCODE(cpustate->daddr);
cpustate->fetch_opcode = ROPCODE(cpustate->faddr);
cpustate->idle = 1; cpustate->idle = 1;
} }