Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-06-05 04:16:28 +03:00
Code Issues Actions 4 Packages Projects Releases Wiki Activity

no more old duart (nw)

Browse Source
This commit is contained in:
Miodrag Milanovic 2014-03-18 07:57:10 +00:00
parent dddcd70190
commit 7fc79693d2
13 changed files with 54 additions and 1077 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
.gitattributes vendored
View File

@ -2162,8 +2162,6 @@ src/emu/machine/6840ptm.c svneol=native#text/plain
src/emu/machine/6840ptm.h svneol=native#text/plain
src/emu/machine/6850acia.c svneol=native#text/plain
src/emu/machine/6850acia.h svneol=native#text/plain
src/emu/machine/68681.c svneol=native#text/plain
src/emu/machine/68681.h svneol=native#text/plain
src/emu/machine/7200fifo.c svneol=native#text/plain
src/emu/machine/7200fifo.h svneol=native#text/plain
src/emu/machine/74123.c svneol=native#text/plain

2
src/emu/machine/68307.c
View File

@ -137,7 +137,7 @@ void m68307_set_port_callbacks(m68307cpu_device *device, m68307_porta_read_callb
device->m_m68307_portb_w = portb_w;
}
void m68307_set_duart68681(m68307cpu_device* cpudev, device_t *duart68681)
void m68307_set_duart68681(m68307cpu_device* cpudev, duartn68681_device *duart68681)
{
if (cpudev->m68307SERIAL)
cpudev->m68307SERIAL->m68307ser_set_duart68681(duart68681);

2
src/emu/machine/68307.h
View File

@ -88,7 +88,7 @@ protected:
static const device_type M68307 = &device_creator<m68307cpu_device>;
extern void m68307_set_port_callbacks(m68307cpu_device *device, m68307_porta_read_callback porta_r, m68307_porta_write_callback porta_w, m68307_portb_read_callback portb_r, m68307_portb_write_callback portb_w);
extern void m68307_set_duart68681(m68307cpu_device* cpudev, device_t *duart68681);
extern void m68307_set_duart68681(m68307cpu_device* cpudev, duartn68681_device *duart68681);
extern UINT16 m68307_get_cs(m68307cpu_device *device, offs_t address);
extern void m68307_timer0_interrupt(m68307cpu_device *cpudev);
extern void m68307_timer1_interrupt(m68307cpu_device *cpudev);

4
src/emu/machine/68307ser.c
View File

@ -24,7 +24,7 @@ READ8_MEMBER( m68307cpu_device::m68307_internal_serial_r )
// if we're piggybacking on the existing 68681 implementation...
if (serial->m_duart68681)
{
if (offset&1) return duart68681_r(serial->m_duart68681, *m68k->program, offset>>1);
if (offset&1) return serial->m_duart68681->read(*m68k->program, offset>>1);
}
else
{
@ -103,7 +103,7 @@ WRITE8_MEMBER( m68307cpu_device::m68307_internal_serial_w )
// if we're piggybacking on the existing 68681 implementation...
if (serial->m_duart68681)
{
if (offset&1) duart68681_w(serial->m_duart68681, *m68k->program, offset>>1, data);
if (offset&1) serial->m_duart68681->write(*m68k->program, offset>>1, data);
}
else
{

6
src/emu/machine/68307ser.h
View File

@ -1,5 +1,5 @@
#include "cpu/m68000/m68000.h"
#include "machine/68681.h"
#include "machine/n68681.h"
#define m68307SER_UMR1_UMR2 (0x01)
#define m68307SER_USR_UCSR (0x03)
@ -24,10 +24,10 @@ class m68307_serial
void reset(void);
UINT8 m_uivr;
void m68307ser_set_duart68681(device_t *duart68681)
void m68307ser_set_duart68681(duartn68681_device *duart68681)
{
m_duart68681 = duart68681;
}
device_t * m_duart68681;
duartn68681_device * m_duart68681;
};

946
src/emu/machine/68681.c
View File

@ -1,946 +0,0 @@
/*
68681 DUART
Written by Mariusz Wojcieszek
Updated by Jonathan Gevaryahu AKA Lord Nightmare
Improved interrupt handling by R. Belmont
*/
#include "emu.h"
#include "68681.h"
#include "devlegcy.h"
#define VERBOSE 0
#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
static const char *const duart68681_reg_read_names[0x10] =
{
"MRA", "SRA", "BRG Test", "RHRA", "IPCR", "ISR", "CTU", "CTL", "MRB", "SRB", "1X/16X Test", "RHRB", "IVR", "Input Ports", "Start Counter", "Stop Counter"
};
static const char *const duart68681_reg_write_names[0x10] =
{
"MRA", "CSRA", "CRA", "THRA", "ACR", "IMR", "CRUR", "CTLR", "MRB", "CSRB", "CRB", "THRB", "IVR", "OPCR", "Set OP Bits", "Reset OP Bits"
};
#define INT_INPUT_PORT_CHANGE 0x80
#define INT_DELTA_BREAK_B 0x40
#define INT_RXRDY_FFULLB 0x20
#define INT_TXRDYB 0x10
#define INT_COUNTER_READY 0x08
#define INT_DELTA_BREAK_A 0x04
#define INT_RXRDY_FFULLA 0x02
#define INT_TXRDYA 0x01
#define STATUS_RECEIVED_BREAK 0x80
#define STATUS_FRAMING_ERROR 0x40
#define STATUS_PARITY_ERROR 0x20
#define STATUS_OVERRUN_ERROR 0x10
#define STATUS_TRANSMITTER_EMPTY 0x08
#define STATUS_TRANSMITTER_READY 0x04
#define STATUS_FIFO_FULL 0x02
#define STATUS_RECEIVER_READY 0x01
#define MODE_RX_INT_SELECT_BIT 0x40
#define RX_FIFO_SIZE 3
struct DUART68681_CHANNEL
{
/* Registers */
UINT8 CR; /* Command register */
UINT8 CSR; /* Clock select register */
UINT8 MR1; /* Mode register 1 */
UINT8 MR2; /* Mode register 2 */
UINT8 MR_ptr; /* Mode register pointer */
UINT8 SR; /* Status register */
/* State */
int baud_rate;
/* Receiver */
UINT8 rx_enabled;
UINT8 rx_fifo[RX_FIFO_SIZE];
int rx_fifo_read_ptr;
int rx_fifo_write_ptr;
int rx_fifo_num;
/* Transmitter */
UINT8 tx_enabled;
UINT8 tx_data;
UINT8 tx_ready;
emu_timer *tx_timer;
};
struct duart68681_state
{
/* device */
device_t *device;
/* config */
const duart68681_config *duart_config;
/* registers */
UINT8 ACR; /* Auxiliary Control Register */
UINT8 IMR; /* Interrupt Mask Register */
UINT8 ISR; /* Interrupt Status Register */
UINT8 IVR; /* Interrupt Vector Register */
UINT8 OPCR; /* Output Port Conf. Register */
UINT8 OPR; /* Output Port Register */
PAIR CTR; /* Counter/Timer Preset Value */
/* state */
UINT8 IP_last_state; /* last state of IP bits */
/* timer */
UINT8 half_period;
emu_timer *duart_timer;
/* UART channels */
DUART68681_CHANNEL channel[2];
};
INLINE duart68681_state *get_safe_token(device_t *device)
{
assert(device != NULL);
assert(device->type() == DUART68681);
return (duart68681_state *)downcast<duart68681_device *>(device)->token();
}
static void duart68681_update_interrupts(duart68681_state *duart68681)
{
/* update SR state and update interrupt ISR state for the following bits:
SRn: bits 7-4: handled elsewhere.
SRn: bit 3 (TxEMTn) (we can assume since we're not actually emulating the delay/timing of sending bits, that as long as TxRDYn is set, TxEMTn is also set since the transmit byte has 'already happened', therefore TxEMTn is always 1 assuming tx is enabled on channel n and the MSR2n mode is 0 or 2; in mode 1 it is explicitly zeroed, and mode 3 is undefined)
SRn: bit 2 (TxRDYn) (we COULD assume since we're not emulating delay and timing output, that as long as tx is enabled on channel n, TxRDY is 1 for channel n and the MSR2n mode is 0 or 2; in mode 1 it is explicitly zeroed, and mode 3 is undefined; however, tx_ready is already nicely handled for us elsewhere, so we can use that instead for now, though we may need to retool that code as well)
SRn: bit 1 (FFULLn) (this bit we actually emulate; if the receive fifo for channel n is full, this bit is 1, otherwise it is 0. the receive fifo should be three words long.)
SRn: bit 0 (RxRDYn) (this bit we also emulate; the bit is always asserted if the receive fifo is not empty)
ISR: bit 7: Input Port change; this should be handled elsewhere, on the input port handler
ISR: bit 6: Delta Break B; this should be handled elsewhere, on the data receive handler
ISR: bit 5: RxRDYB/FFULLB: this is handled here; depending on whether MSR1B bit 6 is 0 or 1, this bit holds the state of SRB bit 0 or bit 1 respectively
ISR: bit 4: TxRDYB: this is handled here; it mirrors SRB bit 2
ISR: bit 3: Counter ready; this should be handled by the timer generator
ISR: bit 2: Delta Break A; this should be handled elsewhere, on the data receive handler
ISR: bit 1: RxRDYA/FFULLA: this is handled here; depending on whether MSR1A bit 6 is 0 or 1, this bit holds the state of SRA bit 0 or bit 1 respectively
ISR: bit 0: TxRDYA: this is handled here; it mirrors SRA bit 2
*/
UINT8 ch = 0;
//logerror("DEBUG: 68681 int check: upon func call, SRA is %02X, SRB is %02X, ISR is %02X\n", duart68681->channel[0].SR, duart68681->channel[1].SR, duart68681->ISR);
for (ch = 0; ch < 2; ch++)
{
//if ( duart68681->channel[ch].rx_enabled )
//{
if ( duart68681->channel[ch].rx_fifo_num > 0 )
{
duart68681->channel[ch].SR |= STATUS_RECEIVER_READY;
}
else
{
duart68681->channel[ch].SR &= ~STATUS_RECEIVER_READY;
}
if ( duart68681->channel[ch].rx_fifo_num == RX_FIFO_SIZE )
{
duart68681->channel[ch].SR |= STATUS_FIFO_FULL;
}
else
{
duart68681->channel[ch].SR &= ~STATUS_FIFO_FULL;
}
//}
//else
//{
//duart68681->channel[ch].SR &= ~STATUS_RECEIVER_READY;
//duart68681->channel[ch].SR &= ~STATUS_FIFO_FULL;
//}
// Handle the TxEMT and TxRDY bits based on mode
switch( duart68681->channel[ch].MR2&0xC0) // what mode are we in?
{
case 0x00: // normal mode
if ( duart68681->channel[ch].tx_enabled )
{
duart68681->channel[ch].SR |= STATUS_TRANSMITTER_EMPTY;
}
else
{
duart68681->channel[ch].SR &= ~STATUS_TRANSMITTER_EMPTY;
}
break;
case 0x40: // automatic echo mode
duart68681->channel[ch].SR &= ~STATUS_TRANSMITTER_EMPTY;
duart68681->channel[ch].SR &= ~STATUS_TRANSMITTER_READY;
break;
case 0x80: // local loopback mode
if ( duart68681->channel[ch].tx_enabled )
{
duart68681->channel[ch].SR |= STATUS_TRANSMITTER_EMPTY;
}
else
{
duart68681->channel[ch].SR &= ~STATUS_TRANSMITTER_EMPTY;
}
break;
case 0xC0: // remote loopback mode
// write me, what the txrdy/txemt regs do for remote loopback mode is undocumented afaik, for now just clear both
duart68681->channel[ch].SR &= ~STATUS_TRANSMITTER_EMPTY;
duart68681->channel[ch].SR &= ~STATUS_TRANSMITTER_READY;
break;
}
// now handle the ISR bits
if ( duart68681->channel[ch].SR & STATUS_TRANSMITTER_READY )
{
if (ch == 0)
duart68681->ISR |= INT_TXRDYA;
else
duart68681->ISR |= INT_TXRDYB;
}
else
{
if (ch == 0)
duart68681->ISR &= ~INT_TXRDYA;
else
duart68681->ISR &= ~INT_TXRDYB;
}
//logerror("DEBUG: 68681 int check: before receiver test, SR%c is %02X, ISR is %02X\n", (ch+0x41), duart68681->channel[ch].SR, duart68681->ISR);
if ( duart68681->channel[ch].MR1 & MODE_RX_INT_SELECT_BIT )
{
if ( duart68681->channel[ch].SR & STATUS_FIFO_FULL )
{
duart68681->ISR |= ((ch == 0) ? INT_RXRDY_FFULLA : INT_RXRDY_FFULLB);
}
else
{
duart68681->ISR &= ((ch == 0) ? ~INT_RXRDY_FFULLA : ~INT_RXRDY_FFULLB);
}
}
else
{
if ( duart68681->channel[ch].SR & STATUS_RECEIVER_READY )
{
duart68681->ISR |= ((ch == 0) ? INT_RXRDY_FFULLA : INT_RXRDY_FFULLB);
}
else
{
duart68681->ISR &= ((ch == 0) ? ~INT_RXRDY_FFULLA : ~INT_RXRDY_FFULLB);
}
}
//logerror("DEBUG: 68681 int check: after receiver test, SR%c is %02X, ISR is %02X\n", (ch+0x41), duart68681->channel[ch].SR, duart68681->ISR);
}
if ( (duart68681->ISR & duart68681->IMR) != 0 )
{
if ( duart68681->duart_config->irq_handler )
{
LOG(( "68681: Interrupt line active (IMR & ISR = %02X)\n", (duart68681->ISR & duart68681->IMR) ));
duart68681->duart_config->irq_handler( duart68681->device, ASSERT_LINE, duart68681->IVR );
}
}
else
{
if ( duart68681->duart_config->irq_handler )
{
LOG(( "68681: Interrupt line not active (IMR & ISR = %02X)\n", (duart68681->ISR & duart68681->IMR) ));
duart68681->duart_config->irq_handler( duart68681->device, CLEAR_LINE, duart68681->IVR );
}
}
};
double duart68681_get_ct_rate(duart68681_state *duart68681)
{
double rate = 0.0f;
if (duart68681->ACR & 0x40)
{
// Timer mode
switch ((duart68681->ACR >> 4) & 3)
{
case 0: // IP2
case 1: // IP2 / 16
//logerror( "68681 (%s): Unhandled timer/counter mode %d\n", duart68681->tag(), (duart68681->ACR >> 4) & 3);
rate = duart68681->device->clock();
break;
case 2: // X1/CLK
rate = duart68681->device->clock();
break;
case 3: // X1/CLK / 16
rate = duart68681->device->clock() / 16;
break;
}
}
else
{
// Counter mode
switch ((duart68681->ACR >> 4) & 3)
{
case 0: // IP2
case 1: // TxCA
case 2: // TxCB
//logerror( "68681 (%s): Unhandled timer/counter mode %d\n", device->tag(), (duart68681->ACR >> 4) & 3);
rate = duart68681->device->clock();
break;
case 3: // X1/CLK / 16
rate = duart68681->device->clock() / 16;
break;
}
}
return rate;
}
UINT16 duart68681_get_ct_count(duart68681_state *duart68681)
{
double clock = duart68681_get_ct_rate(duart68681);
return (duart68681->duart_timer->remaining() * clock).as_double();
}
void duart68681_start_ct(duart68681_state *duart68681, int count)
{
double clock = duart68681_get_ct_rate(duart68681);
duart68681->duart_timer->adjust(attotime::from_hz(clock) * count, 0);
}
static TIMER_CALLBACK( duart_timer_callback )
{
device_t *device = (device_t *)ptr;
duart68681_state *duart68681 = get_safe_token(device);
if (duart68681->ACR & 0x40)
{
// Timer mode
duart68681->half_period ^= 1;
// TODO: Set OP3
if (!duart68681->half_period)
{
duart68681->ISR |= INT_COUNTER_READY;
duart68681_update_interrupts(duart68681);
}
int count = MAX(duart68681->CTR.w.l, 1);
duart68681_start_ct(duart68681, count);
}
else
{
// Counter mode
duart68681->ISR |= INT_COUNTER_READY;
duart68681_update_interrupts(duart68681);
duart68681_start_ct(duart68681, 0xffff);
}
};
static void duart68681_write_MR(duart68681_state *duart68681, int ch, UINT8 data)
{
if ( duart68681->channel[ch].MR_ptr == 0 )
{
duart68681->channel[ch].MR1 = data;
duart68681->channel[ch].MR_ptr = 1;
}
else
{
duart68681->channel[ch].MR2 = data;
}
duart68681_update_interrupts(duart68681);
};
static void duart68681_write_CSR(duart68681_state *duart68681, int ch, UINT8 data, UINT8 ACR)
{
static const int baud_rate_ACR_0[] = { 50, 110, 134, 200, 300, 600, 1200, 1050, 2400, 4800, 7200, 9600, 38400, 0, 0, 0 };
static const int baud_rate_ACR_1[] = { 75, 110, 134, 150, 300, 600, 1200, 2000, 2400, 4800, 1800, 9600, 19200, 0, 0, 0 };
duart68681->channel[ch].CSR = data;
if ( BIT(ACR,7) == 0 )
{
duart68681->channel[ch].baud_rate = baud_rate_ACR_0[data & 0x0f];
if (ch == 0)
{
if ((data & 0xf) == 0xe)
{
duart68681->channel[ch].baud_rate = duart68681->duart_config->ip3clk/16;
}
else if ((data & 0xf) == 0xf)
{
duart68681->channel[ch].baud_rate = duart68681->duart_config->ip3clk;
}
}
else if (ch == 1)
{
if ((data & 0xf) == 0xe)
{
duart68681->channel[ch].baud_rate = duart68681->duart_config->ip5clk/16;
}
else if ((data & 0xf) == 0xf)
{
duart68681->channel[ch].baud_rate = duart68681->duart_config->ip5clk;
}
}
}
else
{
duart68681->channel[ch].baud_rate = baud_rate_ACR_1[data & 0x0f];
}
if ( duart68681->channel[ch].baud_rate == 0 )
{
LOG(( "Unsupported transmitter clock: channel %d, clock select = %02x\n", ch, data ));
}
};
static void duart68681_write_CR(duart68681_state *duart68681, int ch, UINT8 data)
{
duart68681->channel[ch].CR = data;
switch( (data >> 4) & 0x07 )
{
case 0: /* No command */
break;
case 1: /* Reset MR pointer. Causes the Channel A MR pointer to point to MR1 */
duart68681->channel[ch].MR_ptr = 0;
break;
case 2: /* Reset channel A receiver (disable receiver and flush fifo) */
duart68681->channel[ch].rx_enabled = 0;
duart68681->channel[ch].SR &= ~STATUS_RECEIVER_READY;
duart68681->channel[ch].SR &= ~STATUS_OVERRUN_ERROR; // is this correct?
duart68681->channel[ch].rx_fifo_read_ptr = 0;
duart68681->channel[ch].rx_fifo_write_ptr = 0;
duart68681->channel[ch].rx_fifo_num = 0;
break;
case 3: /* Reset channel A transmitter */
duart68681->channel[ch].tx_enabled = 0;
duart68681->channel[ch].SR &= ~STATUS_TRANSMITTER_READY;
if (ch == 0)
duart68681->ISR &= ~INT_TXRDYA;
else
duart68681->ISR &= ~INT_TXRDYB;
duart68681->channel[ch].tx_timer->adjust(attotime::never, ch);
break;
case 4: /* Reset Error Status */
duart68681->channel[ch].SR &= ~(STATUS_RECEIVED_BREAK | STATUS_FRAMING_ERROR | STATUS_PARITY_ERROR | STATUS_OVERRUN_ERROR);
break;
case 5: /* Reset Channel break change interrupt */
if ( ch == 0 )
{
duart68681->ISR &= ~INT_DELTA_BREAK_A;
}
else
{
duart68681->ISR &= ~INT_DELTA_BREAK_B;
}
break;
/* TODO: case 6 and case 7 are start break and stop break respectively, which start or stop holding the TxDA or TxDB line low (space) after whatever data is in the buffer finishes transmitting (following the stop bit?), or after two bit-times if no data is being transmitted */
default:
LOG(( "68681: Unhandled command (%x) in CR%d\n", (data >> 4) & 0x07, ch ));
break;
}
if (BIT(data, 0)) {
duart68681->channel[ch].rx_enabled = 1;
}
if (BIT(data, 1)) {
duart68681->channel[ch].rx_enabled = 0;
duart68681->channel[ch].SR &= ~STATUS_RECEIVER_READY;
}
if (BIT(data, 2)) {
duart68681->channel[ch].tx_enabled = 1;
duart68681->channel[ch].tx_ready = 1;
duart68681->channel[ch].SR |= STATUS_TRANSMITTER_READY;
if (ch == 0)
duart68681->ISR |= INT_TXRDYA;
else
duart68681->ISR |= INT_TXRDYB;
}
if (BIT(data, 3)) {
duart68681->channel[ch].tx_enabled = 0;
duart68681->channel[ch].tx_ready = 0;
duart68681->channel[ch].SR &= ~STATUS_TRANSMITTER_READY;
if (ch == 0)
duart68681->ISR &= ~INT_TXRDYA;
else
duart68681->ISR &= ~INT_TXRDYB;
}
duart68681_update_interrupts(duart68681);
};
static UINT8 duart68681_read_rx_fifo(duart68681_state *duart68681, int ch)
{
UINT8 r;
if ( duart68681->channel[ch].rx_fifo_num == 0 )
{
LOG(( "68681: rx fifo underflow\n" ));
return 0x0;
}
r = duart68681->channel[ch].rx_fifo[duart68681->channel[ch].rx_fifo_read_ptr++];
if ( duart68681->channel[ch].rx_fifo_read_ptr == RX_FIFO_SIZE )
{
duart68681->channel[ch].rx_fifo_read_ptr = 0;
}
duart68681->channel[ch].rx_fifo_num--;
duart68681_update_interrupts(duart68681);
return r;
};
static TIMER_CALLBACK( tx_timer_callback )
{
device_t *device = (device_t *)ptr;
duart68681_state *duart68681 = get_safe_token(device);
int ch = param & 1;
// send the byte unless we're in loopback mode;
// in loopback mode do NOT 'actually' send the byte: the TXn pin is held high when loopback mode is on.
if ((duart68681->duart_config->tx_callback) && ((duart68681->channel[ch].MR2&0xC0) != 0x80))
duart68681->duart_config->tx_callback(device, ch, duart68681->channel[ch].tx_data);
// if local loopback is on, write the transmitted data as if a byte had been received
if ((duart68681->channel[ch].MR2 & 0xC0) == 0x80)
{
if (duart68681->channel[ch].rx_fifo_num >= RX_FIFO_SIZE)
{
LOG(( "68681: FIFO overflow\n" ));
duart68681->channel[ch].SR |= STATUS_OVERRUN_ERROR;
}
else
{
duart68681->channel[ch].rx_fifo[duart68681->channel[ch].rx_fifo_write_ptr++]
= duart68681->channel[ch].tx_data;
if (duart68681->channel[ch].rx_fifo_write_ptr == RX_FIFO_SIZE)
{
duart68681->channel[ch].rx_fifo_write_ptr = 0;
}
duart68681->channel[ch].rx_fifo_num++;
}
}
duart68681->channel[ch].tx_ready = 1;
duart68681->channel[ch].SR |= STATUS_TRANSMITTER_READY;
if (ch == 0)
duart68681->ISR |= INT_TXRDYA;
else
duart68681->ISR |= INT_TXRDYB;
duart68681_update_interrupts(duart68681);
duart68681->channel[ch].tx_timer->adjust(attotime::never, ch);
};
static void duart68681_write_TX(duart68681_state* duart68681, int ch, UINT8 data)
{
attotime period;
duart68681->channel[ch].tx_data = data;
duart68681->channel[ch].tx_ready = 0;
duart68681->channel[ch].SR &= ~STATUS_TRANSMITTER_READY;
if (ch == 0)
duart68681->ISR &= ~INT_TXRDYA;
else
duart68681->ISR &= ~INT_TXRDYB;
duart68681_update_interrupts(duart68681);
period = attotime::from_hz(duart68681->channel[ch].baud_rate / 10 );
duart68681->channel[ch].tx_timer->adjust(period, ch);
};
READ8_DEVICE_HANDLER( duart68681_r )
{
duart68681_state* duart68681 = get_safe_token(device);
UINT8 r = 0xff;
offset &= 0xf;
LOG(( "Reading 68681 (%s) reg %x (%s) ", device->tag(), offset, duart68681_reg_read_names[offset] ));
switch (offset)
{
case 0x00: /* MR1A/MR2A */
if ( duart68681->channel[0].MR_ptr == 0 )
{
r = duart68681->channel[0].MR1;
duart68681->channel[0].MR_ptr = 1;
}
else
{
r = duart68681->channel[0].MR2;
}
break;
case 0x01: /* SRA */
r = duart68681->channel[0].SR;
break;
case 0x03: /* Rx Holding Register A */
r = duart68681_read_rx_fifo(duart68681, 0);
break;
case 0x04: /* IPCR */
{
UINT8 IP;
if ( duart68681->duart_config->input_port_read != NULL )
IP = duart68681->duart_config->input_port_read(duart68681->device);
else
IP = 0x0;
r = (((duart68681->IP_last_state ^ IP) & 0x0f) << 4) | (IP & 0x0f);
duart68681->IP_last_state = IP;
duart68681->ISR &= ~INT_INPUT_PORT_CHANGE;
duart68681_update_interrupts(duart68681);
}
break;
case 0x05: /* ISR */
r = duart68681->ISR;
break;
case 0x06: /* CUR */
r = duart68681_get_ct_count(duart68681) >> 8;
break;
case 0x07: /* CLR */
r = duart68681_get_ct_count(duart68681) & 0xff;
break;
case 0x08: /* MR1B/MR2B */
if ( duart68681->channel[1].MR_ptr == 0 )
{
r = duart68681->channel[1].MR1;
duart68681->channel[1].MR_ptr = 1;
}
else
{
r = duart68681->channel[1].MR2;
}
break;
case 0x09: /* SRB */
r = duart68681->channel[1].SR;
break;
case 0x0b: /* RHRB */
r = duart68681_read_rx_fifo(duart68681, 1);
break;
case 0x0d: /* IP */
if ( duart68681->duart_config->input_port_read != NULL )
r = duart68681->duart_config->input_port_read(duart68681->device);
else
{
r = 0xff;
#if 0
if (device->machine().input().code_pressed(KEYCODE_1)) r ^= 0x0001;
if (device->machine().input().code_pressed(KEYCODE_2)) r ^= 0x0002;
if (device->machine().input().code_pressed(KEYCODE_3)) r ^= 0x0004;
if (device->machine().input().code_pressed(KEYCODE_4)) r ^= 0x0008;
if (device->machine().input().code_pressed(KEYCODE_5)) r ^= 0x0010;
if (device->machine().input().code_pressed(KEYCODE_6)) r ^= 0x0020;
if (device->machine().input().code_pressed(KEYCODE_7)) r ^= 0x0040;
if (device->machine().input().code_pressed(KEYCODE_8)) r ^= 0x0080;
#endif
}
break;
case 0x0e: /* Start counter command */
{
if (duart68681->ACR & 0x40)
{
// Reset the timer
duart68681->half_period = 0;
// TODO: Set OP3 to 1
}
int count = MAX(duart68681->CTR.w.l, 1);
duart68681_start_ct(duart68681, count);
break;
}
case 0x0f: /* Stop counter command */
duart68681->ISR &= ~INT_COUNTER_READY;
// Stop the counter only
if (!(duart68681->ACR & 0x40))
duart68681->duart_timer->adjust(attotime::never);
duart68681_update_interrupts(duart68681);
break;
default:
LOG(( "Reading unhandled 68681 reg %x\n", offset ));
break;
}
LOG(("returned %02x\n", r));
return r;
}
WRITE8_DEVICE_HANDLER( duart68681_w )
{
duart68681_state* duart68681 = get_safe_token(device);
offset &= 0x0f;
LOG(( "Writing 68681 (%s) reg %x (%s) with %04x\n", device->tag(), offset, duart68681_reg_write_names[offset], data ));
switch(offset)
{
case 0x00: /* MRA */
duart68681_write_MR(duart68681, 0, data);
break;
case 0x01: /* CSRA */
duart68681_write_CSR(duart68681, 0, data, duart68681->ACR);
break;
case 0x02: /* CRA */
duart68681_write_CR(duart68681, 0, data);
break;
case 0x03: /* THRA */
duart68681_write_TX(duart68681, 0, data);
break;
case 0x04: /* ACR */
{
UINT8 old_acr = duart68681->ACR;
duart68681->ACR = data;
// bits 6-4: Counter/Timer Mode And Clock Source Select
// bits 3-0: IP3-0 Change-Of-State Interrupt Enable
if ((old_acr ^ data) & 0x40)
{
if (data & 0x40)
{
// Entering timer mode
UINT16 count = MAX(duart68681->CTR.w.l, 1);
duart68681->half_period = 0;
// TODO: Set OP3
duart68681_start_ct(duart68681, count);
}
else
{
// Leaving timer mode (TODO: is this correct?)
duart68681->duart_timer->adjust(attotime::never);
}
}
duart68681_write_CSR(duart68681, 0, duart68681->channel[0].CSR, data);
duart68681_write_CSR(duart68681, 1, duart68681->channel[1].CSR, data);
duart68681_update_interrupts(duart68681); // need to add ACR checking for IP delta ints
break;
}
case 0x05: /* IMR */
duart68681->IMR = data;
duart68681_update_interrupts(duart68681);
break;
case 0x06: /* CTUR */
duart68681->CTR.b.h = data;
break;
case 0x07: /* CTLR */
duart68681->CTR.b.l = data;
break;
case 0x08: /* MRB */
duart68681_write_MR(duart68681, 1, data);
break;
case 0x09: /* CSRB */
duart68681_write_CSR(duart68681, 1, data, duart68681->ACR);
break;
case 0x0a: /* CRB */
duart68681_write_CR(duart68681, 1, data);
break;
case 0x0b: /* THRB */
duart68681_write_TX(duart68681, 1, data);
break;
case 0x0c: /* IVR */
duart68681->IVR = data;
break;
case 0x0d: /* OPCR */
if (data != 0x00)
logerror( "68681 (%s): Unhandled OPCR value: %02x\n", device->tag(), data);
duart68681->OPCR = data;
break;
case 0x0e: /* Set Output Port Bits */
duart68681->OPR |= data;
if (duart68681->duart_config->output_port_write)
duart68681->duart_config->output_port_write(duart68681->device, duart68681->OPR ^ 0xff);
break;
case 0x0f: /* Reset Output Port Bits */
duart68681->OPR &= ~data;
if (duart68681->duart_config->output_port_write)
duart68681->duart_config->output_port_write(duart68681->device, duart68681->OPR ^ 0xff);
break;
}
}
void duart68681_rx_data( device_t* device, int ch, UINT8 data )
{
duart68681_state *duart68681 = get_safe_token(device);
if ( duart68681->channel[ch].rx_enabled )
{
if ( duart68681->channel[ch].rx_fifo_num >= RX_FIFO_SIZE )
{
LOG(( "68681: FIFO overflow\n" ));
duart68681->channel[ch].SR |= STATUS_OVERRUN_ERROR;
return;
}
duart68681->channel[ch].rx_fifo[duart68681->channel[ch].rx_fifo_write_ptr++] = data;
if ( duart68681->channel[ch].rx_fifo_write_ptr == RX_FIFO_SIZE )
{
duart68681->channel[ch].rx_fifo_write_ptr = 0;
}
duart68681->channel[ch].rx_fifo_num++;
duart68681_update_interrupts(duart68681);
}
};
/*-------------------------------------------------
device start callback
-------------------------------------------------*/
static DEVICE_START(duart68681)
{
duart68681_state *duart68681 = get_safe_token(device);
/* validate arguments */
assert(device != NULL);
duart68681->duart_config = (const duart68681_config *)device->static_config();
duart68681->device = device;
duart68681->channel[0].tx_timer = device->machine().scheduler().timer_alloc(FUNC(tx_timer_callback), (void*)device);
duart68681->channel[1].tx_timer = device->machine().scheduler().timer_alloc(FUNC(tx_timer_callback), (void*)device);
duart68681->duart_timer = device->machine().scheduler().timer_alloc(FUNC(duart_timer_callback), (void*)device);
device->save_item(NAME(duart68681->ACR));
device->save_item(NAME(duart68681->IMR));
device->save_item(NAME(duart68681->ISR));
device->save_item(NAME(duart68681->IVR));
device->save_item(NAME(duart68681->OPCR));
device->save_item(NAME(duart68681->CTR));
device->save_item(NAME(duart68681->IP_last_state));
device->save_item(NAME(duart68681->half_period));
device->save_item(NAME(duart68681->channel[0].CR));
device->save_item(NAME(duart68681->channel[0].CSR));
device->save_item(NAME(duart68681->channel[0].MR1));
device->save_item(NAME(duart68681->channel[0].MR2));
device->save_item(NAME(duart68681->channel[0].MR_ptr));
device->save_item(NAME(duart68681->channel[0].SR));
device->save_item(NAME(duart68681->channel[0].baud_rate));
device->save_item(NAME(duart68681->channel[0].rx_enabled));
device->save_item(NAME(duart68681->channel[0].rx_fifo));
device->save_item(NAME(duart68681->channel[0].rx_fifo_read_ptr));
device->save_item(NAME(duart68681->channel[0].rx_fifo_write_ptr));
device->save_item(NAME(duart68681->channel[0].rx_fifo_num));
device->save_item(NAME(duart68681->channel[0].tx_enabled));
device->save_item(NAME(duart68681->channel[0].tx_data));
device->save_item(NAME(duart68681->channel[0].tx_ready));
device->save_item(NAME(duart68681->channel[1].CR));
device->save_item(NAME(duart68681->channel[1].CSR));
device->save_item(NAME(duart68681->channel[1].MR1));
device->save_item(NAME(duart68681->channel[1].MR2));
device->save_item(NAME(duart68681->channel[1].MR_ptr));
device->save_item(NAME(duart68681->channel[1].SR));
device->save_item(NAME(duart68681->channel[1].baud_rate));
device->save_item(NAME(duart68681->channel[1].rx_enabled));
device->save_item(NAME(duart68681->channel[1].rx_fifo));
device->save_item(NAME(duart68681->channel[1].rx_fifo_read_ptr));
device->save_item(NAME(duart68681->channel[1].rx_fifo_write_ptr));
device->save_item(NAME(duart68681->channel[1].rx_fifo_num));
device->save_item(NAME(duart68681->channel[1].tx_enabled));
device->save_item(NAME(duart68681->channel[1].tx_data));
device->save_item(NAME(duart68681->channel[1].tx_ready));
}
/*-------------------------------------------------
device reset callback
-------------------------------------------------*/
static DEVICE_RESET(duart68681)
{
duart68681_state *duart68681 = get_safe_token(device);
emu_timer *save0, *save1;
duart68681->ACR = 0; /* Interrupt Vector Register */
duart68681->IVR = 0x0f; /* Interrupt Vector Register */
duart68681->IMR = 0; /* Interrupt Mask Register */
duart68681->ISR = 0; /* Interrupt Status Register */
duart68681->OPCR = 0; /* Output Port Conf. Register */
duart68681->OPR = 0; /* Output Port Register */
duart68681->CTR.d = 0; /* Counter/Timer Preset Value */
duart68681->IP_last_state = 0; /* last state of IP bits */
// "reset clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR) puts OP0-7 in the high state, stops the counter/timer, and puts channels a/b in the inactive state"
save0 = duart68681->channel[0].tx_timer;
save1 = duart68681->channel[1].tx_timer;
memset(duart68681->channel, 0, sizeof(duart68681->channel));
duart68681->channel[0].tx_timer = save0;
duart68681->channel[1].tx_timer = save1;
if (duart68681->duart_config->output_port_write)
duart68681->duart_config->output_port_write(duart68681->device, duart68681->OPR ^ 0xff);
// reset timers
duart68681->channel[0].tx_timer->adjust(attotime::never);
duart68681->channel[1].tx_timer->adjust(attotime::never, 1);
}
const device_type DUART68681 = &device_creator<duart68681_device>;
duart68681_device::duart68681_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: device_t(mconfig, DUART68681, "DUART 68681", tag, owner, clock, "duart68681", __FILE__)
{
m_token = global_alloc_clear(duart68681_state);
}
duart68681_device::~duart68681_device()
{
global_free(m_token);
}
//-------------------------------------------------
// device_config_complete - perform any
// operations now that the configuration is
// complete
//-------------------------------------------------
void duart68681_device::device_config_complete()
{
}
//-------------------------------------------------
// device_start - device-specific startup
//-------------------------------------------------
void duart68681_device::device_start()
{
DEVICE_START_NAME( duart68681 )(this);
}
//-------------------------------------------------
// device_reset - device-specific reset
//-------------------------------------------------
void duart68681_device::device_reset()
{
DEVICE_RESET_NAME( duart68681 )(this);
}

46
src/emu/machine/68681.h
View File

@ -1,46 +0,0 @@
#ifndef _68681_H
#define _68681_H
struct duart68681_config
{
void (*irq_handler)(device_t *device, int state, UINT8 vector);
void (*tx_callback)(device_t *device, int channel, UINT8 data);
UINT8 (*input_port_read)(device_t *device);
void (*output_port_write)(device_t *device, UINT8 data);
/* clocks for external baud rates */
INT32 ip3clk, ip4clk, ip5clk, ip6clk;
};
class duart68681_device : public device_t
{
public:
duart68681_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
~duart68681_device();
// access to legacy token
struct duart68681_state *token() const { assert(m_token != NULL); return m_token; }
protected:
// device-level overrides
virtual void device_config_complete();
virtual void device_start();
virtual void device_reset();
private:
// internal state
struct duart68681_state *m_token;
};
extern ATTR_DEPRECATED const device_type DUART68681;
#define MCFG_DUART68681_ADD(_tag, _clock, _config) \
MCFG_DEVICE_ADD(_tag, DUART68681, _clock) \
MCFG_DEVICE_CONFIG(_config)
DECLARE_READ8_DEVICE_HANDLER(duart68681_r);
DECLARE_WRITE8_DEVICE_HANDLER(duart68681_w);
void duart68681_rx_data( device_t* device, int ch, UINT8 data );
#endif //_68681_H

2
src/emu/machine/machine.mak
View File

@ -109,12 +109,10 @@ endif
#-------------------------------------------------
#
#@src/emu/machine/68681.h,MACHINES += 68681
#@src/emu/machine/n68681.h,MACHINES += 68681
#-------------------------------------------------
ifneq ($(filter 68681,$(MACHINES)),)
MACHINEOBJS += $(MACHINEOBJ)/68681.o
MACHINEOBJS += $(MACHINEOBJ)/n68681.o
endif

36
src/mame/drivers/bfm_sc4h.c
View File

@ -610,7 +610,7 @@ MACHINE_START_MEMBER(sc4_state,sc4)
bfm_sc4_68307_porta_w,
bfm_sc4_68307_portb_r,
bfm_sc4_68307_portb_w );
m68307_set_duart68681(m_maincpu,machine().device("m68307_68681"));
m68307_set_duart68681(m_maincpu, m_m68307_68681);
@ -672,47 +672,31 @@ WRITE8_MEMBER(sc4_state::bfm_sc4_duart_output_w)
awp_draw_reel(5);
}
void m68307_duart_irq_handler(device_t *device, int state, UINT8 vector)
WRITE_LINE_MEMBER(sc4_state::m68307_duart_irq_handler)
{
sc4_state *drvstate = device->machine().driver_data<sc4_state>();
logerror("m68307_duart_irq_handler\n");
if (state == ASSERT_LINE)
{
m68307_serial_interrupt(drvstate->m_maincpu, vector);
m68307_serial_interrupt(m_maincpu, m_m68307_68681->get_irq_vector());
}
}
void m68307_duart_tx(device_t *device, int channel, UINT8 data)
WRITE_LINE_MEMBER(sc4_state::m68307_duart_txa)
{
if (channel==0)
{
logerror("m68307_duart_tx %02x\n",data);
}
else
{
printf("(illegal channel 1) m68307_duart_tx %02x\n",data);
}
logerror("m68307_duart_tx %02x\n",state);
}
UINT8 m68307_duart_input_r(device_t *device)
READ8_MEMBER(sc4_state::m68307_duart_input_r)
{
logerror("m68307_duart_input_r\n");
return 0x00;
}
void m68307_duart_output_w(device_t *device, UINT8 data)
WRITE8_MEMBER(sc4_state::m68307_duart_output_w)
{
logerror("m68307_duart_output_w %02x\n", data);
}
static const duart68681_config m68307_duart68681_config =
{
m68307_duart_irq_handler,
m68307_duart_tx,
m68307_duart_input_r,
m68307_duart_output_w
};
/* default dmd */
static void bfmdm01_busy(running_machine &machine, int state)
{
@ -731,7 +715,11 @@ MACHINE_CONFIG_START( sc4, sc4_state )
MCFG_CPU_PROGRAM_MAP(sc4_map)
// internal duart of the 68307... paired in machine start
MCFG_DUART68681_ADD("m68307_68681", 16000000/4, m68307_duart68681_config) // ?? Mhz
MCFG_DUARTN68681_ADD("m68307_68681", 16000000/4) // ?? Mhz
MCFG_DUARTN68681_IRQ_CALLBACK(WRITELINE(sc4_state, m68307_duart_irq_handler))
MCFG_DUARTN68681_A_TX_CALLBACK(WRITELINE(sc4_state, m68307_duart_txa))
MCFG_DUARTN68681_INPORT_CALLBACK(READ8(sc4_state, m68307_duart_input_r))
MCFG_DUARTN68681_OUTPORT_CALLBACK(WRITE8(sc4_state, m68307_duart_output_w))
MCFG_MACHINE_START_OVERRIDE(sc4_state, sc4 )
MCFG_MACHINE_RESET_OVERRIDE(sc4_state, sc4 )

19
src/mame/drivers/micro3d.c
View File

@ -25,7 +25,7 @@
#include "cpu/m68000/m68000.h"
#include "cpu/am29000/am29000.h"
#include "cpu/mcs51/mcs51.h"
#include "machine/68681.h"
#include "machine/n68681.h"
#include "machine/mc68901.h"
#include "sound/2151intf.h"
#include "machine/nvram.h"
@ -207,7 +207,7 @@ static ADDRESS_MAP_START( hostmem, AS_PROGRAM, 16, micro3d_state )
AM_RANGE(0x9a0000, 0x9a0007) AM_READWRITE(micro3d_tms_host_r, micro3d_tms_host_w)
AM_RANGE(0x9c0000, 0x9c0001) AM_NOP /* Lamps */
AM_RANGE(0x9e0000, 0x9e002f) AM_DEVREADWRITE8("mc68901", mc68901_device, read, write, 0xff00)
AM_RANGE(0xa00000, 0xa0003f) AM_DEVREADWRITE8_LEGACY("duart68681", duart68681_r, duart68681_w, 0xff00)
AM_RANGE(0xa00000, 0xa0003f) AM_DEVREADWRITE8("duart68681", duartn68681_device, read, write, 0xff00)
AM_RANGE(0xa20000, 0xa20001) AM_READ(micro3d_encoder_h_r)
AM_RANGE(0xa40002, 0xa40003) AM_READ(micro3d_encoder_l_r)
ADDRESS_MAP_END
@ -299,15 +299,6 @@ static const tms34010_config vgb_config =
NULL
};
static const duart68681_config micro3d_duart68681_config =
{
micro3d_duart_irq_handler,
micro3d_duart_tx,
micro3d_duart_input_r,
micro3d_duart_output_w
};
/*************************************
*
* Machine driver
@ -332,7 +323,11 @@ static MACHINE_CONFIG_START( micro3d, micro3d_state )
MCFG_CPU_PROGRAM_MAP(soundmem_prg)
MCFG_CPU_IO_MAP(soundmem_io)
MCFG_DUART68681_ADD("duart68681", XTAL_3_6864MHz, micro3d_duart68681_config)
MCFG_DUARTN68681_ADD("duart68681", XTAL_3_6864MHz)
MCFG_DUARTN68681_IRQ_CALLBACK(WRITELINE(micro3d_state, duart_irq_handler))
MCFG_DUARTN68681_B_TX_CALLBACK(WRITELINE(micro3d_state, duart_txb))
MCFG_DUARTN68681_INPORT_CALLBACK(READ8(micro3d_state, duart_input_r))
MCFG_DUARTN68681_OUTPORT_CALLBACK(WRITE8(micro3d_state, duart_output_w))
MCFG_DEVICE_ADD("mc68901", MC68901, 4000000)
MCFG_MC68901_TIMER_CLOCK(4000000)

9
src/mame/includes/bfm_sc45.h
View File

@ -54,6 +54,7 @@ public:
sc4_state(const machine_config &mconfig, device_type type, const char *tag)
: bfm_sc45_state(mconfig, type, tag),
m_maincpu(*this, "maincpu"),
m_m68307_68681(*this, "m68307_68681"),
m_cpuregion(*this, "maincpu"),
m_nvram(*this, "nvram"),
m_io1(*this, "IN-0"),
@ -74,6 +75,7 @@ public:
}
required_device<m68307cpu_device> m_maincpu;
required_device<duartn68681_device> m_m68307_68681;
required_memory_region m_cpuregion;
// devices
required_device<nvram_device> m_nvram;
@ -108,7 +110,12 @@ public:
DECLARE_WRITE_LINE_MEMBER(bfm_sc4_duart_txa);
DECLARE_READ8_MEMBER(bfm_sc4_duart_input_r);
DECLARE_WRITE8_MEMBER(bfm_sc4_duart_output_w);
DECLARE_WRITE_LINE_MEMBER(m68307_duart_irq_handler);
DECLARE_WRITE_LINE_MEMBER(m68307_duart_txa);
DECLARE_READ8_MEMBER(m68307_duart_input_r);
DECLARE_WRITE8_MEMBER(m68307_duart_output_w);
DECLARE_DRIVER_INIT(sc4);
DECLARE_DRIVER_INIT(sc4mbus);
DECLARE_DRIVER_INIT(sc4cvani);

19
src/mame/includes/micro3d.h
View File

@ -7,6 +7,7 @@
#include "cpu/tms34010/tms34010.h"
#include "cpu/mcs51/mcs51.h"
#include "sound/upd7759.h"
#include "machine/n68681.h"
#define HOST_MONITOR_DISPLAY 0
@ -33,10 +34,10 @@ public:
m_upd7759(*this, "upd7759"),
m_drmath(*this, "drmath"),
m_vgb(*this, "vgb"),
m_palette(*this, "palette") { }
m_palette(*this, "palette"),
m_duart68681(*this, "duart68681") { }
required_shared_ptr<UINT16> m_shared_ram;
device_t *m_duart68681;
UINT8 m_m68681_tx0;
/* Sound */
@ -133,12 +134,18 @@ public:
DECLARE_WRITE8_MEMBER(micro3d_upd7759_w);
DECLARE_WRITE8_MEMBER(data_from_i8031);
DECLARE_READ8_MEMBER(data_to_i8031);
DECLARE_WRITE_LINE_MEMBER(duart_irq_handler);
DECLARE_READ8_MEMBER(duart_input_r);
DECLARE_WRITE8_MEMBER(duart_output_w);
DECLARE_WRITE_LINE_MEMBER(duart_txb);
required_device<cpu_device> m_maincpu;
required_device<i8051_device> m_audiocpu;
required_device<upd7759_device> m_upd7759;
required_device<cpu_device> m_drmath;
required_device<tms34010_device> m_vgb;
required_device<palette_device> m_palette;
required_device<duartn68681_device> m_duart68681;
protected:
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
@ -149,14 +156,6 @@ struct micro3d_vtx
INT32 x, y, z;
};
/*----------- defined in machine/micro3d.c -----------*/
void micro3d_duart_irq_handler(device_t *device, int state, UINT8 vector);
UINT8 micro3d_duart_input_r(device_t *device);
void micro3d_duart_output_w(device_t *device, UINT8 data);
void micro3d_duart_tx(device_t *device, int channel, UINT8 data);
/*----------- defined in audio/micro3d.c -----------*/
struct biquad

38
src/mame/machine/micro3d.c
View File

@ -9,7 +9,6 @@
#include "cpu/tms34010/tms34010.h"
#include "cpu/am29000/am29000.h"
#include "cpu/mcs51/mcs51.h"
#include "machine/68681.h"
#include "includes/micro3d.h"
@ -29,29 +28,17 @@
*
*************************************/
void micro3d_duart_irq_handler(device_t *device, int state, UINT8 vector)
WRITE_LINE_MEMBER(micro3d_state::duart_irq_handler)
{
micro3d_state *drvstate = device->machine().driver_data<micro3d_state>();
drvstate->m_maincpu->set_input_line_and_vector(3, state, vector);
m_maincpu->set_input_line_and_vector(3, state, m_duart68681->get_irq_vector());
};
void micro3d_duart_tx(device_t *device, int channel, UINT8 data)
WRITE_LINE_MEMBER(micro3d_state::duart_txb)
{
micro3d_state *state = device->machine().driver_data<micro3d_state>();
if (channel == 0)
{
#if HOST_MONITOR_DISPLAY
mame_debug_printf("%c", data);
#endif
}
else
{
state->m_m68681_tx0 = data;
state->m_audiocpu->set_input_line(MCS51_RX_LINE, ASSERT_LINE);
// TODO: next line should be behind a timer callback which lasts one audiocpu clock cycle
state->m_audiocpu->set_input_line(MCS51_RX_LINE, CLEAR_LINE);
}
m_m68681_tx0 = state;
m_audiocpu->set_input_line(MCS51_RX_LINE, ASSERT_LINE);
// TODO: next line should be behind a timer callback which lasts one audiocpu clock cycle
m_audiocpu->set_input_line(MCS51_RX_LINE, CLEAR_LINE);
};
READ8_MEMBER(micro3d_state::data_to_i8031)
@ -61,7 +48,7 @@ READ8_MEMBER(micro3d_state::data_to_i8031)
WRITE8_MEMBER(micro3d_state::data_from_i8031)
{
duart68681_rx_data(m_duart68681, 1, data);
m_duart68681->rx_b_w(data);
}
/*
@ -72,7 +59,7 @@ WRITE8_MEMBER(micro3d_state::data_from_i8031)
* 4: -
* 5: -
*/
UINT8 micro3d_duart_input_r(device_t *device)
READ8_MEMBER(micro3d_state::duart_input_r)
{
return 0x2;
}
@ -81,10 +68,9 @@ UINT8 micro3d_duart_input_r(device_t *device)
* 5: /I8051 reset
* 7: Status LED
*/
void micro3d_duart_output_w(device_t *device, UINT8 data)
WRITE8_MEMBER(micro3d_state::duart_output_w)
{
micro3d_state *drvstate = device->machine().driver_data<micro3d_state>();
drvstate->m_audiocpu->set_input_line(INPUT_LINE_RESET, data & 0x20 ? CLEAR_LINE : ASSERT_LINE);
m_audiocpu->set_input_line(INPUT_LINE_RESET, data & 0x20 ? CLEAR_LINE : ASSERT_LINE);
}
@ -620,8 +606,6 @@ DRIVER_INIT_MEMBER(micro3d_state,micro3d)
m_audiocpu->i8051_set_serial_tx_callback(write8_delegate(FUNC(micro3d_state::data_from_i8031),this));
m_audiocpu->i8051_set_serial_rx_callback(read8_delegate(FUNC(micro3d_state::data_to_i8031),this));
m_duart68681 = machine().device("duart68681");
/* The Am29000 program seems to rely on RAM from 0x00470000 onwards being
non-zero on a reset, otherwise the 3D object data doesn't get uploaded! */
space.write_dword(0x00470000, 0xa5a5a5a5);