mirror of
https://github.com/holub/mame
synced 2025-05-22 13:48:55 +03:00
MN10200 updates: [R. Belmont]
- Better IRQ generation and hookup to MAME IRQ system - Preliminary 8-bit timer hookup including prescalers and IRQs - Fixed issue with debugger not showing registers correctly
This commit is contained in:
R. Belmont
parent
7e03d81ecd
commit
80637b51a4
@ -2,7 +2,7 @@
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Panasonic MN10200 emulator
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Written by Olivier Galibert
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MAME conversion by R. Belmont
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MAME conversion, timers, and IRQ controller by R. Belmont
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*/
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@ -16,6 +16,10 @@
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#define MEM_BYTE (0)
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#define MEM_WORD (1)
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#define NUM_PRESCALERS (2)
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#define NUM_TIMERS_8BIT (10)
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#define NUM_IRQ_GROUPS (31)
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extern int mn102_disassemble(char *buffer, UINT32 pc, const UINT8 *oprom);
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typedef struct _mn102_info mn102_info;
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@ -27,30 +31,31 @@ struct _mn102_info
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UINT32 a[4];
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UINT8 nmicr, iagr;
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UINT8 icrl[31], icrh[31];
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UINT8 icrl[NUM_IRQ_GROUPS], icrh[NUM_IRQ_GROUPS];
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UINT16 psw;
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UINT16 mdr;
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struct {
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struct _simple_timer {
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UINT8 mode;
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UINT8 base;
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UINT8 cur;
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} simple_timer[10];
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} simple_timer[NUM_TIMERS_8BIT];
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struct {
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emu_timer *timer_timers[NUM_TIMERS_8BIT];
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struct _prescaler {
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UINT8 cycles;
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UINT8 mode;
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UINT8 base;
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UINT8 cur;
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} prescaler[2];
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} prescaler[NUM_PRESCALERS];
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struct {
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struct _dma {
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UINT32 adr;
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UINT32 count;
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UINT16 iadr;
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UINT8 ctrll, ctrlh, irq;
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} dma[8];
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struct {
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struct _serial {
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UINT8 ctrll, ctrlh;
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UINT8 buf;
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} serial[2];
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@ -121,6 +126,26 @@ INLINE void mn102_write_word(mn102_info *mn102, UINT32 address, UINT16 data)
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memory_write_word_16le(mn102->program, address, data);
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}
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INLINE INT32 r24u(mn102_info *mn102, offs_t adr)
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{
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return mn102_read_word(mn102, adr)|(mn102_read_byte(mn102, adr+2)<<16);
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}
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INLINE void w24(mn102_info *mn102, offs_t adr, UINT32 val)
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{
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/* if(adr == 0x4075aa || adr == 0x40689a || adr == 0x4075a2) {
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log_write("TRACE", adr, val, MEM_LONG);
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}*/
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mn102_write_byte(mn102, adr, val);
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mn102_write_byte(mn102, adr+1, val>>8);
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mn102_write_byte(mn102, adr+2, val>>16);
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}
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INLINE void mn102_change_pc(mn102_info *mn102, UINT32 pc)
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{
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mn102->pc = pc & 0xffffff;
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}
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INLINE mn102_info *get_safe_token(running_device *device)
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{
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assert(device != NULL);
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@ -131,20 +156,156 @@ INLINE mn102_info *get_safe_token(running_device *device)
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return (mn102_info *)device->token;
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}
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static void mn102_take_irq(mn102_info *mn102, int level, int group)
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{
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if(!(mn102->psw & 0x800))
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{
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// if (group != 8) printf("MN10200: Dropping irq L %d G %d pc=%x, a3=%x\n", level, group, mn102->pc, mn102->a[3]);
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return;
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}
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// if (group != 8) printf("MN10200: Taking irq L %d G %d pc=%x, a3=%x\n", level, group, mn102->pc, mn102->a[3]);
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mn102->a[3] -= 6;
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w24(mn102, mn102->a[3]+2, mn102->pc);
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mn102_write_word(mn102, mn102->a[3], mn102->psw);
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mn102_change_pc(mn102, 0x80008);
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mn102->psw = (mn102->psw & 0xf0ff) | (level << 8);
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mn102->iagr = group << 1;
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}
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static void refresh_timer(mn102_info *cpustate, int tmr)
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{
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// enabled?
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if (cpustate->simple_timer[tmr].mode & 0x80)
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{
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UINT8 source = (cpustate->simple_timer[tmr].mode & 3);
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// source is a prescaler?
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if (source >= 2)
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{
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INT32 rate;
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// is prescaler enabled?
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if (cpustate->prescaler[source-2].mode & 0x80)
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{
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// rate = (sysclock / prescaler) / our count
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rate = cpu_get_clock(cpustate->device) / cpustate->prescaler[source-2].cycles;
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rate /= cpustate->simple_timer[tmr].base;
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if (tmr != 8) // HACK: timer 8 is run at 500 kHz by the Taito program for no obvious reason, which kills performance
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timer_adjust_oneshot(cpustate->timer_timers[tmr], ATTOTIME_IN_HZ(rate), tmr);
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}
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else
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{
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logerror("MN10200: timer %d using prescaler %d which isn't enabled!\n", tmr, source-2);
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}
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}
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}
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else // disabled, so stop it
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{
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timer_adjust_oneshot(cpustate->timer_timers[tmr], attotime_never, tmr);
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}
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}
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INLINE void timer_tick_simple(mn102_info *cpustate, int tmr)
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{
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cpustate->simple_timer[tmr].cur--;
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// did we expire?
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if (cpustate->simple_timer[tmr].cur == 0)
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{
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int group, irq_in_grp, level;
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// does timer auto-reload? apparently.
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cpustate->simple_timer[tmr].cur = cpustate->simple_timer[tmr].base;
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// signal the cascade if we're not timer 9
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if (tmr < (NUM_TIMERS_8BIT-1))
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{
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// is next timer enabled?
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if (cpustate->simple_timer[tmr+1].mode & 0x80)
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{
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// is it's source "cascade"?
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if ((cpustate->simple_timer[tmr+1].mode & 0x3) == 1)
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{
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// recurse!
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timer_tick_simple(cpustate, tmr+1);
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}
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}
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}
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// interrupt from this timer if possible
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group = (tmr / 4);
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irq_in_grp = (tmr % 4);
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level = (cpustate->icrh[group]>>4) & 0x7;
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// indicate interrupt pending
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cpustate->icrl[group] |= (1 << (4 + irq_in_grp));
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// interrupt detect = pending AND enable
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cpustate->icrl[group] |= (cpustate->icrh[group]&0x0f) & (cpustate->icrl[group]>>4);
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// is the result enabled?
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if (cpustate->icrl[group] & (1 << irq_in_grp))
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{
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// printf("Timer %d IRQ! (Group %d in_grp %d ICRH %x ICRL %x\n", tmr, group, irq_in_grp, cpustate->icrh[group], cpustate->icrl[group]);
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// try to take it now
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mn102_take_irq(cpustate, level, group + 1);
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}
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}
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}
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static TIMER_CALLBACK( simple_timer_cb )
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{
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mn102_info *cpustate = (mn102_info *)ptr;
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int tmr = param;
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// handle our expiring and also tick our cascaded children
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cpustate->simple_timer[tmr].cur = 1;
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timer_tick_simple(cpustate, tmr);
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// refresh this timer
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refresh_timer(cpustate, tmr);
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}
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static CPU_INIT(mn10200)
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{
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mn102_info *cpustate = get_safe_token(device);
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int tmr;
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memset(cpustate, 0, sizeof(mn102_info));
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cpustate->device = device;
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cpustate->program = device->space(AS_PROGRAM);
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cpustate->io = device->space(AS_IO);
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state_save_register_device_item(device, 0, cpustate->pc);
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state_save_register_device_item_array(device, 0, cpustate->d);
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state_save_register_device_item_array(device, 0, cpustate->a);
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state_save_register_device_item(device, 0, cpustate->nmicr);
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state_save_register_device_item(device, 0, cpustate->iagr);
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state_save_register_device_item_array(device, 0, cpustate->icrl);
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state_save_register_device_item_array(device, 0, cpustate->icrh);
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state_save_register_device_item(device, 0, cpustate->psw);
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state_save_register_device_item(device, 0, cpustate->mdr);
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// state_save_register_device_item_array(device, 0, cpustate->simple_timer);
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// state_save_register_device_item_array(device, 0, cpustate->prescaler);
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// state_save_register_device_item_array(device, 0, cpustate->dma);
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// state_save_register_device_item_array(device, 0, cpustate->serial);
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state_save_register_device_item_array(device, 0, cpustate->ddr);
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for (tmr = 0; tmr < NUM_TIMERS_8BIT; tmr++)
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{
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cpustate->timer_timers[tmr] = timer_alloc(device->machine, simple_timer_cb, cpustate);
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timer_adjust_oneshot(cpustate->timer_timers[tmr], attotime_never, tmr);
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}
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}
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static CPU_RESET(mn10200)
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{
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mn102_info *cpustate = get_safe_token(device);
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int tmr, grp;
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memset(cpustate->d, 0, sizeof(cpustate->d));
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memset(cpustate->a, 0, sizeof(cpustate->a));
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@ -153,6 +314,21 @@ static CPU_RESET(mn10200)
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cpustate->nmicr = 0;
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memset(cpustate->icrl, 0, sizeof(cpustate->icrl));
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memset(cpustate->icrh, 0, sizeof(cpustate->icrh));
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// reset all timers
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for (tmr = 0; tmr < NUM_TIMERS_8BIT; tmr++)
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{
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cpustate->simple_timer[tmr].mode = 0;
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cpustate->simple_timer[tmr].cur = 0;
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cpustate->simple_timer[tmr].base = 0;
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timer_adjust_oneshot(cpustate->timer_timers[tmr], attotime_never, tmr);
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}
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// clear all interrupt groups
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for (grp = 0; grp < NUM_IRQ_GROUPS; grp++)
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{
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cpustate->icrl[grp] = cpustate->icrh[grp] = 0;
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}
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}
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static CPU_EXIT(mn10200)
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@ -164,21 +340,6 @@ static void unemul(mn102_info *mn102)
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fatalerror("MN10200: unknown opcode @ PC=%x\n", mn102->pc);
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}
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INLINE INT32 r24u(mn102_info *mn102, offs_t adr)
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{
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return mn102_read_word(mn102, adr)|(mn102_read_byte(mn102, adr+2)<<16);
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}
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INLINE void w24(mn102_info *mn102, offs_t adr, UINT32 val)
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{
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if(adr == 0x4075aa || adr == 0x40689a || adr == 0x4075a2) {
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log_write("TRACE", adr, val, MEM_LONG);
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}
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mn102_write_byte(mn102, adr, val);
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mn102_write_byte(mn102, adr+1, val>>8);
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mn102_write_byte(mn102, adr+2, val>>16);
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}
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static UINT32 do_add(mn102_info *mn102, UINT32 a, UINT32 b)
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{
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UINT32 r24, r16;
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@ -302,11 +463,6 @@ INLINE void test_nz16(mn102_info *mn102, UINT16 v)
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mn102->psw |= 1;
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}
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INLINE void mn102_change_pc(mn102_info *mn102, UINT32 pc)
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{
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mn102->pc = pc & 0xffffff;
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}
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INLINE void do_jsr(mn102_info *mn102, UINT32 to, UINT32 ret)
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{
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mn102_change_pc(mn102, to & 0xffffff);
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@ -329,27 +485,29 @@ INLINE void do_jsr(mn102_info *mn102, UINT32 to, UINT32 ret)
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psw & 0x0001 ? 'z' : '-');
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#endif
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void mn102_force_irq(mn102_info *mn102, int level, int group, int entry)
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// take an external IRQ
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static void mn102_extirq(mn102_info *mn102, int irqnum, int status)
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{
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if(!(mn102->psw & 0x800))
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{
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if(group != 1 || entry != 3){
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log_event("MN102", "Dropping irq %d %d %d, pc=%x, a3=%x", level, group, entry, mn102->pc, mn102->a[3]);
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}
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return;
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}
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int level = (mn102->icrh[7]>>4)&0x7;
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if(group != 1 || entry != 3) {
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log_event("MN102", "Taking irq %d %d %d, pc=%x, a3=%x", level, group, entry, mn102->pc, mn102->a[3]);
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// printf("mn102_extirq: irq %d status %d G8 ICRL %x\n", irqnum, status, mn102->icrl[7]);
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// if interrupt is enabled, handle it
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if (status)
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{
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// indicate interrupt pending
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mn102->icrl[7] |= (1 << (4 + irqnum));
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// set interrupt detect = pending AND enable
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mn102->icrl[7] |= (mn102->icrh[7]&0x0f) & (mn102->icrl[7]>>4);
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// is the result enabled?
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if (mn102->icrl[7] & (1 << irqnum))
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{
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// try to take it now
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mn102_take_irq(mn102, level, 8);
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}
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}
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mn102->a[3] -= 6;
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w24(mn102, mn102->a[3]+2, mn102->pc);
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mn102_write_word(mn102, mn102->a[3], mn102->psw);
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mn102_change_pc(mn102, 0x80008);
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mn102->psw = (mn102->psw & 0xf0ff) | (level << 8);
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mn102->iagr = group << 1;
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if(group != 0)
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mn102->icrl[group-1] |= 1 << entry;
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}
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static CPU_EXECUTE(mn10200)
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@ -1715,21 +1873,24 @@ static void mn10200_w(mn102_info *mn102, UINT32 adr, UINT32 data, int type)
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// Maskable irq control
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case 0x042: case 0x044: case 0x046: case 0x048: case 0x04a:
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case 0x04c: case 0x04e: case 0x050: case 0x052: case 0x054:
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{
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// note: writes here ack interrupts
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mn102->icrl[((adr & 0x3f)>>1)-1] = data;
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}
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break;
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case 0x043: case 0x045: case 0x047: case 0x049: case 0x04b:
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case 0x04d: case 0x04f: case 0x051: case 0x053: case 0x055: {
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int irq = ((adr & 0x3f)>>1)-1;
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if((mn102->icrh[irq] != data) && (data & 15)) {
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log_event("MN102", "irq %d enabled, level=%x, enable= %s %s %s %s", irq+1, (data >> 4) & 7,
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printf("MN10200: irq %d enabled, level=%x, enable= %s %s %s %s\n", irq+1, (data >> 4) & 7,
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data & 1 ? inames[irq][0] : "-",
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data & 2 ? inames[irq][1] : "-",
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data & 4 ? inames[irq][2] : "-",
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data & 8 ? inames[irq][3] : "-");
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}
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if((mn102->icrh[irq] != data) && !(data & 15)) {
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log_event("MN102", "irq %d disabled", irq+1);
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printf("MN10200: irq %d disabled\n", irq+1);
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}
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mn102->icrh[irq] = data;
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break;
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@ -1795,47 +1956,64 @@ static void mn10200_w(mn102_info *mn102, UINT32 adr, UINT32 data, int type)
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case 0x210: case 0x211: case 0x212: case 0x213: case 0x214:
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case 0x215: case 0x216: case 0x217: case 0x218: case 0x219:
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log_event("MN102", "Timer %d value set %02x", adr-0x210, data);
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mn102->simple_timer[adr-0x210].base = data + 1;
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// printf("MN10200: Timer %d value set %02x\n", adr-0x210, data);
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refresh_timer(mn102, adr-0x210);
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break;
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case 0x21a:
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log_event("MN102", "Prescale 0 cycle count %02x", data);
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mn102->prescaler[0].cycles = data+1;
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// printf("MN10200: Prescale 0 cycle count %d\n", data+1);
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break;
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case 0x21b:
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log_event("MN102", "Prescale 1 cycle count %02x", data);
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mn102->prescaler[1].cycles = data+1;
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// printf("MN10200: Prescale 1 cycle count %d\n", data+1);
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break;
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case 0x220: case 0x221: case 0x222: case 0x223: case 0x224:
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case 0x225: case 0x226: case 0x227: case 0x228: case 0x229: {
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case 0x225: case 0x226: case 0x227: case 0x228: case 0x229:
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{
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// const char *source[4] = { "TMxIO", "cascade", "prescale 0", "prescale 1" };
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// log_event("MN102", "Timer %d %s b6=%d, source=%s", adr-0x220, data & 0x80 ? "on" : "off", (data & 0x40) != 0, source[data & 3]);
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mn102->simple_timer[adr-0x220].mode = data;
|
||||
// printf("MN10200: Timer %d %s b6=%d, source=%s\n", adr-0x220, data & 0x80 ? "on" : "off", (data & 0x40) != 0, source[data & 3]);
|
||||
|
||||
if (data & 0x40)
|
||||
{
|
||||
// printf("MN10200: loading timer %d\n", adr-0x220);
|
||||
mn102->simple_timer[adr-0x220].cur = mn102->simple_timer[adr-0x220].base;
|
||||
}
|
||||
refresh_timer(mn102, adr-0x220);
|
||||
break;
|
||||
}
|
||||
|
||||
case 0x22a:
|
||||
log_event("MN102", "Prescale 0 %s, ps0bc %s",
|
||||
data & 0x80 ? "on" : "off", data & 0x40 ? "-> ps0br" : "off");
|
||||
// printf("MN10200: Prescale 0 %s, ps0bc %s\n",
|
||||
// data & 0x80 ? "on" : "off", data & 0x40 ? "-> ps0br" : "off");
|
||||
mn102->prescaler[0].mode = data;
|
||||
break;
|
||||
|
||||
case 0x22b:
|
||||
log_event("MN102", "Prescale 1 %s, ps1bc %s",
|
||||
data & 0x80 ? "on" : "off", data & 0x40 ? "-> ps1br" : "off");
|
||||
// printf("MN10200: Prescale 1 %s, ps1bc %s\n",
|
||||
// data & 0x80 ? "on" : "off", data & 0x40 ? "-> ps1br" : "off");
|
||||
mn102->prescaler[1].mode = data;
|
||||
break;
|
||||
|
||||
case 0x230: case 0x240: case 0x250: {
|
||||
case 0x230: case 0x240: case 0x250:
|
||||
{
|
||||
// const char *modes[4] = { "single", "double", "ioa", "iob" };
|
||||
// const char *sources[8] = { "pres.0", "pres.1", "iob", "sysclk", "*4", "*1", "6", "7" };
|
||||
// log_event("MN102", "Timer %d comp=%s on_1=%s on_match=%s phase=%s source=%s",
|
||||
// printf("MN10200: Timer %d comp=%s on_1=%s on_match=%s phase=%s source=%s\n",
|
||||
// 10 + ((adr-0x230) >> 4),
|
||||
// modes[data >> 6], data & 0x20 ? "cleared" : "not cleared", data & 0x10 ? "cleared" : "not cleared",
|
||||
// data & 8 ? "tff" : "rsff", sources[data & 7]);
|
||||
break;
|
||||
}
|
||||
|
||||
case 0x231: case 0x241: case 0x251: {
|
||||
case 0x231: case 0x241: case 0x251:
|
||||
{
|
||||
// const char *modes[4] = { "up", "down", "up on ioa", "up on iob" };
|
||||
// log_event("MN102", "Timer %d %s ff=%s op=%s ext_trig=%s %s",
|
||||
// printf("MN10200: Timer %d %s ff=%s op=%s ext_trig=%s %s\n",
|
||||
// 10 + ((adr-0x230) >> 4),
|
||||
// data & 0x80 ? "enable" : "disable", data & 0x40 ? "operate" : "clear",
|
||||
// modes[(data >> 4) & 3], data & 2 ? "on" : "off", data & 1 ? "one-shot" : "repeat");
|
||||
@ -1891,21 +2069,21 @@ static void mn10200_w(mn102_info *mn102, UINT32 adr, UINT32 data, int type)
|
||||
case 0x280: case 0x290: case 0x2a0: case 0x2b0: case 0x2c0: case 0x2d0: case 0x2e0: case 0x2f0: {
|
||||
int dma = (adr-0x280) >> 4;
|
||||
mn102->dma[dma].adr = (mn102->dma[dma].adr & 0x00ffff00) | data;
|
||||
log_event("MN102", "DMA %d adr=%06x", dma, mn102->dma[dma].adr);
|
||||
logerror("MN10200: DMA %d adr=%06x\n", dma, mn102->dma[dma].adr);
|
||||
break;
|
||||
}
|
||||
|
||||
case 0x281: case 0x291: case 0x2a1: case 0x2b1: case 0x2c1: case 0x2d1: case 0x2e1: case 0x2f1: {
|
||||
int dma = (adr-0x280) >> 4;
|
||||
mn102->dma[dma].adr = (mn102->dma[dma].adr & 0x00ff00ff) | (data << 8);
|
||||
log_event("MN102", "DMA %d adr=%06x", dma, mn102->dma[dma].adr);
|
||||
logerror("MN10200: DMA %d adr=%06x\n", dma, mn102->dma[dma].adr);
|
||||
break;
|
||||
}
|
||||
|
||||
case 0x282: case 0x292: case 0x2a2: case 0x2b2: case 0x2c2: case 0x2d2: case 0x2e2: case 0x2f2: {
|
||||
int dma = (adr-0x280) >> 4;
|
||||
mn102->dma[dma].adr = (mn102->dma[dma].adr & 0x0000ffff) | (data << 16);
|
||||
log_event("MN102", "DMA %d adr=%06x", dma, mn102->dma[dma].adr);
|
||||
logerror("MN10200: DMA %d adr=%06x\n", dma, mn102->dma[dma].adr);
|
||||
break;
|
||||
}
|
||||
|
||||
@ -1915,21 +2093,21 @@ static void mn10200_w(mn102_info *mn102, UINT32 adr, UINT32 data, int type)
|
||||
case 0x284: case 0x294: case 0x2a4: case 0x2b4: case 0x2c4: case 0x2d4: case 0x2e4: case 0x2f4: {
|
||||
int dma = (adr-0x280) >> 4;
|
||||
mn102->dma[dma].count = (mn102->dma[dma].count & 0x00ffff00) | data;
|
||||
log_event("MN102", "DMA %d count=%06x", dma, mn102->dma[dma].count);
|
||||
logerror("MN10200: DMA %d count=%06x\n", dma, mn102->dma[dma].count);
|
||||
break;
|
||||
}
|
||||
|
||||
case 0x285: case 0x295: case 0x2a5: case 0x2b5: case 0x2c5: case 0x2d5: case 0x2e5: case 0x2f5: {
|
||||
int dma = (adr-0x280) >> 4;
|
||||
mn102->dma[dma].count = (mn102->dma[dma].count & 0x00ff00ff) | (data << 8);
|
||||
log_event("MN102", "DMA %d count=%06x", dma, mn102->dma[dma].count);
|
||||
logerror("MN10200: DMA %d count=%06x\n", dma, mn102->dma[dma].count);
|
||||
break;
|
||||
}
|
||||
|
||||
case 0x286: case 0x296: case 0x2a6: case 0x2b6: case 0x2c6: case 0x2d6: case 0x2e6: case 0x2f6: {
|
||||
int dma = (adr-0x280) >> 4;
|
||||
mn102->dma[dma].count = (mn102->dma[dma].count & 0x0000ffff) | (data << 16);
|
||||
log_event("MN102", "DMA %d count=%06x", dma, mn102->dma[dma].count);
|
||||
logerror("MN10200: DMA %d count=%06x\n", dma, mn102->dma[dma].count);
|
||||
break;
|
||||
}
|
||||
|
||||
@ -1939,19 +2117,19 @@ static void mn10200_w(mn102_info *mn102, UINT32 adr, UINT32 data, int type)
|
||||
case 0x288: case 0x298: case 0x2a8: case 0x2b8: case 0x2c8: case 0x2d8: case 0x2e8: case 0x2f8: {
|
||||
int dma = (adr-0x280) >> 4;
|
||||
mn102->dma[dma].iadr = (mn102->dma[dma].iadr & 0xff00) | data;
|
||||
log_event("MN102", "DMA %d iadr=%03x", dma, mn102->dma[dma].iadr);
|
||||
logerror("MN10200: DMA %d iadr=%03x\n", dma, mn102->dma[dma].iadr);
|
||||
break;
|
||||
}
|
||||
|
||||
case 0x289: case 0x299: case 0x2a9: case 0x2b9: case 0x2c9: case 0x2d9: case 0x2e9: case 0x2f9: {
|
||||
int dma = (adr-0x280) >> 4;
|
||||
mn102->dma[dma].iadr = (mn102->dma[dma].iadr & 0x00ff) | ((data & 3) << 8);
|
||||
log_event("MN102", "DMA %d iadr=%03x", dma, mn102->dma[dma].iadr);
|
||||
logerror("MN10200: DMA %d iadr=%03x\n", dma, mn102->dma[dma].iadr);
|
||||
break;
|
||||
}
|
||||
|
||||
case 0x28a: case 0x29a: case 0x2aa: case 0x2ba: case 0x2ca: case 0x2da: case 0x2ea: case 0x2fa: {
|
||||
/* static const char *trans[4] = { "M-IO", "M-M", "M-X1", "m-X2" };
|
||||
static const char *trans[4] = { "M-IO", "M-M", "M-X1", "m-X2" };
|
||||
static const char *start[32] = {
|
||||
"soft", "a/d", "ser0tx", "set0rx", "ser1tx", "ser1rx",
|
||||
"timer0", "timer1", "timer2", "timer3", "timer4", "timer5", "timer6", "timer7", "timer8", "timer9",
|
||||
@ -1960,11 +2138,11 @@ static void mn10200_w(mn102_info *mn102, UINT32 adr, UINT32 data, int type)
|
||||
"timer12a", "timer12b",
|
||||
"irq0", "irq1", "irq2", "irq3",
|
||||
"X0e", "X1e", "X0l", "X1l"
|
||||
}; */
|
||||
};
|
||||
|
||||
int dma = (adr-0x280) >> 4;
|
||||
mn102->dma[dma].ctrll = data;
|
||||
log_event("MN102", "DMA %d control ack=%s, trans=%s, start=%s",
|
||||
logerror("MN10200: DMA %d control ack=%s, trans=%s, start=%s\n",
|
||||
dma,
|
||||
data & 0x80 ? "level" : "pulse",
|
||||
trans[(data >> 5) & 3],
|
||||
@ -1973,10 +2151,10 @@ static void mn10200_w(mn102_info *mn102, UINT32 adr, UINT32 data, int type)
|
||||
}
|
||||
|
||||
case 0x28b: case 0x29b: case 0x2ab: case 0x2bb: case 0x2cb: case 0x2db: case 0x2eb: case 0x2fb: {
|
||||
// static const char *tradr[4] = { "inc", "dec", "fixed", "reserved" };
|
||||
static const char *tradr[4] = { "inc", "dec", "fixed", "reserved" };
|
||||
int dma = (adr-0x280) >> 4;
|
||||
mn102->dma[dma].ctrlh = data;
|
||||
/* log_event("MN102", "DMA %d control %s irq=%s %s %s dir=%s %s %s",
|
||||
logerror("MN10200: DMA %d control %s irq=%s %s %s dir=%s %s %s\n",
|
||||
dma,
|
||||
data & 0x80 ? "enable" : "disable",
|
||||
data & 0x40 ? "off" : "on",
|
||||
@ -1984,14 +2162,14 @@ static void mn10200_w(mn102_info *mn102, UINT32 adr, UINT32 data, int type)
|
||||
data & 0x10 ? "burst" : "single",
|
||||
data & 0x08 ? "dst" : "src",
|
||||
data & 0x04 ? "continue" : "normal",
|
||||
tradr[data & 3]);*/
|
||||
tradr[data & 3]);
|
||||
break;
|
||||
}
|
||||
|
||||
case 0x28c: case 0x29c: case 0x2ac: case 0x2bc: case 0x2cc: case 0x2dc: case 0x2ec: case 0x2fc: {
|
||||
int dma = (adr-0x280) >> 4;
|
||||
mn102->dma[dma].irq = data & 7;
|
||||
log_event("MN102", "DMA %d irq=%d", dma, data & 7);
|
||||
logerror("MN10200: DMA %d irq=%d\n", dma, data & 7);
|
||||
break;
|
||||
}
|
||||
|
||||
@ -2085,7 +2263,9 @@ static void mn10200_w(mn102_info *mn102, UINT32 adr, UINT32 data, int type)
|
||||
static UINT32 mn10200_r(mn102_info *mn102, UINT32 adr, int type)
|
||||
{
|
||||
if(type == MEM_WORD)
|
||||
{
|
||||
return mn10200_r(mn102, adr, MEM_BYTE) | (mn10200_r(mn102, adr+1, MEM_BYTE) << 8);
|
||||
}
|
||||
|
||||
switch(adr) {
|
||||
case 0x00e:
|
||||
@ -2125,12 +2305,19 @@ static UINT32 mn10200_r(mn102_info *mn102, UINT32 adr, int type)
|
||||
|
||||
case 0x200: case 0x201: case 0x202: case 0x203: case 0x204:
|
||||
case 0x205: case 0x206: case 0x207: case 0x208: case 0x209:
|
||||
log_event("MN102", "timer %d value read", adr-0x200);
|
||||
// printf("MN10200: timer %d value read = %d\n", adr-0x200, mn102->simple_timer[adr-0x200].cur);
|
||||
return mn102->simple_timer[adr-0x200].cur;
|
||||
break;
|
||||
|
||||
case 0x264: // port 1 data
|
||||
return memory_read_byte_8le(mn102->io, MN10200_PORT1);
|
||||
|
||||
case 0x28c: case 0x29c: case 0x2ac: case 0x2bc: case 0x2cc: case 0x2dc: case 0x2ec: case 0x2fc:
|
||||
{
|
||||
int dma = (adr-0x280) >> 4;
|
||||
return mn102->dma[dma].irq;
|
||||
}
|
||||
|
||||
case 0x3c0: // port 0 data
|
||||
return memory_read_byte_8le(mn102->io, MN10200_PORT0);
|
||||
|
||||
@ -2168,6 +2355,11 @@ static CPU_SET_INFO(mn10200)
|
||||
case CPUINFO_INT_REGISTER + MN10200_A3: cpustate->a[3] = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + MN10200_NMICR: cpustate->nmicr = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + MN10200_IAGR: cpustate->iagr = info->i; break;
|
||||
|
||||
case CPUINFO_INT_INPUT_STATE + MN10200_IRQ0: mn102_extirq(cpustate, 0, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + MN10200_IRQ1: mn102_extirq(cpustate, 1, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + MN10200_IRQ2: mn102_extirq(cpustate, 2, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + MN10200_IRQ3: mn102_extirq(cpustate, 3, info->i); break;
|
||||
}
|
||||
}
|
||||
|
||||
@ -2237,14 +2429,14 @@ CPU_GET_INFO( mn10200 )
|
||||
|
||||
case CPUINFO_STR_REGISTER + MN10200_MDR: sprintf(info->s, "MDR: %04x", cpustate->mdr); break;
|
||||
|
||||
case CPUINFO_STR_REGISTER + MN10200_D0: sprintf(info->s, "D0: %08x", cpustate->d[0]); break;
|
||||
case CPUINFO_STR_REGISTER + MN10200_D1: sprintf(info->s, "D1: %08x", cpustate->d[1]); break;
|
||||
case CPUINFO_STR_REGISTER + MN10200_D2: sprintf(info->s, "D2: %08x", cpustate->d[2]); break;
|
||||
case CPUINFO_STR_REGISTER + MN10200_D3: sprintf(info->s, "D3: %08x", cpustate->d[3]); break;
|
||||
case CPUINFO_STR_REGISTER + MN10200_A0: sprintf(info->s, "A0: %08x", cpustate->a[0]); break;
|
||||
case CPUINFO_STR_REGISTER + MN10200_A1: sprintf(info->s, "A1: %08x", cpustate->a[1]); break;
|
||||
case CPUINFO_STR_REGISTER + MN10200_A2: sprintf(info->s, "A2: %08x", cpustate->a[2]); break;
|
||||
case CPUINFO_STR_REGISTER + MN10200_A3: sprintf(info->s, "A3: %08x", cpustate->a[3]); break;
|
||||
case CPUINFO_STR_REGISTER + MN10200_D0: sprintf(info->s, "D0: %06x", cpustate->d[0]); break;
|
||||
case CPUINFO_STR_REGISTER + MN10200_D1: sprintf(info->s, "D1: %06x", cpustate->d[1]); break;
|
||||
case CPUINFO_STR_REGISTER + MN10200_D2: sprintf(info->s, "D2: %06x", cpustate->d[2]); break;
|
||||
case CPUINFO_STR_REGISTER + MN10200_D3: sprintf(info->s, "D3: %06x", cpustate->d[3]); break;
|
||||
case CPUINFO_STR_REGISTER + MN10200_A0: sprintf(info->s, "A0: %06x", cpustate->a[0]); break;
|
||||
case CPUINFO_STR_REGISTER + MN10200_A1: sprintf(info->s, "A1: %06x", cpustate->a[1]); break;
|
||||
case CPUINFO_STR_REGISTER + MN10200_A2: sprintf(info->s, "A2: %06x", cpustate->a[2]); break;
|
||||
case CPUINFO_STR_REGISTER + MN10200_A3: sprintf(info->s, "A3: %06x", cpustate->a[3]); break;
|
||||
|
||||
case CPUINFO_STR_REGISTER + MN10200_NMICR: sprintf(info->s, "MNICR: %02x", cpustate->nmicr); break;
|
||||
case CPUINFO_STR_REGISTER + MN10200_IAGR: sprintf(info->s, "IAGR: %02x", cpustate->iagr); break;
|
||||
|
||||
@ -37,6 +37,14 @@ enum
|
||||
MN10200_PORT4
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
MN10200_IRQ0,
|
||||
MN10200_IRQ1,
|
||||
MN10200_IRQ2,
|
||||
MN10200_IRQ3
|
||||
};
|
||||
|
||||
CPU_GET_INFO( mn10200 );
|
||||
#define CPU_MN10200 CPU_GET_INFO_NAME( mn10200 )
|
||||
|
||||
|
||||
@ -19,7 +19,7 @@ static ADDRESS_MAP_START(taitozoom_map, ADDRESS_SPACE_PROGRAM, 16)
|
||||
AM_RANGE(0x080000, 0x0fffff) AM_ROM AM_REGION("mn10200", 0)
|
||||
AM_RANGE(0x400000, 0x40ffff) AM_RAM
|
||||
AM_RANGE(0x800000, 0x800fff) AM_DEVREADWRITE("zsg2", zsg2_r, zsg2_w)
|
||||
AM_RANGE(0xe00000, 0xe000ff) AM_RAM // main CPU comms?
|
||||
AM_RANGE(0xe00000, 0xe000ff) AM_RAM // main CPU comms (1fbe0xxx on FX-1B main CPU, banked with eeprom - raystorm writes command at PC=80015240)
|
||||
AM_RANGE(0xc00000, 0xc00001) AM_RAM // TMS57002 comms
|
||||
ADDRESS_MAP_END
|
||||
|
||||
@ -54,6 +54,7 @@ MACHINE_DRIVER_START( taito_zoom_sound )
|
||||
MDRV_CPU_ADD("mn10200", MN10200, 25000000/2)
|
||||
MDRV_CPU_PROGRAM_MAP(taitozoom_map)
|
||||
MDRV_CPU_IO_MAP(taitozoom_io_map)
|
||||
MDRV_CPU_VBLANK_INT("screen", irq0_line_pulse)
|
||||
|
||||
// we assume the parent machine has created lspeaker/rspeaker
|
||||
MDRV_SOUND_ADD("zsg2", ZSG2, 25000000/2)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user