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fix priority ram memory test

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This commit is contained in:
Michaël Banaan Ananas 2013-07-04 21:11:58 +00:00
parent 8c9248216d
commit 80c05d71d9
3 changed files with 28 additions and 43 deletions
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13
src/mame/drivers/tetrisp2.c
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@ -297,7 +297,7 @@ static ADDRESS_MAP_START( tetrisp2_map, AS_PROGRAM, 16, tetrisp2_state )
AM_RANGE(0x100000, 0x103fff) AM_RAM AM_SHARE("spriteram") // Object RAM
AM_RANGE(0x104000, 0x107fff) AM_RAM // Spare Object RAM
AM_RANGE(0x108000, 0x10ffff) AM_RAM // Work RAM
AM_RANGE(0x200000, 0x23ffff) AM_READWRITE8(tetrisp2_priority_r, tetrisp2_priority_w, 0x00ff)
AM_RANGE(0x200000, 0x23ffff) AM_READWRITE(tetrisp2_priority_r, tetrisp2_priority_w)
AM_RANGE(0x300000, 0x31ffff) AM_RAM_WRITE(tetrisp2_palette_w) AM_SHARE("paletteram") // Palette
AM_RANGE(0x400000, 0x403fff) AM_RAM_WRITE(tetrisp2_vram_fg_w) AM_SHARE("vram_fg") // Foreground
AM_RANGE(0x404000, 0x407fff) AM_RAM_WRITE(tetrisp2_vram_bg_w) AM_SHARE("vram_bg") // Background
@ -354,8 +354,7 @@ static ADDRESS_MAP_START( nndmseal_map, AS_PROGRAM, 16, tetrisp2_state )
AM_RANGE(0x100000, 0x103fff) AM_RAM AM_SHARE("spriteram") // Object RAM
AM_RANGE(0x104000, 0x107fff) AM_RAM // Spare Object RAM
AM_RANGE(0x108000, 0x10ffff) AM_RAM // Work RAM
AM_RANGE(0x200000, 0x23ffff) AM_WRITE8(tetrisp2_priority_w, 0x00ff) // Priority
AM_RANGE(0x200000, 0x23ffff) AM_READ(nndmseal_priority_r)
AM_RANGE(0x200000, 0x23ffff) AM_READWRITE(tetrisp2_priority_r, tetrisp2_priority_w)
AM_RANGE(0x300000, 0x31ffff) AM_RAM_WRITE(tetrisp2_palette_w) AM_SHARE("paletteram") // Palette
AM_RANGE(0x400000, 0x403fff) AM_RAM_WRITE(tetrisp2_vram_fg_w) AM_SHARE("vram_fg") // Foreground
AM_RANGE(0x404000, 0x407fff) AM_RAM_WRITE(tetrisp2_vram_bg_w) AM_SHARE("vram_bg") // Background
@ -400,7 +399,7 @@ static ADDRESS_MAP_START( rockn1_map, AS_PROGRAM, 16, tetrisp2_state )
AM_RANGE(0x100000, 0x103fff) AM_RAM AM_SHARE("spriteram") // Object RAM
AM_RANGE(0x104000, 0x107fff) AM_RAM // Spare Object RAM
AM_RANGE(0x108000, 0x10ffff) AM_RAM // Work RAM
AM_RANGE(0x200000, 0x23ffff) AM_READWRITE8(tetrisp2_priority_r, rockn_priority_w, 0x00ff) // Priority
AM_RANGE(0x200000, 0x23ffff) AM_READWRITE(tetrisp2_priority_r, tetrisp2_priority_w)
AM_RANGE(0x300000, 0x31ffff) AM_RAM_WRITE(tetrisp2_palette_w) AM_SHARE("paletteram") // Palette
AM_RANGE(0x400000, 0x403fff) AM_RAM_WRITE(tetrisp2_vram_fg_w) AM_SHARE("vram_fg") // Foreground
AM_RANGE(0x404000, 0x407fff) AM_RAM_WRITE(tetrisp2_vram_bg_w) AM_SHARE("vram_bg") // Background
@ -434,7 +433,7 @@ static ADDRESS_MAP_START( rockn2_map, AS_PROGRAM, 16, tetrisp2_state )
AM_RANGE(0x100000, 0x103fff) AM_RAM AM_SHARE("spriteram") // Object RAM
AM_RANGE(0x104000, 0x107fff) AM_RAM // Spare Object RAM
AM_RANGE(0x108000, 0x10ffff) AM_RAM // Work RAM
AM_RANGE(0x200000, 0x23ffff) AM_READWRITE8(tetrisp2_priority_r, rockn_priority_w, 0x00ff) // Priority
AM_RANGE(0x200000, 0x23ffff) AM_READWRITE(tetrisp2_priority_r, tetrisp2_priority_w)
AM_RANGE(0x300000, 0x31ffff) AM_RAM_WRITE(tetrisp2_palette_w) AM_SHARE("paletteram") // Palette
AM_RANGE(0x500000, 0x50ffff) AM_RAM // Line
AM_RANGE(0x600000, 0x60ffff) AM_RAM_WRITE(tetrisp2_vram_rot_w) AM_SHARE("vram_rot") // Rotation
@ -468,7 +467,7 @@ static ADDRESS_MAP_START( rocknms_main_map, AS_PROGRAM, 16, tetrisp2_state )
AM_RANGE(0x100000, 0x103fff) AM_RAM AM_SHARE("spriteram") // Object RAM
AM_RANGE(0x104000, 0x107fff) AM_RAM // Spare Object RAM
AM_RANGE(0x108000, 0x10ffff) AM_RAM // Work RAM
AM_RANGE(0x200000, 0x23ffff) AM_READWRITE8(tetrisp2_priority_r, rockn_priority_w, 0x00ff) // Priority
AM_RANGE(0x200000, 0x23ffff) AM_READWRITE(tetrisp2_priority_r, tetrisp2_priority_w)
AM_RANGE(0x300000, 0x31ffff) AM_RAM_WRITE(tetrisp2_palette_w) AM_SHARE("paletteram") // Palette
// AM_RANGE(0x500000, 0x50ffff) AM_RAM // Line
AM_RANGE(0x600000, 0x60ffff) AM_RAM_WRITE(tetrisp2_vram_rot_w) AM_SHARE("vram_rot") // Rotation
@ -601,7 +600,7 @@ static ADDRESS_MAP_START( stepstag_map, AS_PROGRAM, 16, stepstag_state )
AM_RANGE(0x000000, 0x0fffff) AM_ROM
AM_RANGE(0x100000, 0x103fff) AM_RAM // Object RAM
AM_RANGE(0x108000, 0x10ffff) AM_RAM // Work RAM
AM_RANGE(0x200000, 0x23ffff) AM_READWRITE8(tetrisp2_priority_r, rockn_priority_w, 0x00ff) // Priority
AM_RANGE(0x200000, 0x23ffff) AM_READWRITE(tetrisp2_priority_r, tetrisp2_priority_w)
AM_RANGE(0x300000, 0x31ffff) AM_RAM // Palette
AM_RANGE(0x400000, 0x403fff) AM_RAM_WRITE(tetrisp2_vram_fg_w) AM_SHARE("vram_fg") // Foreground
AM_RANGE(0x404000, 0x407fff) AM_RAM_WRITE(tetrisp2_vram_bg_w) AM_SHARE("vram_bg") // Background

22
src/mame/includes/tetrisp2.h
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@ -3,8 +3,10 @@ class tetrisp2_state : public driver_device
public:
tetrisp2_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag),
m_spriteram(*this, "spriteram"),
m_spriteram2(*this, "spriteram2") ,
m_maincpu(*this, "maincpu"),
m_subcpu(*this, "sub"),
m_spriteram(*this, "spriteram"),
m_spriteram2(*this, "spriteram2"),
m_vram_fg(*this, "vram_fg"),
m_vram_bg(*this, "vram_bg"),
m_vram_rot(*this, "vram_rot"),
@ -18,9 +20,11 @@ public:
m_rocknms_sub_vram_bg(*this, "sub_vram_bg"),
m_rocknms_sub_scroll_fg(*this, "sub_scroll_fg"),
m_rocknms_sub_scroll_bg(*this, "sub_scroll_bg"),
m_rocknms_sub_rotregs(*this, "sub_rotregs"),
m_maincpu(*this, "maincpu"),
m_subcpu(*this, "sub") { }
m_rocknms_sub_rotregs(*this, "sub_rotregs")
{ }
required_device<cpu_device> m_maincpu;
optional_device<cpu_device> m_subcpu;
required_shared_ptr<UINT16> m_spriteram;
optional_shared_ptr<UINT16> m_spriteram2;
@ -80,11 +84,9 @@ public:
DECLARE_WRITE16_MEMBER(tetrisp2_nvram_w);
DECLARE_WRITE16_MEMBER(tetrisp2_palette_w);
DECLARE_WRITE16_MEMBER(rocknms_sub_palette_w);
DECLARE_WRITE8_MEMBER(tetrisp2_priority_w);
DECLARE_WRITE8_MEMBER(rockn_priority_w);
DECLARE_WRITE16_MEMBER(tetrisp2_priority_w);
DECLARE_WRITE16_MEMBER(rocknms_sub_priority_w);
DECLARE_READ16_MEMBER(nndmseal_priority_r);
DECLARE_READ8_MEMBER(tetrisp2_priority_r);
DECLARE_READ16_MEMBER(tetrisp2_priority_r);
DECLARE_WRITE16_MEMBER(tetrisp2_vram_bg_w);
DECLARE_WRITE16_MEMBER(tetrisp2_vram_fg_w);
DECLARE_WRITE16_MEMBER(tetrisp2_vram_rot_w);
@ -117,8 +119,6 @@ public:
TIMER_CALLBACK_MEMBER(rockn_timer_level1_callback);
TIMER_CALLBACK_MEMBER(rockn_timer_sub_level1_callback);
void init_rockn_timer();
required_device<cpu_device> m_maincpu;
optional_device<cpu_device> m_subcpu;
};
class stepstag_state : public tetrisp2_state

36
src/mame/video/tetrisp2.c
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@ -68,42 +68,28 @@ WRITE16_MEMBER(tetrisp2_state::rocknms_sub_palette_w)
***************************************************************************/
WRITE8_MEMBER(tetrisp2_state::tetrisp2_priority_w)
WRITE16_MEMBER(tetrisp2_state::tetrisp2_priority_w)
{
//if (ACCESSING_BITS_8_15)
{
data |= ((data & 0xff00) >> 8);
if (ACCESSING_BITS_0_7)
m_priority[offset] = data;
}
else
m_priority[offset] = data >> 8;
}
WRITE8_MEMBER(tetrisp2_state::rockn_priority_w)
{
//if (ACCESSING_BITS_8_15)
{
m_priority[offset] = data;
}
}
WRITE16_MEMBER(tetrisp2_state::rocknms_sub_priority_w)
{
if (ACCESSING_BITS_8_15)
{
m_rocknms_sub_priority[offset] = data;
}
}
READ16_MEMBER(tetrisp2_state::nndmseal_priority_r)
READ16_MEMBER(tetrisp2_state::tetrisp2_priority_r)
{
return m_priority[offset] | 0xff00;
}
READ8_MEMBER(tetrisp2_state::tetrisp2_priority_r)
WRITE16_MEMBER(tetrisp2_state::rocknms_sub_priority_w)
{
return m_priority[offset];
if (ACCESSING_BITS_0_7)
m_rocknms_sub_priority[offset] = data;
else
m_rocknms_sub_priority[offset] = data >> 8;
}
/***************************************************************************