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hd63450: CSR/CER behavior (nw)

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This commit is contained in:
AJR 2018-06-25 15:52:27 -04:00
parent 660ed6a616
commit 80d1186218
1 changed files with 6 additions and 2 deletions
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8
src/devices/machine/hd63450.cpp
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@ -159,10 +159,14 @@ WRITE16_MEMBER(hd63450_device::write)
case 0x00: // CSR / CER case 0x00: // CSR / CER
if(ACCESSING_BITS_8_15) if(ACCESSING_BITS_8_15)
{ {
m_reg[channel].csr &= ~((data & 0xff00) >> 8); // Writes to CSR clear all corresponding 1 bits except PCS and ACT
m_reg[channel].csr &= ~((data & 0xf600) >> 8);
// logerror("DMA#%i: Channel status write : %02x\n",channel,dmac.reg[channel].csr); // logerror("DMA#%i: Channel status write : %02x\n",channel,dmac.reg[channel].csr);
// Clearing ERR also resets CER (which is otherwise read-only)
if ((data & 0x1000) != 0)
m_reg[channel].cer = 0;
} }
// CER is read-only, so no action needed there.
break; break;
case 0x02: // DCR / OCR case 0x02: // DCR / OCR
if(ACCESSING_BITS_8_15) if(ACCESSING_BITS_8_15)