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https://github.com/holub/mame
synced 2025-07-05 18:08:04 +03:00
Let's assume no-one uses a broken 450 core in a multi-CPU configuration (nw)
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@ -307,9 +307,9 @@ _compare_exchange32(INT32 volatile *ptr, INT32 compare, INT32 exchange)
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"1: lwarx %[result], 0, %[ptr] \n"
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" cmpw %[compare], %[result] \n"
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" bne 2f \n"
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" sync \n"
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" stwcx. %[exchange], 0, %[ptr] \n"
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" bne- 1b \n"
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" lwsync \n"
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"2: "
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: [dummy] "+m" (*ptr) /* Lets GCC know that *ptr will be read/written in case it's not marked volatile */
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, [result] "=&r" (result)
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@ -343,6 +343,7 @@ _compare_exchange64(INT64 volatile *ptr, INT64 compare, INT64 exchange)
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" bne 2f \n"
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" stdcx. %[exchange], 0, %[ptr] \n"
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" bne- 1b \n"
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" lwsync \n"
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"2: "
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: [dummy] "+m" (*ptr) /* Lets GCC know that *ptr will be read/written in case it's not marked volatile */
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, [result] "=&r" (result)
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@ -371,9 +372,9 @@ _atomic_exchange32(INT32 volatile *ptr, INT32 exchange)
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__asm__ __volatile__ (
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"1: lwarx %[result], 0, %[ptr] \n"
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" sync \n"
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" stwcx. %[exchange], 0, %[ptr] \n"
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" bne- 1b \n"
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" lwsync \n"
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: [dummy] "+m" (*ptr) /* Lets GCC know that *ptr will be read/written in case it's not marked volatile */
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, [result] "=&r" (result)
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: [ptr] "r" (ptr)
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@ -400,9 +401,9 @@ _atomic_add32(INT32 volatile *ptr, INT32 delta)
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__asm__ __volatile__ (
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"1: lwarx %[result], 0, %[ptr] \n"
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" add %[result], %[result], %[delta] \n"
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" sync \n"
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" stwcx. %[result], 0, %[ptr] \n"
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" bne- 1b \n"
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" lwsync \n"
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: [dummy] "+m" (*ptr) /* Lets GCC know that *ptr will be read/written in case it's not marked volatile */
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, [result] "=&b" (result)
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: [ptr] "r" (ptr)
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@ -429,9 +430,9 @@ _atomic_increment32(INT32 volatile *ptr)
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__asm__ __volatile__ (
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"1: lwarx %[result], 0, %[ptr] \n"
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" addi %[result], %[result], 1 \n"
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" sync \n"
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" stwcx. %[result], 0, %[ptr] \n"
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" bne- 1b \n"
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" lwsync \n"
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: [dummy] "+m" (*ptr) /* Lets GCC know that *ptr will be read/written in case it's not marked volatile */
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, [result] "=&b" (result)
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: [ptr] "r" (ptr)
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@ -457,9 +458,9 @@ _atomic_decrement32(INT32 volatile *ptr)
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__asm__ __volatile__ (
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"1: lwarx %[result], 0, %[ptr] \n"
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" addi %[result], %[result], -1 \n"
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" sync \n"
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" stwcx. %[result], 0, %[ptr] \n"
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" bne- 1b \n"
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" lwsync \n"
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: [dummy] "+m" (*ptr) /* Lets GCC know that *ptr will be read/written in case it's not marked volatile */
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, [result] "=&b" (result)
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: [ptr] "r" (ptr)
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@ -133,10 +133,9 @@ INT32 osd_scalable_lock_acquire(osd_scalable_lock *lock)
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" nop \n"
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" b 2b \n"
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"3: li %[tmp], 0 \n"
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" sync \n"
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" stwcx. %[tmp], 0, %[haslock] \n"
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" bne- 1b \n"
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" eieio \n"
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" lwsync \n"
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: [tmp] "=&r" (tmp)
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: [haslock] "r" (&lock->slot[myslot].haslock)
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: "cr0"
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@ -167,7 +166,7 @@ void osd_scalable_lock_release(osd_scalable_lock *lock, INT32 myslot)
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);
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#elif defined(__ppc__) || defined (__PPC__) || defined(__ppc64__) || defined(__PPC64__)
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lock->slot[(myslot + 1) & (WORK_MAX_THREADS - 1)].haslock = TRUE;
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__asm__ __volatile__ ( " eieio " : : );
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__asm__ __volatile__ ( " lwsync " : : );
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#else
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osd_exchange32(&lock->slot[(myslot + 1) & (WORK_MAX_THREADS - 1)].haslock, TRUE);
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#endif
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@ -319,7 +318,7 @@ void osd_lock_release(osd_lock *lock)
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if (--lock->count == 0)
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#if defined(__ppc__) || defined(__PPC__) || defined(__ppc64__) || defined(__PPC64__)
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lock->holder = 0;
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__asm__ __volatile__( " eieio " : : );
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__asm__ __volatile__( " lwsync " : : );
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#else
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osd_exchange_pthread_t(&lock->holder, 0);
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#endif
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