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Let's assume no-one uses a broken 450 core in a multi-CPU configuration (nw)

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This commit is contained in:
Vas Crabb 2015-11-02 22:48:34 +11:00
parent 8247cab558
commit 80f55d4f66
2 changed files with 9 additions and 9 deletions
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11
src/osd/eigccppc.h
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@ -307,9 +307,9 @@ _compare_exchange32(INT32 volatile *ptr, INT32 compare, INT32 exchange)
"1: lwarx %[result], 0, %[ptr] \n"
" cmpw %[compare], %[result] \n"
" bne 2f \n"
" sync \n"
" stwcx. %[exchange], 0, %[ptr] \n"
" bne- 1b \n"
" lwsync \n"
"2: "
: [dummy] "+m" (*ptr) /* Lets GCC know that *ptr will be read/written in case it's not marked volatile */
, [result] "=&r" (result)
@ -343,6 +343,7 @@ _compare_exchange64(INT64 volatile *ptr, INT64 compare, INT64 exchange)
" bne 2f \n"
" stdcx. %[exchange], 0, %[ptr] \n"
" bne- 1b \n"
" lwsync \n"
"2: "
: [dummy] "+m" (*ptr) /* Lets GCC know that *ptr will be read/written in case it's not marked volatile */
, [result] "=&r" (result)
@ -371,9 +372,9 @@ _atomic_exchange32(INT32 volatile *ptr, INT32 exchange)
__asm__ __volatile__ (
"1: lwarx %[result], 0, %[ptr] \n"
" sync \n"
" stwcx. %[exchange], 0, %[ptr] \n"
" bne- 1b \n"
" lwsync \n"
: [dummy] "+m" (*ptr) /* Lets GCC know that *ptr will be read/written in case it's not marked volatile */
, [result] "=&r" (result)
: [ptr] "r" (ptr)
@ -400,9 +401,9 @@ _atomic_add32(INT32 volatile *ptr, INT32 delta)
__asm__ __volatile__ (
"1: lwarx %[result], 0, %[ptr] \n"
" add %[result], %[result], %[delta] \n"
" sync \n"
" stwcx. %[result], 0, %[ptr] \n"
" bne- 1b \n"
" lwsync \n"
: [dummy] "+m" (*ptr) /* Lets GCC know that *ptr will be read/written in case it's not marked volatile */
, [result] "=&b" (result)
: [ptr] "r" (ptr)
@ -429,9 +430,9 @@ _atomic_increment32(INT32 volatile *ptr)
__asm__ __volatile__ (
"1: lwarx %[result], 0, %[ptr] \n"
" addi %[result], %[result], 1 \n"
" sync \n"
" stwcx. %[result], 0, %[ptr] \n"
" bne- 1b \n"
" lwsync \n"
: [dummy] "+m" (*ptr) /* Lets GCC know that *ptr will be read/written in case it's not marked volatile */
, [result] "=&b" (result)
: [ptr] "r" (ptr)
@ -457,9 +458,9 @@ _atomic_decrement32(INT32 volatile *ptr)
__asm__ __volatile__ (
"1: lwarx %[result], 0, %[ptr] \n"
" addi %[result], %[result], -1 \n"
" sync \n"
" stwcx. %[result], 0, %[ptr] \n"
" bne- 1b \n"
" lwsync \n"
: [dummy] "+m" (*ptr) /* Lets GCC know that *ptr will be read/written in case it's not marked volatile */
, [result] "=&b" (result)
: [ptr] "r" (ptr)

7
src/osd/modules/sync/sync_ntc.c
View File

@ -133,10 +133,9 @@ INT32 osd_scalable_lock_acquire(osd_scalable_lock *lock)
" nop \n"
" b 2b \n"
"3: li %[tmp], 0 \n"
" sync \n"
" stwcx. %[tmp], 0, %[haslock] \n"
" bne- 1b \n"
" eieio \n"
" lwsync \n"
: [tmp] "=&r" (tmp)
: [haslock] "r" (&lock->slot[myslot].haslock)
: "cr0"
@ -167,7 +166,7 @@ void osd_scalable_lock_release(osd_scalable_lock *lock, INT32 myslot)
);
#elif defined(__ppc__) || defined (__PPC__) || defined(__ppc64__) || defined(__PPC64__)
lock->slot[(myslot + 1) & (WORK_MAX_THREADS - 1)].haslock = TRUE;
__asm__ __volatile__ ( " eieio " : : );
__asm__ __volatile__ ( " lwsync " : : );
#else
osd_exchange32(&lock->slot[(myslot + 1) & (WORK_MAX_THREADS - 1)].haslock, TRUE);
#endif
@ -319,7 +318,7 @@ void osd_lock_release(osd_lock *lock)
if (--lock->count == 0)
#if defined(__ppc__) || defined(__PPC__) || defined(__ppc64__) || defined(__PPC64__)
lock->holder = 0;
__asm__ __volatile__( " eieio " : : );
__asm__ __volatile__( " lwsync " : : );
#else
osd_exchange_pthread_t(&lock->holder, 0);
#endif