mirror of
https://github.com/holub/mame
synced 2025-04-23 00:39:36 +03:00
hmcs400: add i/o ports
This commit is contained in:
hap
parent
2d74a4e866
commit
819379be1e
@ -247,13 +247,8 @@ void hmcs40_cpu_device::device_reset()
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m_iri = m_irt = 0;
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m_if[0] = m_if[1] = m_tf = 1;
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// clear i/o
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m_d = m_polarity;
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for (int i = 0; i < 16; i++)
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hmcs40_cpu_device::write_d(i, m_polarity);
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for (int i = 0; i < 8; i++)
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hmcs40_cpu_device::write_r(i, m_polarity & 0xf);
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// all I/O ports set to input
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reset_io();
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}
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@ -325,13 +320,22 @@ device_memory_interface::space_config_vector hmcs40_cpu_device::memory_space_con
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//-------------------------------------------------
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// i/o handling
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// i/o ports
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//-------------------------------------------------
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u8 hmcs40_cpu_device::read_r(int index)
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void hmcs40_cpu_device::reset_io()
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{
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m_d = m_polarity;
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m_write_d(m_polarity);
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for (int i = 0; i < 8; i++)
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hmcs40_cpu_device::write_r(i, m_polarity);
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}
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u8 hmcs40_cpu_device::read_r(u8 index)
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{
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index &= 7;
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u8 inp = m_read_r[index](index, 0xff);
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u8 inp = m_read_r[index](index);
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if (m_polarity)
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return (inp & m_r[index]) & 0xf;
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@ -339,38 +343,39 @@ u8 hmcs40_cpu_device::read_r(int index)
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return (inp | m_r[index]) & 0xf;
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}
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void hmcs40_cpu_device::write_r(int index, u8 data)
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void hmcs40_cpu_device::write_r(u8 index, u8 data)
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{
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index &= 7;
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data &= 0xf;
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m_r[index] = data;
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m_write_r[index](index, data, 0xff);
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m_write_r[index](index, data);
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}
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int hmcs40_cpu_device::read_d(int index)
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int hmcs40_cpu_device::read_d(u8 index)
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{
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index &= 15;
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index &= 0xf;
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u16 inp = m_read_d(0, 1 << index);
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if (m_polarity)
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return (m_read_d(index, 0xffff) & m_d) >> index & 1;
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return BIT(inp & m_d, index);
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else
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return (m_read_d(index, 0xffff) | m_d) >> index & 1;
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return BIT(inp | m_d, index);
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}
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void hmcs40_cpu_device::write_d(int index, int state)
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void hmcs40_cpu_device::write_d(u8 index, int state)
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{
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index &= 15;
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state = (state) ? 1 : 0;
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index &= 0xf;
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u16 mask = 1 << index;
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m_d = (m_d & ~(1 << index)) | state << index;
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m_write_d(index, m_d, 0xffff);
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m_d = (m_d & ~mask) | (state ? mask : 0);
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m_write_d(0, m_d, mask);
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}
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// HMCS43:
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// R0 is input-only, R1 is i/o, R2,R3 are output-only, no R4-R7
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// D0-D3 are i/o, D4-D15 are output-only
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u8 hmcs43_cpu_device::read_r(int index)
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u8 hmcs43_cpu_device::read_r(u8 index)
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{
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index &= 7;
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@ -380,7 +385,7 @@ u8 hmcs43_cpu_device::read_r(int index)
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return hmcs40_cpu_device::read_r(index);
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}
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void hmcs43_cpu_device::write_r(int index, u8 data)
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void hmcs43_cpu_device::write_r(u8 index, u8 data)
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{
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index &= 7;
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@ -390,7 +395,7 @@ void hmcs43_cpu_device::write_r(int index, u8 data)
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logerror("ineffective write to port R%d = $%X at $%04X\n", index, data & 0xf, m_prev_pc);
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}
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int hmcs43_cpu_device::read_d(int index)
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int hmcs43_cpu_device::read_d(u8 index)
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{
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index &= 15;
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@ -404,7 +409,7 @@ int hmcs43_cpu_device::read_d(int index)
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// R0-R3 are i/o, R4,R5 are extra registers, no R6,R7
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// D0-D15 are i/o
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u8 hmcs44_cpu_device::read_r(int index)
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u8 hmcs44_cpu_device::read_r(u8 index)
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{
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index &= 7;
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@ -414,7 +419,7 @@ u8 hmcs44_cpu_device::read_r(int index)
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return hmcs40_cpu_device::read_r(index);
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}
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void hmcs44_cpu_device::write_r(int index, u8 data)
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void hmcs44_cpu_device::write_r(u8 index, u8 data)
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{
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index &= 7;
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@ -428,7 +433,7 @@ void hmcs44_cpu_device::write_r(int index, u8 data)
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// R0-R5 are i/o, R6 is output-only, no R7
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// D0-D15 are i/o
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u8 hmcs45_cpu_device::read_r(int index)
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u8 hmcs45_cpu_device::read_r(u8 index)
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{
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index &= 7;
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@ -438,7 +443,7 @@ u8 hmcs45_cpu_device::read_r(int index)
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return hmcs40_cpu_device::read_r(index);
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}
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void hmcs45_cpu_device::write_r(int index, u8 data)
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void hmcs45_cpu_device::write_r(u8 index, u8 data)
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{
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index &= 7;
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@ -450,7 +455,7 @@ void hmcs45_cpu_device::write_r(int index, u8 data)
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//-------------------------------------------------
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// interrupt/timer handling
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// interrupt/timer
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//-------------------------------------------------
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void hmcs40_cpu_device::do_interrupt()
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@ -12,7 +12,7 @@
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#pragma once
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// I/O ports setup
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// input lines
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enum
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{
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@ -195,10 +195,11 @@ protected:
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void pop_stack();
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void push_stack();
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virtual u8 read_r(int index);
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virtual void write_r(int index, u8 data);
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virtual int read_d(int index);
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virtual void write_d(int index, int state);
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virtual void reset_io();
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virtual u8 read_r(u8 index);
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virtual void write_r(u8 index, u8 data);
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virtual int read_d(u8 index);
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virtual void write_d(u8 index, int state);
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void cycle();
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void increment_tc();
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@ -309,9 +310,9 @@ protected:
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hmcs43_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, u16 polarity);
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// overrides
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virtual u8 read_r(int index) override;
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virtual void write_r(int index, u8 data) override;
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virtual int read_d(int index) override;
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virtual u8 read_r(u8 index) override;
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virtual void write_r(u8 index, u8 data) override;
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virtual int read_d(u8 index) override;
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};
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class hd38750_device : public hmcs43_cpu_device
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@ -345,8 +346,8 @@ protected:
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hmcs44_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, u16 polarity);
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// overrides
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virtual u8 read_r(int index) override;
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virtual void write_r(int index, u8 data) override;
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virtual u8 read_r(u8 index) override;
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virtual void write_r(u8 index, u8 data) override;
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};
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class hd38800_device : public hmcs44_cpu_device
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@ -380,8 +381,8 @@ protected:
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hmcs45_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, u16 polarity);
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// overrides
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virtual u8 read_r(int index) override;
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virtual void write_r(int index, u8 data) override;
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virtual u8 read_r(u8 index) override;
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virtual void write_r(u8 index, u8 data) override;
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};
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class hd38820_device : public hmcs45_cpu_device
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@ -663,24 +663,24 @@ void hmcs40_cpu_device::op_lrb()
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void hmcs40_cpu_device::op_p()
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{
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// P p: Pattern Generation
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cycle();
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// P p: Pattern Generation
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u16 address = m_a | m_b << 4 | m_c << 8 | (m_op & 7) << 9 | (m_pc & ~0x3f);
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u16 o = m_program->read_word(address & m_prgmask);
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u16 data = m_program->read_word(address & m_prgmask);
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// destination is determined by the 2 highest bits
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if (o & 0x100)
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if (data & 0x100)
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{
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// B3 B2 B1 B0 A0 A1 A2 A3
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m_a = bitswap<4>(o,0,1,2,3);
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m_b = o >> 4 & 0xf;
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m_a = bitswap<4>(data,0,1,2,3);
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m_b = data >> 4 & 0xf;
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}
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if (o & 0x200)
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if (data & 0x200)
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{
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// R20 R21 R22 R23 R30 R31 R32 R33
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o = bitswap<8>(o,0,1,2,3,4,5,6,7);
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write_r(2, o & 0xf);
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write_r(3, o >> 4 & 0xf);
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data = bitswap<8>(data,0,1,2,3,4,5,6,7);
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write_r(2, data & 0xf);
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write_r(3, data >> 4 & 0xf);
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}
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}
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@ -18,6 +18,8 @@ TODO:
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way to save this register when using interrupts
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- what happens when accessing ROM/RAM out of address range? Hitachi documentation
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says 'unused', but maybe it's mirrored?
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- current I/O ports are hardcoded for HMS402/4/8, which will need to be changed
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when other MCU types are added
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*/
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@ -73,7 +75,11 @@ hmcs400_cpu_device::hmcs400_cpu_device(const machine_config &mconfig, device_typ
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m_rom_size(rom_size),
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m_ram_size(ram_size),
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m_has_div(false),
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m_divider(8)
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m_divider(8),
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m_read_r(*this, 0),
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m_write_r(*this),
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m_read_d(*this, 0),
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m_write_d(*this)
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{ }
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hmcs400_cpu_device::~hmcs400_cpu_device() { }
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@ -185,8 +191,6 @@ void hmcs400_cpu_device::device_start()
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save_item(NAME(m_prev_pc));
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save_item(NAME(m_sp));
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save_item(NAME(m_op));
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save_item(NAME(m_param));
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save_item(NAME(m_i));
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save_item(NAME(m_a));
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save_item(NAME(m_b));
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@ -198,6 +202,9 @@ void hmcs400_cpu_device::device_start()
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save_item(NAME(m_st));
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save_item(NAME(m_ca));
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save_item(NAME(m_r));
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save_item(NAME(m_d));
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// register state for debugger
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state_add(STATE_GENPC, "GENPC", m_pc).formatstr("%04X").noshow();
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state_add(STATE_GENPCBASE, "CURPC", m_pc).formatstr("%04X").noshow();
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@ -225,6 +232,9 @@ void hmcs400_cpu_device::device_reset()
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m_pc = 0;
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m_sp = 0x3ff;
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m_st = 1;
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// all I/O ports set to input
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reset_io();
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}
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@ -278,6 +288,78 @@ device_memory_interface::space_config_vector hmcs400_cpu_device::memory_space_co
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}
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//-------------------------------------------------
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// i/o ports
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//-------------------------------------------------
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void hmcs400_cpu_device::reset_io()
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{
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// D4-D15 are high-voltage
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m_d_mask = m_d = 0x000f;
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m_write_d(m_d_mask);
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for (int i = 0; i < 10; i++)
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{
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// R0-R2 and RA are high-voltage
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u8 mask = (i >= 3 && i <= 9) ? 0xf : 0;
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m_r_mask[i] = m_r[i] = mask;
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m_write_r[i](i, mask);
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}
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}
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u8 hmcs400_cpu_device::read_r(u8 index)
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{
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// reads from write-only or non-existent ports are invalid
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bool write_only = index == 0 || (index >= 6 && index <= 8);
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if (write_only || index > 10)
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{
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logerror("read from %s port R%X at $%04X\n", write_only ? "output" : "unknown", index, m_prev_pc);
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return 0xf;
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}
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u8 inp = m_read_r[index].isunset() ? m_r_mask[index] : m_read_r[index](index);
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u8 mask = (index == 10) ? 3 : 0xf; // port A is 2-bit
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if (m_r_mask[index])
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return (inp & m_r[index]) & mask;
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else
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return (inp | m_r[index]) & mask;
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}
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void hmcs400_cpu_device::write_r(u8 index, u8 data)
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{
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// ignore writes to read-only or non-existent ports
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if (index > 8)
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return;
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data &= 0xf;
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m_r[index] = data;
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m_write_r[index](index, data);
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}
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int hmcs400_cpu_device::read_d(u8 index)
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{
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index &= 0xf;
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u16 mask = 1 << index;
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u16 inp = m_read_d.isunset() ? m_d_mask : m_read_d(0, mask);
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if (m_d_mask & mask)
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return BIT(inp & m_d, index);
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else
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return BIT(inp | m_d, index);
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}
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void hmcs400_cpu_device::write_d(u8 index, int state)
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{
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index &= 0xf;
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u16 mask = 1 << index;
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m_d = (m_d & ~mask) | (state ? mask : 0);
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m_write_d(0, m_d, mask);
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}
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//-------------------------------------------------
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// execute
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//-------------------------------------------------
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@ -19,6 +19,14 @@ public:
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// configuration helpers
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// 10 4-bit R ports (port A is 2-bit)
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template <std::size_t N> auto read_r() { return m_read_r[N].bind(); }
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template <std::size_t N> auto write_r() { return m_write_r[N].bind(); }
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// 16-bit discrete
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auto read_d() { return m_read_d.bind(); }
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auto write_d() { return m_write_d.bind(); }
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// system clock divider mask option (only for HMCS408, HMCS414, HMCS424)
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// valid options: 4, 8, 16, default to 8
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auto &set_divider(u8 div) { assert(m_has_div); m_divider = div; return *this; }
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@ -81,7 +89,16 @@ protected:
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u8 m_st; // status flag
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u8 m_ca; // carry flag
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u16 fetch();
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u8 m_r[10]; // R outputs state
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u8 m_r_mask[10];
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u16 m_d; // D pins state
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u16 m_d_mask;
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// I/O handlers
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devcb_read8::array<8> m_read_r;
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devcb_write8::array<8> m_write_r;
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devcb_read16 m_read_d;
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devcb_write16 m_write_d;
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// misc internal helpers
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u8 ram_r(u8 mem_mask = 0xf);
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@ -89,7 +106,14 @@ protected:
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void pop_stack();
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void push_stack();
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void reset_io();
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u8 read_r(u8 index);
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void write_r(u8 index, u8 data);
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int read_d(u8 index);
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void write_d(u8 index, int state);
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void cycle();
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u16 fetch();
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// opcode handlers
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void op_illegal();
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@ -534,9 +534,9 @@ void hmcs400_cpu_device::op_cal()
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// CAL a: Subroutine Jump on Status 1
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if (m_st)
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{
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cycle();
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push_stack();
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m_pc = m_op & 0x3f;
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cycle();
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}
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else
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m_st = 1;
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@ -563,9 +563,9 @@ void hmcs400_cpu_device::op_tbr()
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void hmcs400_cpu_device::op_rtn()
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{
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// RTN: Return from Subroutine
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cycle();
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cycle();
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pop_stack();
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cycle();
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cycle();
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}
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void hmcs400_cpu_device::op_rtni()
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@ -580,56 +580,82 @@ void hmcs400_cpu_device::op_rtni()
|
||||
void hmcs400_cpu_device::op_sed()
|
||||
{
|
||||
// SED: Set Discrete I/O Latch
|
||||
write_d(m_y, 1);
|
||||
}
|
||||
|
||||
void hmcs400_cpu_device::op_sedd()
|
||||
{
|
||||
// SEDD m: Set Discrete I/O Latch Direct
|
||||
write_d(m_i, 1);
|
||||
}
|
||||
|
||||
void hmcs400_cpu_device::op_red()
|
||||
{
|
||||
// RED: Reset Discrete I/O Latch
|
||||
write_d(m_y, 0);
|
||||
}
|
||||
|
||||
void hmcs400_cpu_device::op_redd()
|
||||
{
|
||||
// REDD m: Reset Discrete I/O Latch Direct
|
||||
write_d(m_i, 0);
|
||||
}
|
||||
|
||||
void hmcs400_cpu_device::op_td()
|
||||
{
|
||||
// TD: Test Discrete I/O Latch
|
||||
m_st = read_d(m_y);
|
||||
}
|
||||
|
||||
void hmcs400_cpu_device::op_tdd()
|
||||
{
|
||||
// TDD m: Test Discrete I/O Latch Direct
|
||||
m_st = read_d(m_i);
|
||||
}
|
||||
|
||||
void hmcs400_cpu_device::op_lar()
|
||||
{
|
||||
// LAR m: Load A from R Port Register
|
||||
m_a = read_r(m_i);
|
||||
}
|
||||
|
||||
void hmcs400_cpu_device::op_lbr()
|
||||
{
|
||||
// LBR m: Load B from R Port Register
|
||||
m_b = read_r(m_i);
|
||||
}
|
||||
|
||||
void hmcs400_cpu_device::op_lra()
|
||||
{
|
||||
// LRA m: Load R Port Register from A
|
||||
write_r(m_i, m_a);
|
||||
}
|
||||
|
||||
void hmcs400_cpu_device::op_lrb()
|
||||
{
|
||||
// LRB m: Load R Port Register from B
|
||||
write_r(m_i, m_b);
|
||||
}
|
||||
|
||||
void hmcs400_cpu_device::op_p()
|
||||
{
|
||||
// P p: Pattern Generation
|
||||
cycle();
|
||||
u16 data = m_program->read_word(m_i << 8 | m_b << 4 | m_a);
|
||||
|
||||
// destination is determined by the 2 highest bits
|
||||
if (data & 0x100)
|
||||
{
|
||||
// to A/B registers
|
||||
m_a = data & 0xf;
|
||||
m_b = data >> 4 & 0xf;
|
||||
}
|
||||
if (data & 0x200)
|
||||
{
|
||||
// to R1/R2 ports
|
||||
write_r(1, data & 0xf);
|
||||
write_r(2, data >> 4 & 0xf);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user