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(MESS) socrates.c: add internal and vsm german speech cart dumps [Team Europe, Lord Nightmare]
Update notes on speech synthesizer chip (it is definitely a tc8802)
This commit is contained in:
Jonathan Gevaryahu
parent
6b2591007b
commit
8195ea6959
@ -6,13 +6,22 @@
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*
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* (driver structure copied from vtech1.c)
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TODO:
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The speech chip is a toshiba tc8802AF running at 800khz clock/10khz output with between 1 and 4 t6684F vsm roms attached; create a sound driver for this!
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fix glitches with keyboard input (double keys still don't work, super painter letter entry still doesn't work)
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hook up hblank
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hook up mouse
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add waitstates for ram access (lack of this causes the system to run way too fast)
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find and hook up any timers/interrupt controls
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keyboard IR decoder MCU is HLE'd for now, needs decap and cpu core (it is rather tms1000 or CIC-like)
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* The speech chip is a toshiba tc8802AF (which is pin and speech
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compatible with the older toshiba t6803, but adds rom read mode and
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apparently does away with the melody mode); the chip is running at
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800khz clock/10khz output with between 1 and 4 t6684F vsm roms
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attached; create a sound driver for this!
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* fix glitches with keyboard input (double keys still don't work, super painter letter entry still doesn't work)
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* hook up hblank (m_hblankstate is inited 0 right now and never changed)
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* hook up mouse
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* add waitstates for ram access (lack of this causes the system to run
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way too fast)
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This will require some probing with the LA and the fluke to figure out
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how many cycles the waitstates are for for rom/ram/etc access.
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* figure out what bit 6 of the status register actually does; is this an
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ir mcu flag?
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* keyboard IR decoder MCU is HLE'd for now, needs decap and cpu core (it
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is rather tms1000 or CIC-like iirc)
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Socrates Educational Video System
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@ -367,9 +376,20 @@ TIMER_CALLBACK_MEMBER(socrates_state::clear_speech_cb)
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WRITE8_MEMBER(socrates_state::speech_command)// write 0x4x, some sort of bitfield; speech chip is probably hitachi hd38880 related but not exact, w/4 bit interface
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{
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/*
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* 76543210
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* |||||||\-- SEL0
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* ||||||\--- SEL1
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* |||||\---- SEL2
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* ||||\----- SEL3
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* |||\------ SEL4
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* ||\------- SEL5
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* |\-------- 64UP (if LOW the chip is in 'dumb' mode and can only play 64 fixed phrases; if HIGH the chip is in 'cpu controlled' mode and commands work) (not 100% sure about this but suspect it is correct)
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* \--------- START (in cpu mode must be toggled from low->high for a cpu command to 'take'; in 'dumb' mode must be toggled low->high to start that 'word')
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*/
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logerror("write to i/o 0x4x of %x\n", data);
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/*
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// the high 4 bits of the write control which 'register' is written to, the low 4 bits are data (this is based on a readback test)
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// old readback test, probably get rid of this junk:
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// 00-0f: readback: 70-7f
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// 10-1f: readback: 70-7f
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// 20-2f: readback: 70-7f
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@ -387,84 +407,73 @@ WRITE8_MEMBER(socrates_state::speech_command)// write 0x4x, some sort of bitfiel
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// e0-ef: readback ALL 76
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// f0-ff: 70-7f
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*/
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/* all this really tells us is: 0x80 is the speech start command;
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all commands are open bus on readback of 4 bits EXCEPT for 0x60 and 0xE0, which are the CTP active and inactive versions of the same command */
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/* following is hd38880 info:
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microcomputer interface of hd38880 is usually 7 wires:
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FP frame pulse, involved with READ command somehow
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SYBS1 data line bit 0, bidirectional
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SYBS2 data line bit 1, "
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SYBS3 data line bit 2, "
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SYBS4 data line bit 3, "
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CTP Command pulse line, sort of a 'write' line
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CMV More or less the 'command is being written' line which is active whenenever any command sequence is being written and during readback.
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/* The speech chip is a toshiba tc8802, it is NOT a t6803 since the t6803
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does not have the rom read mode, which the socrates definitely uses! */
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/* Commands (tc8802):
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SEL 5 4 3 2 1 0
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0 0 n n n n - ADLD - ADress LoaD - writes one nybble to the address
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of vsm rom selected (internal or external) starting
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from the low 4 bits; each subsequent write writes to
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the next higher 4 bits; resetting the chip resets
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the position
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0 1 n n n n - CNDT - CoNDiTion (aka 'setup') - writes one nybble to the
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setting register, starting from the low 4 bits; the
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subsequent write will be to the high 4 bits;
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resetting the chip will reset the position
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The instructions which the hd38880 can be sent are: (msb first/to the left), blank instructions are invalid
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0000 (nop?, used as a dummy read/write during direction change??? invalid when used alone?)
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0001
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0010 ADSET (Transfer address to "vsm-alike serial roms") <followed by 5 nybbles>
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0011 READ (read nybble) <bus changes from cpu->speechchip to speechchip->sys and you get as many nybbles as you pulse the CTP line for, address auto-increments>
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0100 INT1 (initialize 1) <followed by one nybble>
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0101
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0110 INT2 (initialize 2) <followed by one nybble>
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0111
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1000 SYSPD (set speed) <followed by one nybble>
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1001
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1010 STOP
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1011 CONDT (Read state P1) <bus changes from cpu->speechchip to speechchip->sys and you get one nybble>
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1100 START
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1101
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1110 SSTART (same as start but syspd speed is ignored and forced to be set to 9 (scale = 1.0))
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1111
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end hd38880 info.*/
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/* the socrates speech chip does not QUITE match the hd38880 though, but is very similar */
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switch(data&0xF0)
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CNDT bits (? are from T6803 datasheet, which could be wrong on the tc8802AF here):
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* 76543210
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* |||||||\-- ?bits/frame bit 1 (0 = see bit 2; 1 = 98bits/frame (these may be backwards))
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* ||||||\--- ?melody mode select if high
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* |||||\---- speech rom select; 0 is internal 8k mask, 1 is external vsm bus
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* ||||\----- ?voiced source select (0 = A; 1 = B)
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* |||\------ ?filter stages (0 = lpc-10; 1 = lpc-8)
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* ||\------- ?always 0
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* |\-------- ?frame length (0 = 20ms; 1 = 10ms)
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* \--------- ?bits/frame bit 2 (if bit 1 is not set: 0 = 56 bits/frame; 1 = 50 bits/frame)
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*
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1 0 x x x x - DTRD - DaTa ReaD - reads a nybble from the address as loaded
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and increments the address by one nybble. The first
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DTRD command after any other commands is a 'dummy
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read' which serves to reset the bus direction of the
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low 4 SEL lines, identical to the way the TMS5100
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does things. it doesn't affect the bus direction of
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the high two SEL lines.
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1 1 0 x x x - START - Starts speech at the address as loaded.
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1 1 1 x x x - RESET - Resets the internal chip state (clears shifters and
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counters) and forces speech to end/silence
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immediately.
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*/
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switch(data&0xF8)
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{
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case 0x80:
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if (data==0x80)
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{
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/* write me: start talking */
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m_speech_running = 1;
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timer_set(attotime::from_seconds(4), TIMER_CLEAR_SPEECH); // hack
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}
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case 0x80: case 0x88: case 0x90: case 0x98: case 0xA0: case 0xA8: case 0xB0: case 0xB8:
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/* 'dumb' mode speech command: write me: start talking */
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m_speech_running = 1;
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timer_set(attotime::from_seconds(4), TIMER_CLEAR_SPEECH); // hack
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break;
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case 0x90: // unknown, one of these is probably read and branch
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break;
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case 0xA0: // unknown
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break;
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case 0xB0: // unknown
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break;
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case 0xC0: // load address to vsm
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case 0xC0: case 0xC8: // ADLD: load address to vsm
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m_speech_address |= (((int)data&0xF)<<(m_speech_load_address_count*4))<<1;
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m_speech_load_address_count++;
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logerror("loaded address nybble %X, byte address is currently %5X with %d nybbles loaded\n", data&0xF, m_speech_address>>1, m_speech_load_address_count);
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break;
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case 0xD0: // load settings
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case 0xD0: case 0xD8: // CNDT: load settings
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m_speech_settings |= ((data&0xF)<<(m_speech_load_settings_count*4));
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m_speech_load_settings_count++;
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break;
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case 0xE0: // read byte, handled elsewhere
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case 0xE0: case 0xE8: // DTRD: read byte, handled elsewhere
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break;
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case 0xF0: // command: sub 0 is speak, sub 8 is reset
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if ((data&0xF) == 0) // speak
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{
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m_speech_running = 1;
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timer_set(attotime::from_seconds(4), TIMER_CLEAR_SPEECH); // hack
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}
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else if ((data&0xF) == 8) // reset
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{
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m_speech_running = 0;
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m_speech_address = 0;
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m_speech_settings = 0;
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m_speech_dummy_read = 0;
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m_speech_load_address_count = 0;
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m_speech_load_settings_count = 0;
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m_io40_latch &= 0x0f; // set last command to 0 to prevent problems
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}
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else // other
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{
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logerror("speech command 0xF%x is unknown!\n",data&0xF);
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}
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case 0xF0: // SPEAK
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m_speech_running = 1;
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timer_set(attotime::from_seconds(4), TIMER_CLEAR_SPEECH); // hack
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break;
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case 0xF8: // RESET
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m_speech_running = 0;
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m_speech_address = 0;
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m_speech_settings = 0;
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m_speech_dummy_read = 0;
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m_speech_load_address_count = 0;
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m_speech_load_settings_count = 0;
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m_io40_latch &= 0x0f; // set last command to 0 to prevent problems
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break;
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default: // 00 through 70 are packets without the write bit set, ignore them
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break;
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@ -1052,7 +1061,8 @@ ROM_START(socrates)
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? ?? 34 3 ?? ?
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/CE -> 35 2 ?? ?
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GND -- 36 1 -- GND
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Note that a17 goes to what would be pin 2 if a 32 pin rom were installed, which is not the case. (pins 1, 31 and 32 would be tied to vcc)
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Note that a17 goes to what would be pin 2 on a rom chip if a 32 pin rom were installed, which is not the case. (pins 1, 31 and 32 would be tied to vcc)
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It is likely that at least one of the 6 unknown lines is R/W from the z80, and another may be phi1/m1/clock etc to allow for ram to live in cart space
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Cartridge check procedure by socrates is, after screen init and check for speech synth,
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bankswitch to bank 0x10 (i.e. first 0x4000 of cart appears at 4000-7fff in z80 space),
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@ -1073,7 +1083,7 @@ ROM_START(socrates)
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/* english speech cart has a green QC sticker */
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ROM_REGION(0x2000, "speechint", ROMREGION_ERASE00) // speech data inside of the speech chip; fill with 00, if no speech cart is present socrates will see this
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ROM_LOAD_OPTIONAL("speech_internal.bin", 0x0000, 0x2000, CRC(edc1fb3f) SHA1(78b4631fc3b1c038e14911047f9edd6c4e8bae58)) // 8k on the speech chip itself
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ROM_LOAD_OPTIONAL("speech_eng_internal.bin", 0x0000, 0x2000, CRC(edc1fb3f) SHA1(78b4631fc3b1c038e14911047f9edd6c4e8bae58)) // 8k on the speech chip itself
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ROM_REGION(0x10000, "speechext", ROMREGION_ERASE00) // speech serial modules outside of the speech chip but still on speech cart
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ROM_LOAD_OPTIONAL("speech_eng_vsm1.bin", 0x0000, 0x4000, CRC(888e3ddd) SHA1(33AF6A21BA6D826071C9D48557B1C9012752570B)) // 16k in serial rom
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@ -1094,7 +1104,7 @@ ROM_START(socratfc)
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ROM_LOAD("tmp42c40p1844.u2", 0x000, 0x200, NO_DUMP) /* keyboard IR decoder MCU */
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ROM_REGION(0x2000, "speechint", ROMREGION_ERASE00) // speech data inside of the speech chip; fill with 00, if no speech cart is present socrates will see this
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ROM_LOAD_OPTIONAL("speech_fra_internal.bin", 0x0000, 0x2000, BAD_DUMP CRC(edc1fb3f) SHA1(78b4631fc3b1c038e14911047f9edd6c4e8bae58)) // probably same on french and english speech carts
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ROM_LOAD_OPTIONAL("speech_fra_internal.bin", 0x0000, 0x2000, NO_DUMP)
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ROM_REGION(0x10000, "speechext", ROMREGION_ERASE00) // speech serial modules outside of the speech chip but still on speech cart
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ROM_LOAD_OPTIONAL("speech_fra_vsm1.bin", 0x0000, 0x4000, NO_DUMP) // 16k in serial rom
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@ -1118,13 +1128,11 @@ ROM_START(profweis)
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ROM_LOAD("tmp42c40p1844.u2", 0x000, 0x200, NO_DUMP) /* keyboard IR decoder MCU */
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ROM_REGION(0x2000, "speechint", ROMREGION_ERASE00) // speech data inside of the speech chip; fill with 00, if no speech cart is present socrates will see this
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ROM_LOAD_OPTIONAL("speech_ger_internal.bin", 0x0000, 0x2000, BAD_DUMP CRC(edc1fb3f) SHA1(78b4631fc3b1c038e14911047f9edd6c4e8bae58)) // probably same on french and english speech carts
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ROM_LOAD_OPTIONAL("speech_ger_internal.bin", 0x0000, 0x2000, CRC(5ff0fdc6) SHA1(8ef128561a846762a20e3fe9513a4a22aaadc7f6))
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ROM_REGION(0x10000, "speechext", ROMREGION_ERASE00) // speech serial modules outside of the speech chip but still on speech cart
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ROM_LOAD_OPTIONAL("speech_ger_vsm1.bin", 0x0000, 0x4000, NO_DUMP) // 16k in serial rom
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ROM_LOAD_OPTIONAL("speech_ger_vsm2.bin", 0x4000, 0x4000, NO_DUMP) // 16k in serial rom
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ROM_LOAD_OPTIONAL("speech_ger_vsm3.bin", 0x8000, 0x4000, NO_DUMP) // 16k in serial rom
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ROM_FILL(0xC000, 0x4000, 0xff) // last vsm isn't present, FF fill
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ROM_LOAD_OPTIONAL("speech_ger_vsm1.bin", 0x0000, 0x4000, CRC(a979a00b) SHA1(0290844619dbdf336757003aaab3ffd0a75b7ee9)) // 16k in serial rom
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ROM_FILL(0x4000, 0xc000, 0xff) // last 3 vsms aren't present, FF fill
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ROM_END
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